lnfineon XC866 DATA SHEET

查询XC866-2FR供应商
XC866
8-Bit Single-Chip Microcontroller
Data Sheet, V1.0, Feb 2006
Microcontrollers
Edition 2006-02
Published by Infineon Technologies AG, 81726 München, Germany
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, V1.0, Feb 2006
XC866
8-Bit Single-Chip Microcontroller
Microcontrollers
XC866 Data Sheet Revision History: 2006-02 V1.0
Previous Version: V 0.1, 2005-01
Page Subjects (major changes since last revision)
3 LIN support is elaborated in Table 1.
13 Section 3.2 is updated.
34 Section 3.3 is updated.
37 Section 3.4 is updated.
49 The power-on reset requirements are updated in Section 3.7.
49 Section 3.7 is updated.
54 Table 19 is updated with a new range of the f
VCOFREE
parameter.
65 Section 3.12 is updated.
66 Section 3.13 is updated.
78 Figure 34 is updated with the removal of OCDS interrupt.
81 Section 4.1.2 is updated.
82 Section 4.1.3 is updated.
83 Section 4.2.1 is updated.
87 Section 4.2.2 is updated.
91 Section 4.2.4 is updated.
95 “Testing Waveforms” is updated in Section 4.3.1.
97 Section 4.3.3 is updated.
102 Figure 40 is updated.
103 “Quality Declaration” is updated in Section 5.2.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
XC8668-Bit Single-Chip Microcontroller
XC800 Family
1 Summary of Features
• High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers
• On-chip memory – 8 Kbytes of Boot ROM – 256 bytes of RAM – 512 bytes of XRAM – 8/16 Kbytes of Flash; or
8/16 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator)
(further features are on next page)
Flash or ROM
8K/16K x 8
Boot ROM
8K x 8
XRAM
512 x 8
RAM
256 x 8
1)
Timer 0
16-bit
On-Chip Debug Support
XC800 Core
Timer 1
16-bit
Timer 2
16-bit
UART
Capture/Compare Unit
Watchdog
Timer
1) All ROM devices include 4K x 8 Flash
SSC
16-bit
Compare Unit
16-bit
ADC
10-bit
8-channel
Port 0
Port 1
Port 2
Port 3
6-bi t Di gi tal I/O
5-bi t Di gi tal I/O
8-bit Digital/Analog Input
8-bi t Di gi tal I/O
Figure 1 XC866 Functional Units
Data Sheet 1 V1.0, 2006-02
Features (continued):
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation – PLL loss-of-lock detection
• Power saving modes – slow-down mode – idle mode – power-down mode with wake-up capability via RXD or EXINT0 – clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports – 19 pins as digital I/O – 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Three 16-bit timers – Timer 0 and Timer 1 (T0 and T1) –Timer 2
• Capture/compare unit for PWM signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM
• PG-TSSOP-38 pin package
• Temperature range T
:
A
– SAF (-40 to 85 °C) – SAK (-40 to 125 °C)
XC866
Summary of Features
Data Sheet 2 V1.0, 2006-02
XC866
Summary of Features
XC866 Variant Devices
The XC866 product family features eight devices with different configurations and program memory sizes, offering cost-effective solution for different application requirements.
The list of XC866 devices and their differences are summarized in Table 1.
Table 1 Device Summary
Device Type Device Name Flash Size ROM Size LIN BSL
Support
Flash XC866L-4FR 16 Kbytes Yes
XC866-4FR 16 Kbytes No
XC866L-2FR 8 Kbytes Yes
XC866-2FR 8 Kbytes No
ROM XC866L-4RR 4 Kbytes 16 Kbytes Yes
XC866-4RR 4 Kbytes 16 Kbytes No
XC866L-2RR 4 Kbytes 8 Kbytes Yes
XC866-2RR 4 Kbytes 8 Kbytes No
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies:
• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the XC866, please refer to the “Product Catalog Microcontrollers” which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
verification of the respective ROM code.
Data Sheet 3 V1.0, 2006-02
2 General Device Information
2.1 Block Diagram
XC866
Internal Bus
XC800 Core
T0 & T1 UART
CCU6
SSC
Timer 2
WDT
OCDS
TMS
MBC
RESET
V
DDP
V
SSP
V
DDC
V
SSC
XTAL1 XTAL2
8-Kbyte
Boot ROM
1)
256-byte RAM
+
64-byte monitor
RAM
512-byte XRAM
8/16-Kbyte
Flash or ROM
Clock Generator
10 MHz
On-chip OSC
PLL
2)
XC866
General Device Information
Port 0Port 1Port 2Port 3
ADC
P0.0 - P0.5
P1.0 - P1.1 P1.5-P1.7
P2.0 - P2.7
V
AREF
V
AGND
P3.0 - P3.7
1) Includes 1-Kbyte monitor ROM
2) Includes additional 4-Kbyte Flash
Figure 2 XC866 Block Diagram
Data Sheet 4 V1.0, 2006-02
2.2 Logic Symbol
XC866
General Device Information
V
V
AREF
V
AGND
RESET
MBC
TMS
XTAL1
XTAL2
V
Figure 3 XC866 Logic Symbol
DDP
DDC
XC866
V
SSP
Port 0 6-Bit
Port 1 5-Bit
Port 2 8-Bit
Port 3 8-Bit
V
SSC
Data Sheet 5 V1.0, 2006-02
2.3 Pin Configuration
XC866
General Device Information
MBC
P0.3/SCLK_1/COUT63_1
P0.4/MTSR_1/CC62_1
P0.5/MR ST _1/EXINT 0_0 /COUT62_1
XTAL2
XTAL1
V
SSC
V
DDC
P1.6/C CP OS1_1/T12HR_0 /EXINT6
P1.7/CCPOS2_1/T13HR_0
TMS
P0.0/TCK_0/T12HR_1/CC 61_1/CLKOUT/RXDO_1
P0.2/CTRAP_2/TDO_0/TXD_1
P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1
P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0
P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1
P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2
V
DDP
V
SSP
1
2
3
4
5
6
7
8
9
10
XC866
11
12
13
14
15
16
17
18
19
RESET
38
P3.5 /COUT6 2_0
37
P3.4 /CC62_0
36
P3.3 /COUT6 1_0
35
P3.2/CCPOS2_2/CC61_0
34
P3.1/CCPOS0_2/CC61_2/COUT60_0
33
P3.0/CCPOS1_2/CC60_0
32
P3.7/EXINT4/COUT63_0
31
P3.6 /CTRA P_ 0
30
P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0
29
P1.1/EXINT3/TDO_1/TXD_0
28
P1.0 /RXD_ 0/T 2E X
27
P2.7 /AN7
26
V
25
AREF
V
24
AGND
P2.6 /AN6
23
P2.5 /AN5
22
P2.4 /AN4
21
P2.3 /AN3
20
Figure 4 XC866 Pin Configuration, PG-TSSOP-38 Package (top view)
Data Sheet 6 V1.0, 2006-02
General Device Information
2.4 Pin Definitions and Functions
Table 2 Pin Definitions and Functions
Symbol Pin
Number
P0 I/O Port 0
P0.0 12 Hi-Z TCK_0 JTAG Clock Input
P0.1 14 Hi-Z TDI_0 JTAG Serial Data Input
P0.2 13 PU CTRAP_2
P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output
P0.4 3 Hi-Z MTSR_1 SSC Master Transmit Output/
P0.5 4 Hi-Z MRST_1 SSC Master Receive Input/
Type Reset
State
Function
Port 0 is a 6-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC.
T12HR_1 CCU6 Timer 12 Hardware Run
Input
CC61_1 Input/Output of Capture/Compare
channel 1 CLKOUT Clock Output RXDO_1 UART Transmit Data Output
T13HR_1 CCU6 Timer 13 Hardware Run
Input RXD_1 UART Receive Data Input COUT61_1 Output of Capture/Compare
channel 1 EXF2_1 Timer 2 External Flag Output
CCU6 Trap Input TDO_0 JTAG Serial Data Output TXD_1 UART Transmit Data Output/
Clock Output
COUT63_1 Output of Capture/Compare
channel 3
Slave Receive Input
CC62_1 Input/Output of Capture/Compare
channel 2
Slave Transmit Output EXINT0_0 External Interrupt Input 0 COUT62_1 Output of Capture/Compare
channel 2
XC866
Data Sheet 7 V1.0, 2006-02
General Device Information
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin
Number
Type Reset
State
Function
P1 I/O Port 1
Port 1 is a 5-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, and the SSC.
P1.0 27 PU RXD_0 UART Receive Data Input
T2EX Timer 2 External Trigger Input
P1.1 28 PU EXINT3 External Interrupt Input 3
TDO_1 JTAG Serial Data Output TXD_0 UART Transmit Data Output/
Clock Output
P1.5 29 PU CCPOS0_1 CCU6 Hall Input 0
EXINT5 External Interrupt Input 5 EXF2_0 TImer 2 External Flag Output RXDO_0 UART Transmit Data Output
P1.6 9 PU CCPOS1_1 CCU6 Hall Input 1
T12HR_0 CCU6 Timer 12 Hardware Run
Input EXINT6 External Interrupt Input 6
P1.7 10 PU CCPOS2_1 CCU6 Hall Input 2
T13HR_0 CCU6 Timer 13 Hardware Run
Input
P1.5 and P1.6 can be used as a software chip select output for the SSC.
XC866
Data Sheet 8 V1.0, 2006-02
General Device Information
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin
Number
Type Reset
State
Function
P2 I Port 2
Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC.
P2.0 15 Hi-Z CCPOS0_0 CCU6 Hall Input 0
EXINT1 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run
Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0
P2.1 16 Hi-Z CCPOS1_0 CCU6 Hall Input 1
EXINT2 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run
Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1
P2.2 17 Hi-Z CCPOS2_0 CCU6 Hall Input 2
CTRAP_1
CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2
P2.3 20 Hi-Z AN3 Analog Input 3
P2.4 21 Hi-Z AN4 Analog Input 4
P2.5 22 Hi-Z AN5 Analog Input 5
P2.6 23 Hi-Z AN6 Analog Input 6
P2.7 26 Hi-Z AN7 Analog Input 7
XC866
Data Sheet 9 V1.0, 2006-02
XC866
General Device Information
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin
Number
P3 I Port 3
P3.0 32 Hi-Z CCPOS1_2 CCU6 Hall Input 1
P3.1 33 Hi-Z CCPOS0_2 CCU6 Hall Input 0
P3.2 34 Hi-Z CCPOS2_2 CCU6 Hall Input 2
P3.3 35 Hi-Z COUT61_0 Output of Capture/Compare
P3.4 36 Hi-Z CC62_0 Input/Output of Capture/Compare
P3.5 37 Hi-Z COUT62_0 Output of Capture/Compare
P3.6 30 PD CTRAP_0
P3.7 31 Hi-Z EXINT4 External Interrupt Input 4
Type Reset
State
Function
Port 3 is a bidirectional general purpose I/O port. It can be used as alternate functions for the CCU6.
CC60_0 Input/Output of Capture/Compare
channel 0
CC61_2 Input/Output of Capture/Compare
channel 1 COUT60_0 Output of Capture/Compare
channel 0
CC61_0 Input/Output of Capture/Compare
channel 1
channel 1
channel 2
channel 2
CCU6 Trap Input
COUT63_0 Output of Capture/Compare
channel 3
Data Sheet 10 V1.0, 2006-02
General Device Information
Table 2 Pin Definitions and Functions (cont’d)
Symbol Pin
Number
V
V
V
V
V
V
DDP
SSP
DDC
SSC
AREF
AGND
18 I/O Port Supply (3.3 V/5.0 V)
19 I/O Port Ground
8–Core Supply Monitor (2.5 V)
7–Core Supply Ground
25 ADC Reference Voltage
24 ADC Reference Ground
Type Reset
State
Function
XTAL1 6IHi-ZExternal Oscillator Input
(NC if not needed)
XTAL2 5OHi-ZExternal Oscillator Output
(NC if not needed)
TMS 11 I PD Test Mode Select
RESET
38 I PU Reset Input
MBC 1IPUMonitor & BootStrap Loader Control
XC866
Data Sheet 11 V1.0, 2006-02
XC866
Functional Description
3 Functional Description
3.1 Processor Architecture
The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.
The XC866 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs.
Figure 5 shows the CPU functional blocks.
Internal Data
Memory
External SFRs
External Data
Memory
Core SFRs
Regist er Int erfac e
Program Memory
f
CCLK
Memory Wait
Reset
Legacy Exter nal Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
16-bit R egis t ers & Memory Interface
Opcode &
Imm ediate
Registers
Opcode D ecoder
State Mac hine &
Power Saving
Interrupt
Cont roller
ALU
Mult ipli er / D iv ider
Timer 0 / Timer 1
UART
Figure 5 CPU Block Diagram
Data Sheet 12 V1.0, 2006-02
XC866
Functional Description
3.2 Memory Organization
The XC866 CPU operates in the following five address spaces:
• 8 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 512 bytes of XRAM memory (XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 8/16 Kbytes of Flash program memory (Flash devices); or 8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices)
Figure 6 illustrates the memory address spaces of the 16-Kbyte Flash devices. For the
8-Kbyte Flash devices, the shaded banks are not available.
FFFF
H
F200
XRAM
512 byt es
Boot ROM
8 Kbytes
D-Fl ash Ba nk
4 Kbytes
P-Flas h Bank 2
4 Kbytes
P-Flas h Bank 1
4 Kbytes
P-Flas h Bank 0
4 Kbytes
Program S pace External Dat a Spac e Interna l Dat a Spac e
F000
E000
C000
B000
A000
3000
2000
1000
0000
H
H
H
H
H
H
H
H
H
H
XRAM
512 bytes
FFFF
F200
F000
0000
H
H
H
Indirect
Address
Internal RAM
7F
H
Internal RAM
H
00
H
Direct
Addres s
Speci al Func tion
Regist ers
FF
H
80
H
Figure 6 Memory Map of XC866 Flash Device
Data Sheet 13 V1.0, 2006-02
XC866
Functional Description
3.2.1 Memory Protection Strategy
The XC866 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash devices) and ROM (for ROM devices) memory from being read
• Flash program and erase protection (for Flash devices only)
Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 3.
Table 3 Flash Protection Modes
Mode 01
Activation Program a valid password via BSL mode 6
Selection MSB of password = 0 MSB of password = 1
P-Flash contents can be read by
P-Flash program and erase
D-Flash contents can be read by
D-Flash program Possible Not possible
D-Flash erase Possible, on the condition that bit
Read instructions in the P-Flash
Not possible Not possible
Read instructions in any program memory
DFLASHEN in register MISC_CON is set to 1 prior to each erase operation
Read instructions in the P-Flash or D-Flash
Read instructions in the P-Flash or D-Flash
Not possible
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset.
Although no protection scheme can be considered infallible, the XC866 memory protection strategy provides a very high level of protection for a general purpose microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet 14 V1.0, 2006-02
XC866
Functional Description
3.2.2 Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80
to FFH. All registers, except the program counter, reside in the SFR area. The
H
SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1 Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80 of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8F
. To access SFRs in the mapped area, bit RMAP in SFR
H
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 7.
SYSCON0 System Control Register 0 Reset Value: 00
765432 10
to FFH, bringing the number
H
H
010RMAP
rrwrrw
Field Bits Type Description
RMAP 0rwSpecial Function Register Map Control
0 The access to the standard SFR area is
enabled.
1 The access to the mapped SFR area is
enabled.
1 2rwReserved
Returns the last value if read; should be written with 1.
0 1,[7:3] r Reserved
Returns 0 if read; should be written with 0.
Data Sheet 15 V1.0, 2006-02
XC866
Functional Description
Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of
SYSCON0 should not be modified.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software.
SFR Data
(to/from CPU)
SYSCON0.RMAP
rw
Standard Area (R MAP = 0)
Module 1 SFRs
Module 2 SFRs
…...
Module n SFRs
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
…...
Module m SFRs
FF
H
80
H
FF
H
80
H
Direct
Internal Data
Memory Address
Figure 7 Address Extension by Mapping
Data Sheet 16 V1.0, 2006-02
XC866
Functional Description
3.2.2.2 Address Extension by Paging
Address extension is further performed at the module level by paging. With the address extension by mapping, the XC866 has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 8.
SFR Address
(from CPU)
MOD_PAGE.PAGE
rw
PAGE 0
SFR0
SFR1
…...
SFRx
PAGE 1
SFR Data
(to/from CPU )
SFR0
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 8 Address Extension by Paging
Data Sheet 17 V1.0, 2006-02
XC866
Functional Description
In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
value update
from CPU
PAGE
Figure 9 Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines.
The XC866 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers
Data Sheet 18 V1.0, 2006-02
XC866
Functional Description
The page register has the following definition:
MOD_PAGE Page Register fo r mod ule M OD Reset V alue : 00
765432 10
OP STNR 0 PAGE
wwr rw
Field Bits Type Description
PAGE [2:0] rw Page Bits
When written, the value indicates the new page. When read, the value indicates the currently active page.
STNR [5:4] w Storage Number
This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11 the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored.
,
B
H
00 ST0 is selected. 01 ST1 is selected. 10 ST2 is selected. 11 ST3 is selected.
Data Sheet 19 V1.0, 2006-02
Field Bits Type Description
OP [7:6] w Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10 New page programming with automatic page
saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR.
11 Automatic restore page action. The value
written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR.
0 3r Reserved
Returns 0 if read; should be written with 0.
XC866
Functional Description
Data Sheet 20 V1.0, 2006-02
XC866
Functional Description
3.2.3 Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the “close access” password is not written. If “open access” password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD.
PASSWD Password Register Reset Value: 07
76543210
PASS
wh rh rw
PROTECT
Field Bits Type Description
MODE [1:0] rw Bit Protection Scheme Control bits
00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000 MODE[1:0] be registered.
PROTECT_S 2rhBit Protection Signal Status bit
This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected
bits.
PASS [7:3] wh Password bits
The Bit Protection Scheme only recognizes three patterns. 11000BEnables writing of the bit field MODE. 10011BOpens access to writing of all protected bits. 10101BCloses access to writing of all protected bits.
, writing 10011B to the
B
_S
; only then, will the
B
MODE
H
Data Sheet 21 V1.0, 2006-02
XC866
Functional Description
3.2.4 XC866 Register Overview
The SFRs of the XC866 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 4 to Table 12, with the addresses of the bitaddressable SFRs appearing in bold typeface.
The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1).
Table 4 CPU Register Overview
AddrRegister Name Bit 76543210
RMAP = 0 or 1
SP Reset: 07
81
H
Stack Pointer Register
DPL Reset: 00
82
H
Data Pointer Register Low
DPH Reset: 00
83
H
Data Pointer Register High
PCON Reset: 00
87
H
Power Control Register
TCON Reset: 00
88
H
Timer Control Register
TMOD Reset: 00
89
H
Timer Mode Register
TL0 Reset: 00
8A
H
Timer 0 Register Low
TL1 Reset: 00
8B
H
Timer 1 Register Low
TH0 Reset: 00
8C
H
Timer 0 Register High
TH1 Reset: 00
8D
H
Timer 1 Register High
SCON Reset: 00
98
H
Serial Channel Control Register
SBUF Reset: 00
99
H
Serial Data Buffer Register
EO Reset: 00
A2
H
Extended Operation Register
IEN0 Reset: 00
A8
H
Interrupt Enable Register 0
IP Reset: 00
B8
H
Interrupt Priority Register
IPH Reset: 00
B9
H
Interrupt Priority Register High
PSW Reset: 00
D0
H
Program Status Word Register
ACC Reset: 00
E0
H
Accumulator Register
IEN1 Reset: 00
E8
H
Interrupt Enable Register 1
Bit Field
H
Type rw
Bit Field DPL7 DPL6 DPL5 DPL4 DPL 3 DPL2 DPL1 DPL0
H
Type rw rw rw rw rw rw rw rw
Bit Field DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
H
Type rw rw rw rw rw rw rw rw
Bit Field SMOD 0 GF1 GF0 0 IDLE
H
Type rw r rw rw r rw
Bit Field TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
H
Type rwh rw rwh rw rwh rw rwh rw
Bit Field GATE1 0 T1M GATE0 0 T0M
H
Type rw r rw rw r rw
Bit Field VAL
H
Type rwh
Bit Field VAL
H
Type rwh
Bit Field VAL
H
Type rwh
Bit Field VAL
H
Type rwh
Bit Field
H
Type rw rw rw rw rw rwh rwh rwh
Bit Field
H
Type rwh
Bit Field
H
SM0 SM1 SM2 REN TB8 RB8 TI RI
0 TRAP_
Type r rw r rw
Bit Field EA 0 ET2 ES ET1 EX1 ET0 EX0
H
Type rw r rwrwrwrwrwrw
Bit Field 0 PT2 PS PT1 PX1 PT0 PX0
H
Type r rwrwrwrwrwrw
Bit Field
H
Type r rwrwrwrwrwrw
Bit Field CY AC F0 RS1 RS0 OV F1 P
H
Type rw rwh rwh rw rw rwh rwh rh
Bit Field ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
H
Type rw rw rw rw rw rw rw rw
Bit Field ECCIP3ECCIP2ECCIP1ECCIP0EXM EX2 ESSC EADC
H
0 PT2H PSH PT1H PX1H PT0H PX0H
Type rw rw rw rw rw rw rw rw
EN
SP
VAL
0 DPSEL
0
Data Sheet 22 V1.0, 2006-02
XC866
Functional Description
Table 4 CPU Register Overview (cont’d)
AddrRegister Name Bit 76543210
B Reset: 00
F0
H
B Register
IP1 Reset: 00
F8
H
Interrupt Priority Register 1
IPH1 Reset: 00
F9
H
Interrupt Priority Register 1 High
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 5 System Control Register Overview
AddrRegister Name Bit 76543210
RMAP = 0 or 1
SYSCON0 Reset: 00
8F
H
System Control Register 0
RMAP = 0
SCU_PAGE Reset: 00
BF
H
Page Register for System Control
RMAP = 0, Page 0
MODPISEL Reset: 00
B3
H
Peripheral Input Select Register
B4HIRCON0 Reset: 00
Interrupt Request Register 0
IRCON1 Reset: 00
B5
H
Interrupt Request Register 1
EXICON0 Reset: 00
B7
H
External Interrupt Control Register 0
EXICON1 Reset: 00
BA
H
External Interrupt Control Register 1
NMICON Reset: 00
BB
H
NMI Control Register
BCHNMISR Reset: 00
NMI Status Register
BCON Reset: 00
BD
H
Baud Rate Control Register
BG Reset: 00
BE
H
Baud Rate Timer/Reload Register
FDCON Reset: 00
E9
H
Fractional Divider Control Register
FDSTEP Reset: 00
EA
H
Fractional Divider Reload Register
FDRES Reset: 00
EB
H
Fractional Divider Result Register
RMAP = 0, Page 1
Bit Field B7 B6 B5 B4 B3 B2 B1 B0
H
Type rw rw rw rw rw rw rw rw
Bit Field PCCIP3PCCIP2PCCIP1PCCIP0PXM PX2 PSSC PADC
H
Type rw rw rw rw rw rw rw rw
Bit Field PCCIP3HPCCIP2HPCCIP1HPCCIP0HPXMH PX2H PSSCH PADC
H
Type rw rw rw rw rw rw rw rw
Bit Field 0 RMAP
H
Type r rw
Bit Field OP STNR 0 PAGE
H
Type w w r rw
Bit Field 0 JTAG
H
TDIS
JTAG TCKS
0 EXINT
0IS
Type r rw rw r rw rw
Bit Field 0 EXINT6EXINT5EXINT4EXINT3EXINT2EXINT1EXINT
H
Type r rwh rwh rwh rwh rwh rwh rwh
Bit Field 0 ADCS
H
RC1
ADCS
RC0
RIR TIR EIR
Type r rwh rwh rwh rwh rwh
Bit Field EXINT3 EXINT2 EXINT1 EXINT0
H
Type rw rw
Bit Field
H
Type r rw rw rw
Bit Field
H
0 EXINT6 EXINT5 EXINT4
0 NMI
ECC
NMI
VDDP
NMI VDD
Type r rw rw rw
H
Bit Field
0 FNMI
ECC
FNMI
VDDP
FNMI
VDD
Type r rwh rwh rwh
Bit Field BGSEL 0 BREN BRPRE R
H
Type rw r rw rw rw
Bit Field
H
Type rw
Bit Field
H
BGS SYNEN ERRSYNEOFSYNBRK NDOV FDM FDEN
BR_VALUE
Type rw rw rwh rwh
Bit Field STEP
H
Type rw
Bit Field RESULT
H
Type rh
rw rw
NMI
NMI
FLASH
NMI PLL
OCDS
rw rw rw rw
FNMI
FNMI
FLASH
FNMI
PLL
OCDS
rwh rwh rwh rwh
rwh rwh rw rw
H
URRIS
0
NMI
WDT
FNMI WDT
Data Sheet 23 V1.0, 2006-02
XC866
Functional Description
Table 5 System Control Register Overview (cont’d)
AddrRegister Name Bit 76543210
ID Reset: 01
B3
H
Identity Register
PMCON0 Reset: 00
B4
H
Power Mode Control Register 0
PMCON1 Reset: 00
B5
H
Power Mode Control Register 1
B6HOSC_CON Reset: 08
OSC Control Register
PLL_CON Reset: 20
B7
H
PLL Control Register
CMCON Reset: 00
BA
H
Clock Control Register
PASSWD Reset: 07
BB
H
Password Register
FEAL Reset: 00
BC
H
Flash Error Address Register Low
FEAH Reset: 00
BD
H
Flash Error Address Register High
COCON Reset: 00
BE
H
Clock Output Control Register
MISC_CON Reset: 00
E9
H
Miscellaneous Control Register
RMAP = 0, Page 3
B3HXADDRH Reset: F0
On-Chip XRAM Address Higher Order
Bit Field PRODID VERID
H
Type r r
Bit Field 0 WDT
H
RST
WKRS WK
SEL
SD PD WS
Type r rwh rwh rw rw rwh rw
Bit Field 0 T2_DIS CCU
H
_DIS
SSC
_DIS
Type r rw rw rw rw
Bit Field 0 OSCPDXPD OSCSSORD
H
RES
Type r rw rw rw rwh rh
Bit Field NDIV VCO
H
BYP
OSC
DISC
RESLD LOCK
Type rw rw rw rwh rh
Bit Field VCO
H
SEL
0 CLKREL
Type rw r rw
Bit Field PASS PROTE
H
CT_S
Type wh rh rw
Bit Field ECCERRADDR[7:0]
H
Type rh
Bit Field ECCERRADDR[15:8]
H
Type rh
Bit Field 0 TLEN COUT
H
S
COREL
Type r rw rw rw
Bit Field 0 DFLAS
H
Type r rwh
Bit Field
H
Type rw
ADDRH
MODE
ADC _DIS
OSCR
HEN
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6 WDT Register Overview
AddrRegister Name Bit 76543210
RMAP = 1
WDTCON Reset: 00
BB
H
Watchdog Timer Control Register
H
Bit Field
Type r rw rh
WDTREL Reset: 00
BC
H
Watchdog Timer Reload Register
WDTWINB Reset: 00
BD
H
Watchdog Window-Boundary Count Register
WDTL Reset: 00
BE
H
Watchdog Timer Register Low
BF
WDTH Reset: 00
H
Watchdog Timer Register High
Bit Field WDTREL
H
Type rw
Bit Field
H
Type rw
Bit Field
H
Type rh
Bit Field WDT[15:8]
H
Type rh
Data Sheet 24 V1.0, 2006-02
0 WINBENWDTPR0 WDTENWDTRSWDT
IN
r rw rwh rw
WDTWINB
WDT[7:0]
XC866
Functional Description
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 7 Port Register Overview
AddrRegister Name Bit 76543210
RMAP = 0
PORT_PAGE Reset: 00
B2
H
Page Register for PORT
RMAP = 0, Page 0
P0_DATA Reset: 00
80
H
P0 Data Register
P0_DIR Reset: 00
86
H
P0 Direction Register
P1_DATA Reset: 00
90
H
P1 Data Register
P1_DIR Reset: 00
91
H
P1 Direction Register
P2_DATA Reset: 00
A0
H
P2 Data Register
P2_DIR Reset: 00
A1
H
P2 Direction Register
P3_DATA Reset: 00
B0
H
P3 Data Register
P3_DIR Reset: 00
B1
H
P3 Direction Register
RMAP = 0, Page 1
P0_PUDSEL Reset: FF
80
H
P0 Pull-Up/Pull-Down Select Register
P0_PUDEN Reset: C4
86
H
P0 Pull-Up/Pull-Down Enable Register
P1_PUDSEL Reset: FF
90
H
P1 Pull-Up/Pull-Down Select Register
P1_PUDEN Reset: FF
91
H
P1 Pull-Up/Pull-Down Enable Register
P2_PUDSEL Reset: FF
A0
H
P2 Pull-Up/Pull-Down Select Register
P2_PUDEN Reset: 00
A1
H
P2 Pull-Up/Pull-Down Enable Register
P3_PUDSEL Reset: BF
B0
H
P3 Pull-Up/Pull-Down Select Register
P3_PUDEN Reset: 40
B1
H
P3 Pull-Up/Pull-Down Enable Register
RMAP = 0, Page 2
P0_ALTSEL0 Reset: 00
80
H
P0 Alternate Select 0 Register
P0_ALTSEL1 Reset: 00
86
H
P0 Alternate Select 1 Register
P1_ALTSEL0 Reset: 00
90
H
P1 Alternate Select 0 Register
P1_ALTSEL1 Reset: 00
91
H
P1 Alternate Select 1 Register
P3_ALTSEL0 Reset: 00
B0
H
P3 Alternate Select 0 Register
Bit Field
H
Type w w r rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r rw rw
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r
Bit Field
H
Type rw rw rw rw rw rw rw rw
Bit Field
H
Type rw rw rw rw rw rw rw rw
Bit Field
H
Type rw rw rw rw rw rw rw rw
Bit Field
H
Type rw rw rw rw rw rw rw rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field 0 P5 P4 P3 P2 P1 P0
H
Type r rw rw rw rw rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r rw rw
Bit Field P7 P6 P5 0 P1 P0
H
Type rw rw rw r rw rw
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
OP STNR 0 PAGE
rw rw
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
Data Sheet 25 V1.0, 2006-02
XC866
Functional Description
Table 7 Port Register Overview (cont’d)
AddrRegister Name Bit 76543210
P3_ALTSEL1 Reset: 00
B1
H
P3 Alternate Select 1 Register
RMAP = 0, Page 3
P0_OD Reset: 00
80
H
P0 Open Drain Control Register
P1_OD Reset: 00
90
H
P1 Open Drain Control Register
P3_OD Reset: 00
B0
H
P3 Open Drain Control Register
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8 ADC Register Overview
AddrRegister Name Bit 76543210
RMAP = 0
ADC_PAGE Reset: 00
D1
H
Page Register for ADC
RMAP = 0, Page 0
CAHADC_GLOBCTR Reset: 30
Global Control Register
CBHADC_GLOBSTR Reset: 00
Global Status Register
ADC_PRAR Reset: 00
CC
H
Priority and Arbitration Register
ADC_LCBR Reset: B7
CD
H
Limit Check Boundary Register
ADC_INPCR0 Reset: 00
CE
H
Input Class Register 0
ADC_ETRCR Reset: 00
CF
H
External Trigger Control Register
RMAP = 0, Page 1
ADC_CHCTR0 Reset: 00
CA
H
Channel Control Register 0
ADC_CHCTR1 Reset: 00
CB
H
Channel Control Register 1
ADC_CHCTR2 Reset: 00
CC
H
Channel Control Register 2
ADC_CHCTR3 Reset: 00
CD
H
Channel Control Register 3
ADC_CHCTR4 Reset: 00
CE
H
Channel Control Register 4
ADC_CHCTR5 Reset: 00
CF
H
Channel Control Register 5
ADC_CHCTR6 Reset: 00
D2
H
Channel Control Register 6
ADC_CHCTR7 Reset: 00
D3
H
Channel Control Register 7
RMAP = 0, Page 2
Bit Field P7 P6 P5 P4 P3 P2 P1 P0
H
Type rw rw rw rw rw rw rw rw
Bit Field
H
Type r rw rw rw rw rw rw
Bit Field
H
Type rw rw rw r rw rw
Bit Field
H
Type rw rw rw rw rw rw rw rw
Bit Field OP STNR 0 PAGE
H
Type w w r rw
Bit Field ANON DW CTC 0
H
Type rw rw rw r
Bit Field 0 CHNR 0 SAM
H
0 P5 P4 P3 P2 P1 P0
P7 P6 P5 0 P1 P0
P7 P6 P5 P4 P3 P2 P1 P0
PLE
Type r rh r rh rh
Bit Field ASEN1 ASEN0 0 ARBM CSM1 PRIO1 CSM0 PRIO0
H
Type rw rw r rw rw rw rw rw
Bit Field BOUND1 BOUND0
H
Type rw rw
Bit Field STC
H
Type rw
Bit Field SYNEN1SYNEN
H
0
ETRSEL1 ETRSEL0
Type rw rw rw rw
Bit Field
H
Type r rw r rw
Bit Field
H
Type r rw r rw
Bit Field
H
Type r rw r rw
Bit Field
H
Type r rw
Bit Field 0 LCC 0 RESRSEL
H
Type r rw r rw
Bit Field 0 LCC 0 RESRSEL
H
Type r rw r rw
Bit Field 0 LCC 0 RESRSEL
H
Type r rw r rw
Bit Field 0 LCC 0 RESRSEL
H
Type r rw r rw
0 LCC 0 RESRSEL
0 LCC 0 RESRSEL
0 LCC 0 RESRSEL
0 LCC 0 RESRSEL
r rw
BUSY
Data Sheet 26 V1.0, 2006-02
XC866
Functional Description
Table 8 ADC Register Overview (cont’d)
AddrRegister Name Bit 76543210
ADC_RESR0L Reset: 00
CA
H
Result Register 0 Low
ADC_RESR0H Reset: 00
CB
H
Result Register 0 High
ADC_RESR1L Reset: 00
CC
H
Result Register 1 Low
ADC_RESR1H Reset: 00
CD
H
Result Register 1 High
ADC_RESR2L Reset: 00
CE
H
Result Register 2 Low
ADC_RESR2H Reset: 00
CF
H
Result Register 2 High
ADC_RESR3L Reset: 00
D2
H
Result Register 3 Low
ADC_RESR3H Reset: 00
D3
H
Result Register 3 High
RMAP = 0, Page 3
ADC_RESRA0L Reset: 00
CA
H
Result Register 0, View A Low
ADC_RESRA0H Reset: 00
CB
H
Result Register 0, View A High
ADC_RESRA1L Reset: 00
CC
H
Result Register 1, View A Low
ADC_RESRA1H Reset: 00
CD
H
Result Register 1, View A High
ADC_RESRA2L Reset: 00
CE
H
Result Register 2, View A Low
ADC_RESRA2H Reset: 00
CF
H
Result Register 2, View A High
ADC_RESRA3L Reset: 00
D2
H
Result Register 3, View A Low
ADC_RESRA3H Reset: 00
D3
H
Result Register 3, View A High
RMAP = 0, Page 4
ADC_RCR0 Reset: 00
CA
H
Result Control Register 0
ADC_RCR1 Reset: 00
CB
H
Result Control Register 1
ADC_RCR2 Reset: 00
CC
H
Result Control Register 2
ADC_RCR3 Reset: 00
CD
H
Result Control Register 3
ADC_VFCR Reset: 00
CE
H
Valid Flag Clear Register
RMAP = 0, Page 5
Bit Field RESULT[1:0] 0 VF DRC CHNR
H
Type rh r rh rh rh
Bit Field RESULT[9:2]
H
Type rh
Bit Field RESULT[1:0] 0 VF DRC CHNR
H
Type rh r rh rh rh
Bit Field RESULT[9:2]
H
Type rh
Bit Field RESULT[1:0] 0 VF DRC CHNR
H
Type rh r rh rh rh
Bit Field RESULT[9:2]
H
Type rh
Bit Field RESULT[1:0] 0 VF DRC CHNR
H
Type rh r rh rh rh
Bit Field RESULT[9:2]
H
Type rh
Bit Field RESULT[2:0] VF DRC CHNR
H
Type rh rh rh rh
Bit Field RESULT[10:3]
H
Type rh
Bit Field RESULT[2:0] VF DRC CHNR
H
Type rh rh rh rh
Bit Field RESULT[10:3]
H
Type rh
Bit Field RESULT[2:0] VF DRC CHNR
H
Type rh rh rh rh
Bit Field RESULT[10:3]
H
Type rh
Bit Field
H
Type rh rh rh rh
Bit Field
H
Type rh
Bit Field
H
Type rw rw r rw
Bit Field VFCTR WFR 0 IEN 0 DRCT
H
RESULT[2:0] VF DRC CHNR
RESULT[10:3]
VFCTR WFR 0 IEN 0 DRCT
r rw
Type rw rw r rw r rw
Bit Field VFCTR WFR 0 IEN 0 DRCT
H
Type rw rw r rw r rw
Bit Field VFCTR WFR 0 IEN 0 DRCT
H
Type rw rw r rw r rw
Bit Field 0 VFC3 VFC2 VFC1 VFC0
H
Type r w w w w
R
R
R
R
Data Sheet 27 V1.0, 2006-02
XC866
Functional Description
Table 8 ADC Register Overview (cont’d)
AddrRegister Name Bit 76543210
ADC_CHINFR Reset: 00
CA
H
Channel Interrupt Flag Register
ADC_CHINCR Reset: 00
CB
H
Channel Interrupt Clear Register
CCHADC_CHINSR Reset: 00
Channel Interrupt Set Register
ADC_CHINPR Reset: 00
CD
H
Channel Interrupt Node Pointer Register
ADC_EVINFR Reset: 00
CE
H
Event Interrupt Flag Register
CFHADC_EVINCR Reset: 00
Event Interrupt Clear Flag Register
ADC_EVINSR Reset: 00
D2
H
Event Interrupt Set Flag Register
ADC_EVINPR Reset: 00
D3
H
Event Interrupt Node Pointer Register
RMAP = 0, Page 6
CAHADC_CRCR1 Reset: 00
Conversion Request Control Register 1
ADC_CRPR1 Reset: 00
CB
H
Conversion Request Pending Register 1
ADC_CRMR1 Reset: 00
CC
H
Conversion Request Mode Register 1
CDHADC_QMR0 Reset: 00
Queue Mode Register 0
CEHADC_QSR0 Reset: 20
Queue Status Register 0
CFHADC_Q0R0 Reset: 00
Queue 0 Register 0
D2HADC_QBUR0 Reset: 00
Queue Backup Register 0
D2HADC_QINR0 Reset: 00
Queue Input Register 0
Bit Field CHINF7CHINF6CHINF5CHINF4CHINF3CHINF2CHINF1CHINF
H
Type rh rh rh rh rh rh rh rh
Bit Field CHINC7CHINC6CHINC5CHINC4CHINC3CHINC2CHINC1CHINC
H
Type wwwww w w w
Bit Field CHINS7CHINS6CHINS5CHINS4CHINS3CHINS2CHINS1CHINS
H
Type wwwww w w w
Bit Field CHINP7CHINP6CHINP5CHINP4CHINP3CHINP2CHINP1CHINP
H
Type rw rw rw rw rw rw rw rw
Bit Field EVINF7EVINF6EVINF5EVINF
H
4
0 EVINF1EVINF
Type rh rh rh rh r rh rh
Bit Field EVINC7EVINC6EVINC5EVINC
H
4
0 EVINC1EVINC
Type wwww r w w
Bit Field EVINS7EVINS6EVINS5EVINS
H
4
0 EVINS1EVINS
Type wwww r w w
Bit Field EVINP7EVINP6EVINP5EVINP
H
4
0 EVINP1EVINP
Type rw rw rw rw r rw rw
Bit Field CH7 CH6 CH5 CH4 0
H
Type rwhrwhrwhrwh r
Bit Field CHP7 CHP6 CHP5 CHP4 0
H
Type rwhrwhrwhrwh r
Bit Field Rsv LDEV CLR
H
SCAN ENSI ENTR ENGT
PND
Type r w w rw rw rw rw
Bit Field
H
Type wwwwrw rw rw
Bit Field
H
Type r r rh rh r
Bit Field
H
Type rh rh rh rh r rh
Bit Field
H
Type rh rh rh rh r rh
Bit Field EXTR ENSI RF 0 REQCHNR
H
Type www r w
CEV TREV FLUSH CLRV TRMD ENTR ENGT
Rsv 0 EMPTY EV 0
EXTR ENSI RF V 0 REQCHNR
EXTR ENSI RF V 0 REQCHNR
0
0
0
0
0
0
0
0
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 9 Timer 2 Register Overview
AddrRegister Name Bit 76543210
T2_T2CON Reset: 00
C0
H
Timer 2 Control Register
Data Sheet 28 V1.0, 2006-02
Bit Field TF2 EXF2 0 EXEN2 TR2 0 CP/
H
Type rwh rwh r rw rwh r rw
RL2
XC866
Functional Description
Table 9 Timer 2 Register Overview (cont’d)
T2_T2MOD Reset: 00
C1
H
Timer 2 Mode Register
C2HT2_RC2L Reset: 00
Timer 2 Reload/Capture Register Low
C3HT2_RC2H Reset: 00
Timer 2 Reload/Capture Register High
C4HT2_T2L Reset: 00
Timer 2 Register Low
C5HT2_T2H Reset: 00
Timer 2 Register High
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10 CCU6 Register Overview
AddrRegister Name Bit 76543210
RMAP = 0
CCU6_PAGE Reset: 00
A3
H
Page Register for CCU6
RMAP = 0, Page 0
CCU6_CC63SRL Reset: 00
9A
H
Capture/Compare Shadow Regist er for Channel CC63 Low
CCU6_CC63SRH Reset: 00
9B
H
Capture/Compare Shadow Regist er for Channel CC63 High
CCU6_TCTR4L Reset: 00
9C
H
Timer Control Register 4 Low
CCU6_TCTR4H Reset: 00
9D
H
Timer Control Register 4 High
CCU6_MCMOUTSL Reset: 00
9E
H
Multi-Channel Mode Output Shadow Register Low
CCU6_MCMOUTSH Reset: 00
9F
H
Multi-Channel Mode Output Shadow Register High
CCU6_ISRL Reset: 00
A4
H
Capture/Compare Interrupt Stat us Reset Register Low
CCU6_ISRH Reset: 00
A5
H
Capture/Compare Interrupt Stat us Reset Register High
CCU6_CMPMODIFL Reset: 00
A6
H
Compare State Modification Register Low
CCU6_CMPMODIFH Reset: 00
A7
H
Compare State Modification Register High
FA
CCU6_CC60SRL Reset: 00
H
Capture/Compare Shadow Regist er for Channel CC60 Low
Bit Field T2
H
REGST2RHEN
EDGE
PREN T2PRE DCEN
SEL
Type rw rw rw rw rw rw
Bit Field RC2[7:0]
H
Type rwh
Bit Field RC2[15:8]
H
Type rwh
Bit Field THL2[7:0]
H
Type rwh
Bit Field THL2[15:8]
H
Type rwh
Bit Field OP STNR 0 PAGE
H
Type w w r rw
Bit Field CC63SL
H
Type rw
Bit Field CC63SH
H
Type rw
Bit Field T12
H
STD
T12 STR
0 DTRES T12
RES
T12RS T12RR
Type w w r w w w w
Bit Field T13
H
STD
T13 STR
0 T13
RES
T13RS T13RR
Type w w r w w w
Bit Field STRMCM0 MCMPS
H
Type w r rw
Bit Field
H
Type w r rw rw
Bit Field RT12PMRT12OMRCC62FRCC62RRCC61FRCC61RRCC60FRCC60
H
STRHP 0 CURHS EXPHS
Type wwwww w w w
H
Bit Field
RSTR RIDLE RWHE RCHE 0 RTRPF RT13PMRT13
Type wwww r w w w
Bit Field 0 MCC63
H
S
0 MCC62SMCC61SMCC60
Type r w r w w w
Bit Field
H
Type r w r
Bit Field CC60SL
H
0 MCC63
R
0 MCC62RMCC61RMCC60
w w w
Type rwh
R
CM
S
R
Data Sheet 29 V1.0, 2006-02
XC866
Functional Description
Table 10 CCU6 Register Overview (cont’d)
AddrRegister Name Bit 76543210
CCU6_CC60SRH Reset: 00
FB
H
Capture/Compare Shadow Regist er for Channel CC60 High
CCU6_CC61SRL Reset: 00
FC
H
Capture/Compare Shadow Regist er for Channel CC61 Low
FDHCCU6_CC61SRH Reset: 00
Capture/Compare Shadow Regist er for Channel CC61 High
CCU6_CC62SRL Reset: 00
FE
H
Capture/Compare Shadow Regist er for Channel CC62 Low
CCU6_CC62SRH Reset: 00
FF
H
Capture/Compare Shadow Regist er for Channel CC62 High
RMAP = 0, Page 1
CCU6_CC63RL Reset: 00
9A
H
Capture/Compare Register fo r Channel CC63 Low
CCU6_CC63RH Reset: 00
9B
H
Capture/Compare Register fo r Channel CC63 High
CCU6_T12PRL Reset: 00
9C
H
Timer T12 Period Register Low
CCU6_T12PRH Reset: 00
9D
H
Timer T12 Period Register High
CCU6_T13PRL Reset: 00
9E
H
Timer T13 Period Register Low
CCU6_T13PRH Reset: 00
9F
H
Timer T13 Period Register High
CCU6_T12DTCL Reset: 00
A4
H
Dead-Time Control Register for Timer T12 Low
CCU6_T12DTCH Reset: 00
A5
H
Dead-Time Control Register for Timer T12 High
CCU6_TCTR0L Reset: 00
A6
H
Timer Control Register 0 Low
A7HCCU6_TCTR0H Reset: 00
Timer Control Register 0 High
CCU6_CC60RL Reset: 00
FA
H
Capture/Compare Register fo r Channel CC60 Low
CCU6_CC60RH Reset: 00
FB
H
Capture/Compare Register fo r Channel CC60 High
CCU6_CC61RL Reset: 00
FC
H
Capture/Compare Register fo r Channel CC61 Low
Bit Field CC60SH
H
Type rwh
Bit Field CC61SL
H
Type rwh
Bit Field CC61SH
H
Type rwh
Bit Field CC62SL
H
Type rwh
Bit Field CC62SH
H
Type rwh
Bit Field CC63VL
H
Type rh
Bit Field CC63VH
H
Type rh
Bit Field T12PVL
H
Type rwh
Bit Field T12PVH
H
Type rwh
Bit Field T13PVL
H
Type rwh
Bit Field T13PVH
H
Type rwh
Bit Field DTM
H
Type rw
Bit Field
H
Type r rhrhrh
Bit Field CTM CDIR STE12 T12R T12
H
0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0
r rw rw rw
PRE
Type rw rh rh rh rw rw
Bit Field
H
Type r rh rh
Bit Field CC60VL
H
0 STE13 T13R T13
PRE
rw rw
Type rh
Bit Field CC60VH
H
Type rh
Bit Field CC61VL
H
Type rh
T12CLK
T13CLK
Data Sheet 30 V1.0, 2006-02
XC866
Functional Description
Table 10 CCU6 Register Overview (cont’d)
AddrRegister Name Bit 76543210
CCU6_CC61RH Reset: 00
FD
H
Capture/Compare Register fo r Channel CC61 High
CCU6_CC62RL Reset: 00
FE
H
Capture/Compare Register fo r Channel CC62 Low
FFHCCU6_CC62RH Reset: 00
Capture/Compare Register fo r Channel CC62 High
RMAP = 0, Page 2
CCU6_T12MSELL Reset: 00
9A
H
T12 Capture/Compare Mode Select Register Low
CCU6_T12MSELH Reset: 00
9B
H
T12 Capture/Compare Mode Select Register High
CCU6_IENL Reset: 00
9C
H
Capture/Compare Interrupt Enabl e Register Low
CCU6_IENH Reset: 00
9D
H
Capture/Compare Interrupt Enabl e Register High
CCU6_INPL Reset: 40
9E
H
Capture/Compare Interrupt Node Pointer Register Low
9F
CCU6_INPH Reset: 39
H
Capture/Compare Interrupt Node Pointer Register High
CCU6_ISSL Reset: 00
A4
H
Capture/Compare Interrupt Stat us Set Register Low
CCU6_ISSH Reset: 00
A5
H
Capture/Compare Interrupt Stat us Set Register High
A6HCCU6_PSLR Reset: 00
Passive State Level Register
A7HCCU6_MCMCTR Reset: 00
Multi-Channel Mode Control Register
FAHCCU6_TCTR2L Reset: 00
Timer Control Register 2 Low
CCU6_TCTR2H Reset: 00
FB
H
Timer Control Register 2 High
CCU6_MODCTRL Reset: 00
FC
H
Modulation Control Register Low
CCU6_MODCTRH Reset: 00
FD
H
Modulation Control Register High
CCU6_TRPCTRL Reset: 00
FE
H
Trap Control Register Low
Bit Field CC61VH
H
Type rh
Bit Field CC62VL
H
Type rh
Bit Field CC62VH
H
Type rh
Bit Field
H
Type rw
Bit Field DBYP HSYNC MSEL62
H
MSEL61 MSEL60
rw
Type rw rw rw
Bit Field ENT12PMENT12OMENCC
H
62F
ENCC
62R
ENCC
61F
ENCC
61R
ENCC
60F
Type rw rw rw rw rw rw rw rw
Bit Field ENSTR EN
H
IDLEENWHEENCHE
0 EN
TRPF
ENT13PMENT13
Type rw rw rw rw r rw rw rw
Bit Field INPCHE INPCC62 INPCC61 INPCC60
H
Type rw rw rw rw
Bit Field 0 INPT13 INPT12 INPERR
H
Type r rw rw rw
Bit Field ST12PMST12OMSCC62FSCC62RSCC61FSCC61RSCC60FSCC60
H
Type wwwww w w w
Bit Field SSTR SIDLE SWHE SCHE SWHC STRPF ST13PMST13
H
Type wwwww w w w
Bit Field
H
Type rwh r rwh
Bit Field
H
Type r rw r rw
Bit Field
H
Type r rw rw
Bit Field
H
Type r rw rw
Bit Field MC
H
PSL63 0 PSL
0 SWSYN 0 SWSEL
0 T13TED T13TEC T13
0 T13RSEL T12RSEL
0 T12MODEN
MEN
SSC
rw rw
Type rw r rw
Bit Field ECT13O0 T13MODEN
H
Type rw r rw
Bit Field 0 TRPM2 TRPM1 TRPM0
H
Type r rw rw rw
ENCC
60R
CM
R
CM
T12
SSC
Data Sheet 31 V1.0, 2006-02
XC866
Functional Description
Table 10 CCU6 Register Overview (cont’d)
AddrRegister Name Bit 76543210
CCU6_TRPCTRH Reset: 00
FF
H
Trap Control Register High
RMAP = 0, Page 3
CCU6_MCMOUTL Reset: 00
9A
H
Multi-Channel Mode Output Register Low
CCU6_MCMOUTH Reset: 00
9B
H
Multi-Channel Mode Output Register High
CCU6_ISL Reset: 00
9C
H
Capture/Compare Interrupt Stat us Register Low
CCU6_ISH Reset: 00
9D
H
Capture/Compare Interrupt Stat us Register High
CCU6_PISEL0L Reset: 00
9E
H
Port Input Select Register 0 Low
9F
CCU6_PISEL0H Reset: 00
H
Port Input Select Register 0 High
CCU6_PISEL2 Reset: 00
A4
H
Port Input Select Register 2
CCU6_T12L Reset: 00
FA
H
Timer T12 Counter Register Low
CCU6_T12H Reset: 00
FB
H
Timer T12 Counter Register High
CCU6_T13L Reset: 00
FC
H
Timer T13 Counter Register Low
CCU6_T13H Reset: 00
FD
H
Timer T13 Counter Register High
CCU6_CMPSTATL Reset: 00
FE
H
Compare State Register Low
CCU6_CMPSTATH Reset: 00
FF
H
Compare State Register High
Bit Field TRPPENTRPEN
H
13
TRPEN
Type rw rw rw
Bit Field 0 R MCMP
H
Type r rh rh
Bit Field
H
Type r rh
Bit Field
H
Type rh rh rh rh
Bit Field STR ID LE WHE CHE TRPS TRPF T13PM T13CM
H
0 CURH EXPH
rh
T12PM T12OM ICC62 F ICC62RICC61F ICC61RICC60F ICC60
rh rh rh rh
Type rh rh rh rh rh rh rh rh
Bit Field ISTRP ISCC62 ISCC61 ISCC60
H
Type rw rw rw rw
Bit Field IST12HR ISPOS2 ISPOS1 ISPOS0
H
Type rw rw rw rw
Bit Field 0 IST13HR
H
Type r rw
Bit Field T12CVL
H
Type rwh
Bit Field T12CVH
H
Type rwh
Bit Field T13CVL
H
Type rwh
Bit Field T13CVH
H
Type rwh
Bit Field
H
Type r rhrhrh
Bit Field T13IM COUT
H
0 CC63STCCPOS2CCPOS1CCPOS0CC62STCC61STCC60
rh rh rh rh
COUT
63PS
62PS
CC62PSCOUT
61PS
CC61PSCOUT
60PS
Type rwhrwhrwhrwhrwh rwh rwh rwh
R
ST
CC60
PS
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11 SSC Register Overview
AddrRegister Name Bit 76543210
RMAP = 0
SSC_PISEL Reset: 00
A9
H
Port Input Select Register
SSC_CONL Reset: 00
AA
H
Control Register Low
Programming Mode
Operating Mode Bit Field 0 BC
Data Sheet 32 V1.0, 2006-02
Bit Field 0 CIS SIS MIS
H
Type r rw rw rw
Bit Field LB PO PH HB BM
H
Type rw rw rw rw rw
Type r rh
XC866
Functional Description
Table 11 SSC Register Overview
SSC_CONH Reset: 00
AB
H
Control Register High
Programming Mode
Operating Mode Bit Field EN MS 0 BSY BE PE RE TE
ACHSSC_TBL Reset: 00
Transmitter Buffer Register Low
ADHSSC_RBL Reset: 00
Receiver Buffer Register Low
AEHSSC_BRL Reset: 00
Baudrate Timer Reload Register Low
AFHSSC_BRH Reset: 00
Baudrate Timer Reload Register High
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 12 OCDS Register Overview
AddrRegister Name Bit 76543210
RMAP = 1
MMCR2 Reset: 0U
E9
H
Monitor Mode Control Register 2
MMCR Reset: 00
F1
H
Monitor Mode Control Register
F2
MMSR Reset: 00
H
Monitor Mode Status Register
MMBPCR Reset: 00
F3
H
BreakPoints Control Register
MMICR Reset: 00
F4
H
Monitor Mode Interrupt Control Register
F5
MMDR Reset: 00
H
Monitor Mode Data Register
Receive
Transmit Bit Field
HWBPSR Reset: 00
F6
H
Hardware Breakpoints Select Register
HWBPDR Reset: 00
F7
H
Hardware Breakpoints Data Register
Bit Field EN MS 0 AREN BEN PEN REN TEN
H
Type rw rw r rw rw rw rw rw
Type rw rw r rh rwh rwh rwh rwh
Bit Field TB_VALUE
H
Type rw
Bit Field RB_VALUE
H
Type rh
Bit Field BR_VALUE[7:0]
H
Type rw
Bit Field BR_VAL UE[15:8]
H
Type rw
Bit Field EXBC_PEXBC MBCO
H
MBCONMMEP_PMMEP MMODEJENA
N_P
Type w rw w rwh w rwh rh rh
Bit Field MEXIT_PMEXIT MSTEP_PMSTEP MRAM
H
MRAMSTRF RRF
S_P
Type w rwh w rw w rwh rh rh
Bit Field MBCAMMBCIN EXBF SWBF HWB3FHWB2FHWB1FHWB0
H
Type rw rh rwh rwh rw h rwh rwh rwh
Bit Field SWBC HWB3C HWB2C HWB1CHWB0C
H
Type rw rw rw rw rw
Bit Field DVECT DRETR 0 MMUIE_PMMUIE RRIE_PRRIE
H
Type rwh rwh r w rw w rw
H
Bit Field
MMRR
Type rh
MMTR
Type w
H
Bit Field
0 BPSEL
Type r w
Bit Field HWBPxx
H
Type rw
_P
BPSEL
rw
F
Data Sheet 33 V1.0, 2006-02
XC866
Functional Description
3.3 Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently.
Features:
• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
• 32-byte minimum program width
• 1-sector minimum erase width
• 1-byte read access
• 121.6 ns minimum read access time (3 × t
• Operating supply voltage: 2.5 V ± 7.5 %
• Program time: 2.3 ms
• Erase time: 120 ms
3)
3)
1)
CCLK
@ f
=26.7MHz±7.5%2))
CCLK
Table 13 Flash Data Retention and Endurance Targets
Retention up to Endurance up to Programming
Size
Temperature
20 years
5 years
2 years
2 years
1)
2)
3)
4)
5)
4)
4)
4)
4)
P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. f
=80MHz±7.5% (f
sys
f
= 80 MHz ± 7.5% is the only frequency range for Flash programming and erasing. f
sys
obtaining the worst case timing. Specification with 0.2ppm error rate. One cycle refers to the programming of all wordlines in a sector and erasing of the sector.
1,000 cycles
10,000 cycles
70,000 cycles
100,000 cycles
= 26.7 MHz ± 7.5 %) is the maximum frequency range for Flash read access.
CCLK
Data Sheet 34 V1.0, 2006-02
5)
5)
5)
5)
0 – 100°C 15 Kbytes
-40 – 125°C 896 bytes
-40 – 125°C 512 bytes
-40 – 125°C 128 bytes
sysmin
is used for
XC866
Functional Description
3.3.1 Flash Bank Sectorization
The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of embedded Flash memory. These Flash memory sizes are made up of two or four 4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in Figure 10. Both types can be used for code and data storage. The label “Data” neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. The XC866 ROM devices offer a single 4-Kbyte D-Flash bank.
Sec tor 2: 128-by te Sec tor 1: 128-by te
Sect or 0: 3.75-Kbyte
P-Flash D-Flash
Sector 9: 128-byte Sector 8: 128-byte Sector 7: 128-byte Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 2: 512-byte
Sect or 1: 1-Kby te
Sect or 0: 1-Kby te
Figure 10 Flash Bank Sectorization
The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet 35 V1.0, 2006-02
XC866
Functional Description
3.3.2 Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 11).
0000 ….. 0000
0000 ….. 0000
1111 ….. 0000
32 bytes (1 WL)
0000 ….. 0000
H
1111 ….. 1111
H
1111 ….. 1111
H
Progr am 1
H
Progr am 2
H
H
16 bytes 16 bytes
0000 ….. 0000
1111 ….. 0000
Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0.
H
H
1111 ….. 1111
0000 ….. 0000
H
H
Flash memory cells 32-byte write buffers
Figure 11 D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent “over-programming”.
Data Sheet 36 V1.0, 2006-02
XC866
Functional Description
3.4 Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC866 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source.
3.4.1 Interrupt Source
Figure 12 to Figure 16 give a general overview of the interrupt sources and illustrates
the request and control flags.
WDT O verflow
PLL Loss of Lock
Flash O peration
Complete
VDD Pr e-Warning
VDDP P re-Warning FNMIVDDP
Flash E CC Error
FNMIWDT
NMIISR.0
FNMIPLL
NMIISR.1
FNMIFLASH
NMIISR.2
FNMIVDD
NMIISR.4
NMIISR.5
FNMIECC
NMIISR.6
NMIWDT
NMICON.0
NMIPLL
NMICON.1
NMIFLASH
NMIVDD
NMICON.4
NMIVDDP
NMICON.5
NMIECC
NMICON.6
Figure 12 Non-Maskable Interrupt Request Sources
>=1
0073
Non
Maskab le
H
Interrupt
Data Sheet 37 V1.0, 2006-02
XC866
Functional Description
Highest
EINT0
EINT1
Timer 0
Overflow
Timer 1
Overflow
UART
EXINT0
EXICON0.0/1
EXINT 1
EXICON0.2/3
EXINT0
IRCON0.0
EXINT1
IRCON0.1
Bit-addressable
RI
SCON.0
TI
SCON.1
IT0
TCON.0
IT1
TCON.2
TF0
TCON.5
TF1
TCON.7
>=1
IE0
TCON.1
IE1
TCON.3
ET0
IEN0.1
ET1
IEN0.3
ES
IEN0.4
EX0
IEN0.0
EX1
IEN0.2
000B
001B
0023
0003
0013
EA
IEN 0.7
Lowest
H
IP.1/
IPH.1
H
IP.3/
IPH.3
Priority Level
P o l l i n g
H
IP.4/
IPH.4
S e q u e n c e
H
IP.0/
IPH.0
H
IP.2/
IPH.2
Request flag is cleared by hardware
Figure 13 Interrupt Request Sources (Part 1)
Data Sheet 38 V1.0, 2006-02
XC866
Functional Description
Timer 2
Overflow
T2EX
EXEN2
EDGES
EL
T2MOD.5
End of
Syn Byte
Syn Byte Error
EINT2
EINT3
EINT4
EINT5
EINT6
T2CON.3
Normal Divider
Overfl ow
EOFSYN
FDCON.4
ERRSYN
FDCON.5
EXINT3
EXICON0.6/7
EXINT4
EXICON1.0/1
EXINT5
EXICON1.2/3
EXINT6
EXICON1.4/5
EXINT2
EXICON0.4/5
Bit-addressable
Request flag is cleared by hardware
TF2
T2CON.7
EXF2
T2CON.6
NDOV
FDCON.2
SYNEN
FDCON.6
EXINT3
IRCON0.3
EXINT4
IRCON0.4
EXINT5
IRCON0.5
EXINT6
IRCON0.6
>=1
EXINT2
IRCON0.2
>=1
002B
ET2
IEN0.5
EX2
IEN1.2
EXM
IEN1.3
0043
004B
H
IP.5/
IPH.5
H
IP1.2/
IPH1.2
H
IP1.3/
IPH1.3
EA
IEN0 .7
Bit-addressable
Request flag is cleared by hardware
Highest
Lowest
Priority Level
P o l l i n g
S e q u e n c e
Figure 14 Interrupt Request Sources (Part 2)
Data Sheet 39 V1.0, 2006-02
ADC_SRC0
ADC_SRC1
ADCSRC0
IRCON1.3
ADCSRC1
IRCON1.4
>=1
EADC
IEN1.0
0033
Functional Description
H
IP1. 0/
IPH1.0
XC866
Highest
Lowest
Priority Level
SSC_EIR
SSC_TIR
SSC_RIR
Captu re/C ompare
interrupt node 0
Captu re/C ompare
interrupt node 1
Captu re/C ompare
interrupt node 2
Captu re/C ompare
interrupt node 3
Bit-addressable
Request flag is cleared by hardware
EIR
IRCON1.0
IRCON1.1
RIR
IRCON1.2
>=1TIR
ESSC
IEN1.1
003B
H
IP1. 1/
IPH1.1
P o l l i n g
ECCIP0
IEN1.4
ECCIP1
IEN1.5
ECCIP2
IEN1.6
ECCIP3
IEN1.7
005B
0063
006B
H
IP1. 4/
IPH1.4
H
IP1. 5/
IPH1.5
H
IP1. 6/
IPH1.6
H
IP1.7/
IPH1.7
S e q u e n c e
0053
EA IEN0.7
Figure 15 Interrupt Request Sources (Part 3)
Data Sheet 40 V1.0, 2006-02
0 1
2
3
CC60
CC61
CC62
T12 One matc h
T12 Period match
T13 Compare mat ch
T13 Period match
CTRAP
Wrong Hal l Event
Correct Hall Event
Multi -Channel Shadow Transfer
ICC60R
ISL.0
ICC 60F
ISL.1
ICC61R
ISL.2
ICC 61F
ISL.3
ICC62R
ISL.4
ICC 62F
ISL.5
T12OM
ISL.6
T12PM
ISL.7
T13CM
ISH.0
T13PM
ISH.1
TRPF
ISH.2
WHE
ISH.5
CHE
ISH.4
STR
ISH.7
ENCC60R
IENL.0
ENC C60F
IENL.1
ENCC61R
IENL.2
ENC C61F
IENL.3
ENCC62R
IENL.4
ENC C62F
IENL.5
ENT 12OM
IENL.6
ENT 12PM
IENL.7
ENT 13CM
IENH.0
ENT 13PM
IENH.1
ENTRPF
IENH.2
ENWHE
IENH.5
ENCHE
IENH.4
ENSTR
IENH.7
XC866
Functional Description
>=1
INPL.1 INPL.0
>=1
INPL.3 INPL.2
>=1
INPL.5 INPL.4
>=1
INPH.3 INPH.2
>=1
INPH.5 INPH.4
>=1
INPH.1 INPH.0
>=1
INPL.7 INPL.6
CCU6 Interrupt node CCU6 Interrupt node
CCU6 Interrupt node
CCU6 Interrupt node
Figure 16 Interrupt Request Sources (Part 4)
Data Sheet 41 V1.0, 2006-02
XC866
Functional Description
3.4.2 Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC866 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 14.
Table 14 Interrupt Vector Addresses
Interrupt Source
Vector Address
NMI 0073
XINTR0 0003
XINTR1 000B
XINTR2 0013
XINTR3 001B
XINTR4 0023
XINTR5 002B
Assignment for XC866 Enable Bit SFR
H
Watchdog Timer NMI NMIWDT NMICON
PLL NMI NMIPLL
Flash NMI NMIFLASH
VDDC Prewarning NMI NMIVDD
VDDP Prewarning NMI NMIVDDP
Flash ECC NMI NMIECC
H
H
H
H
H
H
External Interrupt 0 EX0 IEN0
Timer 0 ET0
External Interrupt 1 EX1
Timer 1 ET1
UART ES
T2 ET2
Fractional Divider (Normal Divider Overflow)
LIN
Data Sheet 42 V1.0, 2006-02
Table 14 Interrupt Vector Addresses (cont’d)
XC866
Functional Description
XINTR6 0033
XINTR7 003B
XINTR8 0043
XINTR9 004B
XINTR10 0053
XINTR11 005B
XINTR12 0063
XINTR13 006B
H
H
H
H
ADC EADC IEN1
SSC ESSC
External Interrupt 2 EX2
External Interrupt 3 EXM
External Interrupt 4
External Interrupt 5
External Interrupt 6
H
H
H
H
CCU6 INP0 ECCIP0
CCU6 INP1 ECCIP1
CCU6 INP2 ECCIP2
CCU6 INP3 ECCIP3
Data Sheet 43 V1.0, 2006-02
XC866
Functional Description
3.4.3 Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 15.
Table 15 Priority Structure within Interrupt Level
Source Level
Non-Maskable Interrupt (NMI) (highest)
External Interrupt 0 1
Timer 0 Interrupt 2
External Interrupt 1 3
Timer 1 Interrupt 4
UART Interrupt 5
Timer 2,Fractional Divider, LIN Interrupts 6
ADC Interrupt 7
SSC Interrupt 8
External Interrupt 2 9
External Interrupt [6:3] 10
CCU6 Interrupt Node Pointer 0 11
CCU6 Interrupt Node Pointer 1 12
CCU6 Interrupt Node Pointer 2 13
CCU6 Interrupt Node Pointer 3 14
Data Sheet 44 V1.0, 2006-02
XC866
Functional Description
3.5 Parallel Ports
The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC).
Bidirectional Port Features:
• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital inputs and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals
Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module
Data Sheet 45 V1.0, 2006-02
XC866
Functional Description
Internal Bus
AltDat aOut 3 AltDat aOut 2 AltDat aOut1
AltDat aIn
Px_PUD SEL
Pull-up /Pull- down
Select Reg ister
Px_PUDEN
Pull-up /Pull-down Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_AL TSEL0
Alter nate Sele ct
Register 0
Px_AL TSEL1
Alter nate Sele ct
Register 1
Px_Dat a
Data Register
VDDP
Pull
enable
Up
Device
11
10
01
00
Out
In
enable
enable
Schmit t T rigger
Output
Driver
Input Driver
enable
Pull
Down
Device
Pin
Pad
Figure 17 General Structure of Bidirectional Port
Data Sheet 46 V1.0, 2006-02
XC866
Functional Description
Internal Bus
AltDataIn
AnalogIn
Px_PUDSEL
Pull- up/Pul l-down Select Regist er
Px_PUDEN
Pull- up/Pul l-down Enable Regi st er
Px_DIR
Dir ect ion Regist er
Px _ DATA
Data Regis ter
In
enable
Schmitt Trigger
Figure 18 General Structure of Input Port
Input
Dri ve r
enable
enable
VDDP
Pull
Up
Device
Pull
Down
Device
Pin
Pad
Data Sheet 47 V1.0, 2006-02
XC866
Functional Description
3.6 Power Supply System with Embedded Voltage Regulator
The XC866 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 19 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
V
(2.5V)
DDC
FLASH
PLL
XTAL1&
GPIO Ports
(P0-P 3)
EVR
V
DDP
V
SSP
XTAL2
(3.3V/5.0V)
Figure 19 XC866 Power Supply System
EVR Features:
• Input voltage (V
• Output voltage (V
): 3.3 V/5.0 V
DDP
): 2.5 V ± 7.5%
DDC
• Low power voltage regulator provided in power-down mode
V
V
and V
DDC
DDC
DDP
brownout detection
prewarning detection
Data Sheet 48 V1.0, 2006-02
XC866
Functional Description
3.7 Reset Control
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see Table 17) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted until V
reaches 0.9*V
DDC
capacitor at RESET pin. This capacitor value must be selected so that V
0.4 V, but not before V
A typical application example is shown in Figure 20. For a voltage regulator with IDD = 100 mA, the V
DDP
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for V reaches 2.3V. Hence, based on the condition that 10% to 90% V than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 21.
. The delay of external reset can be realized by an external
DDC
reaches 0.9* V
DDC
capacitor value is 10 µF. V
DDC
DDC.
to reach 0.9*V
capacitor value is 220 nF. The
DDC
is less than 50 µs once V
DDC
(slew rate) is less
DDP
RESET
reaches
max
DDP
Vin
typ.
100nF
VR
3.3V/5V
e.g. 100mA
VSSP VDDP
RESET
/
e.g. 10uF
220nF
VDDC VSSC
EVR
30k
XC866
Figure 20 Reset Circuitry
Data Sheet 49 V1.0, 2006-02
XC866
h
Functional Description
Voltage
5V
VDDP
2.5V
2.3V
0.9*VDDC
Voltage
5V
< 0.4V
0V
Figure 21 V
ty p. < 50 us
DDP, VDDC
and V
during Power-on Reset
RESET
VDDC
Time
RESET wit
capac itor
Time
The second type of reset in XC866 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin
is provided for the hardware reset.
RESET
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode.
Data Sheet 50 V1.0, 2006-02
XC866
Functional Description
3.7.1 Module Reset Behavior
Table 16 shows how the functions of the XC866 are affected by the various reset types.
A “ ” means that this function is reset to its default state.
Table 16 Effect of Reset on Device Functions
Module/ Function
CPU Core
Peripherals
On-Chip Static RAM
Oscillator, PLL
Port Pins
EVR The voltage
FLASH
NMI Disabled Disabled
Wake-Up Reset
Not affected,
reliable
regulator is
switched on
Watchdog Reset
Not affected,
reliable
Not affected
Not affected
Hardware Reset
Not affected,
reliable
Power-On Reset
Affected, un-
reliable
Brownout Reset
Affected, un-
reliable
3.7.2 Booting Scheme
When the XC866 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 17 shows the available boot options in the XC866.
Table 17 XC866 Boot Selection
MBC TMS P0.0 Type of Mode PC Start Value
1 0 x User Mode; on-chip OSC/PLL non-bypassed 0000
0 0 x BSL Mode; on-chip OSC/PLL non-bypassed 0000
0 1 0 OCDS Mode; on-chip OSC/PLL non-
bypassed
1 1 0 Standalone User (JTAG) Mode1); on-chip
OSC/PLL non-bypassed (normal)
1)
Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet 51 V1.0, 2006-02
0000
0000
H
H
H
H
XC866
Functional Description
3.8 Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC866. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state.
Features:
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL.In the XC866, the oscillator can be from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator (3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down.
OSC
fosc
P:1
OSCDISC
fp
fn
osc fail
detec t
lock
detec t
PLL
core
N:1
NDIV
fvco
K:1
PLLBYP
VCOBYP
OSCR
LOCK
fsys
Figure 22 CGU Block Diagram
Data Sheet 52 V1.0, 2006-02
XC866
Functional Description
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external clock source. For the XC866, the PLL bypass cannot be set active. Hence, the direct drive mode is not available for use.
f
=
SYSfOSC
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor. Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
×=
--- -
×=
K
1
-------------
PK×
f
SYSfVCObase
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided by the P and K factors.
f
SYSfOSC
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for this PLL mode. The PLL mode is used during normal system operation. .
N
-------------
f
SYSfOSC
×=
PK×
System Frequency Selection
For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to obtain the required system frequency, f for different oscillator inputs. Table 18 provides examples on how f
, the value of N can be selected by bit NDIV
sys
= 80 MHz can be
sys
obtained for the different oscillator sources.
Table 18 System frequency (f
=80MHz)
sys
Oscillator fosc N P K fsys
On-chip 10 MHz 16 1 2 80 MHz
Data Sheet 53 V1.0, 2006-02
XC866
Functional Description
Table 18 System frequency (f
=80MHz)
sys
Oscillator fosc N P K fsys
External 10 MHz 16 1 2 80 MHz
8 MHz 20 1 2 80 MHz
5 MHz 32 1 2 80 MHz
Table 19 shows the VCO range for the XC866.
Table 19 VCO Range
f
VCOmin
f
VCOmax
f
VCOFREEmin
f
VCOFREEmax
Unit
150 200 20 80 MHz
100 150 10 80 MHz
3.8.1 Resonator Circuitry
Figure 23 shows the recommended ceramic resonator circuitry. When using an external
resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists of two load capacitances C
and C2, and in some cases, a feedback (Rf) and/or damp
1
(Rd) resistor might be necessary.
C
1
XTAL1
Ceramic
Resonator
C
2
R
f
R
d
XC866
XTAL2
Figure 23 External Ceramic Resonator Circuitry
Note: The manufacturer of the ceramic resonator should check the resonator circuitry
and make recommendations for the C1, C2, Rf and Rd values to be used for stable start-up behavior.
Data Sheet 54 V1.0, 2006-02
XC866
Functional Description
3.8.2 Clock Management
The CGU generates all clock signals required within the microcontroller from a single clock, f modules are as follow:
• CPU clock: CCLK, SCLK = 26.7 MHz
• CCU6 clock: FCLK = 26.7 MHz
• Other peripherals: PCLK = 26.7 MHz
• Flash Interface clock: CCLK3 = 80 MHz and CCLK = 26.7 MHz
In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the resulting output frequency has 50% duty cycle. Figure 24 shows the clock distribution of the XC866.
. During normal system operation, the typical frequencies of the different
sys
CLKREL
OSC
fosc
PLL
N,P,K
fsys
Figure 24 Clock Generation from f
COREL
sys
/3
TLEN
Toggl e
Latch
CCLK3
FCLK
PCLK
SCLK
CCLK
CCU6
Peripherals
CORE
FLASH
Interface
COUTS
CLKOUT
Data Sheet 55 V1.0, 2006-02
XC866
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 20.
Table 20 System frequency (f
Power Saving Mode Action
Idle Clock to the CPU is disabled.
Slow-down Clocks to the CPU and all the peripherals, including CCU6, are
divided by a common programmable factor defined by bit field CMCON.CLKREL.
Power-down Oscillator and PLL are switched off.
=80MHz)
sys
Data Sheet 56 V1.0, 2006-02
XC866
Functional Description
3.9 Power Saving Modes
The power saving modes of the XC866 provide flexible power consumption through a combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 25) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
any interrupt
& SD=0
set IDLE
bit
IDLE
set IDLE
bit
any interrupt
& SD=1
ACTIVE
set SD
bit
SLOW-DOWN
clear SD
bit
EXINT0/RXD pin
& SD=0
set PD
bit
POWER-DOWN
set PD
bit
EXINT0/RXD pin
& SD=1
Figure 25 Transition between Power Saving Modes
Data Sheet 57 V1.0, 2006-02
XC866
T
Functional Description
3.10 Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC866 will be aborted in a user-specified time period. In debug mode, the WDT is suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
PCLK
/2 or f
• Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed)
PCLK
/128
The WDT is a 16-bit timer incremented by a count rate of f
PCLK
/2 or f
PCLK
/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 26 shows the block diagram of the WDT unit.
ENW DT
ENW DT_P
WDT
Control
1:2
MUX
f
PCLK
Logic
1:128
WDTIN
Clear
WDT Low By te
Overflow/Tim e-out C ontrol &
Window-boundary cont rol
WDTREL
WDT Hi gh Byte
WDTTO
WDTRS
WDT WIN B
Figure 26 WDT Block Diagram
Data Sheet 58 V1.0, 2006-02
XC866
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30H count, after which the system is reset (assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during the WDT’s count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000
.
00
H
After being serviced, the WDT continues counting up from the value (<WDTREL> * 2 The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected to be either f
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
to the value obtained from the concatenation of WDTWINB and
H
PCLK
/2 or f
PCLK
/128
8
).
The period, P
, between servicing the WDT and the next overflow can be determined
WDT
by the following formula:
1WDTIN+ 6×()
P
WDT
2
----------------------------------------------------------------------------------------------------- -=
If the Window-Boundary Refresh feature of the WDT is enabled, the period P
2
f
PCLK
16
WDTREL 2
×()×
8
WDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 27. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not be smaller than WDTREL.
Count
FFFF
H
WDTWINB
WDTREL
No refresh
allowed
Refresh allowed
time
Figure 27 WDT Timing Diagram
Data Sheet 59 V1.0, 2006-02
XC866
Functional Description
Table 21 lists the possible watchdog time range that can be achieved for different
module clock frequencies . Some numbers are rounded to 3 significant digits.
Table 21 Watchdog Time Ranges
Reload value in WDTREL
FF
H
7F
H
00
H
Prescaler for f
PCLK
2 (WDTIN = 0) 128 (WDTIN = 1)
26.7 MHz 26.7 MHz
19.2 µs1.23 ms
2.48 ms 159 ms
4.92 ms 315 ms
Data Sheet 60 V1.0, 2006-02
XC866
Functional Description
3.11 Universal Asynchronous Receiver/Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost.
Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first – fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART can operate in four asynchronous modes as shown in Table 22. Data is transmitted on TXD and received on RXD.
Table 22 UART Modes
Operating Mode Baud Rate
Mode 0: 8-bit shift register f
Mode 1: 8-bit shift UART Variable
Mode 2: 9-bit shift UART f
Mode 3: 9-bit shift UART Variable
PCLK
PCLK
/2
/32 or f
PCLK
/64
There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
/2. In mode 2, the baud rate is generated internally based on the UART input clock
f
PCLK
and can be configured to either f
PCLK
/32 or f
/64. The variable baud rate is set by
PCLK
either the underflow rate on the dedicated baud-rate generator, or by the overflow rate on Timer 1.
Data Sheet 61 V1.0, 2006-02
XC866
Functional Description
3.11.1 Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock f
Frac t ional Di vi der
FDM
, see Figure 28.
PCLK
FDST EP
1
01
8-Bit Rel oad Value
FDEN&FDM
Adder
FDEN
Prescaler
f
DIV
clk
f
PCL K
FDRES
f
MOD
f
DIV
0 (overf low)
‘0’
00
01
11
10
11
10
01
00
0 1
R
8-Bit B aud Rat e Timer
NDOV
f
BR
Figure 28 Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (f output of the prescaler (f
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
MOD
) if the fractional divider is disabled (FDEN = 0). For baud rate
DIV
generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (f
• Input clock f
• Prescaling factor (2
) value is dependent on the following parameters:
BR
PCLK
BRPRE
) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider mode)
Data Sheet 62 V1.0, 2006-02
XC866
Functional Description
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider respectively:
baud rate
f
-----------------------------------------------------------------------------------
BRPRE
16 2
PCLK
BR_VALUE 1+()××
where 2
BRPRE
BR_VALUE 1+()1>×=
f
baud rate
-----------------------------------------------------------------------------------
BRPRE
16 2
PCLK
BR_VALUE 1+()××
The maximum baud rate that can be generated is limited to f
STEP
-------------- -
×=
256
/32. Hence, for a module
PCLK
clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for greater accuracy.
Table 23 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
26.7 MHz is used.
Table 23 Typical Baud rates for UART with Fractional Divider disabled
Baud rate Prescaling Factor
19.2 kBaud 1 (BRPRE=000
9600 Baud 1 (BRPRE=000
4800 Baud 2 (BRPRE=001
2400 Baud 4 (BRPRE=010
BRPRE
(2
)
) 87 (57H) -0.22 %
B
)174 (AEH) -0.22 %
B
)174 (AEH) -0.22 %
B
)174 (AEH) -0.22 %
B
Reload Value (BR_VALUE + 1)
Deviation Error
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 24 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet 63 V1.0, 2006-02
Functional Description
Table 24 Deviation Error for UART with Fractional Divider enabled
XC866
Prescaling Factor
f
PCLK
(2
BRPRE
)
Reload Value (BR_VALUE + 1)
26.67 MHz 1 10 (A
13.33 MHz 1 7 (7
6.67 MHz 1 3 (3
STEP Deviation
Error
) 177 (B1H) +0.03 %
H
)248 (F8
H
)212 (D4
H
) +0.11 %
H
) -0.16 %
H
Data Sheet 64 V1.0, 2006-02
XC866
Functional Description
3.11.2 Baud Rate Generation using Timer 1
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows:
[3.1]
SMOD
Mode 1, 3 baud rate
---------------------------------------------------- -=
32 2 256 TH1()××
2
×
f
PCLK
3.12 Normal Divider Mode (8-bit Auto-reload Timer)
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 28). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
f
an output clock
that is 1/n of the input clock f
MOD
The output frequency in normal divider mode is derived as follows:
f
MODfDIV
, where n is defined by 256 - STEP.
DIV
1
----------------------------- -
×=
256 STEP
[3.2]
Data Sheet 65 V1.0, 2006-02
XC866
Functional Description
3.13 LIN Protocol
The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception.
LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multiple­slave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 29. The frame consists of the:
• header, which comprises a Break (13-bit time low), Synch Byte (55
• response time
• data bytes (according to UART protocol)
• checksum
Frame slot
Frame
), and ID field
H
Inter-
frame
space
Header
Synch
Response
Protected
identifier
space
Data 1
Response
Data 2 Data N
Checksum
Figure 29 Structure of LIN Frame
3.13.1 LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
Data Sheet 66 V1.0, 2006-02
XC866
Functional Description
The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet 67 V1.0, 2006-02
XC866
Functional Description
3.14 High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error)
Data Sheet 68 V1.0, 2006-02
XC866
Functional Description
Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered.
Figure 30 shows the block diagram of the SSC.
PCLK
Baud-rate Generator
SSC Control Bloc k
Register CON
16-Bit Shift
Register
Trans mit B uffer
Register TB
Internal Bus
Figure 30 SSC Block Diagram
Clock
Control
Shift Clock
ControlStatus
Receiv e Buffer
Register RB
RIR
TIR
EIR
Recei ve Int. Request
Trans mit Int. Request
Error Int. Request
Pin
Control
SS_CLK MS_CLK
TXD(Ma s ter)
RXD(Slave)
TXD(Slav e)
RXD(Mast er)
Data Sheet 69 V1.0, 2006-02
XC866
Functional Description
3.15 Timer 0 and Timer 1
Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be configured in four different operating modes for use in a variety of applications, see
Table 25. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their
functions are specialized.
Table 25 Timer 0 and Timer 1 Modes
Mode Operation
0 13-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices.
1 16-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit counter.
2 8-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow.
3 Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled.
Data Sheet 70 V1.0, 2006-02
XC866
Functional Description
3.16 Timer 2
Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as long as it is enabled.
Table 26 Timer 2 Modes
Mode Description
Auto-reload Up/Down Count Disabled
• Count up only
Channel capture
• Start counting from 16-bit reload value, overflow at FFFF
• Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up – Start counting from 16-bit reload value, overflow at FFFF – Reload event triggered by overflow condition – Programmble reload value in register RC2
• Count down – Start counting from FFFF
, underflow at value defined in register
H
RC2 – Reload event triggered by underflow condition – Reload value fixed at FFFF
H
• Count up only
• Start counting from 0000
, overflow at FFFF
H
H
• Reload event triggered by overflow condition
• Reload value fixed at 0000
H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event
H
H
Data Sheet 71 V1.0, 2006-02
XC866
Functional Description
3.17 Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode
Additional Features:
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage
Data Sheet 72 V1.0, 2006-02
)
The block diagram of the CCU6 module is shown in Figure 31.
module kernel
address decoder
T12
channel 0
channel 1
compare
1
dead-
time
1
cont rol
clock
control
interrupt
control
channel 2
sta rt
channel 3T13
compare
T13HR
T12HR
CO UT6 3
CO UT6 0
1
capture
com par e
3
input / output control
CO UT6 2
CC 61
CO UT6 1
CC 60
com par e
com par e
2221
CC 62
CC POS 0
XC866
Functional Description
multi-
channel
control
Hall input
output select
CC POS 1
3
CC POS 2
trap
control
output select
CT RAP
trap input
1
port control
CCU6_bl ock_diagram
Figure 31 CCU6 Block Diagram
Data Sheet 73 V1.0, 2006-02
XC866
Functional Description
3.18 Analog-to-Digital Converter
The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at Port 2.
Features:
• Successive approximation
• 8-bit or 10-bit resolution (TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access (wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter (accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
Data Sheet 74 V1.0, 2006-02
XC866
÷
÷
÷
÷
Functional Description
3.18.1 ADC Clocking Scheme
A common module clock f and digital parts of the ADC module:
•f
•f
is input clock for the analog part.
ADCA
is internal clock for the analog part (defines the time base for conversion length
ADCI
and the sample time). This clock is generated internally in the analog part, based on the input clock f
•f
is input clock for the digital part.
ADCD
ADCA
The internal clock for the analog part f Therefore, the ADC clock prescaler must be programmed to a value that ensures f does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required.
generates the various clock signals used by the analog
ADC
to generate a correct duty cycle for the analog components.
is limited to a maximum frequency of 10 MHz.
ADCI
ADCI
f
= f
ADC
PCLK
f
ADCA
clock prescaler
Condition: f
Figure 32 ADC Clocking Scheme
32
4
3
2
ADCI
f
ADCD
CTC
MUX
arbi ter
regi ster s
interrupts
f
ADCI
10 MHz, where t
anal og
component s
digital part
analog part
ADCI =
f
1
ADCI
Data Sheet 75 V1.0, 2006-02
XC866
Functional Description
For module clock f
= 26.7 MHz, the analog clock f
ADC
frequency can be selected as
ADCI
shown in Table 27.
Table 27 f
Module Clock f
26.7 MHz 00
As f
cannot exceed 10 MHz, bit field CTC should not be set to 00B when f
ADCI
26.7 MHz. During slow-down mode where f
etc., CTC can be set to 00
Frequency Selection
ADCI
ADC
CTC Prescaling Ratio Analog Clock f
B
01
B
10
B
11
(default) ÷ 32 833.3 kHz
B
as long as the divided analog clock f
B
÷ 2 13.3 MHz (N.A)
÷3 8.9MHz
÷4 6.7MHz
may be reduced to 13.3 MHz, 6.7 MHz
ADC
does not exceed
ADCI
ADCI
ADC
is
10 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if f
becomes too low during slow-down mode.
ADC
3.18.2 ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (t
• Sample phase (t
)
S
• Conversion phase
• Write result phase (tWR)
conversion start trigger
SYN
)
Source
interrupt
Conversion PhaseSample Phase
Channel interrupt
Result
interrupt
f
ADCI
BUSY Bit
SAMPLE Bit
t
SYN
t
S
t
CONV
Write Result Phase
t
WR
Figure 33 ADC Conversion Timing
Data Sheet 76 V1.0, 2006-02
XC866
Functional Description
3.19 On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks
• Step through the program code
The OCDS functional blocks are shown in Figure 34. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control.
Note: All the debug functionality described here can normally be used only after XC866
has been started in OCDS mode.
1)
,
1)
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet 77 V1.0, 2006-02
XC866
Functional Description
Memory
User Progr am Memory
User
Internal
RAM
Control
Unit
Boot/
Monitor
ROM
Monitor
RAM
Primary
Debug
Interface
Monitor &
Bootstr ap loader
Control line
System
Control
Unit
JTAG
WDT
Suspend
Reset
Clock
MBC
JTAG Module
TMS TCK TDI TDO
Reset
- pa rts of OCDS
TCK
TDO
Control
TDI
Monitor Mode Control
Debu g
Interface
PROG
& IRAM
Addresse s
PROG
Data
Memory
Control
Reset Clock
XC800
OCDS_XC800-Block_Diagram-UM-v0.2
Figure 34 OCDS Block Diagram
3.19.1 JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04 also true immediately after reset.
The JTAG ID register contents for the XC866 Flash devices are given in Table 28.
Table 28 JTAG ID Summary
Device Type Device Name JTAG ID
Flash XC866L-4FR 1010 0083
XC866-4FR 100F 5083
XC866L-2FR 1010 2083
XC866-2FR 1010 1083
H
H
H
H
), and the same is
H
Data Sheet 78 V1.0, 2006-02
XC866
Functional Description
3.20 Identification Register
The XC866 identity register is located at Page 1 of address B3H.
ID Identity Register Reset Value: 0000 0010
76543210
PRODID VERID
rr
Field Bits Type Description
VERID [2:0] r Version ID
010
B
PRODID [7:3] r Product ID
00000
B
B
Data Sheet 79 V1.0, 2006-02
XC866
Electrical Parameters
4 Electrical Parameters
4.1 General Parameters
4.1.1 Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC866 and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the “Symbol” column:
CC These parameters indicate Controller Characteristics, which are distinctive features of the XC866 and must be regarded for a system design.
SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC866 designed in.
Data Sheet 80 V1.0, 2006-02
XC866
Electrical Parameters
4.1.2 Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC866 can be subjected to without permanent damage.
Table 29 Absolute Maximum Rating Parameters
Parameter Symbol Limit Values Unit Notes
min. max.
Ambient temperature
Storage temperature
Junction temperature
Voltage on power supply pin with respect to
V
SS
Voltage on core supply pin with respect to
V
SS
Voltage on any pin with respect to
V
SS
Input current on any pin during overload condition
Absolute sum of all input currents during overload condition
T T T V
V
V
A
ST
J
DDP
DDC
IN
-40 125 °C under bias
-65 150 °C
-40 150 °C under bias
-0.5 6 V
-0.5 3.25 V
-0.5 V
DDP
+
0.5 or max. 6
I
IN
Σ|
I
-10 10 mA
|– 50 mA
IN
V Whatever is
lower
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (V the voltage on V
pin with respect to ground (VSS) must not exceed the values
DDP
IN>VDDP
or VIN<VSS)
defined by the absolute maximum ratings.
Data Sheet 81 V1.0, 2006-02
XC866
Electrical Parameters
4.1.3 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct operation of the XC866. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted.
Table 30 Operating Condition Parameters
Parameter Symbol Limit Values Unit Notes/
min. max.
Digital power supply voltage
V
DDP
4.5 5.5 V 5V range
3.0 3.6 V 3.3V range
Digital ground voltage
Digital core supply voltage
System Clock Frequency
Ambient temperature
V
SS
V
DDC
1)
f
SYS
T
A
2.3 2.7 V
74 86 MHz
-40 85 °C SAF-XC866...
-40 125 °C SAK-XC866...
1)
f
is the PLL output clock. During normal operating mode, CPU clock is f
SYS
for detailed description.
0V
SYS
Conditions
/ 3. Please refer to Figure 24
Data Sheet 82 V1.0, 2006-02
Electrical Parameters
4.2 DC Parameters
4.2.1 Input/Output Characteristics
Table 31 Input/Output Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
min. max.
V
= 5V Range
DDP
V
Output low voltage
Output high voltage
Input low voltage on port pins (all except P0.0 & P0.1)
Input low voltage on P0.0 & P0.1
Input low voltage on RESET
pin
Input low voltage on TMS pin
Input high voltage on port pins (all except P0.0 & P0.1)
Input high voltage on P0.0 & P0.1
Input high voltage on RESET
pin
Input high voltage on TMS pin
Input Hysteresis
1)
Input low voltage at XTAL1
CC – 1.0 V I
OL
–0.4V
V
OH
CC V
-
–VI
DDP
1.0
V
-
–VI
DDP
0.4
V
SR 0.3 ×
ILP
V
V
SR -0.2 0.3 ×
ILP0
V
V
SR 0.3 ×
ILR
V
V
SR 0.3 ×
ILT
V
V
SR 0.7 ×
IHP
V
V
SR 0.7 ×
IHP0
V
V
SR 0.7 ×
IHR
V
V
SR 0.75 ×
IHT
V
HYS CC 0.08 ×
V
V
SR V
ILX
0.5
–VCMOS Mode
DDP
V
DDP
–VCMOS Mode
DDP
–VCMOS Mode
DDP
–VCMOS Mode
DDP
-
0.3 ×
SS
V
V CMOS Mode
DDP
V CMOS Mode
DDP
V CMOS Mode
DDP
V CMOS Mode
DDP
V CMOS Mode
DDP
V
DDC
=15mA
OL
I
=5mA
OL
OH
OH
=-15mA
=-5mA
XC866
Data Sheet 83 V1.0, 2006-02
Electrical Parameters
Table 31 Input/Output Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
min. max.
Input high voltage at XTAL1
Pull-up current
Pull-down current I
Input leakage current2) I
V
SR 0.7 ×
IHX
V
I
SR -10 µA V
PU
DDC
V
DDC
+0.5
V
-150 µA V
SR 10 µA V
PD
150 µA V
CC -1 1 µA 0 < VIN < V
OZ1
IH,min
IL,max
IL,max
IH,min
DDP
TA≤ 125°C
Input current at XTAL1
Overload current on any
I
CC -10 10 µA
ILX
I
SR -5 5 mA
OV
pin
Absolute sum of overload currents
Maximum current per
V
pin (excluding
V
)
SS
DDP
and
Maximum current for all
pins (excluding V and V
SS
)
DDP
Maximum current into
V
DDP
Maximum current out of
V
SS
Σ|
I
|
OV
–25mA
SR
I
SR – 15 mA
M
Σ|I
|
M
–60mA
SR
I
MVDDP
–80mA
SR
I
MVSS
–80mA
SR
3)
V
= 3.3V Range
DDP
V
Output low voltage
Output high voltage
CC – 1.0 V I
OL
–0.4V
V
OH
CC V
-
–VI
DDP
=8mA
OL
I
=2.5mA
OL
=-8mA
OH
1.0
V
-
–VI
DDP
=-2.5mA
OH
0.4
XC866
,
Data Sheet 84 V1.0, 2006-02
Electrical Parameters
Table 31 Input/Output Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
min. max.
Input low voltage on port pins
V
SR 0.3 ×
ILP
V
V CMOS Mode
DDP
(all except P0.0 & P0.1)
Input low voltage on P0.0 & P0.1
Input low voltage on RESET pin
Input low voltage on TMS pin
Input high voltage on port pins
V
SR -0.2 0.3 ×
ILP0
V
SR 0.3 ×
ILR
V
SR 0.3 ×
ILT
V
SR 0.7 ×
IHP
V
V CMOS Mode
V
DDP
V CMOS Mode
V
DDP
V CMOS Mode
V
DDP
–VCMOS Mode
DDP
(all except P0.0 & P0.1)
Input high voltage on P0.0 & P0.1
Input high voltage on RESET
pin
Input high voltage on TMS pin
Input Hysteresis
1)
Input low voltage at XTAL1
Input high voltage at XTAL1
Pull-up current
Pull-down current I
Input leakage current2) I
V
SR 0.7 ×
IHP0
V
V
SR 0.7 ×
IHR
V
V
SR 0.75 ×
IHT
V
HYS CC 0.03 ×
V
V
SR V
ILX
0.5
V
SR 0.7 ×
IHX
V
I
SR -5 µA V
PU
V
DDP
V CMOS Mode
DDP
–VCMOS Mode
DDP
–VCMOS Mode
DDP
–VCMOS Mode
DDP
-
SS
DDC
0.3 ×
V V
+0.5
DDC
DDC
V
V
-50 µA V
SR 5 µA V
PD
50 µA V
CC -1 1 µA 0 < VIN < V
OZ1
IH,min
IL,max
IL,max
IH,min
DDP
TA≤ 125°C
Input current at XTAL1
Overload current on any
I
CC - 10 10 µA
ILX
I
SR -5 5 mA
OV
pin
XC866
,
Data Sheet 85 V1.0, 2006-02
XC866
Electrical Parameters
Table 31 Input/Output Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
min. max.
Absolute sum of overload currents
Maximum current per
pin (excluding V
V
)
SS
DDP
Maximum current for all
pins (excluding V and V
SS
)
DDP
Maximum current into
V
DDP
Maximum current out of
V
SS
1)
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise.
2)
An additional error current (I
pin have internal pull devices and are not included in the input leakage current characteristic.
RESET
3)
Not subjected to production test, verified by design/characterization.
and
Σ|I
|
OV
–25mA
SR
I
SR – 15 mA
M
Σ|
I
|
M
–60mA
SR
I
MVDDP
–80mA
SR
I
MVSS
–80mA
SR
) will flow if an overload current flows through an adjacent pin. TMS pin and
INJ
3)
Data Sheet 86 V1.0, 2006-02
4.2.2 Supply Threshold Characteristics
5.0V
VDDP
XC866
Electrical Parameters
V
DDPPW
VDDC
2.5V
V
DDCPOR
V
DDCPW
V
DDCBO
V
DDCRDR
V
DDCBOP D
Figure 35 Supply Threshold Parameters
Table 32 Supply Threshold Parameters (Operating Conditions apply)
Parameters Symbol Limit Values Unit
min. typ. max.
V
prewarning voltage
DDC
brownout voltage in
V
DDC
active mode
1)
RAM data retention voltage V
brownout voltage in
V
DDC
power-down mode
V
prewarning voltage
DDP
Power-on reset voltage
1)
Detection is disabled in power-down mode.
2)
Detection is enabled in both active and power-down mode.
3)
Detection is enabled for external power supply of 5.0V. Detection must be disabled for external power supply of 3.3V.
4)
The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
1)
2)
3)
2)4)
V
DDCPW
V
DDCBO
DDCRDR
V
DDCBOPD
V
DDPPW
V
DDCPOR
CC 2.2 2.3 2.4 V
CC 2.0 2.1 2.2 V
CC 0.9 1.0 1.1 V
CC 1.3 1.5 1.7 V
CC 3.4 4.0 4.6 V
CC 1.3 1.5 1.7 V
Data Sheet 87 V1.0, 2006-02
XC866
Electrical Parameters
4.2.3 ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (V externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV.
Table 33 ADC Characteristics (Operating Conditions apply; V
Parameter Symbol Limit Values Unit Test Conditions/
min. typ . max.
Analog reference voltage
Analog reference ground
Analog input
V
AREF
V
AGND
V
AIN
SR
SR
SR V
V
AGND
+ 1
V
SS
- 0.05
AGND
V
V
V
DDPVDDP
+ 0.05
V
SS
AREF
- 1
AREF
V
V
V
DDP
Remarks
voltage range
ADC clocks f
ADC
f
ADCI
20 40 MHz module clock
10 MHz internal analog clock
See Figure 32
Sample time t
Conversion time t
Total unadjusted error
Switched capacitance at the
CC (2 + INPCR0.STC) ×
S
C
TUE
t
ADCI
CC See Section 4.2.3.1 µs
1)
CC – ±1 LSB 8-bit conversion.
µs
––±2 LSB 10-bit conversion.
C
AREFSW
–1020pF
2)3)
CC reference voltage input
Switched capacitance at the
C
AINSW
–57pF
CC
2)4)
analog voltage inputs
Input resistance of
R
CC – 1 2 k
AREF
2)
the reference input
Input resistance of
R
CC – 1 1.5 k
AIN
2)
the selected analog channel
) must be
SS
= 5V Range)
2)
Data Sheet 88 V1.0, 2006-02
XC866
Electrical Parameters
1)
TUE is tested at V
2)
Not subject to production test, verified by design/characterization.
3)
This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4)
The sampling capacity of the conversion C-Network is pre-charged to V the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than V
AREF
=5.0V, V
AGND
=0V , V
DDP
=5.0V.
/2 before connecting the input to
AREF
AREF
Analog Input Circuitry
/2.
R
EXT
V
AIN
C
EXT
V
AGNDx
ANx
R
AIN, On
C
AINSW
Reference Voltage Input Circuitry
R
AREF, On
C
AREFSW
V
AREF
V
V
AGNDx
AREFx
Figure 36 ADC Input Circuits
Data Sheet 89 V1.0, 2006-02
4.2.3.1 ADC Conversion Timing
Conversion time, tC=t
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11
B
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively), t
=1/f
ADC
ADC
× ( 1 + r × (3 + n + STC) ) , where
ADC
,
XC866
Electrical Parameters
Data Sheet 90 V1.0, 2006-02
XC866
Electrical Parameters
4.2.4 Power Supply Current
Table 34 Power Supply Current Parameters (Operating Conditions apply;
V
= 5V range )
DDP
Parameter Symbol Limit Values Unit Test Condition
1)
typ.
V
= 5V Range
DDP
Active Mode
Idle Mode I
Active Mode with slow-down
I
DDP
DDP
I
DDP
22.6 24.5 mA
17.2 19.7 mA
7.2 8.2 mA
enabled
Idle Mode with slow-down
I
DDP
7.1 8 mA
enabled
1)
The typical I
2)
The maximum I
3)
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010
4)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET
5)
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101
6)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101 RESET
values are periodically measured at TA=+25°C and V
DDP
values are measured under worst case conditions (TA= + 125 °C and V
DDP
= V
.
DDP
= V
.
DDP
), RESET = V
B
, RESET = V
B
max.
DDP
DDP
2)
DDP
=5.0V.
.
.
3)
4)
5)
6)
=5.5V).
DDP
,
B
Data Sheet 91 V1.0, 2006-02
XC866
Electrical Parameters
Table 35 Power Down Current (Operating Conditions apply; V
= 5V range )
DDP
Parameter Symbol Limit Values Unit Test Condition
1)
typ.
V
= 5V Range
DDP
Power-Down Mode
3)
I
PDP
11ATA=+25°C.
-3ATA=+85°C.
1)
The typical I
2)
The maximum I
3)
I
(power-down mode) has a maximum value of 200 µA at TA= + 125 °C.
PDP
4)
I
(power-down mode) is measured with: RESET = V
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs.
5)
Not subject to production test, verified by design/characterization.
values are measured at V
PDP
values are measured at V
PDP
DDP
=5.0V.
=5.5V.
DDP
DDP
, V
AGND
2)
max.
= VSS, RXD/INT0 = V
; rest of the ports
DDP
4)
4)5)
Data Sheet 92 V1.0, 2006-02
XC866
Electrical Parameters
Table 36 Power Supply Current Parameters (Operating Conditions apply;
V
= 3.3V range)
DDP
Parameter Symbol Limit Values Unit Test Condition
1)
typ.
V
= 3.3V Range
DDP
Active Mode
Idle Mode I
Active Mode with slow-down
I
DDP
DDP
I
DDP
21.5 23.3 mA
16.4 18.9 mA
6.8 8 mA
enabled
Idle Mode with slow-down
I
DDP
6.8 7.8 mA
enabled
1)
The typical I
2)
The maximum I
3)
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010
4)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET
5)
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101
6)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enable and running at 833 KHz by setting CLKREL in CMCON to 0101 RESET
values are periodically measured at TA=+25°C and V
DDP
values are measured under worst case conditions (TA= + 125 °C and V
DDP
= V
.
DDP
= V
.
DDP
), RESET = V
B
, RESET = V
B
max.
DDP
DDP
2)
=3.3V.
DDP
.
3)
4)
5)
6)
=3.6V).
DDP
.
,,
B
Data Sheet 93 V1.0, 2006-02
XC866
Electrical Parameters
Table 37 Power Down Current (Operating Conditions apply; V
DDP
= 3.3V
range )
Parameter Symbol Limit Values Unit Test Condition
1)
typ.
V
= 3.3V Range
DDP
Power-Down Mode
3)
I
PDP
11ATA=+25°C.
-3ATA=+85°C.
1)
The typical I
2)
The maximum I
3)
I
(power-down mode) has a maximum value of 200 µA at TA= + 125 °C.
PDP
4)
I
(power-down mode) is measured with: RESET = V
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs.
5)
Not subject to production test, verified by design/characterization.
values are measured at V
PDP
values are measured at V
PDP
DDP
=3.3V.
=3.6V.
DDP
DDP
, V
AGND
2)
max.
= VSS, RXD/INT0= V
; rest of the ports
DDP
4)
4)5)
Data Sheet 94 V1.0, 2006-02
XC866
Electrical Parameters
4.3 AC Parameters
4.3.1 Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 37, Figure 38 and Figure 39.
V
DDP
90%
90%
V
SS
10%
t
R
Figure 37 Rise/Fall Time Parameters
V
DDP
V
/ 2
DDE
V
SS
Te st P oi n ts
Figure 38 Testing Waveform, Output Delay
V
+ 0.1 V VOH - 0.1 V
Load
Timing
Reference
V
- 0.1 V VOL - 0.1 V
Load
Points
Figure 39 Testing Waveform, Output High Impedance
10%
t
F
/ 2
V
DDE
Data Sheet 95 V1.0, 2006-02
XC866
Electrical Parameters
4.3.2 Output Rise/Fall Times
Table 38 Output Rise/Fall Times Parameters (Operating Conditions apply)
Parameter Symbol Limit
Values
min. max.
V
= 5V Range
DDP
Rise/fall times
V
= 3.3V Range
DDP
Rise/fall times
1)
Rise/Fall time measurements are taken with 10% - 90% of the pad supply.
2)
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3)
Additional rise/fall time valid for CL= 20pF - 100pF @ 0.125 ns/pF.
4)
Additional rise/fall time valid for CL= 20pF - 100pF @ 0.225 ns/pF.
1) 2)
1) 2)
V
DDP
tR, t
tR, t
90%
F
F
10 ns 20 pF.
10 ns 20 pF.
Unit Test Conditions
3)
4)
90%
V
SS
10%
t
R
10%
t
F
Figure 40 Rise/Fall Times Parameters
Data Sheet 96 V1.0, 2006-02
Loading...