The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, Feb 2006
XC866
8-Bit Single-Chip Microcontroller
Microcontrollers
XC866 Data Sheet
Revision History:2006-02V1.0
Previous Version: V 0.1, 2005-01
PageSubjects (major changes since last revision)
3LIN support is elaborated in Table 1.
13Section 3.2 is updated.
34Section 3.3 is updated.
37Section 3.4 is updated.
49The power-on reset requirements are updated in Section 3.7.
49Section 3.7 is updated.
54Table 19 is updated with a new range of the f
VCOFREE
parameter.
65Section 3.12 is updated.
66Section 3.13 is updated.
78Figure 34 is updated with the removal of OCDS interrupt.
81Section 4.1.2 is updated.
82Section 4.1.3 is updated.
83Section 4.2.1 is updated.
87Section 4.2.2 is updated.
91Section 4.2.4 is updated.
95“Testing Waveforms” is updated in Section 4.3.1.
97Section 4.3.3 is updated.
102Figure 40 is updated.
103“Quality Declaration” is updated in Section 5.2.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
XC8668-Bit Single-Chip Microcontroller
XC800 Family
1Summary of Features
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 512 bytes of XRAM
– 8/16 Kbytes of Flash; or
8/16 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 V/5.0 V and core logic supply at 2.5 V (generated by embedded
voltage regulator)
(further features are on next page)
Flash or ROM
8K/16K x 8
Boot ROM
8K x 8
XRAM
512 x 8
RAM
256 x 8
1)
Timer 0
16-bit
On-Chip Debug Support
XC800 Core
Timer 1
16-bit
Timer 2
16-bit
UART
Capture/Compare Unit
Watchdog
Timer
1) All ROM devices include 4K x 8 Flash
SSC
16-bit
Compare Unit
16-bit
ADC
10-bit
8-channel
Port 0
Port 1
Port 2
Port 3
6-bi t Di gi tal I/O
5-bi t Di gi tal I/O
8-bit Digital/Analog Input
8-bi t Di gi tal I/O
Figure 1XC866 Functional Units
Data Sheet1V1.0, 2006-02
Features (continued):
• Power-on reset generation
• Brownout detection for core logic supply
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports
– 19 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Three 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
–Timer 2
• Capture/compare unit for PWM signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM
• PG-TSSOP-38 pin package
• Temperature range T
:
A
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
XC866
Summary of Features
Data Sheet2 V1.0, 2006-02
XC866
Summary of Features
XC866 Variant Devices
The XC866 product family features eight devices with different configurations and
program memory sizes, offering cost-effective solution for different application
requirements.
The list of XC866 devices and their differences are summarized in Table 1.
Table 1Device Summary
Device TypeDevice NameFlash SizeROM SizeLIN BSL
Support
Flash XC866L-4FR16 Kbytes–Yes
XC866-4FR16 Kbytes–No
XC866L-2FR8 Kbytes–Yes
XC866-2FR8 Kbytes–No
ROM XC866L-4RR4 Kbytes16 KbytesYes
XC866-4RR4 Kbytes16 KbytesNo
XC866L-2RR4 Kbytes8 KbytesYes
XC866-2RR4 Kbytes8 KbytesNo
Ordering Information
The ordering code for Infineon Technologies microcontrollers provides an exact
reference to the required product. This ordering code indentifies:
• The derivative itself, i.e. its function set
• the specified temperature range
• the package and the type of delivery
For the available ordering codes for the XC866, please refer to the “Product CatalogMicrocontrollers” which summarizes all available microcontroller variants.
Note: The ordering codes for the Mask-ROM versions are defined for each product after
Port 1 is a 5-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
P1.027PURXD_0UART Receive Data Input
T2EXTimer 2 External Trigger Input
P1.128PUEXINT3External Interrupt Input 3
TDO_1JTAG Serial Data Output
TXD_0UART Transmit Data Output/
Clock Output
P1.529PUCCPOS0_1 CCU6 Hall Input 0
EXINT5External Interrupt Input 5
EXF2_0TImer 2 External Flag Output
RXDO_0UART Transmit Data Output
P1.69PUCCPOS1_1 CCU6 Hall Input 1
T12HR_0CCU6 Timer 12 Hardware Run
Input
EXINT6External Interrupt Input 6
P1.710PUCCPOS2_1 CCU6 Hall Input 2
T13HR_0CCU6 Timer 13 Hardware Run
Input
P1.5 and P1.6 can be used as a software chip
select output for the SSC.
XC866
Data Sheet8 V1.0, 2006-02
General Device Information
Table 2Pin Definitions and Functions (cont’d)
Symbol Pin
Number
Type Reset
State
Function
P2IPort 2
Port 2 is an 8-bit general purpose input-only port. It
can be used as alternate functions for the digital
inputs of the JTAG and CCU6. It is also used as the
analog inputs for the ADC.
P2.015Hi-ZCCPOS0_0 CCU6 Hall Input 0
EXINT1External Interrupt Input 1
T12HR_2CCU6 Timer 12 Hardware Run
Port 3 is a bidirectional general purpose I/O port. It
can be used as alternate functions for the CCU6.
CC60_0Input/Output of Capture/Compare
channel 0
CC61_2Input/Output of Capture/Compare
channel 1
COUT60_0 Output of Capture/Compare
channel 0
CC61_0Input/Output of Capture/Compare
channel 1
channel 1
channel 2
channel 2
CCU6 Trap Input
COUT63_0 Output of Capture/Compare
channel 3
Data Sheet10 V1.0, 2006-02
General Device Information
Table 2Pin Definitions and Functions (cont’d)
Symbol Pin
Number
V
V
V
V
V
V
DDP
SSP
DDC
SSC
AREF
AGND
18––I/O Port Supply (3.3 V/5.0 V)
19––I/O Port Ground
8––Core Supply Monitor (2.5 V)
7––Core Supply Ground
25––ADC Reference Voltage
24––ADC Reference Ground
Type Reset
State
Function
XTAL16IHi-ZExternal Oscillator Input
(NC if not needed)
XTAL25OHi-ZExternal Oscillator Output
(NC if not needed)
TMS11IPDTest Mode Select
RESET
38IPUReset Input
MBC1IPUMonitor & BootStrap Loader Control
XC866
Data Sheet11 V1.0, 2006-02
XC866
Functional Description
3Functional Description
3.1Processor Architecture
The XC866 is based on a high-performance 8-bit Central Processing Unit (CPU) that is
compatible with the standard 8051 processor. While the standard 8051 processor is
designed around a 12-clock machine cycle, the XC866 CPU uses a 2-clock machine
cycle. This allows fast access to ROM or RAM memories without wait state. Access to
the Flash memory, however, requires an additional wait state (one machine cycle). The
instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions.
The XC866 CPU provides a range of debugging features, including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and SFRs.
Figure 5 shows the CPU functional blocks.
Internal Data
Memory
External SFRs
External Data
Memory
Core SFRs
Regist er Int erfac e
Program Memory
f
CCLK
Memory Wait
Reset
Legacy Exter nal Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
16-bit R egis t ers &
Memory Interface
Opcode &
Imm ediate
Registers
Opcode D ecoder
State Mac hine &
Power Saving
Interrupt
Cont roller
ALU
Mult ipli er / D iv ider
Timer 0 / Timer 1
UART
Figure 5CPU Block Diagram
Data Sheet12 V1.0, 2006-02
XC866
Functional Description
3.2Memory Organization
The XC866 CPU operates in the following five address spaces:
• 8 Kbytes of Boot ROM program memory
• 256 bytes of internal RAM data memory
• 512 bytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
• a 128-byte Special Function Register area
• 8/16 Kbytes of Flash program memory (Flash devices); or
8/16 Kbytes of ROM program memory, with additional 4 Kbytes of Flash
(ROM devices)
Figure 6 illustrates the memory address spaces of the 16-Kbyte Flash devices. For the
8-Kbyte Flash devices, the shaded banks are not available.
FFFF
H
F200
XRAM
512 byt es
Boot ROM
8 Kbytes
D-Fl ash Ba nk
4 Kbytes
P-Flas h Bank 2
4 Kbytes
P-Flas h Bank 1
4 Kbytes
P-Flas h Bank 0
4 Kbytes
Program S paceExternal Dat a Spac eInterna l Dat a Spac e
F000
E000
C000
B000
A000
3000
2000
1000
0000
H
H
H
H
H
H
H
H
H
H
XRAM
512 bytes
FFFF
F200
F000
0000
H
H
H
Indirect
Address
Internal RAM
7F
H
Internal RAM
H
00
H
Direct
Addres s
Speci al Func tion
Regist ers
FF
H
80
H
Figure 6Memory Map of XC866 Flash Device
Data Sheet13 V1.0, 2006-02
XC866
Functional Description
3.2.1Memory Protection Strategy
The XC866 memory protection strategy includes:
• Read-out protection: The user is able to protect the contents in the Flash (for Flash
devices) and ROM (for ROM devices) memory from being read
• Flash program and erase protection (for Flash devices only)
Flash memory protection modes are available only for Flash devices:
• Mode 0: Only the P-Flash is protected; the D-Flash is unprotected
• Mode 1: Both the P-Flash and D-Flash are protected
The selection of each protection mode and the restrictions imposed are summarized in
Table 3.
Table 3Flash Protection Modes
Mode01
ActivationProgram a valid password via BSL mode 6
SelectionMSB of password = 0MSB of password = 1
P-Flash contents
can be read by
P-Flash program
and erase
D-Flash contents
can be read by
D-Flash program PossibleNot possible
D-Flash erasePossible, on the condition that bit
Read instructions in the
P-Flash
Not possibleNot possible
Read instructions in any program
memory
DFLASHEN in register MISC_CON
is set to 1 prior to each erase
operation
Read instructions in the
P-Flash or D-Flash
Read instructions in the
P-Flash or D-Flash
Not possible
BSL mode 6, which is used for enabling Flash protection, can also be used for disabling
Flash protection. Here, the programmed password must be provided by the user. A
password match triggers an automatic erase of the protected P-Flash and D-Flash
contents, including the programmed password. The Flash protection is then disabled
upon the next reset.
Although no protection scheme can be considered infallible, the XC866 memory
protection strategy provides a very high level of protection for a general purpose
microcontroller.
Note: If ROM read-out protection is enabled, only read instructions in the ROM memory
can target the ROM contents.
Data Sheet14 V1.0, 2006-02
XC866
Functional Description
3.2.2Special Function Register
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80
to FFH. All registers, except the program counter, reside in the SFR area. The
H
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
• Mapping
• Paging
3.2.2.1Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80
of addressable SFRs to 256. The extended address range is not directly controlled by
the CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8F
. To access SFRs in the mapped area, bit RMAP in SFR
H
SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed
by clearing bit RMAP. The SFR area can be selected as shown in Figure 7.
SYSCON0
System Control Register 0 Reset Value: 00
765432 10
to FFH, bringing the number
H
H
010RMAP
rrwrrw
FieldBitsType Description
RMAP0rwSpecial Function Register Map Control
0The access to the standard SFR area is
enabled.
1The access to the mapped SFR area is
enabled.
12rwReserved
Returns the last value if read; should be written
with 1.
01,[7:3] rReserved
Returns 0 if read; should be written with 0.
Data Sheet15 V1.0, 2006-02
XC866
Functional Description
Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of
SYSCON0 should not be modified.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
SFR Data
(to/from CPU)
SYSCON0.RMAP
rw
Standard Area (R MAP = 0)
Module 1 SFRs
Module 2 SFRs
…...
Module n SFRs
Mapped Area (RMAP = 1)
Module (n+1) SFRs
Module (n+2) SFRs
…...
Module m SFRs
FF
H
80
H
FF
H
80
H
Direct
Internal Data
Memory Address
Figure 7Address Extension by Mapping
Data Sheet16 V1.0, 2006-02
XC866
Functional Description
3.2.2.2Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC866 has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFR of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFR. A page inside
the extended address range can be selected as shown in Figure 8.
SFR Address
(from CPU)
MOD_PAGE.PAGE
rw
PAGE 0
SFR0
SFR1
…...
SFRx
PAGE 1
SFR Data
(to/from CPU )
SFR0
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 8Address Extension by Paging
Data Sheet17 V1.0, 2006-02
XC866
Functional Description
In order to access a register located in a page different from the actual one, the current
page must be left. This is done by reprogramming the bit field PAGE in the page register.
Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed and finally, the old page
setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and
restore action of the current page setting. By indicating which storage bit field should be
used in parallel with the new page value, a single write operation can:
• Save the contents of PAGE in STx before overwriting with the new value
(this is done in the beginning of the interrupt routine to save the current page setting
and program the new page number); or
• Overwrite the contents of PAGE with the contents of STx, ignoring the value written to
the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
ST3
ST2
ST1
ST0
STNR
value update
from CPU
PAGE
Figure 9Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC866 supports local address extension for:
• Parallel Ports
• Analog-to-Digital Converter (ADC)
• Capture/Compare Unit 6 (CCU6)
• System Control Registers
Data Sheet18 V1.0, 2006-02
XC866
Functional Description
The page register has the following definition:
MOD_PAGE
Page Register fo r mod ule M OD Reset V alue : 00
765432 10
OPSTNR0PAGE
wwr rw
FieldBitsType Description
PAGE[2:0] rwPage Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR[5:4]wStorage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in STx before being
overwritten with the new value.
If OP = 11
the contents of PAGE are overwritten by the
contents of STx. The value written to the bit positions
of PAGE is ignored.
,
B
H
00ST0 is selected.
01ST1 is selected.
10ST2 is selected.
11ST3 is selected.
Data Sheet19 V1.0, 2006-02
FieldBitsType Description
OP[7:6] wOperation
0XManual page mode. The value of STNR is
ignored and PAGE is directly written.
10New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field STx indicated by STNR.
11Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field STx indicated
by STNR.
03r Reserved
Returns 0 if read; should be written with 0.
XC866
Functional Description
Data Sheet20 V1.0, 2006-02
XC866
Functional Description
3.2.3Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. Note that access is opened for
maximum 32 CCLKs if the “close access” password is not written. If “open access”
password is written again before the end of 32 CCLK cycles, there will be a recount of
32 CCLK cycles. The protected bits include NDIV, WDTEN, PD, and SD.
PASSWD
Password RegisterReset Value: 07
76543210
PASS
whrhrw
PROTECT
FieldBitsType Description
MODE[1:0] rwBit Protection Scheme Control bits
00Scheme Disabled
11Scheme Enabled (default)
Others: Scheme Enabled
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000
MODE[1:0] be registered.
PROTECT_S2rhBit Protection Signal Status bit
This bit shows the status of the protection.
0Software is able to write to all protected bits.
1Software is unable to write to any protected
bits.
PASS[7:3]whPassword bits
The Bit Protection Scheme only recognizes three
patterns.
11000BEnables writing of the bit field MODE.
10011BOpens access to writing of all protected bits.
10101BCloses access to writing of all protected bits.
, writing 10011B to the
B
_S
; only then, will the
B
MODE
H
Data Sheet21 V1.0, 2006-02
XC866
Functional Description
3.2.4XC866 Register Overview
The SFRs of the XC866 are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Table 4 to Table 12, with the addresses
of the bitaddressable SFRs appearing in bold typeface.
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 4CPU Register Overview
AddrRegister NameBit76543210
RMAP = 0 or 1
SPReset: 07
81
H
Stack Pointer Register
DPLReset: 00
82
H
Data Pointer Register Low
DPHReset: 00
83
H
Data Pointer Register High
PCONReset: 00
87
H
Power Control Register
TCONReset: 00
88
H
Timer Control Register
TMODReset: 00
89
H
Timer Mode Register
TL0Reset: 00
8A
H
Timer 0 Register Low
TL1Reset: 00
8B
H
Timer 1 Register Low
TH0Reset: 00
8C
H
Timer 0 Register High
TH1Reset: 00
8D
H
Timer 1 Register High
SCONReset: 00
98
H
Serial Channel Control Register
SBUFReset: 00
99
H
Serial Data Buffer Register
EOReset: 00
A2
H
Extended Operation Register
IEN0Reset: 00
A8
H
Interrupt Enable Register 0
IPReset: 00
B8
H
Interrupt Priority Register
IPHReset: 00
B9
H
Interrupt Priority Register High
PSWReset: 00
D0
H
Program Status Word Register
ACCReset: 00
E0
H
Accumulator Register
IEN1Reset: 00
E8
H
Interrupt Enable Register 1
Bit Field
H
Typerw
Bit FieldDPL7 DPL6 DPL5 DPL4 DPL 3 DPL2 DPL1 DPL0
H
Typerwrwrwrwrwrwrwrw
Bit FieldDPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0
H
Typerwrwrwrwrwrwrwrw
Bit Field SMOD0GF1GF00IDLE
H
Typerwrrwrwrrw
Bit FieldTF1TR1TF0TR0IE1IT1IE0IT0
H
Typerwhrwrwhrwrwhrwrwhrw
Bit Field GATE10T1MGATE00T0M
H
Typerwrrwrwrrw
Bit FieldVAL
H
Typerwh
Bit FieldVAL
H
Typerwh
Bit FieldVAL
H
Typerwh
Bit FieldVAL
H
Typerwh
Bit Field
H
Typerwrwrwrwrwrwhrwhrwh
Bit Field
H
Typerwh
Bit Field
H
SM0 SM1SM2 RENTB8RB8TIRI
0TRAP_
Typerrwrrw
Bit FieldEA0ET2ESET1EX1ET0EX0
H
Type rw r rwrwrwrwrwrw
Bit Field0PT2PSPT1PX1PT0PX0
H
Typerrwrwrwrwrwrw
Bit Field
H
Typerrwrwrwrwrwrw
Bit FieldCYACF0RS1 RS0OVF1P
H
Typerwrwhrwhrwrwrwhrwhrh
Bit FieldACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
H
Typerwrwrwrwrwrwrwrw
Bit Field ECCIP3ECCIP2ECCIP1ECCIP0EXM EX2 ESSC EADC
H
0PT2H PSH PT1H PX1H PT0H PX0H
Typerwrwrwrwrwrwrwrw
EN
SP
VAL
0DPSEL
0
Data Sheet22 V1.0, 2006-02
XC866
Functional Description
Table 4CPU Register Overview (cont’d)
AddrRegister NameBit76543210
BReset: 00
F0
H
B Register
IP1Reset: 00
F8
H
Interrupt Priority Register 1
IPH1Reset: 00
F9
H
Interrupt Priority Register 1 High
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 5System Control Register Overview
AddrRegister NameBit 76543210
RMAP = 0 or 1
SYSCON0Reset: 00
8F
H
System Control Register 0
RMAP = 0
SCU_PAGEReset: 00
BF
H
Page Register for System Control
RMAP = 0, Page 0
MODPISELReset: 00
B3
H
Peripheral Input Select Register
B4HIRCON0Reset: 00
Interrupt Request Register 0
IRCON1Reset: 00
B5
H
Interrupt Request Register 1
EXICON0Reset: 00
B7
H
External Interrupt Control Register 0
EXICON1Reset: 00
BA
H
External Interrupt Control Register 1
NMICONReset: 00
BB
H
NMI Control Register
BCHNMISRReset: 00
NMI Status Register
BCONReset: 00
BD
H
Baud Rate Control Register
BGReset: 00
BE
H
Baud Rate Timer/Reload Register
FDCONReset: 00
E9
H
Fractional Divider Control Register
FDSTEPReset: 00
EA
H
Fractional Divider Reload Register
FDRESReset: 00
EB
H
Fractional Divider Result Register
RMAP = 0, Page 1
Bit FieldB7B6B5B4B3B2B1B0
H
Typerwrwrwrwrwrwrwrw
Bit Field PCCIP3PCCIP2PCCIP1PCCIP0PXM PX2 PSSC PADC
H
Typerwrwrwrwrwrwrwrw
Bit Field PCCIP3HPCCIP2HPCCIP1HPCCIP0HPXMH PX2H PSSCH PADC
H
Typerwrwrwrwrwrwrwrw
Bit Field0RMAP
H
Typerrw
Bit FieldOPSTNR0PAGE
H
Typewwrrw
Bit Field0JTAG
H
TDIS
JTAG
TCKS
0EXINT
0IS
Typerrwrwrrwrw
Bit Field0EXINT6EXINT5EXINT4EXINT3EXINT2EXINT1EXINT
H
Typerrwhrwhrwhrwhrwhrwhrwh
Bit Field0ADCS
H
RC1
ADCS
RC0
RIRTIREIR
Typerrwhrwhrwhrwhrwh
Bit FieldEXINT3EXINT2EXINT1EXINT0
H
Typerwrw
Bit Field
H
Typerrwrwrw
Bit Field
H
0EXINT6EXINT5EXINT4
0NMI
ECC
NMI
VDDP
NMI
VDD
Typerrwrwrw
H
Bit Field
0FNMI
ECC
FNMI
VDDP
FNMI
VDD
Typerrwhrwhrwh
Bit FieldBGSEL0BRENBRPRER
H
Typerwrrwrwrw
Bit Field
H
Typerw
Bit Field
H
BGS SYNEN ERRSYNEOFSYNBRK NDOV FDM FDEN
BR_VALUE
Typerwrwrwhrwh
Bit FieldSTEP
H
Typerw
Bit FieldRESULT
H
Typerh
rwrw
NMI
NMI
FLASH
NMI
PLL
OCDS
rwrwrwrw
FNMI
FNMI
FLASH
FNMI
PLL
OCDS
rwhrwhrwhrwh
rwhrwhrwrw
H
URRIS
0
NMI
WDT
FNMI
WDT
Data Sheet23 V1.0, 2006-02
XC866
Functional Description
Table 5System Control Register Overview (cont’d)
AddrRegister NameBit 76543210
IDReset: 01
B3
H
Identity Register
PMCON0Reset: 00
B4
H
Power Mode Control Register 0
PMCON1Reset: 00
B5
H
Power Mode Control Register 1
B6HOSC_CONReset: 08
OSC Control Register
PLL_CONReset: 20
B7
H
PLL Control Register
CMCONReset: 00
BA
H
Clock Control Register
PASSWDReset: 07
BB
H
Password Register
FEALReset: 00
BC
H
Flash Error Address Register Low
FEAHReset: 00
BD
H
Flash Error Address Register High
COCONReset: 00
BE
H
Clock Output Control Register
MISC_CONReset: 00
E9
H
Miscellaneous Control Register
RMAP = 0, Page 3
B3HXADDRHReset: F0
On-Chip XRAM Address Higher Order
Bit FieldPRODIDVERID
H
Typerr
Bit Field0WDT
H
RST
WKRS WK
SEL
SDPDWS
Typerrwhrwhrwrwrwhrw
Bit Field0T2_DIS CCU
H
_DIS
SSC
_DIS
Typerrwrwrwrw
Bit Field0OSCPDXPD OSCSSORD
H
RES
Typerrwrwrwrwhrh
Bit FieldNDIVVCO
H
BYP
OSC
DISC
RESLD LOCK
Typerwrwrwrwhrh
Bit FieldVCO
H
SEL
0CLKREL
Typerwrrw
Bit FieldPASSPROTE
H
CT_S
Typewhrhrw
Bit FieldECCERRADDR[7:0]
H
Typerh
Bit FieldECCERRADDR[15:8]
H
Typerh
Bit Field0TLEN COUT
H
S
COREL
Typerrwrwrw
Bit Field0DFLAS
H
Typerrwh
Bit Field
H
Typerw
ADDRH
MODE
ADC
_DIS
OSCR
HEN
The WDT SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 6WDT Register Overview
AddrRegister NameBit76543210
RMAP = 1
WDTCONReset: 00
BB
H
Watchdog Timer Control Register
H
Bit Field
Typerrwrh
WDTRELReset: 00
BC
H
Watchdog Timer Reload Register
WDTWINBReset: 00
BD
H
Watchdog Window-Boundary Count
Register
WDTLReset: 00
BE
H
Watchdog Timer Register Low
BF
WDTHReset: 00
H
Watchdog Timer Register High
Bit FieldWDTREL
H
Typerw
Bit Field
H
Typerw
Bit Field
H
Typerh
Bit FieldWDT[15:8]
H
Typerh
Data Sheet24 V1.0, 2006-02
0WINBENWDTPR0WDTENWDTRSWDT
IN
rrwrwhrw
WDTWINB
WDT[7:0]
XC866
Functional Description
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 7Port Register Overview
AddrRegister NameBit76543210
RMAP = 0
PORT_PAGEReset: 00
B2
H
Page Register for PORT
RMAP = 0, Page 0
P0_DATAReset: 00
80
H
P0 Data Register
P0_DIRReset: 00
86
H
P0 Direction Register
P1_DATAReset: 00
90
H
P1 Data Register
P1_DIRReset: 00
91
H
P1 Direction Register
P2_DATAReset: 00
A0
H
P2 Data Register
P2_DIRReset: 00
A1
H
P2 Direction Register
P3_DATAReset: 00
B0
H
P3 Data Register
P3_DIRReset: 00
B1
H
P3 Direction Register
RMAP = 0, Page 1
P0_PUDSELReset: FF
80
H
P0 Pull-Up/Pull-Down Select Register
P0_PUDENReset: C4
86
H
P0 Pull-Up/Pull-Down Enable Register
P1_PUDSELReset: FF
90
H
P1 Pull-Up/Pull-Down Select Register
P1_PUDENReset: FF
91
H
P1 Pull-Up/Pull-Down Enable Register
P2_PUDSELReset: FF
A0
H
P2 Pull-Up/Pull-Down Select Register
P2_PUDENReset: 00
A1
H
P2 Pull-Up/Pull-Down Enable Register
P3_PUDSELReset: BF
B0
H
P3 Pull-Up/Pull-Down Select Register
P3_PUDENReset: 40
B1
H
P3 Pull-Up/Pull-Down Enable Register
RMAP = 0, Page 2
P0_ALTSEL0Reset: 00
80
H
P0 Alternate Select 0 Register
P0_ALTSEL1Reset: 00
86
H
P0 Alternate Select 1 Register
P1_ALTSEL0Reset: 00
90
H
P1 Alternate Select 0 Register
P1_ALTSEL1Reset: 00
91
H
P1 Alternate Select 1 Register
P3_ALTSEL0Reset: 00
B0
H
P3 Alternate Select 0 Register
Bit Field
H
Typewwrrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwrrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwrrwrw
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwrrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwr
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit Field0P5P4P3P2P1P0
H
Typerrwrwrwrwrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwrrwrw
Bit FieldP7P6P50P1P0
H
Typerwrwrwrrwrw
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
OPSTNR0PAGE
rwrw
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
P7P6P5P4P3P2P1P0
Data Sheet25 V1.0, 2006-02
XC866
Functional Description
Table 7Port Register Overview (cont’d)
AddrRegister NameBit76543210
P3_ALTSEL1Reset: 00
B1
H
P3 Alternate Select 1 Register
RMAP = 0, Page 3
P0_ODReset: 00
80
H
P0 Open Drain Control Register
P1_ODReset: 00
90
H
P1 Open Drain Control Register
P3_ODReset: 00
B0
H
P3 Open Drain Control Register
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 8ADC Register Overview
AddrRegister NameBit76543210
RMAP = 0
ADC_PAGEReset: 00
D1
H
Page Register for ADC
RMAP = 0, Page 0
CAHADC_GLOBCTRReset: 30
Global Control Register
CBHADC_GLOBSTRReset: 00
Global Status Register
ADC_PRARReset: 00
CC
H
Priority and Arbitration Register
ADC_LCBRReset: B7
CD
H
Limit Check Boundary Register
ADC_INPCR0Reset: 00
CE
H
Input Class Register 0
ADC_ETRCRReset: 00
CF
H
External Trigger Control Register
RMAP = 0, Page 1
ADC_CHCTR0Reset: 00
CA
H
Channel Control Register 0
ADC_CHCTR1Reset: 00
CB
H
Channel Control Register 1
ADC_CHCTR2Reset: 00
CC
H
Channel Control Register 2
ADC_CHCTR3Reset: 00
CD
H
Channel Control Register 3
ADC_CHCTR4Reset: 00
CE
H
Channel Control Register 4
ADC_CHCTR5Reset: 00
CF
H
Channel Control Register 5
ADC_CHCTR6Reset: 00
D2
H
Channel Control Register 6
ADC_CHCTR7Reset: 00
D3
H
Channel Control Register 7
RMAP = 0, Page 2
Bit FieldP7P6P5P4P3P2P1P0
H
Typerwrwrwrwrwrwrwrw
Bit Field
H
Typerrwrwrwrwrwrw
Bit Field
H
Typerwrwrwrrwrw
Bit Field
H
Typerwrwrwrwrwrwrwrw
Bit FieldOPSTNR0PAGE
H
Typewwrrw
Bit FieldANON DWCTC0
H
Typerwrwrwr
Bit Field0CHNR0SAM
H
0P5P4P3P2P1P0
P7P6P50P1P0
P7P6P5P4P3P2P1P0
PLE
Typerrhrrhrh
Bit Field ASEN1 ASEN00ARBM CSM1 PRIO1 CSM0 PRIO0
H
Typerwrwrrwrwrwrwrw
Bit FieldBOUND1BOUND0
H
Typerwrw
Bit FieldSTC
H
Typerw
Bit Field SYNEN1SYNEN
H
0
ETRSEL1ETRSEL0
Typerwrwrwrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrw
Bit Field0LCC0RESRSEL
H
Typerrwrrw
Bit Field0LCC0RESRSEL
H
Typerrwrrw
Bit Field0LCC0RESRSEL
H
Typerrwrrw
Bit Field0LCC0RESRSEL
H
Typerrwrrw
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
0LCC0RESRSEL
rrw
BUSY
Data Sheet26 V1.0, 2006-02
XC866
Functional Description
Table 8ADC Register Overview (cont’d)
AddrRegister NameBit76543210
ADC_RESR0LReset: 00
CA
H
Result Register 0 Low
ADC_RESR0HReset: 00
CB
H
Result Register 0 High
ADC_RESR1LReset: 00
CC
H
Result Register 1 Low
ADC_RESR1HReset: 00
CD
H
Result Register 1 High
ADC_RESR2LReset: 00
CE
H
Result Register 2 Low
ADC_RESR2HReset: 00
CF
H
Result Register 2 High
ADC_RESR3LReset: 00
D2
H
Result Register 3 Low
ADC_RESR3HReset: 00
D3
H
Result Register 3 High
RMAP = 0, Page 3
ADC_RESRA0LReset: 00
CA
H
Result Register 0, View A Low
ADC_RESRA0HReset: 00
CB
H
Result Register 0, View A High
ADC_RESRA1LReset: 00
CC
H
Result Register 1, View A Low
ADC_RESRA1HReset: 00
CD
H
Result Register 1, View A High
ADC_RESRA2LReset: 00
CE
H
Result Register 2, View A Low
ADC_RESRA2HReset: 00
CF
H
Result Register 2, View A High
ADC_RESRA3LReset: 00
D2
H
Result Register 3, View A Low
ADC_RESRA3HReset: 00
D3
H
Result Register 3, View A High
RMAP = 0, Page 4
ADC_RCR0Reset: 00
CA
H
Result Control Register 0
ADC_RCR1Reset: 00
CB
H
Result Control Register 1
ADC_RCR2Reset: 00
CC
H
Result Control Register 2
ADC_RCR3Reset: 00
CD
H
Result Control Register 3
ADC_VFCRReset: 00
CE
H
Valid Flag Clear Register
RMAP = 0, Page 5
Bit FieldRESULT[1:0]0VFDRCCHNR
H
Typerhrrhrhrh
Bit FieldRESULT[9:2]
H
Typerh
Bit FieldRESULT[1:0]0VFDRCCHNR
H
Typerhrrhrhrh
Bit FieldRESULT[9:2]
H
Typerh
Bit FieldRESULT[1:0]0VFDRCCHNR
H
Typerhrrhrhrh
Bit FieldRESULT[9:2]
H
Typerh
Bit FieldRESULT[1:0]0VFDRCCHNR
H
Typerhrrhrhrh
Bit FieldRESULT[9:2]
H
Typerh
Bit FieldRESULT[2:0]VFDRCCHNR
H
Typerhrhrhrh
Bit FieldRESULT[10:3]
H
Typerh
Bit FieldRESULT[2:0]VFDRCCHNR
H
Typerhrhrhrh
Bit FieldRESULT[10:3]
H
Typerh
Bit FieldRESULT[2:0]VFDRCCHNR
H
Typerhrhrhrh
Bit FieldRESULT[10:3]
H
Typerh
Bit Field
H
Typerhrhrhrh
Bit Field
H
Typerh
Bit Field
H
Typerwrwrrw
Bit Field VFCTR WFR0IEN0DRCT
H
RESULT[2:0]VFDRCCHNR
RESULT[10:3]
VFCTR WFR0IEN0DRCT
rrw
Typerwrwrrwrrw
Bit Field VFCTR WFR0IEN0DRCT
H
Typerwrwrrwrrw
Bit Field VFCTR WFR0IEN0DRCT
H
Typerwrwrrwrrw
Bit Field0VFC3 VFC2 VFC1 VFC0
H
Typerwwww
R
R
R
R
Data Sheet27 V1.0, 2006-02
XC866
Functional Description
Table 8ADC Register Overview (cont’d)
AddrRegister NameBit76543210
ADC_CHINFRReset: 00
CA
H
Channel Interrupt Flag Register
ADC_CHINCRReset: 00
CB
H
Channel Interrupt Clear Register
CCHADC_CHINSRReset: 00
Channel Interrupt Set Register
ADC_CHINPRReset: 00
CD
H
Channel Interrupt Node Pointer
Register
ADC_EVINFRReset: 00
CE
H
Event Interrupt Flag Register
CFHADC_EVINCRReset: 00
Event Interrupt Clear Flag Register
ADC_EVINSRReset: 00
D2
H
Event Interrupt Set Flag Register
ADC_EVINPRReset: 00
D3
H
Event Interrupt Node Pointer Register
RMAP = 0, Page 6
CAHADC_CRCR1Reset: 00
Conversion Request Control Register 1
ADC_CRPR1Reset: 00
CB
H
Conversion Request Pending
Register 1
ADC_CRMR1Reset: 00
CC
H
Conversion Request Mode Register 1
CDHADC_QMR0Reset: 00
Queue Mode Register 0
CEHADC_QSR0Reset: 20
Queue Status Register 0
CFHADC_Q0R0Reset: 00
Queue 0 Register 0
D2HADC_QBUR0Reset: 00
Queue Backup Register 0
D2HADC_QINR0Reset: 00
Queue Input Register 0
Bit Field CHINF7CHINF6CHINF5CHINF4CHINF3CHINF2CHINF1CHINF
H
Typerhrhrhrhrhrhrhrh
Bit Field CHINC7CHINC6CHINC5CHINC4CHINC3CHINC2CHINC1CHINC
H
Type wwwwwwww
Bit Field CHINS7CHINS6CHINS5CHINS4CHINS3CHINS2CHINS1CHINS
H
Type wwwwwwww
Bit Field CHINP7CHINP6CHINP5CHINP4CHINP3CHINP2CHINP1CHINP
H
Typerwrwrwrwrwrwrwrw
Bit FieldEVINF7EVINF6EVINF5EVINF
H
4
0EVINF1EVINF
Typerhrhrhrhrrhrh
Bit Field EVINC7EVINC6EVINC5EVINC
H
4
0EVINC1EVINC
Type wwwwrww
Bit Field EVINS7EVINS6EVINS5EVINS
H
4
0EVINS1EVINS
Type wwwwrww
Bit Field EVINP7EVINP6EVINP5EVINP
H
4
0EVINP1EVINP
Typerwrwrwrwrrwrw
Bit FieldCH7CH6CH5CH40
H
Type rwhrwhrwhrwhr
Bit FieldCHP7 CHP6 CHP5 CHP40
H
Type rwhrwhrwhrwhr
Bit FieldRsv LDEV CLR
H
SCAN ENSI ENTRENGT
PND
Typerwwrwrwrwrw
Bit Field
H
Type wwwwrwrwrw
Bit Field
H
Typerrrhrhr
Bit Field
H
Typerhrhrhrhrrh
Bit Field
H
Typerhrhrhrhrrh
Bit FieldEXTR ENSIRF0REQCHNR
H
Type wwwrw
CEV TREV FLUSH CLRV TRMD ENTRENGT
Rsv0 EMPTY EV0
EXTR ENSIRFV0REQCHNR
EXTR ENSIRFV0REQCHNR
0
0
0
0
0
0
0
0
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 9Timer 2 Register Overview
AddrRegister NameBit76543210
T2_T2CONReset: 00
C0
H
Timer 2 Control Register
Data Sheet28 V1.0, 2006-02
Bit FieldTF2 EXF20EXEN2 TR20CP/
H
Typerwhrwhrrwrwhrrw
RL2
XC866
Functional Description
Table 9Timer 2 Register Overview (cont’d)
T2_T2MODReset: 00
C1
H
Timer 2 Mode Register
C2HT2_RC2LReset: 00
Timer 2 Reload/Capture Register Low
C3HT2_RC2HReset: 00
Timer 2 Reload/Capture Register High
C4HT2_T2LReset: 00
Timer 2 Register Low
C5HT2_T2HReset: 00
Timer 2 Register High
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10CCU6 Register Overview
AddrRegister NameBit76543210
RMAP = 0
CCU6_PAGEReset: 00
A3
H
Page Register for CCU6
RMAP = 0, Page 0
CCU6_CC63SRLReset: 00
9A
H
Capture/Compare Shadow Regist er for
Channel CC63 Low
CCU6_CC63SRHReset: 00
9B
H
Capture/Compare Shadow Regist er for
Channel CC63 High
CCU6_TCTR4LReset: 00
9C
H
Timer Control Register 4 Low
CCU6_TCTR4HReset: 00
9D
H
Timer Control Register 4 High
CCU6_MCMOUTSLReset: 00
9E
H
Multi-Channel Mode Output Shadow
Register Low
CCU6_MCMOUTSHReset: 00
9F
H
Multi-Channel Mode Output Shadow
Register High
CCU6_ISRLReset: 00
A4
H
Capture/Compare Interrupt Stat us
Reset Register Low
CCU6_ISRHReset: 00
A5
H
Capture/Compare Interrupt Stat us
Reset Register High
CCU6_CMPMODIFLReset: 00
A6
H
Compare State Modification Register
Low
CCU6_CMPMODIFHReset: 00
A7
H
Compare State Modification Register
High
FA
CCU6_CC60SRLReset: 00
H
Capture/Compare Shadow Regist er for
Channel CC60 Low
Bit FieldT2
H
REGST2RHEN
EDGE
PRENT2PREDCEN
SEL
Typerwrwrwrwrwrw
Bit FieldRC2[7:0]
H
Typerwh
Bit FieldRC2[15:8]
H
Typerwh
Bit FieldTHL2[7:0]
H
Typerwh
Bit FieldTHL2[15:8]
H
Typerwh
Bit FieldOPSTNR0PAGE
H
Typewwrrw
Bit FieldCC63SL
H
Typerw
Bit FieldCC63SH
H
Typerw
Bit FieldT12
H
STD
T12
STR
0DTRES T12
RES
T12RS T12RR
Typewwrwwww
Bit FieldT13
H
STD
T13
STR
0T13
RES
T13RS T13RR
Typewwrwww
Bit FieldSTRMCM0MCMPS
H
Typewrrw
Bit Field
H
Typewrrwrw
Bit Field RT12PMRT12OMRCC62FRCC62RRCC61FRCC61RRCC60FRCC60
H
STRHP0CURHSEXPHS
Type wwwwwwww
H
Bit Field
RSTR RIDLE RWHE RCHE0RTRPF RT13PMRT13
Type wwww rwww
Bit Field0MCC63
H
S
0MCC62SMCC61SMCC60
Typerwrwww
Bit Field
H
Typerwr
Bit FieldCC60SL
H
0MCC63
R
0MCC62RMCC61RMCC60
www
Typerwh
R
CM
S
R
Data Sheet29 V1.0, 2006-02
XC866
Functional Description
Table 10CCU6 Register Overview (cont’d)
AddrRegister NameBit76543210
CCU6_CC60SRHReset: 00
FB
H
Capture/Compare Shadow Regist er for
Channel CC60 High
CCU6_CC61SRLReset: 00
FC
H
Capture/Compare Shadow Regist er for
Channel CC61 Low
FDHCCU6_CC61SRHReset: 00
Capture/Compare Shadow Regist er for
Channel CC61 High
CCU6_CC62SRLReset: 00
FE
H
Capture/Compare Shadow Regist er for
Channel CC62 Low
CCU6_CC62SRHReset: 00
FF
H
Capture/Compare Shadow Regist er for
Channel CC62 High
Capture/Compare Interrupt Node
Pointer Register High
CCU6_ISSLReset: 00
A4
H
Capture/Compare Interrupt Stat us Set
Register Low
CCU6_ISSHReset: 00
A5
H
Capture/Compare Interrupt Stat us Set
Register High
A6HCCU6_PSLRReset: 00
Passive State Level Register
A7HCCU6_MCMCTRReset: 00
Multi-Channel Mode Control Register
FAHCCU6_TCTR2LReset: 00
Timer Control Register 2 Low
CCU6_TCTR2HReset: 00
FB
H
Timer Control Register 2 High
CCU6_MODCTRLReset: 00
FC
H
Modulation Control Register Low
CCU6_MODCTRHReset: 00
FD
H
Modulation Control Register High
CCU6_TRPCTRLReset: 00
FE
H
Trap Control Register Low
Bit FieldCC61VH
H
Typerh
Bit FieldCC62VL
H
Typerh
Bit FieldCC62VH
H
Typerh
Bit Field
H
Typerw
Bit FieldDBYPHSYNCMSEL62
H
MSEL61MSEL60
rw
Typerwrwrw
Bit Field ENT12PMENT12OMENCC
H
62F
ENCC
62R
ENCC
61F
ENCC
61R
ENCC
60F
Typerwrwrwrwrwrwrwrw
Bit Field ENSTR EN
H
IDLEENWHEENCHE
0EN
TRPF
ENT13PMENT13
Typerwrwrwrwrrwrwrw
Bit FieldINPCHEINPCC62INPCC61INPCC60
H
Typerwrwrwrw
Bit Field0INPT13INPT12INPERR
H
Typerrwrwrw
Bit Field ST12PMST12OMSCC62FSCC62RSCC61FSCC61RSCC60FSCC60
H
Type wwwwwwww
Bit FieldSSTR SIDLE SWHE SCHE SWHC STRPF ST13PMST13
H
Type wwwwwwww
Bit Field
H
Typerwhrrwh
Bit Field
H
Typerrwrrw
Bit Field
H
Typerrwrw
Bit Field
H
Typerrwrw
Bit FieldMC
H
PSL630PSL
0SWSYN0SWSEL
0T13TEDT13TECT13
0T13RSELT12RSEL
0T12MODEN
MEN
SSC
rwrw
Typerwrrw
Bit Field ECT13O0T13MODEN
H
Typerwrrw
Bit Field0TRPM2 TRPM1 TRPM0
H
Typerrwrwrw
ENCC
60R
CM
R
CM
T12
SSC
Data Sheet31 V1.0, 2006-02
XC866
Functional Description
Table 10CCU6 Register Overview (cont’d)
AddrRegister NameBit76543210
CCU6_TRPCTRHReset: 00
FF
H
Trap Control Register High
RMAP = 0, Page 3
CCU6_MCMOUTLReset: 00
9A
H
Multi-Channel Mode Output Register
Low
CCU6_MCMOUTHReset: 00
9B
H
Multi-Channel Mode Output Register
High
CCU6_ISLReset: 00
9C
H
Capture/Compare Interrupt Stat us
Register Low
CCU6_ISHReset: 00
9D
H
Capture/Compare Interrupt Stat us
Register High
CCU6_PISEL0LReset: 00
9E
H
Port Input Select Register 0 Low
9F
CCU6_PISEL0HReset: 00
H
Port Input Select Register 0 High
CCU6_PISEL2Reset: 00
A4
H
Port Input Select Register 2
CCU6_T12LReset: 00
FA
H
Timer T12 Counter Register Low
CCU6_T12HReset: 00
FB
H
Timer T12 Counter Register High
CCU6_T13LReset: 00
FC
H
Timer T13 Counter Register Low
CCU6_T13HReset: 00
FD
H
Timer T13 Counter Register High
CCU6_CMPSTATLReset: 00
FE
H
Compare State Register Low
CCU6_CMPSTATHReset: 00
FF
H
Compare State Register High
Bit Field TRPPENTRPEN
H
13
TRPEN
Typerwrwrw
Bit Field0RMCMP
H
Typerrhrh
Bit Field
H
Typerrh
Bit Field
H
Typerhrhrhrh
Bit FieldSTR ID LE WHE CHE TRPS TRPF T13PM T13CM
H
0CURHEXPH
rh
T12PM T12OM ICC62 F ICC62RICC61F ICC61RICC60F ICC60
rhrhrhrh
Typerhrhrhrhrhrhrhrh
Bit FieldISTRPISCC62ISCC61ISCC60
H
Typerwrwrwrw
Bit FieldIST12HRISPOS2ISPOS1ISPOS0
H
Typerwrwrwrw
Bit Field0IST13HR
H
Typerrw
Bit FieldT12CVL
H
Typerwh
Bit FieldT12CVH
H
Typerwh
Bit FieldT13CVL
H
Typerwh
Bit FieldT13CVH
H
Typerwh
Bit Field
H
Type r rhrhrh
Bit FieldT13IM COUT
H
0CC63STCCPOS2CCPOS1CCPOS0CC62STCC61STCC60
rhrhrhrh
COUT
63PS
62PS
CC62PSCOUT
61PS
CC61PSCOUT
60PS
Type rwhrwhrwhrwhrwhrwhrwhrwh
R
ST
CC60
PS
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 11SSC Register Overview
AddrRegister NameBit76543210
RMAP = 0
SSC_PISELReset: 00
A9
H
Port Input Select Register
SSC_CONLReset: 00
AA
H
Control Register Low
Programming Mode
Operating ModeBit Field0BC
Data Sheet32 V1.0, 2006-02
Bit Field0CISSISMIS
H
Typerrwrwrw
Bit FieldLBPOPHHBBM
H
Typerwrwrwrwrw
Typerrh
XC866
Functional Description
Table 11SSC Register Overview
SSC_CONHReset: 00
AB
H
Control Register High
Programming Mode
Operating ModeBit FieldENMS0BSYBEPERETE
ACHSSC_TBLReset: 00
Transmitter Buffer Register Low
ADHSSC_RBLReset: 00
Receiver Buffer Register Low
AEHSSC_BRLReset: 00
Baudrate Timer Reload Register Low
AFHSSC_BRHReset: 00
Baudrate Timer Reload Register High
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 12OCDS Register Overview
AddrRegister NameBit76543210
RMAP = 1
MMCR2Reset: 0U
E9
H
Monitor Mode Control Register 2
MMCRReset: 00
F1
H
Monitor Mode Control Register
F2
MMSRReset: 00
H
Monitor Mode Status Register
MMBPCRReset: 00
F3
H
BreakPoints Control Register
MMICRReset: 00
F4
H
Monitor Mode Interrupt Control Register
F5
MMDRReset: 00
H
Monitor Mode Data Register
Receive
TransmitBit Field
HWBPSRReset: 00
F6
H
Hardware Breakpoints Select Register
HWBPDRReset: 00
F7
H
Hardware Breakpoints Data Register
Bit FieldENMS0AREN BENPEN REN TEN
H
Typerwrwrrwrwrwrwrw
Typerwrwrrhrwhrwhrwhrwh
Bit FieldTB_VALUE
H
Typerw
Bit FieldRB_VALUE
H
Typerh
Bit FieldBR_VALUE[7:0]
H
Typerw
Bit FieldBR_VAL UE[15:8]
H
Typerw
Bit Field EXBC_PEXBC MBCO
H
MBCONMMEP_PMMEP MMODEJENA
N_P
Typewrwwrwhwrwhrhrh
Bit Field MEXIT_PMEXIT MSTEP_PMSTEP MRAM
H
MRAMSTRFRRF
S_P
Typewrwhwrwwrwhrhrh
Bit FieldMBCAMMBCIN EXBF SWBF HWB3FHWB2FHWB1FHWB0
H
Typerwrhrwhrwhrw hrwhrwhrwh
Bit Field SWBCHWB3CHWB2CHWB1CHWB0C
H
Typerwrwrwrwrw
Bit Field DVECT DRETR0MMUIE_PMMUIE RRIE_PRRIE
H
Typerwhrwhrwrwwrw
H
Bit Field
MMRR
Typerh
MMTR
Typew
H
Bit Field
0BPSEL
Typerw
Bit FieldHWBPxx
H
Typerw
_P
BPSEL
rw
F
Data Sheet33 V1.0, 2006-02
XC866
Functional Description
3.3Flash Memory
The Flash memory provides an embedded user-programmable non-volatile memory,
allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V
supply from the Embedded Voltage Regulator (EVR) and does not require additional
programming or erasing voltage. The sectorization of the Flash memory allows each
sector to be erased independently.
Features:
• In-System Programming (ISP) via UART
• In-Application Programming (IAP)
• Error Correction Code (ECC) for dynamic correction of single-bit errors
• Background program and erase operations for CPU load minimization
• Support for aborting erase operation
• 32-byte minimum program width
• 1-sector minimum erase width
• 1-byte read access
• 121.6 ns minimum read access time (3 × t
• Operating supply voltage: 2.5 V ± 7.5 %
• Program time: 2.3 ms
• Erase time: 120 ms
3)
3)
1)
CCLK
@ f
=26.7MHz±7.5%2))
CCLK
Table 13Flash Data Retention and Endurance Targets
Retention up toEndurance up toProgramming
Size
Temperature
20 years
5 years
2 years
2 years
1)
2)
3)
4)
5)
4)
4)
4)
4)
P-Flash: 32-byte wordline can only be programmed once, i.e., one gate disturb allowed.
D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed.
f
=80MHz±7.5% (f
sys
f
= 80 MHz ± 7.5% is the only frequency range for Flash programming and erasing. f
sys
obtaining the worst case timing.
Specification with 0.2ppm error rate.
One cycle refers to the programming of all wordlines in a sector and erasing of the sector.
1,000 cycles
10,000 cycles
70,000 cycles
100,000 cycles
= 26.7 MHz ± 7.5 %) is the maximum frequency range for Flash read access.
CCLK
Data Sheet34 V1.0, 2006-02
5)
5)
5)
5)
0 – 100°C15 Kbytes
-40 – 125°C896 bytes
-40 – 125°C512 bytes
-40 – 125°C128 bytes
sysmin
is used for
XC866
Functional Description
3.3.1Flash Bank Sectorization
The XC866 product family offers four Flash devices with either 8 Kbytes or 16 Kbytes of
embedded Flash memory. These Flash memory sizes are made up of two or four
4-Kbyte Flash banks, respectively. Each Flash device consists of Program Flash
(P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization
shown in Figure 10. Both types can be used for code and data storage. The label “Data”
neither implies that the D-Flash is mapped to the data memory region, nor that it can only
be used for data storage. It is used to distinguish the different Flash bank sectorizations.
The XC866 ROM devices offer a single 4-Kbyte D-Flash bank.
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
be erased separately or in parallel. Contrary to standard EPROMs, erased Flash
memory cells contain 0s.
The D-Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
Data Sheet35 V1.0, 2006-02
XC866
Functional Description
3.3.2Flash Programming Width
For the P-Flash banks, a programmed wordline (WL) must be erased before it can be
reprogrammed as the Flash cells can only withstand one gate disturb. This means that
the entire sector containing the WL must be erased since it is impossible to erase a
single WL.
For the D-Flash bank, the same WL can be programmed twice before erasing is required
as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to
program the same WL, for example, with 16 bytes of data in two times (see Figure 11).
0000 ….. 0000
0000 ….. 0000
1111 ….. 0000
32 bytes (1 WL)
0000 ….. 0000
H
1111 ….. 1111
H
1111 ….. 1111
H
Progr am 1
H
Progr am 2
H
H
16 bytes16 bytes
0000 ….. 0000
1111 ….. 0000
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
H
H
1111 ….. 1111
0000 ….. 0000
H
H
Flash memory cells32-byte write buffers
Figure 11D-Flash Programming
Note: When programming a D-Flash WL the second time, the previously programmed
Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain
its original contents and to prevent “over-programming”.
Data Sheet36 V1.0, 2006-02
XC866
Functional Description
3.4Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC866 interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and determining the interrupt
source.
3.4.1Interrupt Source
Figure 12 to Figure 16 give a general overview of the interrupt sources and illustrates
the request and control flags.
WDT O verflow
PLL Loss of Lock
Flash O peration
Complete
VDD Pr e-Warning
VDDP P re-WarningFNMIVDDP
Flash E CC Error
FNMIWDT
NMIISR.0
FNMIPLL
NMIISR.1
FNMIFLASH
NMIISR.2
FNMIVDD
NMIISR.4
NMIISR.5
FNMIECC
NMIISR.6
NMIWDT
NMICON.0
NMIPLL
NMICON.1
NMIFLASH
NMIVDD
NMICON.4
NMIVDDP
NMICON.5
NMIECC
NMICON.6
Figure 12Non-Maskable Interrupt Request Sources
>=1
0073
Non
Maskab le
H
Interrupt
Data Sheet37 V1.0, 2006-02
XC866
Functional Description
Highest
EINT0
EINT1
Timer 0
Overflow
Timer 1
Overflow
UART
EXINT0
EXICON0.0/1
EXINT 1
EXICON0.2/3
EXINT0
IRCON0.0
EXINT1
IRCON0.1
Bit-addressable
RI
SCON.0
TI
SCON.1
IT0
TCON.0
IT1
TCON.2
TF0
TCON.5
TF1
TCON.7
>=1
IE0
TCON.1
IE1
TCON.3
ET0
IEN0.1
ET1
IEN0.3
ES
IEN0.4
EX0
IEN0.0
EX1
IEN0.2
000B
001B
0023
0003
0013
EA
IEN 0.7
Lowest
H
IP.1/
IPH.1
H
IP.3/
IPH.3
Priority Level
P
o
l
l
i
n
g
H
IP.4/
IPH.4
S
e
q
u
e
n
c
e
H
IP.0/
IPH.0
H
IP.2/
IPH.2
Request flag is cleared by hardware
Figure 13Interrupt Request Sources (Part 1)
Data Sheet38 V1.0, 2006-02
XC866
Functional Description
Timer 2
Overflow
T2EX
EXEN2
EDGES
EL
T2MOD.5
End of
Syn Byte
Syn Byte Error
EINT2
EINT3
EINT4
EINT5
EINT6
T2CON.3
Normal Divider
Overfl ow
EOFSYN
FDCON.4
ERRSYN
FDCON.5
EXINT3
EXICON0.6/7
EXINT4
EXICON1.0/1
EXINT5
EXICON1.2/3
EXINT6
EXICON1.4/5
EXINT2
EXICON0.4/5
Bit-addressable
Request flag is cleared by hardware
TF2
T2CON.7
EXF2
T2CON.6
NDOV
FDCON.2
SYNEN
FDCON.6
EXINT3
IRCON0.3
EXINT4
IRCON0.4
EXINT5
IRCON0.5
EXINT6
IRCON0.6
>=1
EXINT2
IRCON0.2
>=1
002B
ET2
IEN0.5
EX2
IEN1.2
EXM
IEN1.3
0043
004B
H
IP.5/
IPH.5
H
IP1.2/
IPH1.2
H
IP1.3/
IPH1.3
EA
IEN0 .7
Bit-addressable
Request flag is cleared by hardware
Highest
Lowest
Priority Level
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
Figure 14Interrupt Request Sources (Part 2)
Data Sheet39 V1.0, 2006-02
ADC_SRC0
ADC_SRC1
ADCSRC0
IRCON1.3
ADCSRC1
IRCON1.4
>=1
EADC
IEN1.0
0033
Functional Description
H
IP1. 0/
IPH1.0
XC866
Highest
Lowest
Priority Level
SSC_EIR
SSC_TIR
SSC_RIR
Captu re/C ompare
interrupt node 0
Captu re/C ompare
interrupt node 1
Captu re/C ompare
interrupt node 2
Captu re/C ompare
interrupt node 3
Bit-addressable
Request flag is cleared by hardware
EIR
IRCON1.0
IRCON1.1
RIR
IRCON1.2
>=1TIR
ESSC
IEN1.1
003B
H
IP1. 1/
IPH1.1
P
o
l
l
i
n
g
ECCIP0
IEN1.4
ECCIP1
IEN1.5
ECCIP2
IEN1.6
ECCIP3
IEN1.7
005B
0063
006B
H
IP1. 4/
IPH1.4
H
IP1. 5/
IPH1.5
H
IP1. 6/
IPH1.6
H
IP1.7/
IPH1.7
S
e
q
u
e
n
c
e
0053
EA
IEN0.7
Figure 15Interrupt Request Sources (Part 3)
Data Sheet40 V1.0, 2006-02
0
1
2
3
CC60
CC61
CC62
T12
One matc h
T12
Period match
T13
Compare mat ch
T13
Period match
CTRAP
Wrong Hal l
Event
Correct Hall
Event
Multi -Channel
Shadow
Transfer
ICC60R
ISL.0
ICC 60F
ISL.1
ICC61R
ISL.2
ICC 61F
ISL.3
ICC62R
ISL.4
ICC 62F
ISL.5
T12OM
ISL.6
T12PM
ISL.7
T13CM
ISH.0
T13PM
ISH.1
TRPF
ISH.2
WHE
ISH.5
CHE
ISH.4
STR
ISH.7
ENCC60R
IENL.0
ENC C60F
IENL.1
ENCC61R
IENL.2
ENC C61F
IENL.3
ENCC62R
IENL.4
ENC C62F
IENL.5
ENT 12OM
IENL.6
ENT 12PM
IENL.7
ENT 13CM
IENH.0
ENT 13PM
IENH.1
ENTRPF
IENH.2
ENWHE
IENH.5
ENCHE
IENH.4
ENSTR
IENH.7
XC866
Functional Description
>=1
INPL.1 INPL.0
>=1
INPL.3 INPL.2
>=1
INPL.5 INPL.4
>=1
INPH.3 INPH.2
>=1
INPH.5 INPH.4
>=1
INPH.1 INPH.0
>=1
INPL.7 INPL.6
CCU6 Interrupt node
CCU6 Interrupt node
CCU6 Interrupt node
CCU6 Interrupt node
Figure 16Interrupt Request Sources (Part 4)
Data Sheet41 V1.0, 2006-02
XC866
Functional Description
3.4.2Interrupt Source and Vector
Each interrupt source has an associated interrupt vector address. This vector is
accessed to service the corresponding interrupt source request. The interrupt service of
each interrupt source can be individually enabled or disabled via an enable bit. The
assignment of the XC866 interrupt sources to the interrupt vector addresses and the
corresponding interrupt source enable bits are summarized in Table 14.
Table 14Interrupt Vector Addresses
Interrupt
Source
Vector
Address
NMI0073
XINTR00003
XINTR1000B
XINTR20013
XINTR3001B
XINTR40023
XINTR5002B
Assignment for XC866Enable BitSFR
H
Watchdog Timer NMINMIWDTNMICON
PLL NMINMIPLL
Flash NMINMIFLASH
VDDC Prewarning NMINMIVDD
VDDP Prewarning NMINMIVDDP
Flash ECC NMINMIECC
H
H
H
H
H
H
External Interrupt 0EX0IEN0
Timer 0ET0
External Interrupt 1EX1
Timer 1ET1
UARTES
T2ET2
Fractional Divider
(Normal Divider Overflow)
LIN
Data Sheet42 V1.0, 2006-02
Table 14Interrupt Vector Addresses (cont’d)
XC866
Functional Description
XINTR60033
XINTR7003B
XINTR80043
XINTR9004B
XINTR100053
XINTR11005B
XINTR120063
XINTR13006B
H
H
H
H
ADCEADCIEN1
SSCESSC
External Interrupt 2EX2
External Interrupt 3EXM
External Interrupt 4
External Interrupt 5
External Interrupt 6
H
H
H
H
CCU6 INP0ECCIP0
CCU6 INP1ECCIP1
CCU6 INP2ECCIP2
CCU6 INP3ECCIP3
Data Sheet43 V1.0, 2006-02
XC866
Functional Description
3.4.3Interrupt Priority
Each interrupt source, except for NMI, can be individually programmed to one of the four
possible priority levels. The NMI has the highest priority and supersedes all other
interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are
available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in Table 15.
Table 15Priority Structure within Interrupt Level
SourceLevel
Non-Maskable Interrupt (NMI)(highest)
External Interrupt 01
Timer 0 Interrupt2
External Interrupt 13
Timer 1 Interrupt4
UART Interrupt5
Timer 2,Fractional Divider, LIN Interrupts 6
ADC Interrupt7
SSC Interrupt8
External Interrupt 29
External Interrupt [6:3] 10
CCU6 Interrupt Node Pointer 011
CCU6 Interrupt Node Pointer 112
CCU6 Interrupt Node Pointer 213
CCU6 Interrupt Node Pointer 314
Data Sheet44 V1.0, 2006-02
XC866
Functional Description
3.5Parallel Ports
The XC866 has 27 port pins organized into four parallel ports, Port 0 (P0) to Port 3 (P3).
Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1 and P3 are bidirectional and can be used as general
purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip
peripherals. When configured as an output, the open drain mode can be selected. Port
P2 is an input-only port, providing general purpose input functions, alternate input
functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital
Converter (ADC).
Bidirectional Port Features:
• Configurable pin direction
• Configurable pull-up/pull-down devices
• Configurable open drain mode
• Transfer of data through digital inputs and outputs (general purpose I/O)
• Alternate input/output for on-chip peripherals
Input Port Features:
• Configurable input driver
• Configurable pull-up/pull-down devices
• Receive of data through digital input (general purpose input)
• Alternate input for on-chip peripherals
• Analog input for ADC module
Data Sheet45 V1.0, 2006-02
XC866
Functional Description
Internal Bus
AltDat aOut 3
AltDat aOut 2
AltDat aOut1
AltDat aIn
Px_PUD SEL
Pull-up /Pull- down
Select Reg ister
Px_PUDEN
Pull-up /Pull-down
Enable Register
Px_OD
Open Drain
Control Register
Px_DIR
Direction Register
Px_AL TSEL0
Alter nate Sele ct
Register 0
Px_AL TSEL1
Alter nate Sele ct
Register 1
Px_Dat a
Data Register
VDDP
Pull
enable
Up
Device
11
10
01
00
Out
In
enable
enable
Schmit t T rigger
Output
Driver
Input
Driver
enable
Pull
Down
Device
Pin
Pad
Figure 17General Structure of Bidirectional Port
Data Sheet46 V1.0, 2006-02
XC866
Functional Description
Internal Bus
AltDataIn
AnalogIn
Px_PUDSEL
Pull- up/Pul l-down
Select Regist er
Px_PUDEN
Pull- up/Pul l-down
Enable Regi st er
Px_DIR
Dir ect ion Regist er
Px _ DATA
Data Regis ter
In
enable
Schmitt Trigger
Figure 18General Structure of Input Port
Input
Dri ve r
enable
enable
VDDP
Pull
Up
Device
Pull
Down
Device
Pin
Pad
Data Sheet47 V1.0, 2006-02
XC866
Functional Description
3.6Power Supply System with Embedded Voltage Regulator
The XC866 microcontroller requires two different levels of power supply:
• 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports
• 2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 19 shows the XC866 power supply system. A power supply of 3.3 V or 5.0 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps to reduce the power consumption of the
whole chip and the complexity of the application board design.
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
CPU &
Memory
On-chip
OSC
Peripheral
logic
ADC
V
(2.5V)
DDC
FLASH
PLL
XTAL1&
GPIO Ports
(P0-P 3)
EVR
V
DDP
V
SSP
XTAL2
(3.3V/5.0V)
Figure 19XC866 Power Supply System
EVR Features:
• Input voltage (V
• Output voltage (V
): 3.3 V/5.0 V
DDP
): 2.5 V ± 7.5%
DDC
• Low power voltage regulator provided in power-down mode
• V
• V
and V
DDC
DDC
DDP
brownout detection
prewarning detection
Data Sheet48 V1.0, 2006-02
XC866
Functional Description
3.7Reset Control
The XC866 has five types of reset: power-on reset, hardware reset, watchdog timer
reset, power-down wake-up reset, and brownout reset.
When the XC866 is first powered up, the status of certain pins (see Table 17) must be
defined to ensure proper start operation of the device. At the end of a reset sequence,
the sampled values are latched to select the desired boot option, which cannot be
modified until the next power-on reset or hardware reset. This guarantees stable
conditions during the normal operation of the device.
In order to power up the system properly, the external reset pin RESET must be asserted
until V
reaches 0.9*V
DDC
capacitor at RESET pin. This capacitor value must be selected so that V
0.4 V, but not before V
A typical application example is shown in Figure 20. For a voltage regulator with IDD
= 100 mA, the V
DDP
capacitor connected to RESET pin is 100 nF.
Typically, the time taken for V
reaches 2.3V. Hence, based on the condition that 10% to 90% V
than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 21.
. The delay of external reset can be realized by an external
DDC
reaches 0.9* V
DDC
capacitor value is 10 µF. V
DDC
DDC.
to reach 0.9*V
capacitor value is 220 nF. The
DDC
is less than 50 µs once V
DDC
(slew rate) is less
DDP
RESET
reaches
max
DDP
Vin
typ.
100nF
VR
3.3V/5V
e.g. 100mA
VSSP VDDP
RESET
/
e.g. 10uF
220nF
VDDCVSSC
EVR
30k
XC866
Figure 20Reset Circuitry
Data Sheet49 V1.0, 2006-02
XC866
h
Functional Description
Voltage
5V
VDDP
2.5V
2.3V
0.9*VDDC
Voltage
5V
< 0.4V
0V
Figure 21V
ty p. < 50 us
DDP, VDDC
and V
during Power-on Reset
RESET
VDDC
Time
RESET wit
capac itor
Time
The second type of reset in XC866 is the hardware reset. This reset function can be used
during normal operation or when the chip is in power-down mode. A reset input pin
is provided for the hardware reset.
RESET
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is a reset while the device is in
power-down mode (wake-up reset). While the contents of the static RAM are undefined
after a power-on reset, they are well defined after a wake-up reset from power-down
mode.
Data Sheet50 V1.0, 2006-02
XC866
Functional Description
3.7.1Module Reset Behavior
Table 16 shows how the functions of the XC866 are affected by the various reset types.
A “ ” means that this function is reset to its default state.
Table 16Effect of Reset on Device Functions
Module/
Function
CPU Core
Peripherals
On-Chip
Static RAM
Oscillator,
PLL
Port Pins
EVRThe voltage
FLASH
NMI DisabledDisabled
Wake-Up
Reset
Not affected,
reliable
regulator is
switched on
Watchdog
Reset
Not affected,
reliable
Not affected
Not affected
Hardware
Reset
Not affected,
reliable
Power-On
Reset
Affected, un-
reliable
Brownout
Reset
Affected, un-
reliable
3.7.2Booting Scheme
When the XC866 is reset, it must identify the type of configuration with which to start the
different modes once the reset sequence is complete. Thus, boot configuration
information that is required for activation of special modes and conditions needs to be
applied by the external world through input pins. After power-on reset or hardware reset,
the pins MBC, TMS and P0.0 collectively select the different boot options. Table 17
shows the available boot options in the XC866.
Table 17XC866 Boot Selection
MBCTMS P0.0Type of ModePC Start Value
10xUser Mode; on-chip OSC/PLL non-bypassed 0000
00xBSL Mode; on-chip OSC/PLL non-bypassed 0000
010OCDS Mode; on-chip OSC/PLL non-
bypassed
110Standalone User (JTAG) Mode1); on-chip
OSC/PLL non-bypassed (normal)
1)
Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose.
Data Sheet51 V1.0, 2006-02
0000
0000
H
H
H
H
XC866
Functional Description
3.8Clock Generation Unit
The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the
XC866. The power consumption is indirectly proportional to the frequency, whereas the
performance of the microcontroller is directly proportional to the frequency. During user
program execution, the frequency can be programmed for an optimal ratio between
performance and power consumption. Therefore the power consumption can be
adapted to the actual application state.
Features:
• Phase-Locked Loop (PLL) for multiplying clock source by different factors
• PLL Base Mode
• Prescaler Mode
• PLL Mode
• Power-down mode support
The CGU consists of an oscillator circuit and a PLL.In the XC866, the oscillator can be
from either of these two sources: the on-chip oscillator (10 MHz) or the external oscillator
(3 MHz to 12 MHz). The term “oscillator” is used to refer to both on-chip oscillator and
external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be
used by default.The external oscillator can be selected via software. In addition, the PLL
provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows
emergency routines to be executed for system recovery or to perform system shut down.
OSC
fosc
P:1
OSCDISC
fp
fn
osc fail
detec t
lock
detec t
PLL
core
N:1
NDIV
fvco
K:1
PLLBYP
VCOBYP
OSCR
LOCK
fsys
Figure 22CGU Block Diagram
Data Sheet52 V1.0, 2006-02
XC866
Functional Description
Direct Drive (PLL Bypass Operation)
During PLL bypass operation, the system clock has the same frequency as the external
clock source. For the XC866, the PLL bypass cannot be set active. Hence, the direct
drive mode is not available for use.
f
=
SYSfOSC
PLL Base Mode
The system clock is derived from the VCO base frequency clock divided by the K factor.
Both VCO bypass and PLL bypass must be inactive for this PLL mode.
1
×=
--- -
×=
K
1
-------------
PK×
f
SYSfVCObase
Prescaler Mode (VCO Bypass Operation)
In VCO bypass operation, the system clock is derived from the oscillator clock, divided
by the P and K factors.
f
SYSfOSC
PLL Mode
The system clock is derived from the oscillator clock, multiplied by the N factor, and
divided by the P and K factors. Both VCO bypass and PLL bypass must be inactive for
this PLL mode. The PLL mode is used during normal system operation. .
N
-------------
f
SYSfOSC
×=
PK×
System Frequency Selection
For the XC866, the values of P and K are fixed to “1” and “2”, respectively. In order to
obtain the required system frequency, f
for different oscillator inputs. Table 18 provides examples on how f
, the value of N can be selected by bit NDIV
sys
= 80 MHz can be
sys
obtained for the different oscillator sources.
Table 18System frequency (f
=80MHz)
sys
OscillatorfoscNPKfsys
On-chip10 MHz 16 12 80 MHz
Data Sheet53 V1.0, 2006-02
XC866
Functional Description
Table 18System frequency (f
=80MHz)
sys
OscillatorfoscNPKfsys
External 10 MHz16 12 80 MHz
8 MHz20 12 80 MHz
5 MHz32 12 80 MHz
Table 19 shows the VCO range for the XC866.
Table 19VCO Range
f
VCOmin
f
VCOmax
f
VCOFREEmin
f
VCOFREEmax
Unit
1502002080MHz
1001501080MHz
3.8.1Resonator Circuitry
Figure 23 shows the recommended ceramic resonator circuitry. When using an external
resonator, its frequency can be within the range of 3 MHz to 12 MHz. A resonator load
circuitry must be used, connected to both pins, XTAL1 and XTAL2. It normally consists
of two load capacitances C
and C2, and in some cases, a feedback (Rf) and/or damp
1
(Rd) resistor might be necessary.
C
1
XTAL1
Ceramic
Resonator
C
2
R
f
R
d
XC866
XTAL2
Figure 23External Ceramic Resonator Circuitry
Note: The manufacturer of the ceramic resonator should check the resonator circuitry
and make recommendations for the C1, C2, Rf and Rd values to be used for stable
start-up behavior.
Data Sheet54 V1.0, 2006-02
XC866
Functional Description
3.8.2Clock Management
The CGU generates all clock signals required within the microcontroller from a single
clock, f
modules are as follow:
In addition, different clock frequency can output to pin CLKOUT(P0.0). The clock output
frequency can further be divided by 2 using toggle latch (bit TLEN is set to 1), the
resulting output frequency has 50% duty cycle. Figure 24 shows the clock distribution of
the XC866.
. During normal system operation, the typical frequencies of the different
sys
CLKREL
OSC
fosc
PLL
N,P,K
fsys
Figure 24Clock Generation from f
COREL
sys
/3
TLEN
Toggl e
Latch
CCLK3
FCLK
PCLK
SCLK
CCLK
CCU6
Peripherals
CORE
FLASH
Interface
COUTS
CLKOUT
Data Sheet55 V1.0, 2006-02
XC866
Functional Description
For power saving purposes, the clocks may be disabled or slowed down according to
Table 20.
Table 20System frequency (f
Power Saving Mode Action
IdleClock to the CPU is disabled.
Slow-downClocks to the CPU and all the peripherals, including CCU6, are
divided by a common programmable factor defined by bit field
CMCON.CLKREL.
Power-downOscillator and PLL are switched off.
=80MHz)
sys
Data Sheet56 V1.0, 2006-02
XC866
Functional Description
3.9Power Saving Modes
The power saving modes of the XC866 provide flexible power consumption through a
combination of techniques, including:
• Stopping the CPU clock
• Stopping the clocks of individual system components
• Reducing clock speed of some peripheral components
• Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 25) and the system runs in the main system clock frequency. From active mode,
different power saving modes can be selected by software. They are:
• Idle mode
• Slow-down mode
• Power-down mode
any interrupt
& SD=0
set IDLE
bit
IDLE
set IDLE
bit
any interrupt
& SD=1
ACTIVE
set SD
bit
SLOW-DOWN
clear SD
bit
EXINT0/RXD pin
& SD=0
set PD
bit
POWER-DOWN
set PD
bit
EXINT0/RXD pin
& SD=1
Figure 25 Transition between Power Saving Modes
Data Sheet57 V1.0, 2006-02
XC866
T
Functional Description
3.10Watchdog Timer
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC866 system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC866 will be aborted in a user-specified time period. In debug mode, the WDT is
suspended and stops counting. Therefore, there is no need to refresh the WDT during
debugging.
Features:
• 16-bit Watchdog Timer
• Programmable reload value for upper 8 bits of timer
• Programmable window boundary
• Selectable input frequency of f
PCLK
/2 or f
• Time-out detection with NMI generation and reset prewarning activation (after which
a system reset will be performed)
PCLK
/128
The WDT is a 16-bit timer incremented by a count rate of f
PCLK
/2 or f
PCLK
/128. This
16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT
can be preset to a user-programmable value via a watchdog service access in order to
modify the watchdog expire time period. The lower 8 bits are reset on each service
access. Figure 26 shows the block diagram of the WDT unit.
ENW DT
ENW DT_P
WDT
Control
1:2
MUX
f
PCLK
Logic
1:128
WDTIN
Clear
WDT Low By te
Overflow/Tim e-out C ontrol &
Window-boundary cont rol
WDTREL
WDT Hi gh Byte
WDTTO
WDTRS
WDT WIN B
Figure 26WDT Block Diagram
Data Sheet58 V1.0, 2006-02
XC866
Functional Description
If the WDT is not serviced before the timer overflow, a system malfunction is assumed.
As a result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is
entered. The prewarning period lasts for 30H count, after which the system is reset
(assert WDTRST).
The WDT has a “programmable window boundary” which disallows any refresh during
the WDT’s count-up. A refresh during this window boundary constitutes an invalid
access to the WDT, causing the reset prewarning to be entered but without triggering the
WDT NMI. The system will still be reset after the prewarning period is over. The window
boundary is from 0000
.
00
H
After being serviced, the WDT continues counting up from the value (<WDTREL> * 2
The time period for an overflow of the WDT is programmable in two ways:
• the input frequency to the WDT can be selected to be either f
• the reload value WDTREL for the high byte of WDT can be programmed in register
WDTREL
to the value obtained from the concatenation of WDTWINB and
H
PCLK
/2 or f
PCLK
/128
8
).
The period, P
, between servicing the WDT and the next overflow can be determined
If the Window-Boundary Refresh feature of the WDT is enabled, the period P
2
f
PCLK
16
WDTREL–2
×()×
8
WDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL, see Figure 27. This period can be calculated using the same formula by
replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB should not
be smaller than WDTREL.
Count
FFFF
H
WDTWINB
WDTREL
No refresh
allowed
Refresh allowed
time
Figure 27WDT Timing Diagram
Data Sheet59 V1.0, 2006-02
XC866
Functional Description
Table 21 lists the possible watchdog time range that can be achieved for different
module clock frequencies . Some numbers are rounded to 3 significant digits.
Table 21Watchdog Time Ranges
Reload value
in WDTREL
FF
H
7F
H
00
H
Prescaler for f
PCLK
2 (WDTIN = 0)128 (WDTIN = 1)
26.7 MHz26.7 MHz
19.2 µs1.23 ms
2.48 ms159 ms
4.92 ms315 ms
Data Sheet60 V1.0, 2006-02
XC866
Functional Description
3.11Universal Asynchronous Receiver/Transmitter
The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex
asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously. It is
also receive-buffered, i.e., it can commence reception of a second byte before a
previously received byte has been read from the receive register. However, if the first
byte still has not been read by the time reception of the second byte is complete, one of
the bytes will be lost.
Features:
• Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
• Receive buffered
• Multiprocessor communication
• Interrupt generation on the completion of a data transmission or reception
The UART can operate in four asynchronous modes as shown in Table 22. Data is
transmitted on TXD and received on RXD.
Table 22UART Modes
Operating ModeBaud Rate
Mode 0: 8-bit shift registerf
Mode 1: 8-bit shift UARTVariable
Mode 2: 9-bit shift UARTf
Mode 3: 9-bit shift UARTVariable
PCLK
PCLK
/2
/32 or f
PCLK
/64
There are several ways to generate the baud rate clock for the serial port, depending on
the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at
/2. In mode 2, the baud rate is generated internally based on the UART input clock
f
PCLK
and can be configured to either f
PCLK
/32 or f
/64. The variable baud rate is set by
PCLK
either the underflow rate on the dedicated baud-rate generator, or by the overflow rate
on Timer 1.
Data Sheet61 V1.0, 2006-02
XC866
Functional Description
3.11.1Baud-Rate Generator
The baud-rate generator is based on a programmable 8-bit reload value, and includes
divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud
rates based on its input clock f
Frac t ional Di vi der
FDM
, see Figure 28.
PCLK
FDST EP
1
01
8-Bit Rel oad Value
FDEN&FDM
Adder
FDEN
Prescaler
f
DIV
clk
f
PCL K
FDRES
f
MOD
f
DIV
0
(overf low)
‘0’
00
01
11
10
11
10
01
00
0
1
R
8-Bit B aud Rat e Timer
NDOV
f
BR
Figure 28Baud-rate Generator Circuitry
The baud rate timer is a count-down timer and is clocked by either the output of the
fractional divider (f
output of the prescaler (f
) if the fractional divider is enabled (FDCON.FDEN = 1), or the
MOD
) if the fractional divider is disabled (FDEN = 0). For baud rate
DIV
generation, the fractional divider must be configured to fractional divider mode
(FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start
or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit
reload value in register BG and one clock pulse is generated for the serial channel.
Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the
baud rate timer and nullifies the effect of bit BCON.R. See Section 3.12.
The baud rate (f
• Input clock f
• Prescaling factor (2
) value is dependent on the following parameters:
BR
PCLK
BRPRE
) defined by bit field BRPRE in register BCON
• Fractional divider (STEP/256) defined by register FDSTEP
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
Data Sheet62 V1.0, 2006-02
XC866
Functional Description
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
The maximum baud rate that can be generated is limited to f
STEP
-------------- -
×=
256
/32. Hence, for a module
PCLK
clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 23 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
26.7 MHz is used.
Table 23Typical Baud rates for UART with Fractional Divider disabled
Baud ratePrescaling Factor
19.2 kBaud1 (BRPRE=000
9600 Baud1 (BRPRE=000
4800 Baud2 (BRPRE=001
2400 Baud4 (BRPRE=010
BRPRE
(2
)
) 87 (57H)-0.22 %
B
)174 (AEH)-0.22 %
B
)174 (AEH)-0.22 %
B
)174 (AEH)-0.22 %
B
Reload Value
(BR_VALUE + 1)
Deviation Error
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 24 lists the resulting deviation errors from generating a baud rate of
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet63 V1.0, 2006-02
Functional Description
Table 24Deviation Error for UART with Fractional Divider enabled
XC866
Prescaling Factor
f
PCLK
(2
BRPRE
)
Reload Value
(BR_VALUE + 1)
26.67 MHz110 (A
13.33 MHz17 (7
6.67 MHz13 (3
STEPDeviation
Error
)177 (B1H)+0.03 %
H
)248 (F8
H
)212 (D4
H
)+0.11 %
H
)-0.16 %
H
Data Sheet64 V1.0, 2006-02
XC866
Functional Description
3.11.2Baud Rate Generation using Timer 1
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In
theory, this timer could be used in any of its modes. But in practice, it should be set into
auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the
required baud rate. The baud rate is determined by the Timer 1 overflow rate and the
value of SMOD as follows:
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see Figure 28). Once the
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
f
an output clock
that is 1/n of the input clock f
MOD
The output frequency in normal divider mode is derived as follows:
f
MODfDIV
, where n is defined by 256 - STEP.
DIV
1
----------------------------- -
×=
256 STEP–
[3.2]
Data Sheet65 V1.0, 2006-02
XC866
Functional Description
3.13LIN Protocol
The UART can be used to support the Local Interconnect Network (LIN) protocol for both
master and slave operations. The LIN baud rate detection feature provides the capability
to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be
synchronized to the LIN baud rate for data transmission and reception.
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 29. The frame consists of the:
• header, which comprises a Break (13-bit time low), Synch Byte (55
• response time
• data bytes (according to UART protocol)
• checksum
Frame slot
Frame
), and ID field
H
Inter-
frame
space
Header
Synch
Response
Protected
identifier
space
Data 1
Response
Data 2 Data N
Checksum
Figure 29Structure of LIN Frame
3.13.1LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
Data Sheet66 V1.0, 2006-02
XC866
Functional Description
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
Data Sheet67 V1.0, 2006-02
XC866
Functional Description
3.14High-Speed Synchronous Serial Interface
The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and
half-duplex synchronous communication. The serial clock signal can be generated by
the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be
received from an external master (slave mode). Data width, shift direction, clock polarity
and phase are programmable. This allows communication with SPI-compatible devices
or devices using other synchronous serial interfaces.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Transmit and receive buffered
• Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
• Variable baud rate
• Compatible with Serial Peripheral Interface (SPI)
• Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Data Sheet68 V1.0, 2006-02
XC866
Functional Description
Data is transmitted or received on lines TXD and RXD, which are normally connected to
the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave
Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input
via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin
SCLK. Transmission and reception of data are double-buffered.
Figure 30 shows the block diagram of the SSC.
PCLK
Baud-rate
Generator
SSC Control Bloc k
Register CON
16-Bit Shift
Register
Trans mit B uffer
Register TB
Internal Bus
Figure 30SSC Block Diagram
Clock
Control
Shift
Clock
ControlStatus
Receiv e Buffer
Register RB
RIR
TIR
EIR
Recei ve Int. Request
Trans mit Int. Request
Error Int. Request
Pin
Control
SS_CLK
MS_CLK
TXD(Ma s ter)
RXD(Slave)
TXD(Slav e)
RXD(Mast er)
Data Sheet69 V1.0, 2006-02
XC866
Functional Description
3.15Timer 0 and Timer 1
Timers 0 and 1 are count-up timers which are incremented every machine cycle, or in
terms of the input clock, every 2 PCLK cycles. They are fully compatible and can be
configured in four different operating modes for use in a variety of applications, see
Table 25. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their
functions are specialized.
Table 25Timer 0 and Timer 1 Modes
ModeOperation
013-bit timer
The timer is essentially an 8-bit counter with a divide-by-32 prescaler.
This mode is included solely for compatibility with Intel 8048 devices.
116-bit timer
The timer registers, TLx and THx, are concatenated to form a 16-bit
counter.
28-bit timer with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3Timer 0 operates as two 8-bit timers
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
Data Sheet70 V1.0, 2006-02
XC866
Functional Description
3.16Timer 2
Timer 2 is a 16-bit general purpose timer (THL2) that has two modes of operation, a
16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is
disabled, Timer 2 counts with an input clock of PCLK/12. Timer 2 continues counting as
long as it is enabled.
Table 26Timer 2 Modes
ModeDescription
Auto-reload Up/Down Count Disabled
• Count up only
Channel
capture
• Start counting from 16-bit reload value, overflow at FFFF
• Reload event configurable for trigger by overflow condition only, or by
negative/positive edge at input pin T2EX as well
• Programmble reload value in register RC2
• Interrupt is generated with reload event
Up/Down Count Enabled
• Count up or down, direction determined by level at input pin T2EX
• No interrupt is generated
• Count up
– Start counting from 16-bit reload value, overflow at FFFF
– Reload event triggered by overflow condition
– Programmble reload value in register RC2
• Count down
– Start counting from FFFF
, underflow at value defined in register
H
RC2
– Reload event triggered by underflow condition
– Reload value fixed at FFFF
H
• Count up only
• Start counting from 0000
, overflow at FFFF
H
H
• Reload event triggered by overflow condition
• Reload value fixed at 0000
H
• Capture event triggered by falling/rising edge at pin T2EX
• Captured timer value stored in register RC2
• Interrupt is generated with reload or capture event
H
H
Data Sheet71 V1.0, 2006-02
XC866
Functional Description
3.17Capture/Compare Unit 6
The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which
can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor
control. The CCU6 also supports special control modes for block commutation and
multi-phase machines.
The timer T12 can function in capture and/or compare mode for its three channels. The
timer T13 can work in compare mode only.
The multi-channel control unit generates output patterns, which can be modulated by
T12 and/or T13. The modulation sources can be selected and combined for the signal
modulation.
Timer T12 Features:
• Three capture/compare channels, each channel can be used either as a capture or as
a compare channel
• Supports generation of a three-phase PWM (six outputs, individual signals for
highside and lowside switches)
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Dead-time control for each channel to avoid short-circuits in the power stage
• Concurrent update of the required T12/13 registers
• Generation of center-aligned and edge-aligned PWM
• Supports single-shot mode
• Supports many interrupt request sources
• Hysteresis-like control mode
Timer T13 Features:
• One independent compare channel with one output
• 16-bit resolution, maximum count frequency = peripheral clock frequency
• Can be synchronized to T12
• Interrupt generation at period-match and compare-match
• Supports single-shot mode
Additional Features:
• Implements block commutation for Brushless DC-drives
• Position detection via Hall-sensor pattern
• Automatic rotational speed measurement for block commutation
• Integrated error handling
• Fast emergency stop without CPU load via external signal (CTRAP
• Control modes for multi-channel AC-drives
• Output levels can be selected and adapted to the power stage
Data Sheet72 V1.0, 2006-02
)
The block diagram of the CCU6 module is shown in Figure 31.
module kernel
address
decoder
T12
channel 0
channel 1
compare
1
dead-
time
1
cont rol
clock
control
interrupt
control
channel 2
sta rt
channel 3T13
compare
T13HR
T12HR
CO UT6 3
CO UT6 0
1
capture
com par e
3
input / output control
CO UT6 2
CC 61
CO UT6 1
CC 60
com par e
com par e
2221
CC 62
CC POS 0
XC866
Functional Description
multi-
channel
control
Hall input
output select
CC POS 1
3
CC POS 2
trap
control
output select
CT RAP
trap input
1
port control
CCU6_bl ock_diagram
Figure 31CCU6 Block Diagram
Data Sheet73 V1.0, 2006-02
XC866
Functional Description
3.18Analog-to-Digital Converter
The XC866 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with
eight multiplexed analog input channels. The ADC uses a successive approximation
technique to convert the analog voltage levels from up to eight different sources. The
analog input channels of the ADC are available at Port 2.
Features:
• Successive approximation
• 8-bit or 10-bit resolution
(TUE of ± 1 LSB and ± 2 LSB, respectively)
• Eight analog channels
• Four independent result registers
• Result data protection for slow CPU access
(wait-for-read mode)
• Single conversion mode
• Autoscan functionality
• Limit checking for conversion results
• Data reduction filter
(accumulation of up to 2 conversion results)
• Two independent conversion request sources with programmable priority
• Selectable conversion request trigger
• Flexible interrupt generation with configurable service nodes
• Programmable sample time
• Programmable clock divider
• Cancel/restart feature for running conversions
• Integrated sample and hold circuitry
• Compensation of offset errors
• Low power modes
Data Sheet74 V1.0, 2006-02
XC866
÷
÷
÷
≤
÷
Functional Description
3.18.1ADC Clocking Scheme
A common module clock f
and digital parts of the ADC module:
•f
•f
is input clock for the analog part.
ADCA
is internal clock for the analog part (defines the time base for conversion length
ADCI
and the sample time). This clock is generated internally in the analog part, based on
the input clock f
•f
is input clock for the digital part.
ADCD
ADCA
The internal clock for the analog part f
Therefore, the ADC clock prescaler must be programmed to a value that ensures f
does not exceed 10 MHz. The prescaler ratio is selected by bit field CTC in register
GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of
the ADC is not required.
generates the various clock signals used by the analog
ADC
to generate a correct duty cycle for the analog components.
is limited to a maximum frequency of 10 MHz.
ADCI
ADCI
f
= f
ADC
PCLK
f
ADCA
clock prescaler
Condition: f
Figure 32ADC Clocking Scheme
32
4
3
2
ADCI
f
ADCD
CTC
MUX
arbi ter
regi ster s
interrupts
f
ADCI
10 MHz, where t
anal og
component s
digital part
analog part
ADCI =
f
1
ADCI
Data Sheet75 V1.0, 2006-02
XC866
Functional Description
For module clock f
= 26.7 MHz, the analog clock f
ADC
frequency can be selected as
ADCI
shown in Table 27.
Table 27f
Module Clock f
26.7 MHz00
As f
cannot exceed 10 MHz, bit field CTC should not be set to 00B when f
ADCI
26.7 MHz. During slow-down mode where f
etc., CTC can be set to 00
Frequency Selection
ADCI
ADC
CTCPrescaling RatioAnalog Clock f
B
01
B
10
B
11
(default)÷ 32833.3 kHz
B
as long as the divided analog clock f
B
÷ 213.3 MHz (N.A)
÷38.9MHz
÷46.7MHz
may be reduced to 13.3 MHz, 6.7 MHz
ADC
does not exceed
ADCI
ADCI
ADC
is
10 MHz. However, it is important to note that the conversion error could increase due to
loss of charges on the capacitors, if f
becomes too low during slow-down mode.
ADC
3.18.2ADC Conversion Sequence
The analog-to-digital conversion procedure consists of the following phases:
• Synchronization phase (t
• Sample phase (t
)
S
• Conversion phase
• Write result phase (tWR)
conversion start
trigger
SYN
)
Source
interrupt
Conversion PhaseSample Phase
Channel
interrupt
Result
interrupt
f
ADCI
BUSY Bit
SAMPLE Bit
t
SYN
t
S
t
CONV
Write Result Phase
t
WR
Figure 33ADC Conversion Timing
Data Sheet76 V1.0, 2006-02
XC866
Functional Description
3.19On-Chip Debug Support
The On-Chip Debug Support (OCDS) provides the basic functionality required for the
software development and debugging of XC800-based systems.
The OCDS design is based on these principles:
• use the built-in debug functionality of the XC800 Core
• add a minimum of hardware overhead
• provide support for most of the operations by a Monitor Program
• use standard interfaces to communicate with the Host (a Debugger)
Features:
• Set breakpoints on instruction address and within a specified address range
• Set breakpoints on internal RAM address
• Support unlimited software breakpoints in Flash/RAM code region
• Process external breaks
• Step through the program code
The OCDS functional blocks are shown in Figure 34. The Monitor Mode Control (MMC)
block at the center of OCDS system brings together control signals and supports the
overall functionality. The MMC communicates with the XC800 Core, primarily via the
Debug Interface, and also receives reset and clock signals. After processing memory
address and control signals from the core, the MMC provides proper access to the
dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for
work-data and Monitor-stack). The OCDS system is accessed through the JTAG
which is an interface dedicated exclusively for testing and debugging activities and is not
normally used in an application. The dedicated MBC pin is used for external
configuration and debugging control.
Note: All the debug functionality described here can normally be used only after XC866
has been started in OCDS mode.
1)
,
1)
The pins of the JTAG port can be assigned to either Port 0 (primary) or Ports 1 and 2 (secondary).
User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system.
Data Sheet77 V1.0, 2006-02
XC866
Functional Description
Memory
User
Progr am
Memory
User
Internal
RAM
Control
Unit
Boot/
Monitor
ROM
Monitor
RAM
Primary
Debug
Interface
Monitor &
Bootstr ap loader
Control line
System
Control
Unit
JTAG
WDT
Suspend
Reset
Clock
MBC
JTAG Module
TMS
TCK
TDI
TDO
Reset
- pa rts of
OCDS
TCK
TDO
Control
TDI
Monitor Mode Control
Debu g
Interface
PROG
& IRAM
Addresse s
PROG
Data
Memory
Control
Reset Clock
XC800
OCDS_XC800-Block_Diagram-UM-v0.2
Figure 34OCDS Block Diagram
3.19.1JTAG ID Register
This is a read-only register located inside the JTAG module, and is used to recognize the
device(s) connected to the JTAG interface. Its content is shifted out when
INSTRUCTION register contains the IDCODE command (opcode 04
also true immediately after reset.
The JTAG ID register contents for the XC866 Flash devices are given in Table 28.
Table 28JTAG ID Summary
Device TypeDevice NameJTAG ID
Flash XC866L-4FR1010 0083
XC866-4FR100F 5083
XC866L-2FR1010 2083
XC866-2FR1010 1083
H
H
H
H
), and the same is
H
Data Sheet78 V1.0, 2006-02
XC866
Functional Description
3.20Identification Register
The XC866 identity register is located at Page 1 of address B3H.
ID
Identity RegisterReset Value: 0000 0010
76543210
PRODIDVERID
rr
FieldBitsType Description
VERID[2:0]rVersion ID
010
B
PRODID[7:3]rProduct ID
00000
B
B
Data Sheet79 V1.0, 2006-02
XC866
Electrical Parameters
4Electrical Parameters
4.1General Parameters
4.1.1Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XC866
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
• CC
These parameters indicate Controller Characteristics, which are distinctive features of
the XC866 and must be regarded for a system design.
• SR
These parameters indicate System Requirements, which must be provided by the
microcontroller system in which the XC866 designed in.
Data Sheet80 V1.0, 2006-02
XC866
Electrical Parameters
4.1.2Absolute Maximum Rating
Maximum ratings are the extreme limits to which the XC866 can be subjected to without
permanent damage.
Table 29Absolute Maximum Rating Parameters
ParameterSymbolLimit ValuesUnit Notes
min.max.
Ambient temperature
Storage temperature
Junction temperature
Voltage on power supply pin with
respect to
V
SS
Voltage on core supply pin with
respect to
V
SS
Voltage on any pin with respect
to
V
SS
Input current on any pin during
overload condition
Absolute sum of all input currents
during overload condition
T
T
T
V
V
V
A
ST
J
DDP
DDC
IN
-40125°Cunder bias
-65150°C
-40150°Cunder bias
-0.56V
-0.53.25V
-0.5V
DDP
+
0.5 or
max. 6
I
IN
Σ|
I
-1010mA
|–50mA
IN
VWhatever is
lower
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (V
the voltage on V
pin with respect to ground (VSS) must not exceed the values
DDP
IN>VDDP
or VIN<VSS)
defined by the absolute maximum ratings.
Data Sheet81 V1.0, 2006-02
XC866
Electrical Parameters
4.1.3Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the XC866. All parameters mentioned in the following table refer to these
operating conditions, unless otherwise noted.
Table 30Operating Condition Parameters
ParameterSymbolLimit ValuesUnit Notes/
min.max.
Digital power supply voltage
V
DDP
4.55.5V5V range
3.03.6V3.3V range
Digital ground voltage
Digital core supply voltage
System Clock Frequency
Ambient temperature
V
SS
V
DDC
1)
f
SYS
T
A
2.32.7V
7486MHz
-4085°CSAF-XC866...
-40125°CSAK-XC866...
1)
f
is the PLL output clock. During normal operating mode, CPU clock is f
Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta
stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching
due to external system noise.
2)
An additional error current (I
pin have internal pull devices and are not included in the input leakage current characteristic.
RESET
3)
Not subjected to production test, verified by design/characterization.
and
Σ|I
|
OV
–25mA
SR
I
SR –15mA
M
Σ|
I
|
M
–60mA
SR
I
MVDDP
–80mA
SR
I
MVSS
–80mA
SR
) will flow if an overload current flows through an adjacent pin. TMS pin and
Detection is enabled in both active and power-down mode.
3)
Detection is enabled for external power supply of 5.0V.
Detection must be disabled for external power supply of 3.3V.
4)
The reset of EVR is extended by 300 µs typically after the VDDC reaches the power-on reset voltage.
1)
2)
3)
2)4)
V
DDCPW
V
DDCBO
DDCRDR
V
DDCBOPD
V
DDPPW
V
DDCPOR
CC 2.22.32.4V
CC 2.02.12.2V
CC 0.91.01.1V
CC 1.31.51.7V
CC 3.44.04.6V
CC 1.31.51.7V
Data Sheet87 V1.0, 2006-02
XC866
Electrical Parameters
4.2.3ADC Characteristics
The values in the table below are given for an analog power supply between 4.5 V to
5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case,
the analog parameters may show a reduced performance. All ground pins (V
externally connected to one single star point in the system. The voltage difference
between the ground pins must not exceed 200mV.
Table 33ADC Characteristics (Operating Conditions apply; V
ParameterSymbolLimit ValuesUnitTest Conditions/
min.typ .max.
Analog reference
voltage
Analog reference
ground
Analog input
V
AREF
V
AGND
V
AIN
SR
SR
SR V
V
AGND
+ 1
V
SS
- 0.05
AGND
V
V
–V
DDPVDDP
+ 0.05
V
SS
AREF
- 1
AREF
V
V
V
DDP
Remarks
voltage range
ADC clocksf
ADC
f
ADCI
–2040MHzmodule clock
––10MHzinternal analog clock
See Figure 32
Sample timet
Conversion timet
Total unadjusted
error
Switched
capacitance at the
CC (2 + INPCR0.STC) ×
S
C
TUE
t
ADCI
CC See Section 4.2.3.1µs
1)
CC ––±1LSB8-bit conversion.
µs
––±2LSB10-bit conversion.
C
AREFSW
–1020pF
2)3)
CC
reference voltage
input
Switched
capacitance at the
C
AINSW
–57pF
CC
2)4)
analog voltage
inputs
Input resistance of
R
CC –12kΩ
AREF
2)
the reference input
Input resistance of
R
CC –11.5kΩ
AIN
2)
the selected analog
channel
) must be
SS
= 5V Range)
2)
Data Sheet88 V1.0, 2006-02
XC866
Electrical Parameters
1)
TUE is tested at V
2)
Not subject to production test, verified by design/characterization.
3)
This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead of this, smaller capacitances are successively switched to the reference voltage.
4)
The sampling capacity of the conversion C-Network is pre-charged to V
the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than V
AREF
=5.0V, V
AGND
=0V , V
DDP
=5.0V.
/2 before connecting the input to
AREF
AREF
Analog Input Circuitry
/2.
R
EXT
V
AIN
C
EXT
V
AGNDx
ANx
R
AIN, On
C
AINSW
Reference Voltage Input Circuitry
R
AREF, On
C
AREFSW
V
AREF
V
V
AGNDx
AREFx
Figure 36ADC Input Circuits
Data Sheet89 V1.0, 2006-02
4.2.3.1ADC Conversion Timing
Conversion time, tC=t
r = CTC + 2 for CTC = 00B, 01B or 10B,
r = 32 for CTC = 11
B
CTC = Conversion Time Control (GLOBCTR.CTC),
STC = Sample Time Control (INPCR0.STC),
n = 8 or 10 (for 8-bit and 10-bit conversion respectively),
t
=1/f
ADC
ADC
× ( 1 + r × (3 + n + STC) ) , where
ADC
,
XC866
Electrical Parameters
Data Sheet90 V1.0, 2006-02
XC866
Electrical Parameters
4.2.4Power Supply Current
Table 34Power Supply Current Parameters (Operating Conditions apply;
V
= 5V range )
DDP
ParameterSymbolLimit ValuesUnit Test Condition
1)
typ.
V
= 5V Range
DDP
Active Mode
Idle ModeI
Active Mode with slow-down
I
DDP
DDP
I
DDP
22.624.5mA
17.219.7mA
7.28.2mA
enabled
Idle Mode with slow-down
I
DDP
7.18mA
enabled
1)
The typical I
2)
The maximum I
3)
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010
4)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET
5)
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101
6)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enabled and running at 833 KHz by setting CLKREL in CMCON to 0101
RESET
values are periodically measured at TA=+25°C and V
DDP
values are measured under worst case conditions (TA= + 125 °C and V
DDP
= V
.
DDP
= V
.
DDP
), RESET = V
B
, RESET = V
B
max.
DDP
DDP
2)
DDP
=5.0V.
.
.
3)
4)
5)
6)
=5.5V).
DDP
,
B
Data Sheet91 V1.0, 2006-02
XC866
Electrical Parameters
Table 35Power Down Current (Operating Conditions apply; V
= 5V range )
DDP
ParameterSymbolLimit ValuesUnit Test Condition
1)
typ.
V
= 5V Range
DDP
Power-Down Mode
3)
I
PDP
110µATA=+25°C.
-30µATA=+85°C.
1)
The typical I
2)
The maximum I
3)
I
(power-down mode) has a maximum value of 200 µA at TA= + 125 °C.
PDP
4)
I
(power-down mode) is measured with: RESET = V
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
5)
Not subject to production test, verified by design/characterization.
values are measured at V
PDP
values are measured at V
PDP
DDP
=5.0V.
=5.5V.
DDP
DDP
, V
AGND
2)
max.
= VSS, RXD/INT0 = V
; rest of the ports
DDP
4)
4)5)
Data Sheet92 V1.0, 2006-02
XC866
Electrical Parameters
Table 36Power Supply Current Parameters (Operating Conditions apply;
V
= 3.3V range)
DDP
ParameterSymbolLimit ValuesUnit Test Condition
1)
typ.
V
= 3.3V Range
DDP
Active Mode
Idle ModeI
Active Mode with slow-down
I
DDP
DDP
I
DDP
21.523.3mA
16.418.9mA
6.88mA
enabled
Idle Mode with slow-down
I
DDP
6.87.8mA
enabled
1)
The typical I
2)
The maximum I
3)
I
(active mode) is measured with: CPU clock and input clock to all peripherals running at 26.7 MHz(set by
DDP
on-chip oscillator of 10 MHz and NDIV in PLL_CON to 0010
4)
I
(idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals
DDP
enabled and running at 26.7 MHz, RESET
5)
I
(active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals
DDP
running at 833 KHz by setting CLKREL in CMCON to 0101
6)
I
(idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input
DDP
clock to all peripherals enable and running at 833 KHz by setting CLKREL in CMCON to 0101
RESET
values are periodically measured at TA=+25°C and V
DDP
values are measured under worst case conditions (TA= + 125 °C and V
DDP
= V
.
DDP
= V
.
DDP
), RESET = V
B
, RESET = V
B
max.
DDP
DDP
2)
=3.3V.
DDP
.
3)
4)
5)
6)
=3.6V).
DDP
.
,,
B
Data Sheet93 V1.0, 2006-02
XC866
Electrical Parameters
Table 37Power Down Current (Operating Conditions apply; V
DDP
= 3.3V
range )
ParameterSymbolLimit ValuesUnit Test Condition
1)
typ.
V
= 3.3V Range
DDP
Power-Down Mode
3)
I
PDP
110µATA=+25°C.
-30µATA=+85°C.
1)
The typical I
2)
The maximum I
3)
I
(power-down mode) has a maximum value of 200 µA at TA= + 125 °C.
PDP
4)
I
(power-down mode) is measured with: RESET = V
PDP
are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating
inputs.
5)
Not subject to production test, verified by design/characterization.
values are measured at V
PDP
values are measured at V
PDP
DDP
=3.3V.
=3.6V.
DDP
DDP
, V
AGND
2)
max.
= VSS, RXD/INT0= V
; rest of the ports
DDP
4)
4)5)
Data Sheet94 V1.0, 2006-02
XC866
Electrical Parameters
4.3AC Parameters
4.3.1Testing Waveforms
The testing waveforms for rise/fall time, output delay and output high impedance are
shown in Figure 37, Figure 38 and Figure 39.
V
DDP
90%
90%
V
SS
10%
t
R
Figure 37Rise/Fall Time Parameters
V
DDP
V
/ 2
DDE
V
SS
Te st P oi n ts
Figure 38Testing Waveform, Output Delay
V
+ 0.1 VVOH - 0.1 V
Load
Timing
Reference
V
- 0.1 VVOL - 0.1 V
Load
Points
Figure 39Testing Waveform, Output High Impedance
10%
t
F
/ 2
V
DDE
Data Sheet95 V1.0, 2006-02
XC866
Electrical Parameters
4.3.2Output Rise/Fall Times
Table 38Output Rise/Fall Times Parameters (Operating Conditions apply)
ParameterSymbolLimit
Values
min. max.
V
= 5V Range
DDP
Rise/fall times
V
= 3.3V Range
DDP
Rise/fall times
1)
Rise/Fall time measurements are taken with 10% - 90% of the pad supply.
2)
Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
3)
Additional rise/fall time valid for CL= 20pF - 100pF @ 0.125 ns/pF.
4)
Additional rise/fall time valid for CL= 20pF - 100pF @ 0.225 ns/pF.
1) 2)
1) 2)
V
DDP
tR, t
tR, t
90%
F
F
–10ns20 pF.
–10ns20 pF.
Unit Test Conditions
3)
4)
90%
V
SS
10%
t
R
10%
t
F
Figure 40Rise/Fall Times Parameters
Data Sheet96 V1.0, 2006-02
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.