查询HYS 64V32300GU-75-C2供应商
3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules
168-pin Unbuffered DIMM Modules
HYS 64/72V32300GU
SDRAM-Modules
• 168 Pin unbuffered 8 Byte Dual-In- Line
SDRAM Modules for PC main memory
applications using 256Mbit technology.
• PC100-222, PC133-333 and PC133-222
versions
• One bank 32M
× 6 4 an d 32M × 72
organisation
• Optimized for byte-write non-parity or ECC
applications
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 module specification
• Programmed Latencies:
Product Speed CL
t
RCDtRP
-7 PC133 2 2 2
-7.5 PC133 3 3 3
-8 PC100 2 2 2
• SDRAM Perform a nc e:
-7 / -7.5 -8 Unit
PC133 PC100
f
Clock Frequency (max.) 133 100 MHz
CK
t
Clock A cc e ss T im e 5.4 6 ns
AC
• Single + 3.3 V (
• Programmable CAS
± 0 .3 V) power supply
Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Prese nc e Dete c t with E
2
PROM
• Uses I nfi n eon 256Mbit SDRAM com po nent s
in 32M × 8 organization and TSOPII-54
packages
• Gold contact pads, card size:
133.35mm
× 31.75 mm × 3.00 mm
(JEDEC MO-161-BA)
Description
The HYS 64V32300GU and HYS 72V32300GU are industry standard 168-pin 8-byte Dual in-line
Memory Mo dule s (DI MM s) whic h are or gan iz ed as 32 M
× 64 and 32M × 72 in 1 memory bank high
speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and
ECC applications. The DIMMs use -7 speed sorted 32M
× 8 SDRAM devices in T SO P54 p ac kag es
to mee t the P C133- 22 2 req uirem ent , -7.5 co mpo nents for PC13 3-333 an d -8 com pon ents for th e
standard PC100 applications. Decoupling capacitors are mounted on the PC boar d. The P C board
design is according to INTEL’s module specification. The DIMMs have a serial presence detect,
implemented with a serial E
2
PROM using the 2-p in I2C protocol. The first 128 bytes are utilized by
the DI M M m a nu facturer an d the second 128 bytes are av ai lable to th e e nd us e r . A l l In f i ne on 16 8pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with
1.25“ (31.75 mm) heig ht.
INFINEON Techno logies 1 9.01
HYS 64/72V32300GU
SDRAM-Modules
Ordering Information
Type Code Package Descriptions Module
Height
HYS 64V32 300GU-7-D PC133 -2 22 - 52 0 L-DIM-16 8- 33 PC133 32M
× 64 1 bank
SDRAM module
HYS 72V32 300GU-7-D PC133 -2 22 - 52 0 L-DIM-16 8- 33 PC133 32M
× 72 1 bank
ECC-SDRAM module
HYS 64V32300GU-7.5-C2
HYS 64V32300GU-7.5-D
HYS 72V32300GU-7.5-C2
HYS 72V32300GU-7.5-D
HYS 64V32300GU-8-C2 PC100-222-620 L-DIM-168-33 PC100 32M
PC133- 333-520 L-DIM-168-33 PC133 32M
SDRAM module
PC133- 333-520 L-DIM-168-33 PC133 32M
ECC-SDRAM module
× 64 1 bank
× 72 1 bank
× 64 1 bank
SDRAM module
HYS 72V32300GU-8-C2 PC100-222-620 L-DIM-168-33 PC100 32M
× 72 1 bank
ECC-SDRAM module
Note: All part numbers end with a place code designating the die revision. Consult factory for
current revision. Example: HYS 64V32300GU-8-C2, indicating Rev. C2 dies are used for
SDRAM comp onents.
Pin Definitions and Functions
A0 - A12 Address Inputs CLK0 - CLK3 Clock Input
BA0, BA1 Bank Selects DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output CS0
CB0 - CB7 Check Bits (x72 organisation only)
RAS
CAS
WE
Row Address Strobe V
Column Address Strobe SCL Clock for Presence Detect
Read/Write Input SDA Serial Data Out for
, CS2 Chip Select
V
DD
SS
Power (+ 3.3 V)
Ground
Presence Detect
CKE0 Clock Enable N.C./DU No Connection
1.25“
1.25“
1.25“
1.25“
1.25“
1.25“
Address Format
Part Number Rows Columns Bank Select Refresh Period Interval
× 64/72 HYS64/72V32300GU 13 10 2 8k 64 ms 7.8 µs
32M
INFINEON Techno logies 2 9.01
HYS 64/72V32300GU
SDRAM-Modules
Pin Configuration
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
1 V
SS
2 DQ0 44 DU 86 DQ32 128 CKE0
3DQ1 45CS2
4 DQ2 46 DQMB2 88 DQ34 130 DQMB6
5 DQ3 47 DQMB3 89 DQ35 131 DQMB7
6 V
DD
7DQ4 49V
8 DQ5 50 N.C. 92 DQ37 134 N.C.
9 DQ6 51 N.C. 93 DQ38 135 N.C.
10 DQ7 52 N.C. (CB2) 94 DQ39 136 CB6
11 DQ8 53 N.C. (CB3) 95 DQ40 137 CB7
12 V
SS
13 DQ9 55 DQ16 97 DQ41 139 DQ48
14 DQ10 56 DQ17 98 DQ42 140 DQ49
15 DQ11 57 DQ18 99 DQ43 141 DQ50
16 DQ12 58 DQ19 100 DQ44 142 DQ51
17 DQ13 59 V
18 V
DD
19 DQ14 61 N.C. 103 DQ46 145 N.C.
20 DQ15 62 DU 104 DQ47 146 DU
21 N.C. (CB0) 63 N.C. 105 N.C. (CB4) 147 N.C.
22 N.C. (CB1) 64 V
23 V
SS
24 N.C. 66 DQ22 108 N.C. 150 DQ54
25 N.C. 67 DQ23 109 N.C. 151 DQ55
26 V
DD
27 WE 69 DQ24 111 CAS 153 DQ56
28 DQMB0 70 DQ25 112 DQMB4 154 DQ57
29 DQMB1 71 DQ26 113 DQMB5 155 DQ58
30 CS0
31 DU 73 V
32 V
SS
33 A0 75 DQ29 117 A1 159 DQ61
34 A2 76 DQ30 118 A3 160 DQ62
35 A4 77 DQ31 119 A5 161 DQ63
36 A6 78 V
37 A8 79 CLK2 121 A9 163 CLK3
38 A10 80 N.C. 122 BA0 164 N.C.
39 BA1 81 WP 123 A11 165 SA0
40 V
41 V
DD
DD
42 CLK0 84 V
43 V
SS
85 V
SS
127 V
SS
87 DQ33 129 N.C.
48 DU 90 V
91 DQ36 133 V
96 V
101 DQ45 143 V
54 V
DD
SS
DD
60 DQ20 102 V
SS
106 N.C. (CB5) 148 V
65 DQ21 107 V
68 V
SS
110 V
DD
SS
DD
SS
DD
132 N.C.
DD
138 V
SS
DD
144 DQ52
149 DQ53
SS
152 V
SS
72 DQ27 114 N.C. 156 DQ59
74 DQ28 116 V
DD
SS
82 SDA 124 V
115 RAS 157 V
SS
158 DQ60
120 A7 162 V
DD
166 SA1
DD
SS
83 SCL 125 CLK1 167 SA2
DD
126 A12 168 V
DD
Note: Pin names in parantheses are for the x72 ECC versions; example: Pin 106 = (CB5)
INFINEON Techno logies 3 9.01
WE
CS0
DQMB0
DQ(7:0)
DQMB1
CS2
DQMB2
DQ(23:16)
HYS 64/72V32300GU
WE
CS CS WE
DQM
DQ0-DQ7
DQM
DQ0-DQ7DQ(15:8)
DQM
DQ0-DQ7CB(7:0)
DQM
DQ0-DQ7
D0
CS
WE
D1
CS
WE
D8
CS
WE WE
D2
DQMB4
DQ(39:32)
DQMB5
DQMB6
DQ(55:48)
DQM
DQ0-DQ7
DQM
DQ0-DQ7DQ(47:40)
CS
DQM
DQ0-DQ7
SDRAM-Modules
D4
WECS
D5
D6
CS
DQMB3
DQ(31:24)
DQM
DQ0-DQ7
WE
D3
A0-A12, BA0, BA1 D0-D 7, (D8)
V
CC
D0-D7, (D8)
C0-C15, (C16, C17)
V
SS
D0-D7, (D8)
DQMB7
DQ(63:56)
CS
WE
DQM
DQ0-DQ7
D7
2
E PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA1
SA2
SA2
SCLSCL
SDA
WP
47 k
Ω
RAS D0-D7, (D8)
D0-D7, (D8)CAS
CKE0 D0-D7, (D8)
Note: D8 is only used in the x72 ECC version and
all resistor values are 10 Ohm except
otherwise noted.
CLK0
CLK1
CLK2
CLK3
Clock Wiring
16 M x 64 16 M x 72
4 SDRAM + 3.3 pF 5 SDRAM
Termina tion Termina tion
TerminationTermination
4 SDRAM + 3.3 pF4 SDRAM + 3.3 pF
BL013
Block Diagram: 32M x 64/72 One Bank SDRAM DIMM Modules
INFINEON Techno logies 4 9.01
HYS 64/72V32300GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter Symbol Limit Values Unit
min. max.
Input / Output voltage relative to V
Power supply voltage on V
Storage temperature range T
Power dissipation per SDRAM component P
Data out current (short circuit) I
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
SS
DD
V
IN, VOUT
V
DD
STG
D
OS
DC Characteristics
T
= 0 to 70 °C; VSS=0V; VDD=3.3V± 0.3 V
A
Parameter Symbol Limit Values Unit
Input High Voltage
Input Low Voltage
Output High Voltage (
Output Low Voltage (
I
= – 4.0 mA) V
OUT
I
=4.0 mA) V
OUT
Input Leakage Current, any input
V
(0 V <
< 3.6 V, all other inputs = 0 V)
IN
Output Leakage Current
V
< V
(DQ is disabled, 0 V <
OUT
)
DD
– 1.0 4.6 V
– 1.0 4.6 V
-55 +150
– 1W
– 50 mA
o
C
min. max.
V
V
I
I
IH
IL
OH
OL
I(L)
O(L)
2.0 VDD+0.3 V
– 0.5 0.8 V
2.4 – V
– 0.4 V
– 40 40 µA
– 40 40 µA
Capacitance
T
= 0 to 70 °C; VDD=3.3V± 0.3 V, f =1MHz
A
Parameter Symbol Limit Values Unit
Input Capacitance
(A0 to A11, BA0, BA1, RAS, CA S, WE)
Input Capacitance (CS0
- CS3) C
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0)
Input Ca pa c ita nc e ( DQ M B 0 - DQM B 7)
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
max.
32M x 64
C
I1
I2
C
ICL
C
I3
C
I4
C
IO
C
SC
C
SD
65 72 pF
32 40 pF
38 40 pF
65 72 pF
13 16 pF
10 10 pF
88pF
88pF
max.
32M x 72
INFINEON Techno logies 5 9.01
HYS 64/72V32300GU
SDRAM-Modules
Operating Currents per SDRAM Component
T
= 0 to 70oC, VDD = 3.3 V ± 0.3 V
A
Parameter Test
Operating current
t
= t
RCMIN.
, tCK= t
CKMIN.
RC
1)
Condition
–
Symbol -7.5 -8 Unit Note
max.
I
CC1
230 170 mA
2)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data acce ss
Precharge stand-by current
t
=min. I
CK
CC2P
22mA
2)
in Power Down Mode
= V
CS
Precharge Stand-by Current
in Non-Power Down Mode
= V
CS
No operating current
t
= min., CS = V
CK
active state (max. 4 banks)
Burst operating curr ent
t
=min.,
CK
Read command cycling
Auto ref r es h cu rr e nt
t
=min.,
CK
IH(MIN.)
IH (MIN.)
, CKE ≤ V
, CKE≥ V
IH(MIN.)
IL(MAX.)
IH(MIN.)
,
t
=min. I
CK
≥ V
CKE
CKE ≤ V
–
–
CC2N
IH(MIN.)ICC3N
IL(MAX.)ICC3P
I
CC4
I
CC5
40 30 mA
50 45 mA
10 10 mA
150 100 mA
240 220 mA
2)
2)
2)
2), 3)
2)
Auto Ref r es h co m ma nd cycling
Self refresh current
I
CC6
33mA
2)
Self Refresh Mode, CKE = 0.2 V
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency
for -7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during t
3. These paramete rs are m easured with continuous d ata stream d uring read access and a ll DQ toggl ing.
CL = 3 and BL = 4 are assumed and the data-out current is excluded.
, excepts for I
CK
and for stand-by currents when tCK= infinity.
CC6
INFINEON Techno logies 6 9.01
HYS 64/72V32300GU
SDRAM-Modules
AC Characteristics
T
= 0 to 70 °C; VSS=0V; VDD=3.3V± 0.3 V, tT=1ns
A
Parameter
1), 2)
Symbol
PC133-222
min. max min. max. min. max.
Clock
Clock Cycle Time
CAS Laten c y = 3
CAS Laten c y = 2
System Frequency
CAS
Latenc y = 3
Latenc y = 2
CAS
Clock Access Time
CAS
Latenc y = 3
Latenc y = 2
CAS
Clock Hi gh Pulse Width t
Clock Low Pulse Width t
t
CK
7.5
7.5––
f
CK
––133
t
AC
––5.4
2.5 – 2.5 – 3 – ns
CH
2.5 – 2.5 – 3 – ns
CL
Setup and Hold Tim es
t
Input Setup Time
Input Hold Time t
Power Down Mode Entry Time t
Power Down Mode Exit Setup Time t
Mode Register Setup Time t
Transition Time (rise and fall)
1.5 – 1.5 – 2 – ns
CS
0.8 – 0.8 – 1 – ns
CH
– 1 – 1 – 1CLK
SB
1 – 1 – 1 – CLK
PDE
2 – 2 – 2 – CLK
RSC
t
1 – 1 – 1 – ns –
T
Limit Values Un it Note
-7
-7.5
PC133-333-8 PC100-222
7.510––1010––ns
133
133––
100– –
5.46––66ns
5.4––
100
100
–
ns
–
MHz
MHz
3), 4)
ns
4)
4)
5)
5)
6)
7)
Common Parame te rs
to CAS Delay t
RAS
Precharge Time
Active Command Period
Cycle Time
Bank to Bank Delay Time
to CAS Delay Time (same bank) t
CAS
15 – 20 – 20 – ns –
RCD
t
15 – 20 – 20 – ns –
RP
t
42 – 45 100k 50 100k ns –
RAS
t
60 – 67.5 – 70 – ns –
RC
t
14 – 15 – 16 – ns –
RRD
1 – 1 – 1 – CLK –
CCD
INFINEON Techno logies 7 9.01
HYS 64/72V32300GU
SDRAM-Modules
AC Characteristics (cont’d)
T
= 0 to 70 °C; VSS=0V; VDD=3.3V± 0.3 V, tT=1ns
A
Parameter
1), 2)
Symbol
PC133-222
min. max min. max. min. max.
Refresh Cycle
t
Refres h Period (8192 cycles )
Self Refresh Exit Time t
64 ––64 – 64 ms
REF
– 11– 1 – CLK
SREX
Read Cycle
t
Data Out Hold Tim e
Data Out to Low Imped an ce t
Data Out to High Impedance
DQM Data Out Disable Latency t
3 – 3 – 3 – ns
OH
0 – 0 – 0 – ns –
LZ
t
373738ns
HZ
– 2 – 2 – 2CLK–
DQZ
Write Cycle
t
Data Input to Precharge
(write recovery)
DQM Write Mask Latency
2 – 2 – 2 – CLK –
WR
t
0 – 0 – 0 – CLK –
DQW
Limit Values Un it Note
-7
-7.5
PC133-333-8 PC100-222
6)
8)
2)
9)
INFINEON Techno logies 8 9.01
HYS 64/72V32300GU
SDRAM-Modules
Notes
1. All AC characteristics ar e shown fo r the SDRAM components.
1.4 V
µs is required after power-up. Then a Precharge All Banks command must
V
= 0.4 V and VIH= 2.4 V with the timing referenced to the 1.4 V crossover
IL
− 1) ns must be added to this parameter.
T
t
CH
2.4 V
0.4 V
t
T
t
CL
t
IH
V
and VIL. All AC measurements assume
IH
t
/2 − 0.5) ns must be added to this parameter.
T
t
is satisfied
RC
An init ial pause of 100
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begi n.
2. AC timing tests have
point. The transition time is measured between
t
= 1 ns with the AC o utp ut lo ad cir cui t show n i n Fi gur e be lo w . Sp ec ifie d tAC and tOH parameters
T
are meas ured with a 50 pF only, w it hout any res is tiv e ter m in ation and with a in put signal of 1V/
ns edge rate between 0. 8V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
4. Rated at 1.4 V.
t
is longer than 1 ns, a time (t
5. If
T
6. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
7. Timing is a as ync hro no us. I f se tup t im e is not met b y r i sing e dg e o f t he cl ock t he n the C KE s igna l
is assu med latched on the next cycl e.
8. Self Refresh Ex it is a sync hro no us op era t io n and be gi ns on th e seco nd posi tiv e cl oc k edg e af ter
CKE returns high. Se lf Refre sh Ex it is not com plete u ntil a time pe riod e qual to
after the Self Refresh Exit command is registered.
9. This is refer enced to the time at w hich the output a chieved t he open c ircuit con dition, not to
output voltage levels.
CLOCK
t
IS
INPUT
OUTPUT 1.4 V
1.4 V
t t
AC
t
LZ
AC
t
OH
t
HZ
IO.vsd
I/O
50 pF
Measurement conditi ons for
t
and t
AC
OH
Serial Presen ce Detec t
A serial presence detect storage device - E
about th e module conf iguration, sp eed, etc. is written into the E
produc tio n us ing a serial pres e nc e de tect protoco l (I
2
PROM - is as sembled onto the mo dule. Info rmation
2
C synch r on ou s 2- w i re bus).
2
PROM de vice during m odule
INFINEON Techno logies 9 9.01
HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 64 (256MByte non-ECC) Modules HYS64V32300GU
Byte# Descrip tion SPD Entry Value Hex
32M x 64
-7 -7.5 -8
0 Number of SPD Bytes 128 80
1 Total Bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses 13 0D
4 Number of Column Addresses 10 0A
5 Number of DIMM Banks 1 01
6 Module Data Width 64 40
7 Module Data Width (cont’d) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL = 3 7.5 / 10 ns 75 75 A0
10 SDRAM Access Time at CL = 3 5.4 / 6 ns 54 54 60
11 DIMM Con fig non- E CC 00
12 Refresh Rate/Type Self-Refresh,
7.8
µs
13 SDRAM Width, Primary x8 08
14 Error Checking S DRAM Data Width na 00
15 Minimum Clock Delay for Back-to-
t
=1CLK 01
CCD
Back Ra ndom Colum n Address
16 Burs t Leng th Suppo rte d 1, 2, 4 & 8 0F
17 Number of SDRAM Banks 4 04
18 Supported CAS
19 CS
20 WE
Latencies CS latency = 0 01
Latencies Write latency = 0 01
Latencies CL = 2 & 3 06
21 SDRAM DIMM Module Attributes unbuffered 00
22 SDRAM Device Attributes: General
V
tol +/– 10% 0E
DD
23 SDRAM Cycle Time at CL = 2 7.5 / 10.0 ns 75 A0 A0
24 SDRAM Access Time at CL = 2 5.4 / 6.0 ns 54 60 60
25 SDRAM Cycle Time at CL = 1 not supported 00 FF FF
26 SDRAM Access Time at CL= 1 not supported 00 FF FF
27 Minimum Row Precharge Time 15 / 20 ns 0F 14 1 4
28 Min. Row to Row Active Delay
29 Minimum RAS
30 Minimum RAS
to CAS Delay t
Pulse Width t
RAS
t
RCD
RRD
14 / 15 / 16 ns 0E 0F 10
15 / 20 ns 0F 14 14
42 / 45 / 50 ns 2A 2D 32
31 Module Bank Density (per bank) 256 MByte 40
32 SDRAM Input Setup Time 1.5 / 2.0 ns 15 15 20
33 SDRAM Input Hold Time 0.8 / 1.0 ns 08 08 10
34 SDRAM Data Input Hold Time 1.5 / 2.0 ns 15 15 20
35 SDRAM Data Input Setup Time 0.8 / 1.0 ns 08 08 10
82
INFINEON Techno logies 10 9.01
HYS 64/72V32300GU
SDRAM-Modules
Byte# Descrip tion SPD Entry Value Hex
32M x 64
-7 -7.5 -8
36-61 Superset Information – FF FF FF
62 SPD Revision Revision 1.2 12 12 12
63 Checksum f or Bytes 0 - 62 – F3 36 99
64 Manufacturers JEDEC ID Code – C1
65-71 Manufacturer INFINEO(N)
72 Module Assembly Locaction
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Code
95-98 Module Serial Number
99-125 Superset Information
126 Frequency Specification 64 64 64
127 100 MHz Support Details – AF AF AF
128+ Unu sed Storage Lo cations – FF
INFINEON Techno logies 11 9.01
HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 72 (256MByte ECC ) Modules HYS72V 32300GU
Byte# Descrip tion SPD Entry Value Hex
32M x 72
-7 -7.5 -8
0 Number of SPD Bytes 128 80
1 Total Bytes in Serial PD 256 08
2 Memory Type SDRAM 04
3 Number of Row Addresses 13 0D
4 Number of Column Addresses 10 0A
5 Number of DIMM Banks 1 01
6 Module Data Width 72 48
7 Module Data Width (cont’d) 0 00
8 Module Interface Levels LVTTL 01
9 SDRAM Cycle Time at CL = 3 7.5 / 10 ns 75 75 A0
10 SDRAM Access Time at CL = 3 5.4 / 6 ns 54 54 60
11 DIMM Config ECC 02
12 Refresh Rate/Type Self-Refresh,
7.8
µs
13 SDRAM Width, Primary x8 08
14 Error Checking S DRAM Data Width x8 08
15 Minimum Clock Delay for Back-to-
t
=1CLK 01
CCD
Back Ra ndom Colum n Address
16 Burs t Leng th Suppo rte d 1, 2, 4 & 8 0F
17 Number of SDRAM Banks 4 04
18 Supported CAS
19 CS
20 WE
Latencies CS latency = 0 01
Latencies Write latency = 0 01
Latencies CL = 2 & 3 06
21 SDRAM DIMM Module Attributes unbuffered 00
22 SDRAM Device Attributes: General
V
tol +/– 10% 0E
DD
23 SDRAM Cycle Time at CL = 2 7.5 / 10.0 ns 75 A0 A0
24 SDRAM Access Time at CL = 2 5.4 / 6.0 ns 54 60 60
25 SDRAM Cycle Time at CL = 1 not supported 00 FF FF
26 SDRAM Access Time at CL= 1 not supported 00 FF FF
27 Minimum Row Precharge Time 15 / 20 ns 0F 14 1 4
28 Min. Row to Row Active Delay
29 Minimum RAS
30 Minimum RAS
to CAS Delay t
Pulse Width t
RAS
t
RCD
RRD
14 / 15 / 16 ns 0E 0F 10
15 / 20 ns 0F 14 14
42 / 45 / 50 ns 2A 2D 32
31 Module Bank Density (per bank) 256 MByte 40
32 SDRAM Input Setup Time 1.5 / 2.0 ns 15 15 20
33 SDRAM Input Hold Time 0.8 / 1.0 ns 08 08 10
34 SDRAM Data Input Hold Time 1.5 / 2.0 ns 15 15 20
35 SDRAM Data Input Setup Time 0.8 / 1.0 ns 08 08 10
82
INFINEON Techno logies 12 9.01
HYS 64/72V32300GU
SDRAM-Modules
Byte# Descrip tion SPD Entry Value Hex
32M x 72
-7 -7.5 -8
36-61 Superset Information – FF FF FF
62 SPD Revision Revision 1.2 12 12 12
63 Checksum f or Bytes 0 - 62 – 05 48 AB
64 Manufacturers JEDEC ID Code – C1
65-71 Manufacturer INFINEO(N)
72 Module Assembly Locaction
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Code
95-98 Module Serial Number
99-125 Superset Information
126 Frequency Specification 64 64 64
127 100 MHz Support Details – AF AF AF
128+ Unu sed Storage Lo cations – FF
INFINEON Techno logies 13 9.01
Package Outlines
L-DIM-168-33 (JEDEC MO-161-BA)
SDRAM DIMM Module Package
4
-
+ 0.13
31.75
3
10 11
1
3 6.35 6.35
1.27
42.18
91 x 1.27 = 115.57
133.35
127.35
*)
4140
+ 0.15
-
HYS 64/72V32300GU
SDRAM-Modules
3 max.
84
+ 0.1
-
1.27
3.125
17.78
0.25
85 94 95 124 125 168
3min.
Detail of Contacts
1.27
2
3
*) on ECC modules only
2.55
1
L-DIM-168-33
Note: All tolerances according to JEDEC standard
Dimensions in mm
INFINEON Techno logies 14 9.01
HYS 64/72V32300GU
SDRAM-Modules
INFINEON Techno logies 15 9.01
Chan ge List:
14.1.1999 Input capacitances adjusted
18.4.1999 -8A speed sort added
12.5.99 Some ICC current values changed due to new inputs
21.7.99 HYS64/72V32200GU changed to HYS64/72V32300GU due to the use of L-
23.8.99 Byte 126 changed to 64h for PC133 modules
6.9.99 Template from R&L
29.9.99 Some minor errors corrected
20.10.99 CL=2 max. frequency for -7.5 modules changes to 83 MHz
2.12.99 Some timing parameters according to INTEL’S PC133 specification
20.1.2000 Capacitance values for x72 adjusted (new measurements)
10.3.2000 Implemented differences between 256Mbit S20 and S17 PC133 modules
10.5.2000 Reference to JEDEC MO-161-BA added
14.02.2001 -8A speedsort removed
25.07.2001 256M S14 based modules including -7 added
06.09.2001 SCR : Absolute Maximum Ratings table added
HYS 64/72V32300GU
SDRAM-Modules
SPD codes updated according to new 256M speedsorts
256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2
256Mbit S17 based modules are backwards compatible to PC100-2-2-2
leading to changes in SPD code of bytes 23, 63 (checksum) and 126
Infineon logo added
DIM168-33 instead of L-DIM168-30
-8B version removed
TPCR issued
for 256M S17 and later only
INFINEON Techno logies 16 9.01
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