Datasheet HYS72D64x20HU-5-C, HYS72D32x00HU-5-C, HYS64D16x01HU-5-C, HYS64D64x20HU-5-C, HYS64D32x00HU-5-C Datasheet (lnfineon)
...
Data Sheet, V1.0, July 2003
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
HYS64D16x01HU-[5/6]-C
184-Pin Unbuffered Dual-In-Line Memory Modules
Reg DIMM
DDR SDRAM
Memory Products
Never stop thinking.
Edition 2003-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon T echnologies, if a failure of such components can reasonably be expected to cause the failure
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and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.0, July 2003
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
HYS64D16x01HU-[5/6]-C
184-Pin Unbuffered Dual-In-Line Memory Modules
Reg DIMM
DDR SDRAM
Memory Products
Never stop thinking.
HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, HYS64D16x01HU-[5/6]-C
Revision History: V1.0 2003-07
Previous Version: –
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HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table of Contents
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet 5 V1.0, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules
Reg DIMM
HYS[64/72]D64x20HU-[5/6]-C
HYS[64/72]D32x00HU-[5/6]-C
HYS64D16x01HU-[5/6]-C
1 Overview
1.1 Features
• 184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory
applications
• One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
• Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
• Programmable CAS
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial P resence Detect with E
• JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
• Jedec standard reference layout
• Gold plated contacts
• DDR400 Speed Grade supported
• Lead-free
Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
2
PROM
f
CK3
f
CK2.5
f
CK2
200 166 MHz
166 166 MHz
133 133 MHz
Table 1 Performance
Part Number Speed Code –5 –6Unit
Module Speed Grade DDR400B DDR333B –
Component Module PC3200-3033 PC2700-2533 –
max. Clock Frequency @ CL = 3
@ CL = 2.5
@ CL = 2
1.2 Description
The HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, and HYS64D16x01HU-[5/6]-C are industry
standard 184-Pin Unbuffered Dual-In-Line Memory Modules (Reg DIMM) organized as 16M × 64, 32M × 64 and
64M × 64 for non-parity and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is
designed with 256Mbit Double Data Rate Synchron ous DRA Ms . A var i ety of d ecoupling capacitors ar e mo unte d
on the printed circ uit board. T he DIM Ms feature serial prese nc e d etec t (SPD ) bas ed on a se rial E
using the 2-pin I
are available to the customer
2
C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes
2
PROM device
Data Sheet 6 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 2 Ordering Information
Type Compliance Code Description SDRAM Technology
PC3200 (CL=3)
HYS64D16301HU-5-C PC3200U-30330-C0 one rank 128MB DIMM 256 Mb it (× 16)
HYS64D32300HU-5-C PC3200U-30330-A0 one ran k 256MB DIMM 256 Mbit (× 8)
HYS72D32300HU-5-C PC3200U-30330-A0 one ran k 256MB ECC-DIMM 256 Mb it (× 8)
HYS64D64320HU-5-C PC3200U-30330-B0 two ranks 512MB DIMM 256 Mbit (×8)
HYS72D64320HU-5-C PC3200U-30330-B0 two ranks 512MB ECC-DIMM 256 Mbit (×8)
PC2700 (CL=2.5)
HYS64D16301HU-6-C PC2700U-25330-C0 one rank 128MB DIMM 256 Mb it (× 16)
HYS64D32300HU-6-C PC2700U-25330-A0 one ran k 256MB DIMM 256 Mbit (× 8)
HYS72D32300HU-6-C PC2700U-25330-A0 one ran k 256MB ECC-DIMM 256 Mb it (× 8)
HYS64D64320HU-6-C PC2700U-25330-B0 two ranks 512MB DIMM 256 Mbit (×8)
HYS72D64320HU-6-C PC2700U-25330-B0 two ranks 512MB ECC-DIMM 256 Mbit (×8)
Note:All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The
Compliance Code is printe d on the module labels describin g the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
Overview
1)
latency of
1) RCD: Row-Column-Delay
Data Sheet 7 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
2 Pin Configuration
Table 3 Pin Definitions and Functions
Symbol Type
A0 - A12 I Address Inputs
BA0, BA1 I Bank Selects
DQ0 - DQ63 I/O Data Input/Output
CB0 - CB7 I/O Check Bits (×72 organization only)
RAS,
CAS, WE I Command Inputs
CKE0 - CKE1 I Clock Enable
DQS0 - DQS8 I/O SDRAM low data strobes
CK0 - CK2, I SDRAM clock (positive lines)
CK0
- CK2 I SDRAM clock (negative lines)
DM0 - DM8
DQS9 - DQS17
S0
, S1 I Chip Selects for Rank0 and Rank1
V
DD
V
SS
V
DDQ
V
DDID
V
REF
V
DDSPD
SCL I Serial bus clock
SDA I/O Serial bus data line
SA0 - SA2 I slave address sele ct
NC NC Not Connected
1)
I
I/O
PWR Power (+2.5 V)
GND Ground
PWR I/O Driver power supply
PWR VDD Indentification flag
AI I/O reference supply
PWR Serial EEPROM power supply
Function
SDRAM low data mask/
high data strobes
Pin Configuration
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note:S1 and CKE1 are used on two rank modules only
Data Sheet 8 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4 Pin Configuration
Frontside Backside
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
1
V
REF
48 A0 93 V
SS
140 NC /
DM8/DQS17
2 DQ0 49 NC / CB2 94 DQ4 141 A10
3
4 DQ1 51 NC / CB3 96
V
SS
50 V
SS
95 DQ5 142 NC / CB6
V
DDQD
143 V
DDQD
5 DQS0 52 BA1 97 DM0/ DQS9 144 NC / CB7
6DQ2 Key 98 DQ6 Key
7
V
DD
8 DQ3 53 DQ32 100
9NC 54V
DDQ
99 DQ7
V
SS
145 V
SS
101 NC 146 DQ36
10 NC 55 DQ33 102 NC 147 DQ37
11
12 DQ8 57 DQ34 104 V
13 DQ9 58
V
SS
56 DQS4 103 NC 148 V
DDQ
V
SS
105 DQ12 150 DQ38
149 DM4/DQS13
DD
14 DQS1 59 BA0 106 DQ13 151 DQ39
15
16 CK1 61 DQ40 108 V
17 CK1 62
18 V
19 DQ10 64 DQ41 111 CKE1 156
20 DQ11 65 CAS 112 V
21 CKE0 66 V
22 V
23 DQ16 68 DQ42 115 NC / A12 160
24 DQ17 69 DQ43 116 V
25 DQS2 70
26
27 A9 72 DQ48 119 DM2/DQS11 164
28 DQ18 73 DQ49 120 V
29 A7 74
30
31 DQ19 76 CK2 123 DQ23 168
32 A5 77 V
V
V
V
DDQ
SS
DDQ
SS
DDQ
60 DQ35 107 DM1/DQS10 152 V
153 DQ44
V
DDQ
DD
109 DQ14 154 RAS
SS
63 WE 110 DQ15 155 DQ45
V
DDQ
157 S0
SS
DDQ
113 NC (BA2) 158 S1
67 DQS5 114 DQ20 159 DM5/DQS14
V
SS
SS
V
DD
117 DQ21 162 DQ47
161 DQ46
71 NC 118 A11 163 NC
V
DDQ
DD
V
SS
121 DQ22 166 DQ53
165 DQ52
75 CK 2 122 A8 167 NC (A13)
V
DD
DDQ
124 V
SS
169 DM6/DQS15
33 DQ24 78 DQS6 125 A6 170 DQ54
34
35 DQ25 80 DQ51 127 DQ29 172
36 DQS3 81 V
37 A4 82
38
39 DQ26 84 DQ57 131 DQ30 176
V
SS
V
DD
79 DQ50 126 DQ28 171 DQ55
V
DDQ
V
SS
DDID
128 V
DDQ
129 DM3/DQS12 174 DQ60
173 NC
83 DQ56 130 A3 175 DQ61
V
SS
Data Sheet 9 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 4 Pin Configuration (cont’d)
Frontside Backside
PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol
40 DQ27 85
41 A2 86 DQS7 133 DQ31 178 DQ62
42
43 A1 88 DQ59 135 NC / CB5 180
44 NC / CB0 89 V
45 NC / CB1 90 NC 137 CK0 182 SA1
46
47 NC / DQS8 92 SCL 139
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connect ed”) on ×64 organised non-ECC
Table 5 Address Format
Density Organization Memory
128MB 16M × 64 1 16M × 164 13/2/10 8K 64 ms 7.8 µs
V
SS
V
DD
modules.
87 DQ58 134 NC / CB4 179 DQ63
91 SDA 138 CK0 183 SA2
Ranks
V
DD
SS
SDRAMs # of
SDRAMs
132 V
136 V
V
# of row/bank/
columns bits
SS
DDQ
SS
177 DM7/DQS16
181 SA0
184 V
Refresh Period Interval
Pin Configuration
V
DDQ
DDSPD
256MB 32M × 64 1 32M × 8 8 13/2/11 8K 64 ms 7.8 µs
256MB 32M × 72 1 32M × 8 9 13/2/11 8K 64 ms 7.8 µs
512MB 64M × 64 2 32M × 8 16 13/2/11 8K 64 ms 7.8 µs
512MB 64M × 72 2 32M × 8 18 13/2/11 8K 64 ms 7.8 µs
Data Sheet 10 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
S
DQS1
DM1/DQS10
DQS0
DM0/DQS9
DQS3
DM3/DQS12
DQS2
DM2/DQS11
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
S
D0
S
D1
DQS5
DM5/DQS14
DQS4
DM4/DQS13
DQS7
DM7/DQS16
DQS6
DM6/DQS15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D2
S
D3
* Clock Wiring
Clock
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per Clock Loading
Table/Wiring Diag rams
SDRAMs
NC
2 SDRAMs
2 SDRAMs
V
DD
V
DD/VDDQ
V
SPD
V
V
DDID
REF
Serial PD
SPD
D0 - D3
SCL
WP
A0
SA0 SA1
A1 A2
SA2
SDA
D0 - D3
SS
D0 - D3
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
BA0 - BA1
BA0-BA1: SDRAMs D0 - D3
A0 - A13 A0-A13: SDRAMs D0 - D3
RAS
CAS
RAS: SDRAMs D0 - D3
CAS: SDRAMs D0 - D3
CKE0 CKE: SDRAMs D0 - D3
WE
WE: SDRAMs D0 - D3
2. DQ/DQS/DM/CKE /S re latio n ship s mu st be ma in tained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. V
strap connections
DDID
(for memory device V
STRAP OU T (OPEN): V
DD
, V
STRAP IN (VSS): VDD ≠ V
DD
DDQ
= V
DDQ
):
DDQ
5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms ± 5%
Figure 1 Block Diagram - One Rank 16M × 64 DDR SDRAM DIMM HYS64D16301GU using ×16
organized SDRAMs
Data Sheet 11 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 I/O 7
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Serial PD
SCL
BA0 - BA 1
A0 - A13 A0-A13: SDRAMs D0 - D7
RAS RAS: SDRAMs D0 - D7
CAS
CKE0 CKE: SDRAMs D0 - D7
WE
WP
A0
SA0 SA1 SA2
S0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A1 A2
BA0-BA1: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
S
D0
S
D1
D2
S
D3
S
DQS4
DM4/DQS13
DQS
DQS5
DM5/DQS14
DQS
DQS
DQS
* Clock Wiring
Clock
SDA
V
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per Clock Loading
Tabl e/Wiring D i a grams
SPD
V
DD
DD/VDDQ
V
REF
V
SS
V
DDID Strap: see Note 4
DQS6
DM6/DQS15
DQS7
DM7/DQS16
SDRAMs
2 SDRAMs
3 SDRAMs
3 SDRAMs
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SPD
D0 - D7
D0 - D7
D0 - D7
Pin Configuration
DM
S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/C K E/S re la ti on shi ps must be
maintain ed as shown.
3. DQ, DQS, DM/DQS re sistors: 22 ohms ± 5%
4. V
DDID
(for memory device V
STRAP OUT (OPEN): V
STRAP IN (VSS): VDD ≠ V
5. BAx, Ax, RAS
+
5%
DQS
D4
DQS
S
D5
S
DQS
D6
S
DQS
D7
strap connections
, V
DD
DD
, CAS, WE resistors: 5.1 ohms
DDQ
= V
DDQ
):
DDQ
.
Figure 2 Block Diagram - One Rank 32M × 64 DDR-I SDRAM DIMM HYS64D32×00GU / HYS64D32300EU
using ×8 organized SDRAMs
Data Sheet 12 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 I/O 7
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
SPD
V
DD
V
DD/VDDQ
V
REF
V
SS
V
DDID
BA0 - BA 1
A0 - A13
CKE1 CKE: SDRAMs D8 - D15
RAS RAS: SDRAMs D0 - D15
CAS
CKE0 CKE: SDRAMs D0 - D7
WE
S0
BA0-BA1: SDRAMs D0 - D15
A0-A13: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
DQS
S
DM
I/O 0
I/O 1
D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
S
DM
I/O 0
I/O 1
D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DM
S S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQS
D2
S S
DQS
D3
SPD
D0 - D15
D0 - D15
D0 - D15
Strap: see Note 4
1
S
DM
DM
DM
DM
S
D8
S
D9
D10
D11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
Clock
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per Clock Loading
Tabl e/Wiring D i a grams
DQS4
DM4/DQS13
DQS
DQS5
DM5/DQS14
DQS
DQS6
DM6/DQS15
DQS
DQS7
DM7/DQS16
DQS
Serial PD
WP
A0
SA0 SA1 SA2
* Clock Wiring
SDRAMs
4 SDRAMs
6 SDRAMs
6 SDRAMs
A1
A2
Pin Configuration
DD
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
, V
DD
DM
DM
DM
DM
DDQ
= V
DDQ
DM
S S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DM
DQS
D5
S S
DQS DQS
D6
S S
DQS DQS
D7
SDA
Notes:
1. DQ-to-I/O wi ring is shown as recomm ended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintain e d as show n.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. V
strap connections
DDID
(for memory device V
STRAP OUT (OPEN): V
STRAP IN (VSS): VDD ≠ V
5. BAx, Ax, RAS , CAS, WE resistors: 3 ohms
+
5%
DQSDQS
D12
DQS
D13
D14
D15
):
DDQ
Figure 3 Block Diagram - Two Rank 64M × 64 DDR-I SDRAM DIMM HYS64D64×20GU using ×8
Organized SDRAMs
Data Sheet 13 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15 I/O 7
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0 - BA1 BA0-BA1: SDRAMs D0 - D8
A0 - A13 A0-A13: SDRAMs D0 - D8
RAS RAS: SDRAMs D0 - D8
CAS
CKE0 CKE: SDRAMs D0 - D8
WE
S0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CAS: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
S
D0
D1
D2
D3
S
D8
Pin Configuration
DQS4
DM4/DQS13
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQS5
DM5/DQS14
DQS
S
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQS6
DM6/DQS15
S
DQS
DQS7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DM7/DQS16
S
DQS
DQS
Serial PD
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SCL
WP
A0
A1
A2
V
DD
V
DD/VDDQ
V
V
V
SPD
REF
SS
DDID
SA0 SA1
Strap: see Note 4
SA2
SPD
D0 - D8
D0 - D8
D0 - D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SDA
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. V
DDID
(for memory device V
STRAP OUT (OPEN): V
STRAP IN (VSS): VDD ≠ V
5. BAx, Ax, RAS
+
5%
DQS
S
D4
DQS
S
D5
S
DQS
D6
S
DQS
D7
* Clock Wiring
Clock
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per Clock Loading
Tabl e/Wiring D i a grams
strap connections
, V
DD
DD
, CAS, WE resistors: 5.1 ohm
SDRAMs
3 SDRAMs
3 SDRAMs
3 SDRAMs
):
DDQ
= V
DDQ
.
DDQ
Figure 4 Block Diagram - One Rank 32M × 72 DDR-I SDRAM DIMM HYS72D32×00GU using ×8
organized SDRAMs
Data Sheet 14 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
BA0 - BA1 BA0-BA1: SDRAMs D0 - D17
A0 - A13
CKE1 CKE: SDRAMs D9 - D17
RAS RAS: SDRAMs D0 - D17
CAS
CKE0 CKE: SDRAMs D0 - D8
WE
CB7
S0
DM
S S
I/O 0
I/O 1
D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S
I/O 0
I/O 1
D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
DM
I/O 0
I/O 1
D2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S S
I/O 0
I/O 1
D3
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
S S
I/O 0
I/O 1
D8
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0-A13: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
DQS
DQS
DQS
DQS
DQS
SCL
S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1
DM
DM
DM
DM
DM
DQS4
DM4/DQS13
DQS
D9
DQS5
DM5/DQS14
DQS
S
D10
DQS6
DM6/DQS15
DQS
S
D11
DQS
D12
V
DD
V
DD/VDDQ
DQS
D17
Serial PD
WP
A0
A1 A2
SA0 SA1 SA2
DQS7
DM7/DQS16
SPD
V
REF
V
SS
V
DDID
Strap: see Note 4
SDA
Pin Configuration
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DM
DM
DM
DQS
S S
D4
DQS
S S
D5
DQS
S S
D6
S S
D7
SPD
D0 - D17
D0 - D17
D0 - D17
Notes:
1. DQ-to-I/O wi ring is shown as recomm ended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintain ed as show n.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. V
strap connections
DDID
(for memory device V
STRAP OUT (OPEN): V
STRAP IN (VSS): VDD ≠ V
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+
5%
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
* Clock Wir ing
Clock
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
* Wire per C l oc k Load i ng
Table/ Wiring Diag ra ms
, V
DD
DDQ
= V
DDQ
):
DDQ
DD
D13
DQS
D14
D15
DQSDQS
D16
SDRAMs
6 SDRAMs
6 SDRAMs
6 SDRAMs
DQS
DQS
Figure 5 Block Diagram - Two Rank 64M × 72 DDR-I SDRAM DIMM HYS72D64×20GU using ×8
Organized SDRAMs
Data Sheet 15 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
6 DRAM Loads
CK
DIMM
Connector
CK
3 DRAM Loads
DIMM
Connector
1 DRAM Loads
R = 120 Ω ± 5%
R = 120 Ω ± 5%
DRAM1
DRAM2
DRAM3
DRAM4
DRAM5
DRAM6
DRAM1
Cap.
DRAM3
Cap.
DRAM5
Cap.
Cap.
4 DRAM Loads
DIMM
Connector
2 DRAM Loads
DIMM
Connector
R = 120 Ω ± 5%
R = 120 Ω ± 5%
Pin Configuration
DRAM1
DRAM2
Cap.
Cap.
DRAM5
DRAM6
DRAM1
Cap.
Cap.
Cap.
DIMM
Connector
Cap. = 1/2 DDR SDRAM input capacitance; 1. 0 pF ± 20%
R = 120 Ω ± 5%
Figure 6 Clock Net Wiring
Cap.
DRAM3
Cap.
Cap.
Cap.
DRAM5
Cap.
Data Sheet 16 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3 Electrical Characteristics
3.1 Operating Conditions
Table 6 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/ Test
min. typ. max.
Voltage on I/O pins relative to
V
SS
V
, V
IN
–0.5 – V
OUT
DDQ
+
0.5
Voltage on inputs relative to
Voltage on
Voltage on
V
supply relative to V
DD
V
supply relative to V
DDQ
V
SS
SS
SS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component) P
Short circuit output current
V
V
V
T
T
I
IN
DD
DDQ
A
STG
D
OUT
–1 – +3.6 V –
–1 – +3.6 V –
–1 – +3.6 V –
0–+70°C–
-55 – +150 °C–
–1–W–
–50–mA–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional oper ation should be restricted to recommended o peration
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Condition
V–
Table 7 Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note/Test Condition
Min. Typ. Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage V
Output Supply Voltage V
EEPROM supply voltage V
Supply Voltage, I/O Supply
Voltage
Input Ref erence Voltage
Input Ref erence Voltage V
I/O Termination Voltage
V
DD
V
DD
DDQ
DDQ
DDSPD
V
SS
V
SSQ
V
REF
REF
V
TT
2.3 2.5 2.7 V f
≤166 MHz
CK
2.5 2.6 2.7 V fCK>166MHz
2.3 2.5 2.7 V f
≤166 MHz
CK
2.5 2.6 2.7 V fCK>166MHz
2.3 2.5 3.6 V —
,
00V—
0.49 × V
V
/ 2
DDQ
– 50 mV
V
– 0.04 V
REF
DDQ
0.5 × V
V
/ 2 V
DDQ
DDQ
0.51 × V
/ 2
DDQ
+ 50 mV
+ 0.04 V
REF
DDQ
V f
≤166 MHz
CK
V fCK>166MHz
5)
2)
3)
2)3)
4)
2)4)
(System)
Input High (Logic1) Voltage V
Input Low (Logic0) Voltage V
Input Voltage Level,
CK and CK
Inputs
Input Differential Voltage,
CK and CK
Inputs
V
V
IH(DC)
IL(DC)
IN(DC)
ID(DC)
V
+ 0.15 V
REF
–0.3 V
–0.3 V
0.36 V
+ 0.3 V
DDQ
– 0.15 V
REF
+ 0.3 V
DDQ
+ 0.6 V
DDQ
8)
8)
8)
8)6)
1)
Data Sheet 17 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 7 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter Symbol Values Unit Note/Test Condition
1)
Min. Typ. Max.
VI-Matching Pull-up
VI
Ratio
0.71 1.4 —
7)
Current to Pull-down
Current
Input Leakage Current I
I
–2 2 µA Any input 0 V ≤VIN≤VDD;
All other pins not under test
8)9)
=0V
Output Leakage Current I
Output High Current,
OZ
I
OH
–5 5 µA DQs are disabled;
0V ≤
V
≤ V
—–16.2mAV
OUT
=
OUT
1.95 V
DDQ
8)
8)
Normal Strength Driver
Output Low
I
OL
16.2 — mA V
= 0.35 V
OUT
8)
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
V
3) Under all conditions,
4) Peak to peak AC noise on
V
is not applied directly to the dev ic e. VTT is a system supply fo r signal term in ation resistors, is expected to be set equal
5)
TT
to
V
, and must track variations in the DC level of V
REF
V
is the magnitude of the difference between the input level on CK and the input level on CK.
6)
ID
7) The ration of the pull-up current to th e p ul l-do w n c urre nt is s pecified for the same tem pe ratu r e and v olta ge , o ver th e e nti re
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until
9) Values are shown per DDR SDRAM component
must be less than or equal to VDD.
DDQ
V
may not exceed ±2% V
REF
V
stabilizes.
REF
REF
REF (DC)
.
. V
is also expected to track noise variations in V
REF
DDQ
.
Data Sheet 18 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2 Current Conditions and Specification
Table 8 IDD Conditions
Parameter Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤
V
IL,MAX
Precharge Floating Standby Current
CS
≥ V
address and other control inputs changing once per clock cycle;
, all banks idle; CKE ≥ V
IH,,MIN
IH,MIN
;
V
IN
= V
for DQ, DQS and DM.
REF
Precharge Quiet Standby Current
CS
≥ V
address and other control inputs stable at ≥
, all banks idle; CKE ≥ V
IHMIN
IH,MIN
; VIN = V
V
IH,MIN
for DQ, DQS and DM;
REF
or ≤ V
IL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤
V
ILMAX
; VIN = V
for DQ, DQS and DM.
REF
Active Standby Curre nt
one bank active; CS
≥ V
IH,MIN
; CKE ≥ V
IH,MIN
; tRC= t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
=0mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
= t
, distributed refresh
RFCMIN
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
Data Sheet 19 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 9
I
Specification (PC2700, –6)
DD
HYS64D16301HU-6-C
HYS64D32000HU-6-C
HYS72D32000HU-6-C
HYS64D64020HU-6-C
HYS72D64020HU-6-C
Electrical Characteristics
Unit Note
1)2)
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 ×64 ×72
1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks
Part Number & Organization
–6 –6 –6 –6 –6
Symbol typ. max. typ. max. typ. max. typ. max. typ. max.
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
1) Module IDD values are ca lc ulated on the bas is of component IDD and can be mea su red differently accordin g to DQ loading
capacity.
2) Test condition for maximum values: VDD=2.7V, TA=10°C
3) The module I
m ×
4) DQ I/O (I
5) The module I
260 300 480 600 540 675 736 904 828 1017 mA
320 380 560 680 630 765 816 984 918 1107 mA
14 18 28 36 31.5 40.5 56 72 63 81 mA
100 340 200 240 225 270 400 480 450 540 mA
68 96 136 192 153 216 272 384 306 432 mA
44 60 88 120 99 135 176 240 198 270 mA
136 160 256 304 288 342 512 608 576 684 mA
340 400 560 680 630 765 816 984 918 1107 mA
360 440 600 720 675 810 856 1024 963 1152 mA
540 640 1080 1280 1215 1440 1336 1584 1503 1782 mA
5.6 11.2 11.2 22.4 12.6 25.2 44.8 22.4 25.2 25.2 mA
820 960 1440 1720 1620 1935 1696 2024 1908 2277 mA
values are calculated from the I
I
DDx
DDx
[component] + n × I
) currents are not included in the calculations (see note 1)
DDQ
values are calculated from the corrponent I
DDx
[component] with m and n number of comp onents of rank 1 and 2; n=0 for 1 rank m odules
DD3N
values of the component data sheet as follows:
DDx
data sheet values as: (m + n) × I
DDx
DDx
3)
3)4)
5)
5)
5)
5)
5)
3)4)
3)
3)
5)
3)4)
[component]
Data Sheet 20 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 10
I
Specification (PC3200, –5)
DD
HYS64D16301HU-5-C
HYS64D32000HU-5-C
HYS72D32000HU-5-C
HYS64D64020HU-5-C
Electrical Characteristics
Unit Note
HYS72D64020HU-5-C
1)2)
128MB 256MB 256MB 512MB 512MB
×64 ×64 × 72 ×64 ×72
1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks
Part Number & Organization
–5 –5 –5 –5 –5
Symbol typ. max. typ. max. typ. max. typ. max. typ. max.
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading
capacity.
2) Test condition for maximum values: VDD=2.7V, TA=10°C
3) The module I
m ×
4) DQ I/O (I
5) The module I
280 340 560 640 630 720 848 984 954 1107 mA
340 420 640 760 720 855 928 1104 1044 1242 mA
14 18 28 36 31.5 40.5 56 72 63 81 mA
120 144 240 288 270 324 480 576 540 648 mA
76 104 152 208 171 234 304 416 342 468 mA
48 64 96 128 108 144 192 256 216 288 mA
152 184 288 344 324 387 576 688 648 774 mA
400 480 680 800 765 900 968 1144 1089 1287 mA
420 520 720 840 810 945 1008 1184 1134 1332 mA
600 720 1200 1440 1350 1620 1488 1784 1674 2007 mA
6 11.6 12 23.2 13.5 26.1 24 46.4 27 52.2 mA
900 1060 1600 1920 1800 2160 1888 2264 2124 2547 mA
values are calculated from the I
I
DDx
DDx
[component] + n × I
) currents are not included in the calculations (see note 1)
DDQ
values are calculated from the corrponent I
DDx
[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
DD3N
values of the component data sheet as follows:
DDx
data sheet values as: (m + n) × I
DDx
[component]
DDx
3)
3)4)
5)
5)
5)
5)
5)
3)4)
3)
3)
5)
3)4)
Data Sheet 21 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.3 AC Characteristics
Table 11 AC Timing - Absolute Specifications –6/–5
Parameter Symbol –6 –5 Unit Note/ Test
CK
CK
CK
CK
CK
CK
CK
CK
CK
Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
3)4)5)6)10)
DQ output access time from CK/CK
DQS output access time from CK/CK t
CK high-level width t
CK low-level width t
Clock Half Period t
Clock cycle time t
DQ and DM input hold time t
DQ and DM input setup time t
Control and Addr. input pulse width (ea ch
input)
DQ and DM input pulse width (each input) t
Data-out high-impedance time from CK/CK t
Data-out low-impedance time from CK/CK t
Write command to 1st DQS latching transition t
DQS-DQ skew (DQS and associated DQ
signals)
Data hold skew factor t
DQ/DQS output hold time t
DQS input low (high) pulse width (write cycle) t
DQS falling edge to CK setup time (write cycle) t
DQS falling edge hold time from CK (write
cycle)
Mode register set command cycle time t
Write preamble setup time t
Write postamble t
Write preamble t
Address and control input setup time t
t
AC
DQSCK
CH
CL
HP
CK
DH
DS
t
IPW
DIPW
HZ
LZ
DQSS
t
DQSQ
QHS
QH
DQSL,H
DSS
t
DSH
MRD
WPRES
WPST
WPRE
IS
DDR333 DDR400B
Min. Max. Min. Max.
–0.7 +0.7 –0.6 +0.6 ns
–0.6 +0.6 –0.5 +0.5 ns
0.45 0.55 0.45 0.55 t
0.45 0.55 0.45 0.55 t
min. (tCL, tCH)min. (tCL, tCH)ns
6 12 5 12 ns CL = 3.0
6 12 6 12 ns CL = 2.5
7.5 12 7.5 12 ns CL = 2.0
0.45—0.4—ns
0.45—0.4—ns
2.2 — tbd — ns
1.75 — tbd — ns
–0.7 +0.7 –0.6 +0.6 ns
–0.7 +0.7 –0.6 +0.6 ns
0.75 1.25 0.75 1.25 t
— +0.40 — +0.40 ns TFBGA
— +0.45 — +0.40 ns TSOPII
— +0.50 — +0.50 ns TFBGA
— +0.55 — +0.50 ns TSOPII
t
–
HP
t
QHS
— tHP –
t
QHS
—ns
0.35 — 0.35 — t
0.2 — 0.2 — t
0.2 — 0.2 — t
2—2—t
0—0—ns
0.40 0.60 0.40 0.60 t
0.25 — 0.25 — t
0.75 — 0.6 — ns fast slew rate
1)
2)3)4)5)
2)3)4)5)
2)3)4)5)
0.8 — 0.7 — ns slow slew rate
3)4)5)6)10)
Address and control input hold time t
Read preamble t
IH
RPRE
0.75 — 0.6 — ns fast slew rate
0.8 — 0.7 — ns slow slew rate
0.9 1.1 0.9 1.1 t
CK
3)4)5)6)10)
3)4)5)6)10)
2)3)4)5)
Data Sheet 22 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 11 AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter Symbol –6 –5 Unit Note/ Test
DDR333 DDR400B
Condition
1)
Min. Max. Min. Max.
Read postamble
Active to Precharge command t
Active to Active/Auto-refresh command period t
Auto-refresh to Active/Auto-refresh command
t
RPST
RAS
RC
t
RFC
0.40 0.60 0.40 0.60 t
42 70E+3 40 70E+3 ns
60 — 55 — ns
72 — 65 — ns
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
period
Active to Read or Write delay t
Precharge command period t
Active to Autoprecharge delay t
Active bank A to Active bank B command t
Write recovery time t
Auto precharge write recovery + precharge
RCD
RP
RAP
RRD
WR
t
DAL
18 — 15 — ns
18 — 15 — ns
18 — 15 — ns
12 — 10 — ns
15 — 15 — ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
t
CK
time
Internal write to read command delay t
Exit self-refresh to non-read command t
Exit self-refresh to read command t
Average Periodic Refresh Interval t
1) 0 °C ≤ TA ≤ 70 °C; V
= 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); V
DDQ
WTR
XSNR
XSRD
REFI
1—1—t
75 — 75 — ns
200 — 200 — t
—7.8—7.8µs
= 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V (DDR400)
DDQ
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK
level for signals other than CK/CK
4) Inputs are not recognized as valid until
input reference level (f or timing refere nce to CK/CK) is th e point at wh ich CK and CK cross: the in put reference
, is V
. CK/CK slew rate are ≥ 1.0 V/ns.
REF
V
stabilizes.
REF
5) The Output timing reference level , as measured a t the timing r eference poin t indicated i n AC Characteris tics (note 3) i s
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
t
and tLZ transitions occur in the s am e a cc ess tim e wind ow s as v al id data transitions. The se pa ram ete rs are no t re ferre d
7)
HZ
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific req ui rem ent is th at D QS b e v al id (H IG H, L OW , or some point on a va lid tra ns itio n) on or b efo re this CK edge.
A valid transition is d efined as monoton ic and meeting the input slew rate specificatio ns of the devi ce. When no writ es were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
t
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
DQSS
.
9) The maximum limi t for th is paramet er is not a devic e limit . The devi ce ope rates with a greater v alue for th is para meter, bu t
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for co mmand/ad dress and CK & CK
V
measured between
OH(ac)
and V
11) For each of the terms, if not already an integer, round to the next highest integer.
OL(ac)
.
t
is equal to the actual system clock
CK
cycle time.
12) A maximum o f eight Autorefresh commands can be posted to any given DDR SDRAM device.
2)3)4)5)
CK
2)3)4)5)
2)3)4)5)
CK
2)3)4)5)12)
slew rate > 1.0 V/ns,
V
TT
.
Data Sheet 23 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
SPD Contents
4 SPD Contents
Table 12 SPD Codes for PC2700 Modules “–6”
HYS64D16301HU–6–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 ×64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
0 Programmed SPD Bytes in
E2PROM
1 Total number of Bytes in
E2PROM
2 Memory Type DDR-I = 07h DDR SDRAM 07 07 07 07 07
3 # of Row Addresses 13 0D 0D 0D 0D 0D
4 # Number of Column
Addresses
5 # of DIMM Banks 1/2 01 01 01 02 02
6 Data Width (LSB) ×64/×72 40 40 48 40 48
7 Data Width (MSB) 0 00 00 00 00 00
8 Interface Voltage Levels SSTL_2.5 04 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 6 ns 60 60 60 60 60
10 tAC SDRAM @ CLmax
(Byte 18) [ns]
11 DIMM Configuration Type
(non- / ECC)
12 Refresh Rate Self-Refresh 7.8 µs82828282 82
13 Primary SDRAM width ×16/×8 10080808 08
14 Error Checking SDRAM
width
15 tCCD [cycles]
16 Burst Length Supported 2, 4 & 8 0E 0E 0E 0E 0E
17 Number of Banks on
SDRAM
18 CAS Latency CAS latency = 2 & 2.5 0C 0C 0C 0C 0C
19 CS Latency CS latency = 0 01 01 01 01 01
20 WE (Write) Latency Write latency = 1 02 02 02 02 02
21 DIMM Attributes unbuffered 20 20 20 20 20
128 80 80 80 80 80
256 08 08 08 08 08
9/10 09 0A 0A 0A 0A
0.75 ns 70 70 70 70 70
non-ECC/ECC 00000200 02
na/×8 00000800 08
t
=1 CLK 01010101 01
CCD
4 04040404 04
–6 –6 –6 –6 –6
HYS64D32300HU–6–C
HYS72D32300HU–6–C
HYS64D64320HU–6–C
HYS72D64320HU–6–C
Data Sheet 24 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 12 SPD Codes for PC2700 Modules “–6” (cont’d)
HYS64D16301HU–6–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 ×64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
22 Component Attributes — C1 C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18)
[ns]
24 tAC SDRAM @ CLmax -0.5
[ns]
25 tCK @ CLmax -1 (Byte 18)
[ns]
26 tAC SDRAM @ CLmax -1
[ns]
27 tRPmin (ns) 18 ns 48 48 48 48 48
28 tRRDmin [ns] 12 ns 30 30 30 30 30
29 tRCDmin [ns] 18 ns 48 48 48 48 48
30 tRASmin [ns] 42 ns 2A 2A 2A 2A 2A
31 Module Density per Bank 128 MByte/ 256 MByte 20 40 40 40 40
32 tAS, tCS [ns] 0.75 ns 75 75 75 75 75
33 tAH, TCH [ns] 0.75 ns 75 75 75 75 75
34 tDS [ns] 0.45 ns 45 45 45 45 45
35 tDH [ns] 0.45 ns 45 45 45 45 45
36 to 40 not used — 00 00 00 00 00
41 tRCmin [ns] 60 ns 3C 3C 3C 3C 3C
42 tRFCmin [ns] 72 ns 48 48 48 48 48
43 tCKmax [ns] 12 ns 30 30 30 30 30
44 tDQSQmax [ns] 0.45 ns 2D 2D 2D 2D 2D
45 tQHSmax [ns] 0.55 ns 55 55 55 55 55
46 to 61 not used — 00 00 00 00 00
62 SPD Revision Revision 0.0 00 00 00 00 00
63 Checksum of Byte 0-62
(LSB only)
64 JEDEC ID Code for Infineon — C1 C1 C1 C1 C1
65 to 71 JEDEC ID Code for Infineon — 00 00 00 00 00
7.5ns 75757575 75
0.70 ns 70 70 70 70 70
not supported 00 00 00 00 00
not supported 00 00 00 00 00
—E801130214
–6 –6 –6 –6 –6
HYS64D32300HU–6–C
HYS72D32300HU–6–C
SPD Contents
HYS64D64320HU–6–C
HYS72D64320HU–6–C
Data Sheet 25 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 12 SPD Codes for PC2700 Modules “–6” (cont’d)
HYS64D16301HU–6–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 ×64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
72 Module Manufacturer
Location
73 Part Number, Char 1 — 36 36 37 36 37
74 Part Number, Char 2 — 34 34 32 34 32
75 Part Number, Char 3 — 44 44 44 44 44
76 Part Number, Char 4 — 31 33 33 36 36
77 Part Number, Char 5 — 36 32 32 34 34
78 Part Number, Char 6 — 33 33 33 33 33
79 Part Number, Char 7 — 30 30 30 32 32
80 Part Number, Char 8 — 31 30 30 30 30
81 Part Number, Char 9 — 48 48 48 48 48
82 Part Number, Char 10 — 55 55 55 55 55
83 Part Number, Char 11 — 36 36 36 36 36
84 Part Number, Char 12 — 43 43 43 43 43
85 Part Number, Char 13 — 20 20 20 20 20
86 Part Number, Char 14 — 20 20 20 20 20
87 Part Number, Char 15 — 20 20 20 20 20
88 Part Number, Char 16 — 20 20 20 20 20
89 Part Number, Char 17 — 20 20 20 20 20
90 Part Number, Char 18 — 20 20 20 20 20
91 Module Revision Code — xx xx xx xx xx
92 Test Program Revision
Code
93 Module Manufacturing Date
Year
94 Module Manufacturing Date
Week
95 to 98 Module Serial Number — xx xx xx xx xx
99 to 127 not used — 00 00 00 00 00
—xxxxxxxxxx
—xxxxxxxxxx
—xxxxxxxxxx
—xxxxxxxxxx
–6 –6 –6 –6 –6
HYS64D32300HU–6–C
HYS72D32300HU–6–C
SPD Contents
HYS64D64320HU–6–C
HYS72D64320HU–6–C
Data Sheet 26 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 13 SPD Codes for PC3200 Modules “–5”
HYS64D16301HU–5–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 × 64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
0 Programmed SPD Bytes in E2PROM 128 80 80 80 80 80
1 Total number of Bytes in E2PROM 256 08 08 08 08 08
2 Memory Type DDR-I = 07h DDR SDRAM 07 07 07 07 07
3 # of Row Addresses 13 0D 0D 0D 0D 0D
4 # Number of Column Addresses 9/10 09 0A 0A 0A 0A
5 # of DIMM Banks 1/2 01 01 01 02 02
6 Data Width (LSB) ×64/×72 40 40 48 40 48
7 Data Width (MSB) 0 00 00 00 00 00
8 Interface Voltage Levels SSTL_2.5 04 04 04 04 04
9 tCK @ CLmax (Byte 18) [ns] 5 ns 50 50 50 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 0.50 ns 50 50 50 50 50
11 DIMM Configuration Type (non- / ECC) non-
12 Refresh Rate Self-Refresh
13 Primary SDRAM width ×16/×8 10080808 08
14 Error Checking SDRAM width na/×8 00000800 08
15 tCCD [cycles]
16 Burst Length Supported 2, 4 & 8 0E 0E 0E 0E 0E
17 Number of Banks on SDRAM 4 04 04 04 04 04
18 CAS Latency CAS
19 CS Latency CS
20 WE (Write) Latency Write
21 DIMM Attributes unbuffered 20 20 20 20 20
22 Component Attributes — C1 C1 C1 C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 6.0 ns 60 60 60 60 60
ECC/ECC
7.8 µs
t
=1 CLK01010101 01
CCD
latency = 2,
2.5, 3
latency = 0
latency = 1
–5 –5 –5 –5 –5
00 00 02 00 02
82 82 82 82 82
1C 1C 1C 1C 1C
01 01 01 01 01
02 02 02 02 02
HYS64D32300HU–5–C
HYS72D32300HU–5–C
SPD Contents
HYS64D64320HU–5–C
HYS72D64320HU–5–C
Data Sheet 27 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 13 SPD Codes for PC3200 Modules “–5” (cont’d)
HYS64D16301HU–5–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 × 64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
24 tAC SDRAM @ CLmax -0.5 [ns] 0.50 ns 50 50 50 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 7.5 ns 75 75 75 75 75
26 tAC SDRAM @ CLmax -1 [ns] 0.50 ns 50 50 50 50 50
27 tRPmin (ns) 15 ns 3C 3C 3C 3C 3C
28 tRRDmin [ns] 10 ns 28 28 28 28 28
29 tRCDmin [ns] 15 ns 3C 3C 3C 3C 3C
30 tRASmin [ns] 40 ns 28 28 28 28 28
31 Module Density per Bank 128 MByte/
32 tA S, tCS [ns ] 0.60 ns 60 60 60 60 60
33 tAH, TCH [ns] 0.60 ns 60 60 60 60 60
34 tDS [ns] 0.40 ns 40 40 40 40 40
35 tDH [ns] 0.40 ns 40 40 40 40 40
36 to 40 not used — 00 00 00 00 00
41 tRCmin [ns] 55 ns 37 37 37 37 37
42 tRFCmin [ns] 65 ns 41 41 41 41 41
43 tCKmax [ns] 10 ns 28 28 28 28 28
44 tDQSQmax [ns] 0.40 ns 28 28 28 28 28
45 tQHSmax [ns] 0.50 ns 50 50 50 50 50
46 to 61 not used — 00 00 00 00 00
62 SPD Revision Revision 0.0 00 00 00 00 00
63 Checksum of Byte 0-62 (LSB only) — E4 FD 0F FE 10
64 JEDEC ID Code for Infineon — C1 C1 C1 C1 C1
65 to 71 JEDEC ID Code for Infineon — 00 00 00 00 00
72 Module Manufacturer Location — xx xx xx xx xx
73 Part Number, Char 1 — 36 36 37 36 37
74 Part Number, Char 2 — 34 34 32 34 32
75 Part Number, Char 3 — 44 44 44 44 44
76 Part Number, Char 4 — 31 33 33 36 36
77 Part Number, Char 5 — 36 32 32 34 34
256 MByte
–5 –5 –5 –5 –5
20 40 40 40 40
HYS64D32300HU–5–C
HYS72D32300HU–5–C
SPD Contents
HYS64D64320HU–5–C
HYS72D64320HU–5–C
Data Sheet 28 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
Table 13 SPD Codes for PC3200 Modules “–5” (cont’d)
HYS64D16301HU–5–C
128MB 256MB 256MB 512MB 512MB
×64 ×64 ×72 × 64 ×72
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Part Number & Organization
Byte# Description HEX HEX HEX HEX HEX
78 Part Number, Char 6 — 33 33 33 33 33
79 Part Number, Char 7 — 30 30 30 32 32
80 Part Number, Char 8 — 31 30 30 30 30
81 Part Number, Char 9 — 48 48 48 48 48
82 Part Number, Char 10 — 55 55 55 55 55
83 Part Number, Char 11 — 35 35 35 35 35
84 Part Number, Char 12 — 43 43 43 43 43
85 Part Number, Char 13 — 20 20 20 20 20
86 Part Number, Char 14 — 20 20 20 20 20
87 Part Number, Char 15 — 20 20 20 20 20
88 Part Number, Char 16 — 20 20 20 20 20
89 Part Number, Char 17 — 20 20 20 20 20
90 Part Number, Char 18 — 20 20 20 20 20
91 Module Revision Code — xx xx xx xx xx
92 Test Program Revision Code — xx xx xx xx xx
93 Module Manufacturing Date Year — xx xx xx xx xx
94 Module Manufacturing Date Week — xx xx xx xx xx
95 to 98 Module Serial Number — xx xx xx xx xx
99 to 127not used — 0000 0
–5 –5 –5 –5 –5
HYS64D32300HU–5–C
HYS72D32300HU–5–C
SPD Contents
HYS64D64320HU–5–C
HYS72D64320HU–5–C
Data Sheet 29 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
5 Package Outlines
BC
A
0.1
±0.1
4
1
±0.1
2.36
ø0.1
ACB
64.77
133.35
128.95
6.62
2.175
Package Outlines
0.15
1)
A
±0.13
31.75
92
6.35
49.53
B
0.4
B
A C
2.7 MAX.
C
±0.1
1.27
±0.13
3.8
93
3 MIN.
Detail of contacts
0.2
±0.2
2.5
95
1.8
=1.27x 120.65
±0.1
0.1
BAC
184
10
17.8
1.27
1) On ECC modules only
Burr max. 0.4 allowed
Figure 7 Package Outlines - Raw Card C (128 MByte, 1 Rank Module)
Data Sheet 30 V1.0, 2003-07
1
±0.05
0.1
BA C
L-DIM-184-18
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
L-DIM
Unbuffered DDR SDRAM Modules
133.35
1)
128.95
A
±0.1
4
ACB
0.1
Package Outlines
0.15
±0.13
BA C
2.7 MAX.
31.75
92
1
1
2.36
±0.1
ø0.1
A B
64.77
C
6.62
2.175
6.35
49.53
1.27x95 120.65=
92
B
0.4
C
1.27
±0.1
±0.13
3.8
93
3 MIN.
Detail of contacts
0.2
1.27
1) On ECC modules only
Burr max. 0.4 allowed
1
±0.05
±0.2
2.5
0.1
BA C
1.8
±0.1
0.1
CA
B
184
10
17.8
-184-30
Figure 8 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, ECC)
Data Sheet 31 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
L-DIM-184-31
Unbuffered DDR SDRAM Modules
133.35
128.95
1)
6.62
2.175
95 x 1.27 = 120.65
A
6.35
92
±0.1
4
ACB
0.1
1
2.36
±0.1
ø0.1
BA C
64.77 49.53
Package Outlines
0.15
ACB
4 MAX.
±0.13
31.75
B
C
0.4
1.27
±0.1
±0.1
ACB
1.8
1)
0.1
A B C
±0.13
3.8
93 184
3 MIN.
Detail of contacts
±0.2
1
2.5
±0.05
0.1
0.2
1.27
1) On ECC modules only
Burr max. 0.4 allowed
10
17.8
Figure 9 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, ECC)
Data Sheet 32 V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
133.35
128.95
6.62
2.175
A
92
92
92
6.35
49.53
±0.1
4
A BC
0.1
1
1
2.36
±0.1
ø0.1
CBA
64.77
Package Outlines
0.15
±0.13
31.75
B
0.4
B
A C
2.7 MAX.
C
±0.1
1.27
±0.13
3.8
93
3 MIN.
Detail of contacts
0.2
±0.2
2.5
95 x
1.8
±0.1
120.651.27 =
0.1
A
CB
184
10
17.8
1.27
Burr max. 0.4 allowed
Figure 10 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, Non ECC)
Data Sheet 33 V1.0, 2003-07
±0.05
1
0.1
BA C
L-DIM-184-32
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C
Unbuffered DDR SDRAM Modules
133.35
128.95
6.62
2.175
1.27x=
95
A
92
6.35
49.53
120.65
±0.1
4
CB
A
0.1
1
2.36
±0.1
ø0.1
A B
64.77
C
Package Outlines
0.15
±0.13
31.75
B
0.4
A C
4 MAX.
C
1.27
B
±0.1
±0.13
3.8
93
3 MIN.
Detail of contacts
0.2
1.27
Burr max. 0.4 allowed
1
±0.05
±0.2
2.5
0.1
ACB
1.8
±0.1
0.1
BA C
184
10
17.8
L-DIM-184-33
Figure 11 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, Non ECC)
Data Sheet 34 V1.0, 2003-07
www.infineon.com
Published by Infineon Technologies AG
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