The BTS 7960 is a fully integrated high current half
bridge for motor drive applications. It is part of the
TM
NovalithIC
MOSFET and one n-channel lowside MOSFET with an
integrated driver IC in one package. Due to the p-channel
highside switch the need for a charge pump is eliminated
thus minimizing EMI. Interfacing to a microcontroller is
made easy by the integrated driver IC which features
logic level inputs, diagnosis with current sense, slew rate
adjustment, dead time generation and protection against
overtemperature, overvoltage, undervoltage,
overcurrent and short circuit.
family containing one p-channel highside
BTS 7960B
BTS 7960P
BTS 7960B
P-TO-263-7
BTS 7960P
P-TO-220-7
The BTS 7960 provides a cost optimized solution for
protected high current PWM motor drives with very low
board space consumption.
Basic Features
• Path resistance of typ. 16 mΩ @25°C
• Low quiescent current of typ. 7 µA @ 25 °C
• PWM capability of up to 25 kHz combined with active freewheeling
• Switched mode current limitation for reduced power dissipation in overcurrent
• Current limitation level of 43 A typ.
• Status flag diagnosis with current sense capability
The BTS 7960 is part of the NovalithIC family containing three separate chips in one
package: One p-channel highside MOSFET and one n-channel lowside MOSFET
together with a driver IC, forming a fully integrated high current half-bridge. All three
chips are mounted on one common leadframe, using the chip on chip and chip by chip
technology. The power switches utilize vertical MOS technologies to ensure optimum on
state resistance. Due to the p-channel highside switch the need for a charge pump is
eliminated thus minimizing EMI. Interfacing to a microcontroller is made easy by the
integrated driver IC which features logic level inputs, diagnosis with current sense, slew
rate adjustment, dead time generation and protection against overtemperature,
overvoltage, undervoltage, overcurrent and short circuit. The BTS 7960 can be
combined with other BTS 7960 to form H-bridge and 3-phase drive configurations.
1.1Block Diagram
IN
INH
SR
IS
BTS 7960
Top-chip
Gate Driver
Dead Time Gen.
Slew Rate Adj.
UV Shut Down
OV Lock Out
OT Shut Down
Current Lim.
Diagnosis
Current Sense
HS base-chip
VS
OUT
LS base-chip
GND
Figure 1Block Diagram
Data Sheet3Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
1.2Terms
Following figure shows the terms used in this data sheet.
V
VS ,VS
V
IN
V
INH
V
SR
V
I
IS
I
IN
INH
I
SR
I
IN
INH
BTS 7960
SR
IS
IS
VS
GND
IVS, -I
D(HS)
OUT
I
OUT
V
V
SD (L S)
DS(HS)
, I
L
Overview
V
OUT
Figure 2Terms
I
GND,ID(LS)
Data Sheet4Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
2Pin Configuration
2.1Pin Assignment
BTS 7960B
P-TO-263-7
8
Pin Configuration
BTS 7960P
P-TO-220-7
8
123567
4
6
4
1235
7
Figure 3Pin Assignment BTS 7960B and BTS 7960P (top view)
2.2Pin Definitions and Functions
PinSymbolI/OFunction
1GND -Ground
2INIInput
Defines whether high- or lowside switch is activated
3INH IInhibit
When set to low device goes in sleep mode
4,8OUTOPower output of the bridge
5SRISlew Rate
The slew rate of the power switches can be adjusted
by connecting a resistor between SR and GND
6ISOCurrent Sense and Diagnosis
7VS-Supply
Bold type: pin needs power wiring
Data Sheet5Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Maximum Ratings
3Maximum Ratings
T
-40 °C <
PosParameterSymbolLimitsUnitTest Condition
Electrical Maximum Ratings
3.0.1Supply voltage
3.0.2Logic Input Voltage
3.0.3HS/LS continuous drain
3.0.4HS pulsed drain current
3.0.5LS pulsed drain current
3.0.6Voltage at SR pin
3.0.7Voltage between VS and
< 150 °C (unless otherwise specified)
j
V
VS
V
IN
V
INH
I
D(HS)
current
I
D(LS)
I
D(HS)
I
D(LS)
V
SR
V
VS -VIS
IS pin
minmax
-0.345V
-0.35.3V
-4040
-6060
-6060
1)
ATC < 85°C
1)
ATC < 85°C
1)
A
-0.31.0V
-0.345V
switch active
t
= 10ms
pulse
3.0.8Voltage at IS pin
V
IS
-2045V
Thermal Maximum Ratings
3.0.9Junction temperature
3.0.10 Storage temperature
T
j
T
stg
-40150°C
-55150°C
ESD Susceptibility
3.0.11 ESD susceptibility HBM
V
ESD
kVaccording to EIA/
JESD 22-A 114B
IN, INH, SR, IS
OUT, GND, VS
1)
Maximum reachable current may be smaller depending on current limitation level
-2
-6
2
6
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the device. Exposure to maximum rating conditions
for extended periods of time may affect device reliability
Data Sheet6Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
4Block Description and Characteristics
4.1Supply Characteristics
– 40 °C < Tj < 150 °C, 8 V < VS < 18 V, IL = 0A (unless otherwise specified)
The power stages of the BTS 7960 consist of a p-channel vertical DMOS transistor for
the high side switch and a n-channel vertical DMOS transistor for the low side switch. All
protection and diagnostic functions are located in a separate top chip. Both switches can
be operated up to 25 kHz, allowing active freewheeling and thus minimizing power
dissipation in the forward operation of the integrated diodes.
The on state resistance
junction temperature
Figure 4.
High Side Switch
25
mΩ
R
is dependent on the supply voltage VS as well as on the
ON
T
. The typical on state resistance characteristics are shown in
j
Low Side Switch
25
mΩ
R
ON(HS)
20
15
= 150°C
T
10
5
481216202428
j
= 25°C
T
j
= -40°C
T
j
V
S
V
R
ON(LS)
20
15
10
5
481216202428
Figure 4Typical On State Resistance vs. Supply Voltage
Tj = 150°C
Tj = 25°C
Tj = -40°C
V
S
V
Data Sheet8Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
4.2.1Power Stages - Static Characteristics
– 40 °C < Tj < 150 °C, 8 V < VS < 18 V (unless otherwise specified)
Due to active freewheeling, diode is conducting only for a few µs, depending on R
Data Sheet9Rev. 1.1, 2004-12-07
SR
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
4.2.2Switching Times
IN
t
dr(HS)tr(HS)
V
OUT
90%
∆V
OUT
10%
Figure 5Definition of switching times high side (R
t
df(HS)tf(HS)
∆V
OUT
to GND)
load
t
90%
10%
t
IN
t
V
OUT
90%
10%
t
df(LS)tf(LS)
∆V
OUT
t
dr(LS)tr(LS)
∆V
OUT
90%
10%
t
Figure 6Definition of switching times low side (R
load
to VS)
Due to the timing differences for the rising and the falling edge there will be a slight
difference between the length of the input pulse and the length of the output pulse. It can
be calculated using the following formulas:
The device provides integrated protection functions. These are designed to prevent IC
destruction under fault conditions described in the data sheet. Fault conditions are
considered as “outside” normal operating range. Protection functions are not to be used
for continuous or repetitive operation, with the exception of the current limitation
(Chapter 4.3.4). In a fault condition the BTS 7960 will apply the highest slew rate
possible independent of the connected slew rate resistor. Overvoltage, overtemperature
and overcurrent are indicated by a fault current I
IS(LIM)
at the IS pin as described in the
paragraph “Status Flag Diagnosis With Current Sense Capability” on Page 17 and
Figure 10.
In the following the protection functions are listed in order of their priority. Overvoltage
lock out overrides all other error modes.
4.3.1Overvoltage Lock Out
To assure a high immunity against overvoltages (e.g. load dump conditions) the device
shuts the lowside MOSFET off and turns the highside MOSFET on, if the supply voltage
is exceeding the over voltage protection level
again with a hysteresis
voltage
V
OV(ON)
. In H-bridge configuration, this behavior of the BTS 7960 will lead to
V
OV(HY)
if the supply voltage decreases below the switch-on
freewheeling in highside during over voltage.
V
OV(OFF)
. The IC operates in normal mode
4.3.2Undervoltage Shut Down
To avoid uncontrolled motion of the driven motor at low voltages the device shuts off
(output is tri-state), if the supply voltage drops below the switch-off voltage
IC becomes active again with a hysteresis
switch-on voltage
V
UV(ON)
.
V
UV(HY)
if the supply voltage rises above the
V
UV(OFF)
. The
4.3.3Overtemperature Protection
The BTS 7960 is protected against overtemperature by an integrated temperature
sensor. Overtemperature leads to a shut down of both output stages. This state is
latched until the device is reset by a low signal with a minimum length of
pin, provided that its temperature has decreased at least the thermal hysteresis ∆
t
reset
at the INH
T in the
meantime.
Repetitive use of the overtemperature protection might reduce lifetime.
4.3.4Current Limitation
The current in the bridge is measured in both switches. As soon as the current in forward
direction in one switch (high side or low side) is reaching the limit
deactivated and the other switch is activated for
t
. During that time all changes at the
CLS
I
, this switch is
CLx
Data Sheet13Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
IN pin are ignored. However, the INH pin can still be used to switch both MOSFETs off.
After
t
the switches return to their initial setting. The error signal at the IS pin is reset
CLS
t
after 2 *
. Unintentional triggering of the current limitation by short current spikes
CLS
(e.g. inflicted by EMI coming from the motor) is suppressed by internal filter circuitry. Due
to thresholds and reaction delay times of the filter circuitry the effective current limitation
level
I
depends on the slew rate of the load current dI/dt as shown in Figure 8
CLx
I
I
CLx
I
CLx0
L
t
CLS
Figure 7Timing Diagram Current Limitation
Low SideSwitchHigh Side Switch
80
75
70
[A]
65
CLH
I
60
55
50
45
40
I
CLH0
Tj = 25°C
Tj = -40°C
Tj = 150°C
80
75
70
[A]
65
CLL
I
60
55
50
45
40
I
CLL0
= -40°C
T
j
Tj = 25°C
Tj = 150°C
t
35
0500100015002000
dIL/dt
[A/ms]
35
0500100015002000
dIL/dt
[A/ms]
Figure 8Current Limitation Level vs. Current Slew Rate dI/dt
Data Sheet14Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
High Side Switch
65
A
60
55
I
CLH
50
45
40
35
4 6 8101214161820
Tj = -40°C
Tj = 25°C
Tj = 150°C
Block Description and Characteristics
Low Side Switch
65
A
60
55
I
CLL
50
45
40
35
V
V
S
4 6 8101214161820
Tj = -40°C
Tj = 25°C
Tj = 150°C
V
V
S
Figure 9Typical Current Limitation Detection Levels vs. Supply Voltage
In combination with a typical inductive load, such as a motor, this results in a switched
mode current limitation. That way of limiting the current has the advantage that the power
dissipation in the BTS 7960 is much smaller than by driving the MOSFETs in linear
mode. Therefore it is possible to use the current limitation for a short time without
exceeding the maximum allowed junction temperature (e.g. for limiting the inrush current
during motor start up). However, the regular use of the current limitation is allowed as
long as the specified maximum junction temperature is not exceeded. Exceeding this
temperature can reduce the lifetime of the device.
4.3.5Short Circuit Protection
The device is short circuit protected against
• output short circuit to ground
• output short circuit to supply voltage
• short circuit of load
The short circuit protection is realized by the previously described current limitation in
combination with the over-temperature shut down of the device
The control inputs IN and INH consist of TTL/CMOS compatible schmitt triggers with
hysteresis which control the integrated gate drivers for the MOSFETs. Setting the INH
pin to high enables the device. In this condition one of the two power switches is switched
on depending on the status of the IN pin. To deactivate both switches, the INH pin has
to be set to low. No external driver is needed. The BTS 7960 can be interfaced directly
to a microcontroller.
4.4.2Dead Time Generation
In bridge applications it has to be assured that the highside and lowside MOSFET are
not conducting at the same time, connecting directly the battery voltage to GND. This is
assured by a circuit in the driver IC, generating a so called dead time between switching
off one MOSFET and switching on the other. The dead time generated in the driver IC is
automatically adjusted to the selected slew rate.
4.4.3Adjustable Slew Rate
In order to optimize electromagnetic emission, the switching speed of the MOSFETs is
adjustable by an external resistor. The slew rate pin SR allows the user to optimize the
balance between emission and power dissipation within his own application by
R
connecting an external resistor
to GND.
SR
4.4.4Status Flag Diagnosis With Current Sense Capability
The status pin IS is used as a combined current sense and error flag output. In normal
operation (current sense mode), a current source is connected to the status pin, which
delivers a current proportional to the forward load current flowing through the active high
side switch. If the high side switch is inactive or the current is flowing in the reverse
direction no current will be driven except for a marginal leakage current
external resistor
value of 8500 for the current sense ratio
V
to
= (IL / 8.5 A)V. In case of a fault condition the status output is connected to a
IS
R
determines the voltage per output current. E.g. with the nominal
IS
k
= IL / IIS, a resistor value of RIS = 1kΩ leads
ILIS
current source which is independent of the load current and provides I
maximum voltage at the IS pin is determined by the choice of the external resistor and
the supply voltage. In case of current limitation the
I
IS(lim)
is activated for 2 * t
I
IS(LK)
IS(lim)
CLS
. The
. The
.
Data Sheet17Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
Normal operation:
current sense mode
VS
ESD-ZD
IS
IIS~ I
Load
Sense
V
I
IS(lim)
output
logic
R
IS
IS
Figure 10Sense current and fault current
Fault condition:
error flag mode
VS
Sense
I
IS(lim)
output
logic
ESD-ZD
IS
R
IS
V
IS
Data Sheet18Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
4.4.5Truth Table
Device StateInputsOutputsMode
INHINHSSLSSIS
Normal operation0XOFFOFF0Stand-by mode
10OFFON0LSS active
11ONOFFCSHSS active
Over-voltage (OV)XXONOFF1Shut-down of LSS,
HSS activated,
error detected
Under-voltage (UV)XXOFFOFF0UV lockout
Overtemperature or
short circuit of HSS or
LSS
0XOFFOFF0Stand-by mode, reset
of latch
1XOFFOFF1Shut-down with latch,
error detected
Current limitation mode11OFFON1Switched mode, error
detected
10ONOFF1Switched mode, error
detected
Inputs:SwitchesStatus Flag IS:
0 = Logic LOWOFF = switched offCS = Current sense mode
1 = Logic HIGHON = switched on1 = Logic HIGH (error)
X = 0 or 1
Data Sheet19Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Block Description and Characteristics
4.4.6Electrical Characteristics - Control and Diagnostics
– 40 °C < Tj < 150 °C, 8 V < VS < 18 V (unless otherwise specified)
4.4.7Maximum analog
sense current, sense
current in fault
condition
4.4.8Isense leakage current
4.4.9Isense leakage current,
active high side switch
IS
k
ILIS
I
IS(lim)
I
ISL
I
ISH
3
10
6
5
3
8.5
8.5
8.5
11
12
14
R
= 1 kΩ
IS
I
= 30 A
L
I
= 15 A
L
I
= 5 A
L
44.57mAVS = 13.5 V
R
= 1kΩ
IS
––1µAVIN= 0 V or
V
= 0 V
INH
–1200µAVIN = V
I
= 0 A
L
INH
= 5 V
Data Sheet20Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
Thermal Characteristics
5Thermal Characteristics
PosParameterSymbolLimitsUnitTest Condition
minmax
5.0.1 Thermal Resistance
Junction-Case, Low Side Switch
R
thjc(LS)
= ∆T
j(LS)
/ P
5.0.2 Thermal Resistance
Junction-Case, High Side Switch
R
thjc(HS)
= ∆T
j(HS)
/ P
5.0.3 Thermal Resistance
Junction-Case, both Switches
R
(
P
thjc
v(HS)
= max[∆T
+ P
v(LS)
j(HS)
)
, ∆T
5.0.4 Thermal Resistance
Junction-Ambient
v(LS)
v(HS)
j(LS)
] /
R
thjc(LS)
R
thjc(HS)
R
thjc
R
thja
–1.8K/W
–0.9K/W
–1.0K/W
–35K/W6cm2 cooling
area
Data Sheet21Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
6Application
6.1Application Example
MicrocontrollerReverse Polarity
µC
I/O I/O I/O I/O
BTS 7960B
I/O
Reset
Vdd
Vss
VS
INH
Voltage Regulator
WO
RO
Q
D
TLE
4278G
GND
I
VS
Protection
BTS 7960B
INH
SPD
50P03L
Application
V
S
IN
IS
SR
OUT
GND
M
OUT
GND
IN
IS
SR
High Current H-Bridge
Figure 11Application Example: H-Bridge with two BTS 7960B
6.2Layout Considerations
Due to the fast switching times for high currents, special care has to be taken to the PCB
layout. Stray inductances have to be minimized in the power bridge design as it is
necessary in all switched high power bridges. The BTS 7960 has no separate pin for
power ground and logic ground. Therefore it is recommended to assure that the offset
between the ground connection of the slew rate resistor, the current sense resistor and
ground pin of the device (GND / pin 1) is minimized. If the BTS 7960 is used in a H-bridge
or B6 bridge design, the voltage offset between the GND pins of the different devices
should be small as well.
A ceramic capacitor from VS to GND close to each device is recommended to provide
current for the switching phase via a low inductance path and therefore reducing noise
and ground bounce. A reasonable value for this capacitor would be about 470 nF.
The digital inputs need to be protected from excess currents (e.g. caused by induced
voltage spikes) by series resistors in the range of 10 kΩ.
Data Sheet22Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
7Package Outlines P-TO-263-7
P-TO-263-7
(Plastic Transistor Single Outline Package)
9.9
A
7.5
17
6.6
5
.
6
3
.
0
±
1
2
5
.
1
0
.
)
9
.
4
1
(
±
0
±
2
.
2
.
9
0
1
0...0.1 5
7 x 0.6
+0.1
-0.03
6 x 1.27
M
0.25
AB
Package Outlines P-TO-263-7
4.4
+0.1
1.3
-0.02
B
0.05
5
.
1)
5
0
.
±
0
±
7
0.1
.
7
4
.
2
2.4
±
0
0
.
5
.
1
5
8
°
M
A
X
.
0.1
B
1) Shear and punch direction no burrs this surf ace
Back side, heatsink contour
All metal suf aces tin plated, except area of cut .
Footprint
4
5
1
.
6
1
.
9
6
.
4
10.8
0.47
0.8
8.42
HLGF1019
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
Data Sheet23Rev. 1.1, 2004-12-07
Dimensions in mm
High Current PN Half Bridge
BTS 7960
8Package Outlines P-TO-220-7
P-TO-220-7
(Plastic Transistor Single Outline Package)
±0.2
9.9
A
±0.2
9.5
7.5
6.6
3
.
3
.
0
0
±
5
.
7
1
3
±
1
6
.
5
1
5
1
.
0
-
7
.
3
1.3
2
.
0
±
8
.
2
0.05
Package Outlines P-TO-220-7
4.4
+0. 1
-0.0 2
B
1)
2
.
0
±
2
.
9
3
.
0
±
3
.
3
C
7 x 0.6
0.25
0...0.15
M
17
±0.1
6 x 1.27
C
AB
3
3
.
.
0
0
±
±
6
2
.
.
8
0
1
4.5
8.4
2.4
±0.3
±0.3
0.5
1) Shear and punch direction no burrs this surface
Back side, heatsink contour
All metal surfaces tin plated, except area of cut.
±0.1
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
Data Sheet24Rev. 1.1, 2004-12-07
High Current PN Half Bridge
BTS 7960
9Revision History
Revision DateChanges / Comments
n.a.2004-03-18Target Data Sheet
0.92004-10-10Target Data Sheet converted to new layout
1.02004-11-30Preliminary Data Sheet
1.12004-12-07“Preliminary” removed; No other changes
Revision History
Data Sheet252004-12-07
High Current PN Half Bridge
BTS 7960
Edition 2004-12-07
Published by Infineon Technologies AG,
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet262004-12-07
http://www.infineon.com
Published by Infineon Technologies AG
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