lnfineon BTS 736 L2 User Manual

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

PROFET

®

BTS 736 L2

Smart High-Side Power Switch

Two Channels: 2 x 40mΩ

Status Feedback

Product Summary Package

Operating Voltage V

Active channels one two parallel On-state Resistance R Nominal load current I Current limitation I

General Description

• N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and

diagnostic feedback, monolithically integrated in Smart SIPMOS

• Providing embedded protective functions

4.75...41V

bb(on)

40mΩ 20mΩ

ON

4.8A 7.3A

L(NOM)

30A 30A

L(SCr)

P-DSO-20-9



technology.

Applications

• µC compatible high-side power switch with diagnostic feedback for 5V, 12V and 24V grounded loads

• All types of resistive, inductive and capacitve loads

• Most suitable for loads with high inrush currents, so as lamps

• Replaces electromechanical relays, fuses and discrete circuits

Basic Functions

• Very low standby current

• CMOS compatible input

• Fast demagnetization of inductive loads

• Stable behaviour at undervoltage

• Wide operating voltage range

• Logic ground independent from load ground

Protection Functions

• Short circuit protection

Block Diagram

Vbb

• Overload protection

• Current limitation

• Thermal shutdown

• Overvoltage protection (including load dump) with external

resistor

• Reverse battery protection with external resistor

• Loss of ground and loss of V

protection

bb

• Electrostatic discharge protection (ESD)

Diagnostic Function

• Diagnostic feedback with open drain output

• Open load detection in ON-state

IN1

ST1

IN2

ST2

Logic

Channel

1

Logic

Channel

2

PROFET

GND

OUT 1

OUT 2

Load 2

• Feedback of thermal shutdown in ON-state

Load 1

Semiconductor Group 1 of 14 2003-Oct-01

p

g

BTS 736 L2

Functional diagram

IN1

ST1

GND1

IN2

ST2

GND2

Pin Definitions and Functions

Pin Symbol Function

1,10, 11,12, 15,16, 19,20 3 IN1 Input 1,2, activates channel 1,2 in case of 7 IN2 logic high signal 17,18 OUT1 Output 1,2, protected high-side power output 13,14 OUT2 of channel 1,2. Design the wiring for the max.

4 ST1 Diagnostic feedback 1,2 of channel 1,2, 8 ST2 open drain, low on failure 2 GND1 Ground 1 of chip 1 (channel 1) 6 GND2 Ground 2 of chip 2 (channel 2) 5,9 N.C. Not Connected

overvoltage

volta

rotection

internal

e supply

logic

gate

control

+

charge

pump

temperature

sensor

ESD

Open load

detection

Channel 1

Control and protection circuit

of

channel 2

V

Positive power supply voltage. Design the

bb

wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance

short circuit current

current limit

clamp for

inductive load

VBB

OUT1

LOAD

OUT2

PROFET

Pin configuration

(top view)

V

1 • 20 V

bb

GND1 2 19 Vbb

IN1 3 18 OUT1

ST1 4 17 OUT1

N.C. 5 16 Vbb

GND2 6 15 Vbb

IN2 7 14 OUT2

ST2 8 13 OUT2

N.C. 9 12 Vbb

Vbb 10 11 Vbb

bb

Semiconductor Group 2 2003-Oct-01

BTS 736 L2

Maximum Ratings at T

= 25°C unless otherwise specified

j

Parameter Symbol Values Unit

Supply voltage (overvoltage protection see page 4) Vbb 43 V Supply voltage for full short circuit protection

T

= -40 ...+150°C

j,start

Vbb 24 V

Load current (Short-circuit current, see page 5) IL self-limited A

3

Load dump protection1) V

2)

R

= 2 Ω, td = 200 ms; IN = low or high,

I

LoadDump

= VA + Vs, VA = 13.5 V

V

Load dump

)

60 V

each channel loaded with RL = 9.0 Ω, Operating temperature range Storage temperature range Power dissipation (DC)4) Ta = 25°C: (all channels active)

T

= 85°C:

a

Maximal switchable inductance, single pulse V

= 12V, T

bb

j,start

= 150°C4),

IL = 4.0 A, EAS = 296 mJ, 0 Ω one channel: IL = 6.0 A, E

= 631 mJ, 0 Ω two parallel channels:

AS

Tj T

stg

3.8

P

tot

-40 ...+150

-55 ...+150

ZL

2.0

19.0

17.5

°C

W

mH

see diagrams on page 9 Electrostatic discharge capability (ESD) IN:

(Human Body Model) ST: out to all other pins shorted: acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993

R=1.5kΩ; C=100pF

V

1.0

ESD

kV

4.0

8.0

Input voltage (DC) VIN -10 ... +16 V Current through input pin (DC) Current through status pin (DC)

IIN IST

±2.0 ±5.0

mA

see internal circuit diagram page 8

Thermal Characteristics

Parameter and Conditions Symbol Values Unit

Thermal resistance junction - soldering point

4),5)

each channel: R junction - ambient4) one channel active: all channels active:

1)

Supply voltages higher than V

resistor for the GND connection is recommended.

2)

RI = internal resistance of the load dump test pulse generator

3)

V

Load dump

4)

Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm

connection. PCB is vertical without blown air. See page 14

5)

Soldering point: upper side of solder edge of device pin 15. See page 14

is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839

require an external current limit for the GND and status pins (a 150Ω

bb(AZ)

Semiconductor Group 3 2003-Oct-01

min typ Max

thjs

R

thja

2

(one layer, 70µm thick) copper area for Vbb

-- -- 12

--

40 33

--

K/W

BTS 736 L2

Electrical Characteristics

Parameter and Conditions, each of the two channels Symbol Values Unit

at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified

Load Switching Capabilities and Characteristics

min typ Max

On-state resistance (Vbb to OUT); I

= 2 A, Vbb ≥ 7V

L

each channel, Tj = 25°C:

T

= 150°C:

j

two parallel channels, Tj = 25°C:

see diagram, page 10

Nominal load current one channel active:

two parallel channels active:

6)

Device on PCB Output current while GND disconnected or pulled up

V

= 30 V, V

bb

Turn-on time8) IN to 90% V Turn-off time IN to 10% V

, Ta = 85°C, Tj ≤ 150°C

= 0, see diagram page 8

IN

7)

OUT OUT

RL = 12 Ω Slew rate on 8) Tj = -40°C:

10 to 30% V

OUT

, R

= 12 Ω Tj = 25°C...150°C:

L

Slew rate off 8) Tj = -40°C: 70 to 40% V

, RL = 12 Ω Tj = 25°C...150°C:

OUT

Operating Parameters

RON

I

L(NOM)

4.4

--

6.7

;

I

:

ton

:

t

L(GNDhigh)

off

-- -- 2 mA 50

50

dV/dton 0.15

0.15

-dV/dt

0.15

off

0.15

36 67

18

4.8

40

mΩ

75 20

-- A

7.3

100 120

--

200

250

0.8

µs

1

V/µs

1

V/µs

Operating voltage Tj=-40 T Overvoltage protection I

= 40 mA Tj =25...150°C:

bb

Standby current V

= 0; see diagram page 10 T

IN

10

9)

Tj =-40°C:

)

Tj =-40°C...25°C:

Leakage output current (included in I

= I

+ I

GND1

, if IST > 0

ST

11)

, V

= 5V,

IN

, one channel on:

GND2

bb(AZ)

VIN = 0

Operating current I

GND

two channels on:

6)

Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm

connection. PCB is vertical without blown air. See page 14

7)

not subject to production test, specified by design

8)

See timing diagram on page 11.

9)

Supply voltages higher than V resistor for the GND connection is recommended). See also V circuit diagram on page 8.

10)

Measured with load; for the whole device; all channels off

11)

Add I

=25...150°C:

j

=150°C:

j

)

bb(off)

require an external current limit for the GND and status pins (a 150Ω

V

4.75 --

bb(on)

41

bb(AZ)

43

I

--

bb(off)

--

I

-- 1 10 µA

L(off)

I

GND

--

2

(one layer, 70µm thick) copper area for Vbb

in table of protection functions and

ON(CL)

--

47 10

--

0.8

1.6

41

V

43

--

V

52 16

µA

50

1.4

mA

2.8

Semiconductor Group 4 2003-Oct-01

BTS 736 L2

Parameter and Conditions, each of the two channels Symbol Values Unit

at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified

min typ Max

Protection Functions

12)

Current limit, (see timing diagrams, page 12)

=-40°C:

Tj

=25°C:

Tj

=+150°C:

Tj

I

40

L(lim)

33 23

49 41 29

60 48 35

A

Repetitive short circuit current limit, Tj = Tjt each channel two parallel channels

(see timing diagrams, page 12)

Initial short circuit shutdown time T

j,start

=25°C:

I

--

L(SCr)

t

-- 1.7 -- ms

off(SC)

--

30 30

--

A

--

(see timing diagrams on page 12)

Output clamp (inductive load switch off)

at V

ON(CL)

= Vbb - V

, IL= 40 mA

OUT

Tj

13)

=-40°C:

Tj

=25°C...150°C:

V

ON(CL)

41 43

--

47

V

--

52 Thermal overload trip temperature Tjt 150 -- -- °C Thermal hysteresis

∆

Tjt -- 10 -- K

Reverse Battery

Reverse battery voltage Drain-source diode voltage (V

= - 4.0 A, Tj = +150°C

IL

14)

-Vbb -- -- 32 V

out

> V

bb

)

-VON -- 600 -- mV

12)

Integrated protection functions are designed to prevent IC destruction under fault conditions described in the

data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation.

13)

If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest

V

14)

Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source

diode has to be limited by the connected load. Power dissipation is higher compared to normal operating conditions due to the voltage drop across the drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 8).

ON(CL)

Semiconductor Group 5 2003-Oct-01

BTS 736 L2

Parameter and Conditions, each of the two channels Symbol Values Unit

at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified

Diagnostic Characteristics

min typ Max

Open load detection current, (on-condition) each channel I

Input and Status Feedback

15)

Input resistance

(see circuit page 8) Input turn-on threshold voltage V Input turn-off threshold voltage V Input threshold hysteresis ∆ V Off state input current VIN = 0.4 V: I On state input current VIN = 5 V: I Delay time for status with open load after switch

L (OL)1

RI 2.5 3.5 6 kΩ

1.7 -- 3.2 V

IN(T+)

1.5 -- -- V

IN(T-)

-- 0.5 -- V

IN(T)

1 -- 50 µA

IN(off)

20 50 90 µA

IN(on)

t

d(ST OL4)

100 520 900 µs

100

-- 900 mA

off; (see diagram on page 13) Status invalid after positive input slope (open load)

t

d(ST)

-- -- 500 µs

Status output (open drain) Zener limit voltage IST = +1.6 mA: ST low voltage IST = +1.6 mA:

V

ST(high)

V

ST(low)

5.4

--

6.1

--

0.4

--

V

15)

If ground resistors R

are used, add the voltage drop across these resistors.

GND

Semiconductor Group 6 2003-Oct-01

BTS 736 L2 Truth Table

Channel 1 Input 1 Output 1 Status 1 Channel 2 Input 2 Output 2 Status 2

Normal operation Open load L

Overtemperature

L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit H = "High" Level Status signal valid after the time delay shown in the timing diagrams

Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.

level BTS 736L2

level

L

H

H L H

L H Z H L L

H H H L H L

Terms

I

bb

V

bb

I

IN1

3

I

ST1

V

IN1

Leadframe (V External R

4

V

ST1

R

) is connected to pin 1,10,11,12,15,16,19,20

bb

optional; two resistors R

GND

battery protection up to the max. operating voltage.

GND1

Leadframe

V

bb

PROFET

Chip 1

GND1

2

I

GND1

OUT1

I

L1

17,18

GND1

V

, R

I

IN2

V

I

ST2

7

ST2

8

R

GND2

ON1

V

IN2

OUT1

= 150 Ω or a single resistor R

GND2

Leadframe

V

bb

PROFET

Chip 2

GND2

6

I

GND2

OUT2

I

V

L2

13,14

GND

ON2

V

OUT2

= 75 Ω for reverse

Semiconductor Group 7 2003-Oct-01

BTS 736 L2

Input circuit (ESD protection), IN1 or IN2

R

IN

I

ESD-ZD

I

GND

I

The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.

Status output, ST1 or ST2

R

ST(ON)

GND

ESD-Zener diode: 6.1 V typ., max 5.0 mA; R at 1.6 mA. The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.

ESDZD

+5V

ST

ST(ON)

< 375 Ω

Overvolt. and reverse batt. protection

+ 5V

R

ST

R

I

IN

Logic

ST

R

ST

V

Z1

= 6.1 V typ., VZ2 = 47 V typ., R

V

Z1

R

= 15 kΩ, RI= 3.5 kΩ typ.

ST

R

Signal GND

GND

V

Z2

PRO FET

GND

In case of reverse battery the load current has to be limited by the load. Temperature protection is not active

+ V

bb

OUT

R

Load

Load GND

= 150 Ω,

Open-load detection OUT1 or OUT2

ON-state diagnostic Open load, if V

ON

< R

ON·IL(OL)

; IN high

+ V

bb

Inductive and overvoltage output clamp,

OUT1 or OUT2

VON clamped to V

V

ON(CL)

Z

= 47 V typ.

Power GND

V

+V

bb

ON

OUT

ON

Logic

unit

GND disconnect

IN

ST

VbbV

IN

V

ST

Open load

detection

V

PROFET

GND

bb

V

GND

OUT

V

ON

Any kind of load. In case of IN = high is V Due to V

> 0, no V

GND

= low signal available.

ST

OUT

≈ V

IN

- V

IN(T+)

Semiconductor Group 8 2003-Oct-01

.

BTS 736 L2

GND disconnect with GND pull up

V

PROFET

> V

GND

IN

bb

V

- V

OUT

GND

device stays off

IN(T+)

V

bb

V

IN

Any kind of load. If V Due to V

> 0, no VST = low signal available.

GND

IN

ST

GND

Vbb disconnect with energized inductive load

high

IN

ST

V

bb

PROFET

GND

OUT

Inductive load switch-off energy dissipation

E

bb

E

V

=

E

L

bb

PROFET

GND

1

/

·L·I

2

OUT(CL)

OUT

2 L

ON(CL)·iL

|) ln (1+

IN

=

ST

Energy stored in load inductance:

While demagnetizing load inductance, the energy dissipated in PROFET is

= Ebb + EL - ER= V

E

AS

with an approximate solution for RL > 0

· L

I

AS

=

L

(V

+ |V

bb

·R

2

L

E

AS

Z

Ω:

|V

L

{

R

L

(t) dt,

·R

I

L

OUT(CL)

E

)

|

E

Load

L

R

V

bb

For inductive load currents up to the limits defined by ZL (max. ratings and diagram on page 9) each switch is protected against loss of Vbb.

Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current flows through the GND connection.

Maximum allowable load inductance for a single switch off (one channel)

L = f (I

L

ZL [mH]

1000

100

10

); T

j,start

150°C, V

=

bb

4)

= 12 V, RL = 0 Ω

1

23456789101112

IL [A]

Semiconductor Group 9 2003-Oct-01

BTS 736 L2

Typ. on-state resistance

R

= f (Vbb,T

ON

R

[mOhm]

ON

80

70

60

50

40

30

); IL = 2 A, IN = high

j

Tj = 150°C

25°C

-40°C

20

10

3 5 7 9 30 40

V

bb

[V]

Typ. standby current

I

= f (T

bb(off)

[µA]

I

bb(off)

45

40

35

30

25

20

j

); V

= 9...34 V, IN1,2 = low

bb

15

10

5

0

-50 0 50 100 150 200

T

[°C]

j

Semiconductor Group 10 2003-Oct-01

BTS 736 L2

Timing diagrams

Both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2

Figure 1a: Vbb turn on:

IN1

IN2

V

OUT1

V

bb

OUT2

Figure 2b: Switching a lamp:

IN

ST

V

OUT

ST1 open drain

ST2 open drain

Figure 2a: Switching a resistive load, turn-on/off time and slew rate definition:

IN

V

OUT

90%

t

on

dV/dton

10%

t

off

dV/dtoff

I

L

t

The initial peak current should be l i m i ted by the lamp and not by the current limit of the dev i ce.

Figure 2c: Switching an inductive load

IN

ST

V

OUT

t

I

L

I

L

I

L(OL)

t

*) if the time constant of load is too large, open-load-status m ay occur

Semiconductor Group 11 2003-Oct-01

BTS 736 L2

Figure 3a: Turn on into short circuit:

shut down by overtemperature, restart by cooling

IN1

I

L1

ST

other channel: normal operation

I

L(lim)

I

L(SCr)

t

off(SC)

Figure 4a: Overtemperature: Reset if T

<Tjt

j

IN

ST

V

OUT

T

J

t

Heating up of the chip may require several millisec onds, depending on external conditions

Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2)

IN1/2

I + I

L1 L2

2xI

L(lim)

I

L(SCr)

Figure 5a: Open load: detection in ON-state, open load occurs in on-state

IN

ST

V

OUT

t

d(ST OL)

t

d(ST OL)

t

ST1/2

t

off(SC)

I

t

normal

L

open

normal

t

ST1 and ST2 have to be configured as a ' Wi red OR' function ST1/2 with a single pull-up res i stor.

t

d(ST OL)

= 10 µs typ.

Semiconductor Group 12 2003-Oct-01

t

BTS 736 L2

Figure 5b: Open load: turn on/off to open load

IN

ST

I

L

d(STOL4)

Semiconductor Group 13 2003-Oct-01

BTS 736 L2

Package and Ordering Code

Standard: P-DSO-20-9

Sales Code BTS 736 L2

Ordering Code Q67060-S7011-A2

All dimensions in millimetres

Definition of soldering point with temperature T upper side of solder edge of device pin 15.

Pin 15

Printed circuit board (FR4, 1.5mm thick, one layer 70µm, 6cm max. power dissipation P I

L(NOM)

2

active heatsink area) as a reference for

, nominal load current

and thermal resistance R

tot

thja

:

s

Attention please!

The information herein is given t o describe certain components and shall not be considered as a guarantee of characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement , regardi ng circuits, descripti ons and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technol ogy, delivery terms and conditi ons and prices please contact your nearest Infineon Technologies Offi ce in Germany or our Infineon Technologies Representatives worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous substances. For inform ation on the types in question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used i n life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the f ailure of that lif e-support devic e or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human lif e. If they fail, it is reasonable to ass ume that the health of the user or other persons m ay be endangered.

Semiconductor Group 14 2003-Oct-01

lnfineon BTS 736 L2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual