Smart Four Channel Highside Power Switch
)
Product Summary
Features
•
Overload protection
•
Current limitation
•
Short-circuit protection
•
Thermal shutdown
•
Overvoltage protection
(including load dump)
•
Fast demagnetization of inductive loads
•
Reverse battery protection
•
Undervoltage and overvoltage shutdown
with auto-restart and hysteresis
•
Open drain diagnostic output
•
Open load detection in ON-state
•
CMOS compatible input
•
Loss of ground and loss of V
•
Electrostatic discharge (ESD) protection
1
)
protection
bb
Application
•
µC compatible power switch with diagnostic feedback
for 12 V and 24 V DC grounded loads
•
All types of resistive, inductive and capacitive loads
•
Replaces electromechanical relays and discrete circuits
Overvoltage Protection
Operating voltage
active channels: one
On-state resistance
Nominal load current
Current limitation
R
ON
I
L(NOM
I
L(SCr)
PROFET® BTS721L1
V
bb(AZ)
V
bb(on)
two parallel four parallel
5.0 ... 34 V
100 50 25
2.9 4.3 6.3
888
43 V
m
Ω
A
A
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection
functions.
Pin Definitions and Functions
Pin Symbol Function
1,10,
11,12,
15,16,
19,20
3 IN1 Input 1 .. 4, activates channel 1 .. 4 in case of
5 IN2 logic high signal
7 IN3
9 IN4
18 OUT1 Output 1 .. 4, protected high-side power output
17 OUT2 of channel 1 .. 4. Design the wiring for the
14 OUT3 max. short circuit current
13 OUT4
4 ST1/2 Diagnostic feedback 1/2 of channel 1 and
8 ST3/4 Diagnostic feedback 3/4 of channel 3 and
2 GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2)
6 GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4)
V
bb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 4 and also for low
thermal resistance
channel 2, open drain, low on failure
channel 4, open drain, low on failure
Pin configuration
Vbb1
GND1/2 2 19 V
IN1 3 18 OUT1
ST1/2 4 17 OUT2
IN2 5 16 V
GND3/4 6 15 V
IN3 7 14 OUT3
ST3/4 8 13 OUT4
IN4 9 12 V
Vbb10 11 V
•
(top view)
20 V
bb
bb
bb
bb
bb
bb
)
1
With external current limit (e.g. resistor R
connection, reverse load current limited by connected load.
=150 Ω) in GND connection, resistor in series with ST
GND
Semiconductor Group 1 06.96
Block diagram
Four Channels; Open Load detection in on state;
Voltage
source
V
Logic
Voltage
sensor
3
IN1
IN2
5
4
ST1/2
ESD
Logic
Overvoltage
protection
Level shifter
Rectifier 1
Charge
pump 1
Charge
pump 2
Current
limit 1
Current
limit 2
Gate 1
protection
Limit for
unclamped
ind. loads 1
Open load
Short to Vbb
detection 1
Gate 2
protection
Temperature
sensor 1
+ V
Channel 1
OUT1
Channel 2
BTS721L1
bb
Leadframe
18
Signal GND
Chip 1
Signal GND
Chip 2
2
8
6
7
9
GND1/2
IN3
IN4
ST3/4
GND3/4
Chip 1
PROFET
Chip 2
Level shifter
Rectifier 2
unclamped
ind. loads 2
Open load
Short to Vbb
detection 2
Logic and protection circuit of chip 2
(equivalent to chip 1)
Limit for
Temperature
sensor 2
OUT2
RR
O1
Channel 3
RR
O3
GND1/2
Channel 4
GND3/4
+ V
OUT3
OUT4
O2
bb
O4
17
Load
Load GND
Leadframe
14
13
Load
Load GND
Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
Maximum Ratings
at
= 25°C unless otherwise specified
j
T
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
T
= -40 ...+150°C
j,start
V
V
bb
bb
43 V
34 V
Semiconductor Group 2
BTS721L1
)
Maximum Ratings at
T
= 25°C unless otherwise specified
j
Parameter Symbol Values Unit
Load current (Short-circuit current, see page 5)
)
Load dump protection
)
3
R
= 2 Ω,
I
t
= 200 ms; IN = low or high,
d
each channel loaded with
2
V
LoadDump
R
= 4.7 Ω,
L
=
U
+
V
,
A
U
s
Operating temperature range
Storage temperature range
Power dissipation (DC)
(all channels active)
5
T
T
= 13.5 V
A
= 25°C:
a
= 85°C:
a
I
L
V
Load dump
T
j
T
stg
P
tot
self-limited A
)
4
-40 ...+150
60 V
°C
-55 ...+150
3.7
W
1.9
Inductive load switch-off energy dissipation, single pulse
V
= 12V,
bb
I
= 2.9 A, Z
L
I
= 4.3 A, Z
L
I
= 6.3 A, Z
L
see diagrams on page 9 and page 10
Electrostatic discharge capability (ESD
T
= 150°C5),
j,start
= 58 mH, 0 Ω one channel:
L
= 58 mH, 0 Ω two parallel channels:
L
= 58 mH, 0 Ω four parallel channels:
L
E
V
AS
ESD
0.3
0.65
1.5
1.0 kV
(Human Body Model)
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
see internal circuit diagram page 8
V
I
I
IN
ST
IN
-10 ... +16 V
±2.0
mA
±5.0
J
Thermal resistance
junction - soldering point
junction - ambient
5)
5),6)
each channel:
one channel active:
R
R
thjs
thja
all channels active:
)
2
Supply voltages higher than V
150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input
protection is integrated.
3)
R
= internal resistance of the load dump test pulse generator
I
4)
V
Load dump
)
5
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
connection. PCB is vertical without blown air. See page 15
)
6
Soldering point: upper side of solder edge of device pin 15. See page 15
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
require an external current limit for the GND and status pins, e.g. with a
bb(AZ)
2
(one layer, 70µm thick) copper area for V
15 K/W
41
34
bb
Semiconductor Group 3
Electrical Characteristics
BTS721L1
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
each of the four channels
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT)
IL = 2 A each channel,
two parallel channels,
four parallel channels,
T
= 25°C:
j
T
= 150°C:
j
T
= 25°C:
j
T
= 25°C:
j
Nominal load current one channel active:
two parallel channels active:
four parallel channels active:
Device on PCB5),
T
= 85°C,
a
T
≤ 150°C
j
Output current while GND disconnected or pulled
up; V
= 30 V,
bb
Turn-on time to 90%
Turn-off time to 10%
R
= 12 Ω
L
T
,
V
= 0, see diagram page 9
IN
=-40...+150°C
j
V
V
OUT
OUT
:
:
Slew rate on
10 to 30%
V
OUT
R
,
= 12 Ω
L
T
,
=-40...+150°C:
j
Slew rate off
70 to 40%
V
OUT
,
R
L
= 12 Ω
T
,
=-40...+150°C:
j
Symbol Values Unit
min typ max
R
ON
I
L(NOM)
I
L(GNDhigh)
t
on
t
off
dV/dt
on
-dV/dt
off
--
2.5
3.8
5.9
85
170
43
22
2.9
4.3
6.3
100
200
50
25
-- -- 10 mA
80
80
200
200
400
400
0.1 -- 1 V/µs
0.1 -- 1 V/µs
mΩ
-- A
µs
Operating Parameters
)
Operating voltage
7
Undervoltage shutdown
Undervoltage restart
T
=-40...+150°C:
j
T
=-40...+150°C:
j
T
Undervoltage restart of charge pump
see diagram page 14
T
=-40...+150°C:
j
Undervoltage hysteresis
V
∆
bb(under)
Overvoltage shutdown
Overvoltage restart
Overvoltage hysteresis
Overvoltage protection
I
= 40 mA
bb
7)
At supply voltage increase up to
8)
see also
=
V
ON(CL)
V
bb(u rst)
V
-
bb(under)
)
8
V
in circuit diagram on page 8.
T
=-40...+150°C:
j
T
=-40...+150°C:
j
T
=-40...+150°C: ∆
j
T
=-40...+150°C:
j
= 5.6 V typ without charge pump,
bb
=-40...+25°C:
j
T
=+150°C:
j
V
bb(on)
V
bb(under)
V
bb(u rst)
V
bb(ucp)
V
∆
bb(under)
V
bb(over)
V
bb(o rst)
V
bb(over)
V
bb(AZ)
V
5.0 --
3.5 --
-- -- 5.0
-- 5.6 7.0 V
-- 0.2 -- V
34 -33 -- -- V
-- 0.5 -- V
42 47 -- V
≈
V
OUT
bb
- 2 V
34 V
5.0 V
7.0
43 V
V
Semiconductor Group 4
BTS721L1
)
j
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
each of the four channels
Standby current, all channels off
V
= 0
IN
Leakage output current (included in
= 0
=
I
GND1/2
+
I
GND3/4
V
IN
,
= 5V,
T
IN
V
Operating current 9),
I
GND
I
bb(off
=-40...+150°C
one channel on:
four channels on:
Protection Functions
Initial peak short circuit current limit,
diagrams, page 12)
each channel,
(see timing
two parallel channels
four parallel channels
Repetitive short circuit current limit,
T
=
T
each channel
j
jt
two parallel channels
four parallel channels
(see timing diagrams, page 12)
Initial short circuit shutdown time
T
T
(see page 11 and timing diagrams on page 12)
Output clamp (inductive load switch off)
at V
ON(CL)
= Vbb - V
OUT
Thermal overload trip temperature
Thermal hysteresis
T
=25°C
j
T
=150°C:
j
)
=-40°C:
j
T
=25°C:
j
T
=+150°C:
j
T
=-40°C:
j,start
= 25°C:
j,start
10)
Symbol Values Unit
min typ max
:
I
bb(off)
I
L(off)
I
GND
I
L(SCp)
--
--
28
44
-- -- 12
--
--
11
9
5
2
8
18
14
8
60
70
25
22
14
twice the current of one channel
four times the current of one channel
I
L(SCr)
t
off(SC)
V
ON(CL)
T
jt
∆T
jt
--
--
--
--
--
8
8
8
3.8
3
-- 47 -- V
150 -- -- °C
-- 10 -- K
µ
µ
312mA
--
--
--
----ms
A
A
A
A
Reverse Battery
)
Reverse battery voltage
Drain-source diode voltage
= - 2.9 A,
L
I
)
9
Add
10
11
)
)
I
If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
V
ON(CL)
Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 3 and circuit page 8).
ST
, if
j
T
I
ST
= +150°C
> 0
11
(V
out
> Vbb)
-
V
bb
-
V
ON
-- -- 32 V
-- 610 -- mV
Semiconductor Group 5
BTS721L1
)
)
Parameter and Conditions,
at Tj = 25 °C,
V
= 12 V unless otherwise specified
bb
each of the four channels
Diagnostic Characteristics
Open load detection current,
(on-condition)
each channel,
T
= -40°C:
j
T
= 25°C:
j
T
= 150°C:
j
two parallel channels
Open load detection voltage
four parallel channels
)
12
T
=-40..+150°C:
j
Internal output pull down
T
(OUT to GND), V
OUT
= 5 V
Input and Status Feedback
13
=-40..+150°C:
j
)
Input resistance
(see circuit page 8)
T
=-40..+150°C:
j
Input turn-on threshold voltage
T
=-40..+150°C:
j
Input turn-off threshold voltage
T
=-40..+150°C:
j
Input threshold hysteresis
Off state input current
T
=-40..+150°C:
j
On state input current
T
=-40..+150°C:
j
V
= 0.4 V:
IN
V
IN
= 5 V:
Delay time for status with open load after switch
off (other channel in off state
(see timing diagrams, page 13
),
T
=-40..+150°C:
j
Delay time for status with open load after switch
off (other channel in on state
(see timing diagrams, page 13
),
T
=-40..+150°C:
j
Status invalid after positive input slope
(open load)
T
=-40..+150°C:
j
Status output (open drain)
Zener limit voltage
ST low voltage
T
=-40...+150°C,
j
T
=-40...+25°C,
j
T
= +150°C,
j
I
= +1.6 mA:
ST
I
= +1.6 mA:
ST
I
= +1.6 mA:
ST
Symbol Values Unit
min typ max
I
L (OL)
1
20
20
20
--
400
--
300
--
300
mA
twice the current of one channel
four times the current of one channel
V
OUT(OL)
R
O
R
I
V
IN(T+)
V
IN(T-)
∆
V
IN(T)
I
IN(off)
I
IN(on)
t
d(ST OL4)
t
d(ST OL5)
t
d(ST)
V
ST(high)
V
ST(low)
234V
41030k
2.5 3.5 6 k
1.7 -- 3.5 V
1.5 -- -- V
-- 0.5 -- V
1--50
20 50 90
100 320 800
-- 5 20
-- 200 600
5.4
--
--
6.1
--
--
--
0.4
0.6
Ω
Ω
µ
A
µ
A
µ
s
µ
s
µ
s
V
12)
External pull up resistor required for open load detection in off state.
13)
If ground resistors R
are used, add the voltage drop across these resistors.
GND
Semiconductor Group 6
Truth Table
BTS721L1
Channel 1 and 2 Chip 1
Channel 3 and 4
Chip 2
IN1 IN2 OUT1 OUT2 ST1/2
IN3 IN4 OUT3 OUT4 ST3/4
(equivalent to channel 1 and 2)
BTS 721L1
Normal operation L
Open load
Channel 1 (3)
Channel 2 (4)
Short circuit to V
bb
Channel 1 (3)
Channel 2 (4)
Overtemperature
both channel
Channel 1 (3)
Channel 2 (4)
L
H
H
L
L
H
L
H
X
L
L
H
L
H
X
L
X
H
L
H
X
X
L
H
L
H
L
H
X
L
L
H
L
H
X
L
L
H
L
H
X
X
X
L
H
L
L
H
H
Z
Z
H
L
H
X
H
H
H
L
H
X
L
L
L
L
L
X
X
L
H
L
H
L
H
X
Z
Z
H
L
H
X
H
H
H
L
L
L
X
X
L
L
H(L
H(L
L
H(L
L
H(L
H
H
H
H
14
H
L
14
H
L
15
H
16
15)
H
16
H
L
L
H
L
H
L
)
)
)
)
)
)
)
)
)
Undervoltage/ Overvoltage X X L L H
L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and
outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4
have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
I
bb
V
bb
V
IN1
I
IN1
3
IN1
I
IN2
5
4
IN2
ST1/2
R
GND1/2
I
ST1/2
V
V
IN2
ST1/2
Leadframe
V
bb
PROFET
Chip 1
GND1/2
2
OUT1
OUT2
I
GND1/2
V
ON1
V
ON2
I
L1
18
I
L2
17
V
IN3
V
OUT2
V
OUT1
I
IN3
7
IN4
9
8
IN3
IN4
ST3/4
R
GND3/4
I
I
ST3/4
V
V
IN4
ST3/4
Leadframe
V
bb
PROFET
Chip 2
GND3/4
6
OUT3
OUT4
I
GND3/4
V
ON3
V
ON4
I
L3
14
I
L4
13
V
OUT3
V
OUT4
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External R
optional; two resistors R
GND
GND1/2
,R
GND3/4
= 150 Ω or a single resistor R
GND
= 75 Ω for
reverse battery protection up to the max. operating voltage.
)
14
With additional external pull up resistor
15)
An external short of output to Vbb in the off state causes an internal current from output to ground. If R
used, an offset voltage at the GND and ST pins will occur and the V
)
16
Low resistance to
V
may be detected by no-load-detection
bb
signal may be errorious.
ST low
GND
Semiconductor Group 7
is
BTS721L1
I
I
IN1...4
Input circuit (ESD protection),
R
IN
I
ESD-ZD
I
GND
ESD zener diodes are not to be used as voltage clamp at
DC conditions. Operation in this mode may result in a drift of
the zener voltage (increase of up to 1 V).
Status output,
ESD-Zener diode: 6.1 V typ., max 5.0 mA; R
ST1/2 or ST3/4
R
ST(ON)
GND
ESDZD
+5V
ST
ST(ON)
< 380
Ω
at 1.6 mA, ESD zener diodes are not to be used as voltage
clamp at DC conditions. Operation in this mode may result in
a drift of
the zener voltage (increase of up to 1 V).
Inductive and overvoltage output clamp,
OUT1...4
+V
bb
V
Z
Overvoltage protection of logic part
GND1/2 or GND3/4
+ V
bb
V
Z2
GND
R
GND
,
R
V
= 6.1 V typ., V
Z1
R
= 150
GND
R
I
IN
IN
ST
ST
V
Z1
= 47 V typ., RI = 3.5 kΩ typ.
Z2
Logic
Signal GND
Ω
Reverse battery protection
V
R
Power GND
-
OUT
L
bb
+ 5V
R
ST
R
I
IN
R
GND
= 150 Ω,
ST
= 3.5 kΩ typ
R
I
Logic
GND
R
GND
Signal GND
,
Power
Inverse
Diode
Temperature protection is not active during inverse current
operation.
V
ON
OUT
PROFET
Power GND
clamped to
V
ON
V
ON(CL)
= 47 V typ.
Semiconductor Group 8
BTS721L1
Open-load detection,
OUT1...4
ON-state diagnostic condition:
< R
Logic
unit
ON
·
L(OL)
ON
; IN high
Open load
detection
V
ON
I
OFF-state diagnostic condition:
V
> 3 V typ.; IN low
OUT
OFF
GND disconnect with GND pull up
(channel 1/2 or 3/4)
+ V
V
OUT
bb
V
IN1
ON
V
bb
Any kind of load. If V
Due to V
> 0, no VST = low signal available.
GND
IN1
IN2
V
IN2
ST
V
ST
GND
PROFET
GND
V
>
V
bb
OUT1
OUT2
V
GND
V
IN
-
device stays off
IN(T+)
Vbb disconnect with energized inductive
load
R
EXT
V
high
OUT
IN1
IN2
ST
V
bb
PROFET
GND
OUT1
OUT2
Logic
unit
Open load
detection
Signal GND
GND disconnect
(channel 1/2 or 3/4)
I
V
bb
PROFET
GND
bb
V
OUT1
OUT2
GND
V
bb
IN1
IN2
ST
V
V
IN1
IN2
V
ST
Any kind of load. In case of IN = high is
Due to V
>
0, no VST = low signal available.
GND
V
R
OUT
O
V
bb
For an inductive load current up to the limit defined by E
AS
(max. ratings see page 3 and diagram on page 10) each
switch is protected against loss of Vbb.
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load the whole load
current flows through the GND connection.
V
V
≈
-
IN
IN(T+)
.
Semiconductor Group 9
Inductive load switch-off energy
dissipation
E
bb
E
AS
V
IN
bb
E
BTS721L1
Load
PROFET
=
ST
GND
OUT
L
Z
L
{
R
L
Energy stored in load inductance:
/
2
·L·
2
I
L
1
E
=
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
E
= Ebb + EL - ER= ∫ V
AS
with an approximate solution for R
·
I
L
L
=
(
V
+ |V
OUT(CL)
bb
·
R
2
L
|)
E
AS
ON(CL)
>
L
ln
(1+
0
·
iL(t) dt,
Ω
:
|V
·
I
R
L
L
OUT(CL)
|
Maximum allowable load inductance for
a single switch off
L = f (IL );
T
j,start
150°C, V
=
(one channel)
bb
5)
= 12 V, RL = 0
Ω
E
L
E
R
)
L [mH]
10000
1000
100
10
1
12345678
I
[A]
L
Semiconductor Group 10
BTS721L1
Typ. on-state resistance
RON = f (Vbb,Tj )
[mOhm]
R
ON
300
250
200
150
100
50
0
0 10203040
= 2 A, IN = high
; I
L
Tj = 15 0° C
85°C
25°C
-40°C
Vbb [V]
Typ. standby current
I
I
= f (Tj )
bb(off)
[µA]
bb(off)
60
50
40
30
20
10
0
-50 0 50 100 150 200
; V
bb
= 9...34 V, IN
1...4
= low
Tj [°C]
Typ. open load detection current
I
L(OL)
I
L(OL)
220
200
180
160
140
120
100
80
60
40
20
= f (Vbb,Tj );
[mA]
V
< 6
bb
for V
no-load detection not specified
IN
= high
-40°C
25°C
85°C
Tj = 15 0° C
Typ. initial short circuit shutdown time
t
t
off(SC)
off(SC)
4
3.5
3
2.5
2
1.5
1
0.5
= f (T
[msec]
j,start
)
; V
bb
=12 V
0
0 5 10 15 20 25 30
Vbb [V]
Semiconductor Group 11
0
-50 0 50 100 150 200
T
[°C]
j,start
BTS721L1
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams
are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently
the diagrams are valid for each channel as well as for permuted channels
Figure 1a: V
turn on:
bb
IN1
IN2
V
bb
V
OUT1
V
OUT2
ST open drain
Figure 2a: Switching a lamp:
IN
Figure 2b: Switching an inductive load
IN
t
ST
V
OUT
I
L
I
L(OL)
d(ST)
*)
t
*) if the time constant of load is too large, open-load-status may
occur
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
IN1
other chan ne l: no r m a l ope ration
t
ST
V
OUT
I
L
t
The initial peak current should be limited by the lamp and not by
the initial short circuit current I
= 14 A typ. of the device.
L(SCp)
Semiconductor Group 12
I
L1
I
L(SCp)
I
L(SCr)
t
off(SC)
ST
t
Heating up of the chip may require several milliseconds, depending
on external conditions (t
off(SC)
vs. T
see page 11)
j,start
BTS721L1
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
IN1/2
I + I
L1 L2
I
L(SCp)
I
L(SCr)
t
off(SC)
ST1/2
Figure 5a: Open load: detection in ON-state, open
load occurs in on-state
IN1
IN2 channel 2: normal operation
V
OUT1
channel 1:
I
L1
open
t
d(ST OL1)
load
normal
t
d(ST OL2)
load
open
t
d(ST OL1)
load
ST
t
t
d(ST OL2)
t
Figure 4a: Overtemperature:
T
Reset if
T
<
j
jt
IN
ST
V
OUT
T
J
t
d(ST OL1)
= 30 µs typ., t
d(ST OL2)
= 20 µs typ
Figure 5b: Open load: detection in ON-state, turn
on/off to open load
IN1
IN2 channel 2: normal operation
V
OUT1
I
L1
channel 1: open load
t
d(ST)
t
ST
t
d(ST OL4)
t
d(ST)
t
d(ST OL5)
t
Semiconductor Group 13
The status delay time t
failure modes "open load in ON-state" and "overtemperature".
d(STOL4)
allows to distinguish between the
BTS721L1
Figure 5c: Open load: detection in ON- and OFF-state
(with R
), turn on/off to open load
EXT
IN1
IN2 channel 2: no rm al op eration
V
OUT1
I
L1
ST
channel 1: open load
t
d(ST)
t
d(ST)
t
d(ST OL5)
t
t
impedance
depends on external circuitry because of high
d(ST OL5)
Figure 6b: Undervoltage restart of charge pump
V
V
on
off-state
V
bb(u rst)
V
bb(u cp)
V
bb(under)
IN = high, normal load conditions.
Charge pump starts at V
bb(ucp)
= 5.6 V typ.
V
on-state
V
bb(o rst)
ON(CL)
bb(over)
off-state
V
bb
Figure 6a: Undervoltage:
IN
V
bb
V
OUT
ST open drain
V
bb(under)
V
bb(u cp)
V
bb(u rst)
Figure 7a: Overvoltage:
IN
V
V
bb
OUT
V
ON(CL)
V
bb(over)
V
bb(o rst)
ST
t
t
Semiconductor Group 14
Package and Ordering Code
BTS721L1
Standard P-DSO-20-9
BTS721L1 Q67060-S7002-A2
All dimensions in millimetres
1) Does not include plastic or metal protrusions of 0.15 max per side
2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature Ts:
upper side of solder edge of device pin 15.
Ordering Code
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70µm, 6cm
max. power dissipation P
I
L(NOM)
2
active heatsink area) as a reference for
, nominal load current
and thermal resistance R
tot
thja
Semiconductor Group 15
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