Littelfuse SP725 User Manual

TVS Diode Arrays (SPA

V+

(SOIC)

V+

®

Diodes)

General Purpose ESD Protection - SP725 Series

SP725 Series 5pF 8kV Diode Array

Pinout

V-

1

In

SP725

2

In

3

In

4

In

Functional Block Diagram

5, 6

1

IN

V-

7, 8

2

IN

8

V-

7

V+

6

5

IN

3, 4

RoHS

Pb

GREEN

Description

The SP725 is an array of SCR/Diode bipolar structures for
ESD and overvoltage protection of sensitive input circuits.
The SP725 has 2 protection SCR/Diode device structures
per input. There are a total of 4 available inputs that can be
used to protect up to 4 external signal or bus lines. Over­voltage protection is from the IN (Pins 1 - 4) to V+ or V-.

The SCR structures are designed for fast triggering at a
threshold of one +V
or one –V

diode threshold below V- (Pin 7,8). From an

BE

diode threshold above V+ (Pin 5,6)

BE

IN input, a clamp to V+ is activated if a transient pulse
causes the input to be increased to a voltage level greater
than one V
a negative pulse, one V

above V+. A similar clamp to V- is activated if

BE

less than V-, is applied to an IN

BE

input.

Refer to Fig 1 and Table 1 for further details. Refer to
Application Note AN9304 and AN9612 for further detail.

Features

• ESD Interface per HBM Standards

- IEC 61000-4-2, Direct Discharge .......... 8kV (Level 4)

- IEC 61000-4-2, Air Discharge ...............15kV (Level 4)

- MIL-STD-3015.7 .................................................25kV

• Peak Current Capability

- IEC 61000-4-5 8/20 µs Peak Pulse Current ..... ± 14 A

- Single Transient Pulse, 100 µs Pulse Width ...... ± 8 A

• Designed to Provide Over-Voltage Protection

- Single-Ended Voltage Range to ........................ +30V

- Differential Voltage Range to ............................ ±15V

• Fast Switching ..............................................2ns Risetime

• Low Input Leakages ..........................5 nA at 25 ºC Typical

• Low Input Capacitance ....................................5 pF Typical

• An Array of 4 SCR/Diode Pairs

• Operating Temperature Range..................-40 ºC to 105 ºC

Additional Information

Datasheet

Life Support Note:

Not Intended for Use in Life Support or Life Saving Applications

The products shown herein are not designed for use in life sustaining or life saving
applications unless otherwise expressly indicated.

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

Resources

Samples

Applications

• Microprocessor/Logic
Input Protection

• Data Bus Protection

• Analog Device Input
Protection

• Voltage Clamp

TVS Diode Arrays (SPA

®

Diodes)

General Purpose ESD Protection - SP725 Series

Absolute Maximum Ratings

Parameter Rating Units

Continuous Supply Voltage, (V+) - (V-) +35 V
Forward Peak Current, IIN to VCC , IIN to GND

(Refer to Figure 5)
Peak Pulse Current, 8/20µs ± 14 A
ESD Ratings and Capability (Figure 1, Table 1)

Load Dump and Reverse Battery (Note 2)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied.

Electrical Characteristics T

= -40oC to 105oC, V

A

± 8, 100 µs A

= 0.5VCC , Unless Otherwise Specified

IN

Thermal Information

Parameter Rating Units

Thermal Resistance (Typical, Note 1) θ

SOIC Package 170

Storage Temperature Range -65 to 150oC

Maximum Junction Temperature 150
Maximum Lead Temperature

(Soldering 20-40s) (SOIC - Lead Tips Only)

JA

260

o

C/W

o

C/W

o

C

o

C

Parameter Symbol Test Conditions Min Typ Max Units

Operating Voltage Range,
V

= [(V+) - (V-)]

SUPPLY

V

SUPPLY

- 2 to 30 - V

Forward Voltage Drop

IN to V- V

IN to V+ V

Input Leakage Current I

Quiescent Supply Current I

QUIESCENT

FWDL

FWDH

IN

I

= 2A (Peak Pulse)

IN

- 2 - V

- 2 - V

-20 5 +20 nA

- 50 200 nA

Equivalent SCR ON Threshold (Note 3) - 1. 1 - V

Equivalent SCR ON Resistance V

Input Capacitance C

Input Switching Speed t

Notes:

1. θ

is measured with the component mounted on an evaluation PC board in free air

JA

2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery V+ and V- pins are connected to the same supply
voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP725 supply pins to limit
reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended.

3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule information to determine peak
current and dissipation under EOS conditions.

IN

ON

; (Note 3) - 0.5 - Ω

FWD/IFWD

5 - pF

- 2 - ns

Typical Application of the SP725

(Application as an Input Clamp for Overvoltage, Greater than 1VBE
Above V+ or less than -1VBE below V-)

+V

CC

INPUT

DRIVERS

OR

SIGNAL

SOURCES

IN 1 - 4

SP725

SP725 INPUT PROTECTION CIRCUIT (1 OF 4 SHOWN)

+V

LINEAR OR
DIGITAL IC
INTERFACE

TO +V

V+

V-

CC

CC

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13

TVS Diode Arrays (SPA

R

R

23

®

Diodes)

General Purpose ESD Protection - SP725 Series

ESD Capability

ESD capability is dependent on the application and defined
test standard.The evaluation results for various test
standards and methods based on Figure 1 are shown in
Table 1.

The SP725 has a Level 4 HBM capability when tested as a
device to the IEC 61000-4-2 standard. Level 4 specifies a
required capability greater than 8kV for direct discharge and
greater than 15kV for air discharge.

For the “Modified” MIL-STD-3015.7 condition that is
defined as an “incircuit” method of ESD testing, the V+
and V- pins have a return path to ground and the SP725
ESD capability is typically greater than 25kV from 100pF
through 1.5kΩ . By strict definition of MIL-STD-3015.7 using
“pinto-pin” device testing, the ESD voltage capability is
greater than 10kV.

For the SP725 EIAJ IC121 Machine Model (MM) standard,
the ESD capability is typically greater than 2kV from 200pF
with no series resistance.

Figure 1: Electrostatic Discharge Test

H.V.

SUPPLY

± V

1

CHARGE

SWITCH

D

IEC 61000-4-2: R150 to 100MΩ

MIL-STD-3015.7: R11 to 10MΩ

D

DISCHARGE

C

D

SWITCH

IN

DUT

Table 1: ESD Test Conditions

Standard Type/Mode R

IEC 61000-4-2
(Level 4)

MIL-STD-3015.7

HBM, Air Discharge 330 Ω 150pF 15kV

HBM, Direct Discharge 330 Ω 150pF 8kV

Modified HBM 1.5k Ω 100pF 25kV

Standard HBM 1.5k Ω 100pF 10kV

EIAJ IC121 Machine Model 0k Ω 200pF 2kV

C

D

±V

D

D

Figure 2: Low Current SCR Forward Voltage Drop Curve

200

TA = 25ºC

SINGLE PULSE

160

120

80

40

FORWARD SCR CURRENT (mA)

0

600 800 1000 1200

FORWARD SCR VOLT AGE DROP (mV)

Figure 3: High Current SCR Forward Voltage Drop Curve

5

TA = 25°C
SINGLE PULSE

4

3

2

EQUIV. SAT. ON

1

FORWARD SCR CURRENT (A)

0

THRESHOLD ~ 1.1V

01

FORWARD SCR VOLT AGE DROP (V)

I

FWD

V

FWD

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

TVS Diode Arrays (SPA

General Purpose ESD Protection - SP725 Series

Peak Transient Current Capability for Long Duration Surges

®

Diodes)

The peak transient current capability rises sharply as the
width of the current pulse narrows. Destructive testing
was done to fully evaluate the SP725 ’s ability to withstand
a wide range of peak current pulses vs time. The circuit
used to generate current pulses is shown in Figure 4.

The test circuit of Figure 4 is shown with a positive pulse
input. For a negative pulse input, the (-) current pulse input
goes to an SP725 ‘IN’ input pin and the (+) current pulse
input goes to the SP725 V- pin. The V+ to V- supply of the
SP725 must be allowed to float. (i.e., It is not tied to the
ground reference of the current pulse generator.) Figure
5 shows the point of overstress as defined by increased
leakage in excess of the data sheet published limits.

The maximum peak input current capability is dependent
on the ambient temperature, improving as the temperature
is reduced. Peak current curves are shown for ambient
temperatures of 25 º C and 105 º C and a 15V power supply
condition. The safe operating range of the transient peak
current should be limited to no more than 75% of the
measured overstress level for any given pulse width as
shown in the curves of Figure 5.

Note that adjacent input pins of the SP725 may be
paralleled to improve current (and ESD) capability. The
sustained peak current capability is increased to nearly
twice that of a single pin.

Figure 4: Typical SP725 Peak Current Test Circuit

with a Variable Pulse Width Input

VARIABLE TIME DURATION

+

V

X

-

R1~ 10Ω TYPICAL
VXADJ. 10V/ATYPICAL

C1 ~ 100μF

R

VO LTAGE

PROBE

CURRENT PULSE GENERATOR

1

CURRENT

SENSE

(+)

IN

1

2

IN

3

IN

IN

4

SP725

(-)

8

V-

7

V-

6

V+

5

V+

+

-

C1

Figure 5: SP725 Typical Nonrepetitive Peak Current

Pulse Capability

Showing the Measured Point of Overstress in Amperes vs
pulse width time in milliseconds

14

12

T

= 105ºC

A

TA = 25ºC

10

8

6

4

PEAK CURRENT (A)

2

0

0.0001 0.01 0.1 110100 1000

CAUTION: SAFE OPERATING CONDITIONS LIMIT

THE MAXIMUM PEAK CURRENT FOR A GIVEN
PULSE WIDTH TO BE NO GREATER THAN 75%
OF THE VALUES SHOWN ON EACH CURVE

V+ TO V-SUPPLY = 15V

PULSE WIDTH TIME (ms)

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13

TVS Diode Arrays (SPA

t

R

R

o

C

e

T

®

Diodes)

General Purpose ESD Protection - SP725 Series

Soldering Parameters

Reflow Condition Pb – Free assembly

Pre Heat

- Temperature Min (T

- Temperature Max (T

) 150°C

s(min)

) 200°C

s(max)

- Time (min to max) (ts) 60 – 180 secs

Average ramp up rate (Liquidus) Temp
(T

) to peak

L

to TL - Ramp-up Rate 5°C/second max

T

S(max)

Reflow

- Temperature (TL) (Liquidus) 217°C

- Temperature (tL) 60 – 150 seconds

Peak Temperature (TP) 260

Time within 5°C of actual peak
Temperature (t

)

p

5°C/second max

+0/-5

°C

20 – 40 seconds

Ramp-down Rate 5°C/second max

Time 25°C to peak Temperature (T

) 8 minutes Max.

P

Do not exceed 260°C

Package Dimensions — Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) CA

Notes:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication
Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating
plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily
exact.

MBS

E

-B-

SEATING PLANE

A

-C-

M

0.25(0.010)B

H

µ

A1

0.10(0.004)

MM

L

o

h x 45

C

t

T

P

Ramp-up

t

S

amp-up

PreheatPrehea

T

L

T

S(max)

Temperature

T

S(min)

25

time to peak temperature

P

t

L

Ramp-down

amp-d

Time

Package SOIC

Pins 8

JEDEC MS-012

Millimeters Inches

Min Max Min Max

A 1.35 1.75 0.0532 0.0688 -

A1 0.10 0.25 0.0040 0.0098 -

B 0.33 0.51 0.013 0.020 9

C 0.19 0.25 0.0075 0.0098 -

D 4.80 5.00 0.1890 0.1968 3

E 3.80 4.00 0.1497 0.1574 4

e 1.27 BSC 0.050 BSC -

H 5.80 6.20 0.2284 0.2440 -

h 0.25 0.50 0.0099 0.0196 5

L 0.40 1.27 0.016 0.050 6

N 8 8 7

o

µ 0

8o 0o 8o -

Critical Zone

ritical Zon

L to TP

to

T

Notes

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

TVS Diode Arrays (SPA

User Feeding Direction

Pin 1 Location

®

Diodes)

General Purpose ESD Protection - SP725 Series

Part Numbering System Product Characteristics

SP 725

TVS Diode Arrays

®

(SPA

Diodes)

Series

AB

*

Package Type
AB: 8 Leaded SOIC

G=Green

TG=Tape and Reel

Lead Plating Matte Tin

Lead Material Copper Alloy

Lead Coplanarity 0.004 inches (0.102mm)

Substitute Material Silicon

Body Material Molded Epoxy

Flammability UL 94 V-0

Notes:

1. All dimensions are in millimeters.

2. Dimensions include solder plating.

3. Dimensions are exclusive of mold flash & metal burr.

4.Blo is facing up for mold and facing down for trim/form, i.e. reverse trim/form.

5. Package surface matte finish VDI 11-13.

Ordering Information

Part Number Temp. Range (ºC) Package Marking Min. Order Qty.

SP725ABG -40 to 105 8 Ld SOIC SP725AB(T)G

SP725ABTG -40 to 105 8 Ld SOIC Tape and Reel SP725AB(T)G

Notes:

1. SP725AB(T)G means device marking either SP725ABG or SP725ABTG.

1

1

1960

2500

Embossed Carrier Tape & Reel Specification - SOIC Package

Symbol

Millimetres Inches

Min Max Min Max

E 1.65 1.85 0.065 0.073

F 5.4 5.6 0.213 0.22

P2 1.95 2.05 0.077 0.081

D 1. 5 1. 6 0.059 0.063

D1 1.50 Min 0.059 Min

P0 3.9 4.1 0.154 0.161

10P0 40.0 ± 0.20 1.574 ± 0.008

W 11. 9 12.1 0.468 0.476

P 7. 9 8.1 0.311 0.319

A0 6.3 6.5 0.248 0.256

B0 5.1 5.3 0.2 0.209

K0 2 2.2 0.079 0.087

t 0.30 ± 0.05 0.012 ± 0.002

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13