Littelfuse SP720 User Manual

TVS Diode Arrays (SPA

V+

RoHS

GREEN

IN

IN

IN

IN

IN

IN

V-

IN

V+

®

Diodes)

General Purpose ESD Protection - SP720 Series

SP720 Series 3pF 4kV Diode Array

Pinout

3 - 7
9 - 15

16

IN

15

14

IN

13

IN

IN

12

IN

11

IN

10

IN

9

SP720 (PDIP, SOIC)

TOP VIEW

Functional Block Diagram

16

IN

1

IN

2

1

2

3

4

5

6

7

8

IN

Pb

Description

The SP720 is an array of SCR/Diode bipolar structures for
ESD and over-voltage protection to sensitive input circuits.
The SP720 has 2 protection SCR/Diode device structures
per input. A total of 14 available inputs can be used to
protect up to 14 external signal or bus lines. Over-voltage
protection is from the IN (pins 1-7 and 9-15) to V+ or V-.

The SCR structures are designed for fast triggering at a
threshold of one +V
a -V

diode threshold below V- (Pin 8). From an IN input,

BE

a clamp to V+ is activated if a transient pulse causes the
input to be increased to a voltage level greater than one
V

above V+. A similar clamp to V- is activated if a negative

BE

pulse, one V

less than V-, is applied to an IN input.

BE

Standard ESD Human Body Model (HBM) Capability is:

Features

• ESD Interface Capability for HBM Standards

- MIL STD 3015.7 ................................................. 15kV

- IEC 61000-4-2, Direct Discharge,

- Single Input .......................................... 4kV (Level 2)

- Two Inputs in Parallel ............................ 8kV (Level 4)

- IEC 61000-4-2, Air Discharge ...............15kV (Level 4)

• High Peak Current Capability

- IEC 61000-4-5 (8/20µs) ....................................... ±3A

- Single Pulse, 100µs Pulse Width ........................ ±2A

- Single Pulse, 4µs Pulse Width ............................ ±5A

• Designed to Provide Over-Voltage Protection

- Single-Ended Voltage Range to ........................ +30V

- Differential Voltage Range to ............................ ±15V

• Fast Switching ..............................................2ns Risetime

• Low Input Leakages ................................. 1nA at 25º (Typ)

• Low Input Capacitance ....................................... 3pF (Typ)

• An Array of 14 SCR/Diode Pairs

• Operating Temperature Range....................-40ºC to 105ºC

diode threshold above V+ (Pin 16) or

BE

V-

8

Additional Information

Datasheet

Life Support Note:

Not Intended for Use in Life Support or Life Saving Applications

The products shown herein are not designed for use in life sustaining or life saving
applications unless otherwise expressly indicated.

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

Resources

Samples

Applications

• Microprocessor/Logic
Input Protection

• Data Bus Protection

• Analog Device Input
Protection

• Voltage Clamp

TVS Diode Arrays (SPA

®

Diodes)

General Purpose ESD Protection - SP720 Series

Absolute Maximum Ratings

Parameter Rating Units

Continuous Supply Voltage, (V+) - (V-) +35 V

Forward Peak Current, I
(Refer to Figure 5)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied.

Note:

ESD Ratings and Capability - See Figure 1, Table 1
Load Dump and Reverse Battery (Note 2)

Electrical Characteristics T

to VCC, IIN to GND

IN

= -40oC to 105oC, V

A

±2, 100µs A

= 0.5VCC , Unless Otherwise Specified

IN

Thermal Information

Parameter Rating Units

Thermal Resistance (Typical, Note 1) θ

PDIP Package 90

SOIC Package 130

Maximum Storage Temperature Range -65 to 150oC
Maximum Junction Temperature (Plastic

Package)

Maximum Lead Temperature
(Soldering 20-40s) (SOIC Lead Tips Only)

1. θJA is measured with the component mounted on an evaluation PC board in free air.

150

260

o

JA

o

o

C/W

C/W

C/W

o

C

o

C

Parameter Symbol Test Conditions Min Typ Max Units

Operating Voltage Range,

= [(V+) - (V-)]

V

SUPPLY

V

SUPPLY

- 2 to 30 - V

Forward Voltage Drop: IIN = 1A (Peak Pulse)

IN to V- V

IN to V+ V

Input Leakage Current I

Quiescent Supply Current I

QUIESCENT

FWDL

FWDH

IN

- 2 - V

- 2 - V

-20 5 20 nA

- 50 200 nA

Equivalent SCR ON Threshold Note 3 - 1. 1 - V

Equivalent SCR ON Resistance V

Input Capacitance C

Input Switching Speed t

Notes:

2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and everse battery V+ and V- pins are connected to the same supply
voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP720 supply pins to limit
reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended.

3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule nformation to determine peak
current and dissipation under EOS conditions.

IN

ON

; Note 3 - 1 - Ω

FWD/IFWD

- 3 - pF

- 2 - ns

Typical Application of the SP720

(Application as an Input Clamp for Over-voltage, greater than 1VBE
Above V+ or less than -1VBE below V-)

+V

INPUT

DRIVERS

OR

SIGNAL

SOURCES

SP720 INPUT
PROTECTION CIRCUIT
(1 OF 14 ON CHIP)

CC

SP720

IN 9-15IN 1-7

LINEAR OR
DIGITAL IC
INTERFACE

TO +V

V+

V-

+V

CC

CC

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13

TVS Diode Arrays (SPA

R

®

Diodes)

General Purpose ESD Protection - SP720 Series

ESD Capability

ESD capability is dependent on the application and defined
test standard. The evaluation results for various test
standards and methods based on Figure 1 are shown in
Table 1.

For the “Modified” MIL-STD-3015.7 condition that is
defined as an “in-circuit” method of ESD testing, the V+
and V- pins have a return path to ground and the SP720
ESD capability is typically greater than 15kV from 100pF
through 1.5kΩ. By strict definition of MIL-STD-3015.7 using
“pin-to-pin” device testing, the ESD voltage capability
is greater than 6kV. The MIL-STD-3015.7 results were
determined from AT&T ESD Test Lab measurements.

The HBM capability to the IEC 61000-4-2 standard is
greater than 15kV for air discharge (Level 4) and greater
than 4kV for direct discharge (Level 2). Dual pin capability (2
adjacent pins in parallel) is well in excess of 8kV (Level 4).

For ESD testing of the SP720 to EIAJ IC121 Machine
Model (MM) standard, the results are typically better than
1kV from 200pF with no series resistance.

Figure 1: Electrostatic Discharge Test

H.V.

SUPPLY

V

R

1

CHARGE
SWITCH

D

IEC 1000-4-2: R150 to 100M

MIL STD 3015.7: R11 to 10M

C

D

D

DISCHARGE

SWITCH

IN

DUT

Table 1: ESD Test Conditions

Standard Type/Mode R

MIL STD 3015.7

Modified HBM 1.5kΩ 100pF 15kV

Standard HBM 1.5kΩ 100pF 6kV

HBM, Air Discharge 330Ω 150pF 15kV

IEC 61000-4-2

HBM, Direct Discharge 330Ω 150pF 4kV

HBM, Direct Discharge,
Two Parallel Input Pins

330Ω 150pF 8kV

EIAJ IC121 Machine Model 0kΩ 200pF 1kV

C

D

±V

D

D

Figure 2: Low Current SCR Forward Voltage Drop Curve

100

TA = 25°C

SINGLE PULSE

80

60

40

20

FORWARD SCR CURRENT (mA)

0

600800 1000 1200

FORWARD SCR VO LTAGE DROP (mV)

Figure 3: High Current SCR Forward Voltage Drop Curve

2.5

TA = 25°C
SINGLE PULSE

2

1.5

1

EQUIV. SAT. ON

0.5

FORWARD SCR CURRENT (A)

0

THRESHOLD ~ 1.1V

0

1

FORWARD SCR VOLTAGE DROP (V)

I

FWD

V

FWD

2

3

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

TVS Diode Arrays (SPA

+

-

CURRENT

SENSE

VOLTAG E

PROBE

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

IN

IN

IN

IN

IN

IN

V-

IN

V+

IN

IN

IN

IN

IN

IN

IN

+

-

R1 ~ 10 TYPICAL

SP720

V

G

VG ADJ. 10V/A TYPICAL

R

1

(-)

(+)

C1 ~ 100 µF

C1

VARIABLE TIME DURATION
CURRENT PULSE GENERA TOR

General Purpose ESD Protection - SP720 Series

Peak Transient Current Capability for Long Duration Surges

®

Diodes)

The peak transient current capability rises sharply as the
width of the current pulse narrows. Destructive testing
was done to fully evaluate the SP720’s ability to withstand
a wide range of transient current pulses. The circuit used to
generate current pulses is shown in Figure 4.

The test circuit of Figure 4 is shown with a positive pulse
input. For a negative pulse input, the (-) current pulse input
goes to an SP720 ‘IN’ input pin and the (+) current pulse
input goes to the SP720 V- pin. The V+ to V- supply of the
SP720 must be allowed to float. (i.e., It is not tied to the
ground reference of the current pulse generator.) Figure
5 shows the point of overstress as defined by increased
leakage in excess of the data sheet published limits.

The maximum peak input current capability is dependent
on the V+ to V- voltage supply level, improving as the
supply voltage is reduced. Values of 0, 5, 15 and 30
voltages are shown. The safe operating range of the
transient peak current should be limited to no more than
75% of the measured overstress level for any given pulse
width as shown in Figure 5.

When adjacent input pins are paralleled, the sustained
peak current capability is increased to nearly twice that
of a single pin. For comparison, tests were run using dual
pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and
14+15.

The overstress curve is shown in Figure 5 for a 15V supply
condition. The dual pins are capable of 10A peak current
for a 10µs pulse and 4A peak current for a 1ms pulse. The
complete for single pulse peak current vs. pulse width time
ranging up to 1 second are shown in Figure 5.

Figure 4: Typical SP720 Peak Current Test Circuit

with a Variable Pulse Width Input

Figure 5: SP720 Typical Nonrepetitive Peak Current

Pulse Capability

Showing the Measured Point of Overstress in Amperes vs
pulse width time in milliseconds (TA = 25oC)

10

9

8

7

6

5

4

3

PEAK CURRENT (A)

2

1

0

0.001 0.01 0.1 1

CAUTION: SAFE OPERATING CONDITIONS LIMIT

THE MAXIMUM PEAK CURRENT FOR A GIVEN
PULSE WIDTH TO BE NO GREATER THAN 75%

OF THE VALUES SHOWN ON EACH CURVE.
SINGLE PIN STRESS CURVES
DUAL PIN STRESS CURVE

0V
5V

30V

V+ TOV-SUPPLY

PULSE WIDTH TIME (ms)

10

100 1000

15V

15V

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13

TVS Diode Arrays (SPA

t

R

R

o

C

e

T

®

Diodes)

General Purpose ESD Protection - SP720 Series

Soldering Parameters

Reflow Condition Pb – Free assembly

Pre Heat

- Temperature Min (T

- Temperature Max (T

) 150°C

s(min)

) 200°C

s(max)

- Time (min to max) (ts) 60 – 180 secs

Average ramp up rate (Liquidus) Temp
(T

) to peak

L

to TL - Ramp-up Rate 5°C/second max

T

S(max)

Reflow

- Temperature (TL) (Liquidus) 217°C

- Temperature (tL) 60 – 150 seconds

Peak Temperature (TP) 260

Time within 5°C of actual peak
Temperature (t

)

p

5°C/second max

+0/-5

°C

20 – 40 seconds

Ramp-down Rate 5°C/second max

Time 25°C to peak Temperature (T

) 8 minutes Max.

P

Do not exceed 260°C

Package Dimensions Dual-In-Line Plastic Packages (PDIP)

N

INDEX

AREA

PLANE

SEATING

PLANE

Notes:

1. Controlling Dimensions: INCH. in case of conflict between English and Metric
dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No.

95.

4. Dimensions A, A1 and L are measured with the package seated in JE-DEC seating
plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.010 inch (0.25mm).

6. E and e

7. e

and eC are measured at the lead tips with the leads unconstrained. eC must be zero

B

or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall
not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1
dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

12 3 N/2

-A-

BASE

D1

B1

are measured with the leads constrained to be perpendicular to datum -C- .

A

D

e

B

0.010 (0.25) CAM BS

E1

-B-

E

A2

-C-

D1

A

L

A1

e

C

C

L

e

A

C

e

B

t

T

P

Ramp-up

t

amp-up

PreheatPrehea

S

T

L

T

S(max)

Temperature

T

S(min)

25

time to peak temperature

P

t

L

Critical Zone

ritical Zon

L to TP

T

Ramp-down

amp-d

Time

Package PDIP

Pins 16 Lead Dual-in-Line

JEDEC MS-001

Millimeters Inches

Min Max Min Max

A - 5.33 - 0.210 4

A1 0.39 - 0.015 - 4

A2 2.93 4.95 0.115 0.195 -

B 0.356 0.558 0.014 0.022 -

B1 1. 1 5 1.77 0.045 0.070 8, 10

C 0.204 0.355 0.008 0.014 -

D 18.66 19.68 0.735 0.775 5

D1 0.13 - 0.005 - 5

E 7.62 8.25 0.300 0.325 6

E1 6.10 7. 11 0.240 0.280 5

e 2.54 BSC 0.100 BSC -

e

A

e

B

7.62 BSC 0.300 BSC 6

- 10.92 - 0.430 7

L 2.93 3.81 0.115 0.150 4

N 16 16 9

to

Notes

© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13

TVS Diode Arrays (SPA

SP720

Series

Package

P=Lead Free
G=Green
TG= Tape and Reel / Green

AB = 16 Ld SOIC
AP = 16 Ld PDIP

TVS Diode Arrays
(SPA

®

Diodes)

**

**

General Purpose ESD Protection - SP720 Series

Package Dimensions — Small Outline Plastic Packages (SOIC)

®

Diodes)

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010)CAM BS

Notes:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication
Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating
plane, shall not exceed a maximum value of 0.61mm (0.024 inch).

10. Controlling dimension:MILLIMETER. Converted inch dimensions are not necessarily
exact.

E

-B-

SEATING PLANE

-C-

M

H

A

A1

0.25(0.010)BM M

L

h x 45

µ

0.10(0.004)

o

C

Package SOIC

Pins 16

JEDEC MS-012

Millimeters Inches

Min Max Min Max

A 1.35 1.75 0.0532 0.0688 -

A1 0.10 0.25 0.0040 0.0098 -

B 0.33 0.51 0.013 0.020 9
C 0.19 0.25 0.0075 0.0098 -
D 9.80 10.00 0.3859 0.3937 3
E 3.80 4.00 0.1497 0.1574 4

e 1.27 BSC 0.050 BSC -
H 5.80 6.20 0.2284 0.2440 -
h 0.25 0.50 0.0099 0.0196 5

L 0.40 1.27 0.016 0.050 6
N 16 16 7

µ 0º 8º 0º 8º -

Notes

Part Numbering System

Product Characteristics

Lead Plating Matte Tin

Lead Material Copper Alloy

Lead Coplanarity 0.004 inches (0.102mm)

Substitute Material Silicon

See Ordering Information section for specific options available

Body Material Molded Epoxy

Flammability UL 94 V-0

Ordering Information

Part Number Temp. Range (ºC) Package

SP720APP -40 to 105 16 Ld PDIP Lead-free SP720AP(P)

SP720ABG -40 to 105 16 Ld SOIC Green SP720A(B)G

SP720ABTG -40 to 105

Notes:

1. SP720AP(P) means device marking either SP720AP or SP720APP.

2. SP720A(B)G means device marking either SP720AG or SP720ABG which are good for types SP720ABG and SP720ABTG.

16 Ld SOIC

Tape and Reel

Environmental

Informaton

Green SP720A(B)G

Marking Min. Order

1

150 0

2

1920

2

2500

Specifications are subject to change without notice.

© 2013 Littelfuse, Inc.

Revised: 04/24/13