Linear Technology LTM9004, LTM9004-AB, LTM9004-AA, LTM9004-AC User Manual

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Page 1

LTM9004

14-Bit Direct Conversion

Receiver Subsystem

FeaTures

Integrated Dual 14-Bit, High-Speed ADC, Lowpass

Filter, Differential Gain Stages and I/Q Demodulator

Lowpass Filter for Each ADC Channel

1.92MHz (LTM9004-AA)

4.42MHz (LTM9004-AB)

9.42MHz (LTM9004-AC) 20MHz (LTM9004-AD)

RF Input Frequency Range: 0.7GHz to 2.7GHz

50Ω Single-Ended RF and LO Ports

I/Q Gain Mismatch: 0.2dB Typical

I/Q Phase Mismatch: 1.5 Deg Typical

Voltage-Adjustable Demodulator DC Offsets

76dB/1.92MHz SNR (LTM9004-AA)

63.5dB SFDR (LTM9004-AA)

Clock Duty Cycle Stabilizer

Low Power: 1.83W

Shutdown and Nap Modes

15mm × 22mm LGA Package

applicaTions

Telecommunications

Direct Conversion Receivers

Cellular Basestations

DescripTion

The LTM®9004 is a 14-bit direct conversion receiver sub- system. Utilizing an integrated technology, the LTM9004 is a μModule includes a dual high speed 14-bit A/D converter, lowpass filter, differential gain stages and a quadrature demodula tor. Contact Linear Technology regarding customization.

The LTM9004 is perfect for zero-IF communications applications, with AC performance that includes 76dB SNR and 63.5dB spurious free dynamic range (SFDR). The entire chain is DC-coupled and provides access for DC offset adjustment. The integrated on-chip broadband transformers provide 50Ω single-ended interfaces at the RF and LO inputs.

A 5V supply powers the mixer and first amplifier for minimal distortion while a 3V supply allows low power ADC operation. A separate supply allows the outputs to drive 0.5V to 3.3V logic. An optional multiplexer allows both channels to share a digital output bus. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

L, LT, LTC, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. µModule is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

system in a package (SiP)

receiver that

Typical applicaTion

= 5V

CC1

LNA

OFFSET ADJUST

DC OFFSET CONTROL

0°

90°

= 3V

CC2

For more information www.linear.com/LTM9004

CC3

GND

ADC

LTM9004-AD

DAC

9004 TA01

0.5V TO

3.6V

CLKOUT

ADC CLK MUX OF

OGND

LTM9004-AA: 64k Point FFT

fIN = 1950.5MHz, –1dBFS

SENSE = V

0 –10 –20 –30 –40 –50

HD2

–60 –70 –80

AMPLITUDE (dBFS)

–90

–100 –110 –120

HD3

81612

FREQUENCY (MHz)

9004 TA01b

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LTM9004

L K J H G F E D C BM A

(Notes 1, 2)

pin conFiguraTionabsoluTe MaxiMuM raTings

Supply Voltage (V Supply Voltage (V

, V

CC1 CC3

) ..................... –0.3V to 5.5V

CC2

, LTM9004-AA,

LTM9004-AB) ........................................... –0.3V to 5.5V

Supply Voltage (V

, LTM9004-AC,

CC3

LTM9004-AD) ........................................... –0.3V to 3.5V

Supply Voltage (V

, OVDD) ..................... –0.3V to 4.0V

Digital Output Ground Voltage (OGND) ........ –0.3V to 1V

LO Input Power ....................................................10dBm

RF Input Power ....................................................20dBm

RF Input DC Voltage ............................................... ±0.1V

LO Input DC Voltage ............................................... ±0.1V

x_ADJ Input Voltage ........................–0.3V to V

SENSE Input Voltage .................................. –0.3V to V

CC1

, V

CC2

Digital Input Voltage (MIXENABLE)

............................. –0.3V to (V

CC1

+ 0.3V)

Digital Input Voltage

MP1ENABLE)........................... –

0.3V to (V

CC2

+ 0.3V)

Digital Input Voltage

MP2ENABLE)

.......................... –0.3V to (V

CC3

+ 0.3V) Digital Input Voltage (except MIXENABLE and

AMPxENABLE) ............................. –0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

+ 0.3V)

Operating Temperature Range

LTM9004C ............................................... 0°C to 70°C

LTM9004I ............................................ –40°C to 85°C

Storage Temper ature Range .................. –65°C to 125°C

204-LEAD (22mm × 15mm × 2.91mm)

= 125°C, θJA = 18.2°C/W, θ

JMAX

= 7.1°C/W, VALUES DETERMINED PER JEDEC 51-9, 51-12, WEIGHT = 1.9g

LGA PACKAGE

= 9.9°C/W, θ

JCtop

JCbottom

= 6.9°C/W,

CAUTION: This part is sensitive to electrostatic discharge (ESD). It is very important that proper ESD precautions be observed when handling the RF and LO inputs of the LTM9004.

orDer inForMaTion

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTM9004CV-AA#PBF LTM9004CV-AA#PBF LTM9004V AA LTM9004IV-AA#PBF LTM9004IV-AA#PBF LTM9004V AA LTM9004CV-AB#PBF LTM9004CV-AB#PBF LTM9004V AB LTM9004IV-AB#PBF LTM9004IV-AB#PBF LTM9004V AB LTM9004CV-AC#PBF LTM9004CV-AC#PBF LTM9004V AC LTM9004IV-AC#PBF LTM9004IV-AC#PBF LTM9004V AC LTM9004CV-AD#PBF LTM9004CV-AD#PBF LTM9004V AD LTM9004IV-AD#PBF LTM9004IV-AD#PBF LTM9004V AD Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA 204-Lead (15mm × 22mm × 2.91mm) LGA

.com/leadfree/

For more information www.linear.com/LTM9004

0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C

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LTM9004

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V (LTM9004-AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

RF Input Frequency Range No External Matching (High Band)

LO Input Frequency Range No External Matching (High Band)

Baseband Frequency Range LTM9004-AA

Input Return Loss Z

RF LO Input Return Loss Z RF Input Power for –1dBFS RF = 1950MHz –7.3 dBm LO Input Power –13 to 5 dBm I/Q Gain Mismatch 0.2 dB I/Q Phase Mismatch 1.5 Deg LO to RF Leakage RF = 900MHz

RF to LO Isolation RF = 900MHz

Maximum DC Offset Voltage, No RF (Note 5) 35 mV

ariation –40°C to 85°C 210 µV/°C

Delay Flatness DC to 1.92MHz (LTM9004-AA)

LPF

DC Offset V Gain Flatness DC to 1.92MHz (LTM9004-AA)

Group

Rejection LTM

Lowpass Filter Cutoff Frequency 1dB Point (LTM9004-AA)

= 5V (LTM9004-AA, LTM9004-AB), PLO = 0dBm. (Note 3)

CC3

With External Matching (Low Band, Mid Band)

LTM9004-AB LTM9004-AC LTM9004-AD

= 50Ω, 1.5GHz to 2.7GHz, Internally Matched >10 dB

RF = 1900MHz

DC to 4.42MHz (LTM9004-AB) DC to 9.42MHz (LTM9004-AC) DC to 20MHz (LTM9004-AD)

9004-AA 5MHz 10MHz

9004-AB

LTM

7.5MHz

12.5MHz

9004-AC

LTM

12.5MHz

17.5MHz

9004-AD

LTM 30MHz 40MHz

1dB Point (LTM9004-AB) 1dB Point (LTM9004-AC) 1dB Point (LTM9004-AD)

CC1

= V

= 5V, VDD = OVDD = 3V, V

CC2

1.5 to 2.7

0.7 to 1.5

1.5 to 2.7

0.7 to 1.5

DC DC to 4.42 DC to 9.42

DC to 20

to 1.92

–60.8 –64.6

59.7

57.1

0.2

0.3 15

15 15

5.3

33.5

0.5

1.5

5.5

6.3 15 28

CC3

= 3V

GHz GHz

MHz MHz MHz MHz

dBm dBm

dB dB

dB dB dB dB

nsec nsec nsec nsec

dB dB

MHz MHz MHz MHz

For more information www.linear.com/LTM9004

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LTM9004

DynaMic accuracy

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IIP3 Input 3rd-Order Intercept, 1 Tone 22 dBm

IIP2 Input 2nd-Order Intercept, 1 Tone 58 dBm

= 5V (LTM9004-AA, LTM9004-AB), PLO = 0dBm.

CC3

CC1

= V

= 5V, VDD = OVDD = 3V, V

CC2

= 3V (LTM9004-AC,

CC3

SNR Signal-to-Noise Ratio at –1dBFS 1.92MHz (LTM9004-AA)

SFDR Spurious

3rd Harmonic at –1dBFS

SFDR Spurious Free Dynamic Range 4th or

Higher at –1dBFS

S/(N+D) Signal-to-Noise Plus Distortion Ratio

at –1dBFS

HD2 2nd Order Harmonic Distortion Ratio

at –1dBFS

HD3 3rd Order Harmonic Distortion Ratio

at –1dBFS

Free Dynamic Range 2nd or

4.42MHz (LTM9004-AB)

9.42MHz (LTM9004-AC) 20MHz (LTM9004-AD)

LTM9004-AA RF = 1950.5MHz, LO =1950MHz

LTM9004-AB RF = 1951MHz, LO =1950MHz

LTM9004-AC RF = 1952.5MHz, LO =1950MHz

LTM9004-AD RF = 1955MHz, LO =1950MHz

LTM9004-AA RF = 1950.5MHz, LO =1950MHz

LTM9004-AB RF = 1951MHz, LO =1950MHz

LTM9004-AC RF = 1952.5MHz, LO =1950MHz

LTM9004-AD RF = 1955MHz, LO =1950MHz

LTM9004-AA RF = 1950.5MHz, LO =1950MHz

LTM9004-AB RF = 1951MHz, LO =1950MHz

LTM9004-AC RF = 1952.5MHz, LO =1950MHz

LTM9004-AD RF = 1955MHz, LO =1950MHz

LTM9004-AA RF = 1950.5MHz, LO =1950MHz

LTM9004-AB RF = 1951MHz, LO =1950MHz

LTM9004-AC RF = 1952.5MHz, LO =1950MHz

LTM9004-AD RF = 1955MHz, LO =1950MHz

LTM9004-AA RF = 1950.5MHz, LO =1950MHz

LTM9004-AB RF = 1951MHz, LO =1950MHz

LTM9004-AC RF = 1952.5MHz, LO =1950MHz

LTM9004-AD RF = 1955MHz, LO =1950MHz

l l l l

70.6

69.7

70.3

66.3

52.5

51.5 58.5

51.5

76.1

75.2 72

68.9

63.5

/1.92MHz

dB dB/4.42MHz dB/9.42MHz

dB/20MHz

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For more information www.linear.com/LTM9004

Page 5

LTM9004

The l denotes the specifications which apply over the full operating

converTer characTerisTics

temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V (LTM9004-AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) Integral Linearity Error (Note 4) Differential Analog Input ±1.5 LSB Differential Linearity Error Differential Analog Input ±1 LSB

DigiTal inpuTs anD ouTpuTs

the l denotes the specifications which apply over the full operating

= 5V (LTM9004-AA, LTM9004-AB)

CC3

temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V (LTM9004-AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

= 5V (LTM9004-AA, LTM9004-AB)

CC3

Mixer Logic Input (MIXENABLE)

First Amplifier Logic Input (AMP1ENABLE)

Second Amplifier Logic Input (AMP2ENABLE, LTM9004-AA, LTM9004-AB)

Second Amplifier Logic Input (AMP2ENABLE, LTM9004-AC, LTM9004-AD)

ADC Logic Inputs (CLK, OE, ADCSHDN, MODE, MUX

SENSE

MODE

High Level Input Voltage V Low Level Input Voltage V Input Current VIN = V

CC1

= 5V = 5V

CC1

Turn On Time 120 ns Turn Off Time 750 ns

High Level Input Voltage V Low Level Input Voltage V Input Pull-Up Resistance V

CC2

= 5V = 5V = 5V, V

AMP1ENABLE

= 0V to 0.5V 25 70 kΩ Turn On Time 200 ns Turn Off Time 50 ns

High Level Input Voltage V Low Level Input Voltage V Input Pull-Up Resistance V

CC3

= 5V = 5V = 5V, V

AMP2ENABLE

= 2.9V to 0V 40 66 90 kΩ Turn On Time 4 µs Turn Off Time 350 ns

High Level Input Voltage V Low Level Input Voltage V Input Pull-Up Resistance V

CC3

= 3V = 3V = 3V, V

AMP2ENABLE

= 0V to 0.5V 60 100 140 kΩ Turn On Time 200 ns Turn Off Time 50 ns

)

High Level Input Voltage V Low Level Input Voltage V Input Current V

= 3V

= 0V to V

Input Capacitance (Note 6) 3 pF SENSE Input Leakage 0V < SENSE < 1V MODE Input Leakage 0V < MODE < V

CC1

= V

= 5V, VDD = OVDD = 3V. V

CC2

14 Bits

= V

= 5V, VDD = OVDD = 3V. V

CC2

2 V

1 V

120 µA

2.55 2 V

– 0.6 V

CC3

2.55 2.25 V

2 V

–10 10 µA

–3 3 µA

1.8 1.25 V

– 2.1 V

CC3

0.7 0.4 V

0.8 V

CC3

= 3V

For more information www.linear.com/LTM9004

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LTM9004

The l denotes the specifications which apply over the full operating

DigiTal inpuTs anD ouTpuTs

temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V (LTM9004-AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Logic Outputs

= 3V

Hi-Z Output Capacitance OE = 3V (Note 6) 3 pF

SOURCE

SINK

Hi-Z Output Capacitance OE = 3V (Note 6) 3 pF Output Source Current V

Output Source Current V Output Sink Current V

Output Sink Current V High Level Output Voltage IO = –10μA

High Level Output Voltage IO = –10μA

Low Level Output Voltage IO = 10μA

= 2.5V

High Level Output Voltage IO = –200μA 2.49 V

High Level Output Voltage IO = –200μA 2.49 V Low Level Output Voltage IO = 1.6mA 0.09 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 1.8V

High Level Output Voltage IO = –200μA 1.79 V

High Level Output Voltage IO = –200μA 1.79 V Low Level Output Voltage IO = 1.6mA 0.09 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 5V (LTM9004-AA, LTM9004-AB)

CC3

= 0V 50 mA

OUT

= 3V 50 mA

OUT

= –200μA

= 1.6mA

CC1

= V

= 5V, VDD = OVDD = 3V. V

CC2

2.7

2.995

2.99

0.005

0.09

0.4

= 3V

CC3

V V

power requireMenTs

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V AC, LTM9004-AD), V

= 5V (LTM9004-AA, LTM9004-AB) (Note 3)

CC3

CC1

= V

= 5V, VDD = OVDD = 3V. V

CC2

= 3V (LTM9004-

CC3

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CC1

CC2

CC3

CC1

CC1(SHDN)

Mixer Supply Voltage First Amplifier Supply Voltage Second Amplifier Supply Voltage LTM9004-AA, LTM9004-AB

LTM9004-AC, LTM9004-AD ADC Analog Supply Voltage ADC Digital Output Supply Voltage Mixer Supply Current Mixer Shutdown Current MIXENABLE = 0V, AMPxENABLE = HIGH,

4.5 5.25 V

4.5

2.7

2.7 3 3.6 V

0.5 3 3.6 V

129 180 mA

10 11 mA

5.25

3.5

ADCSHDN = 0V, OE = 0V

CC2

CC2(SHDN)

First Amplifier Supply Current First Amplifier Shutdown Current MIXENABLE = 5V, AMP1ENABLE = 0V,

52 63 mA

7.5 9 mA AMP2ENABLE = HIGH, ADCSHDN = 0V, OE = 0V

CC3

CC3(SHDN)

Second Amplifier Supply Current LTM9004-AA, LTM9004-AB Second Amplifier Shutdown Current LTM9004-AA, LTM9004-AB, MIXENABLE =

21 24 mA

0.8 4 mA AMP1ENABLE = 5V, AMP2ENABLE = 0V, ADCSHDN = 0V, OE = 0V

CC3

CC3(SHDN)

Second Amplifier Supply Current LTM9004-AC, LTM9004-AD Second Amplifier Shutdown Current LTM9004-AC, LTM9004-AD, MIXENABLE =

36 44 mA

0.6 4 mA AMP1ENABLE = 5V, AMP2ENABLE = 0V, ADCSHDN = 0V, OE = 0V

ADC Supply Current

273 306 mA

V V

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For more information www.linear.com/LTM9004

Page 7

LTM9004

power requireMenTs

The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

D(SLEEP)

D(NAP)

D(TOTAL)

TiMing characTerisTics

The l denotes the specifications which apply over the full operating temperature

Sleep Power MIXENABLE = AMPxENABLE = 0V,

Nap Mode Power MIXENABLE = AMPxENABLE = 0V,

Total Power Dissipation LTM9004-AA, LTM9004_AB,

= 5V (LTM9004-AA, LTM9004-AB) (Note 3)

CC3

ADCSHDN = 3V, OE = 3V, No CLK

ADCSHDN = 3V, OE = 0V, No CLK

MIXENABLE = AMP1ENABLE = AMP2ENABLE = 5V, ADCSHDN = 0V, f = MAX

LTM9004-AC, LTM9004-AD MIXENABLE = AMP1ENABLE = 5V, AMP2ENABLE = 3V, ADCSHDN = 0V, f = MAX

range, otherwise specifications are at TA = 25°C. Unless otherwise noted, V AC, LTM9004-AD), V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

JITTER

Sampling Frequency CLK Low Time Duty Cycle Stabilizer Off (Note 6)

CLK High Time Duty Cycle Stabilizer Off (Note 6)

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps Sample-and-Hold Aperture Delay 0 ns CLK to DATA delay CL = 5pF (Note 6) DATA to CLKOUT Skew (t MUX to DATA Delay CL = 5pF (Note 6) DATA Access Time After OE↓ BUS Relinquish Time (Note 6) Pipeline Latency 5 Cycles

= 5V (LTM9004-AA, LTM9004-AB)

CC3

Duty Cycle Stabilizer Off (Note 6)

- tC) (Note 6)

= 5pF (Note 6)

CC1

= V

= 5V, VDD = OVDD = 3V. V

CC2

SAMPLE

= V

= 5V, VDD = OVDD = 3V. V

CC2

l l

= 3V (LTM9004-

CC3

7 mW

33 mW

1.83 W

= 3V (LTM9004-

CC3

1 125 MHz

3.8 3

1.4 2.7 5.4 ns

–0.6 0 0.6 ns

1.4 2.7 5.4 ns

4 4

4.3 10 ns

3.3 8.5 ns

500 500

ns ns

RMS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: f

= 125MHz, CLKI = CLKQ unless otherwise noted.

SAMPLE

Note 4: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 5: DC offset voltage is defined as the DC voltage corresponding to the output code with LO signal applied, but no RF signal.

Note 6: Guaranteed by design, not subject to test.

For more information www.linear.com/LTM9004

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LTM9004

TiMing DiagraMs

ANALOG

INPUT

CLKI = CLKQ

D0-D13, OF

CLKOUT

N – 5

Dual Digital Output Bus Timing

N + 2 N + 4

N + 1

N – 3N – 4 N – 1 NN – 2

N + 3 N + 5

9004 TD01

CLKI = CLKQ = MUX

DEMODULATOR

ANALOG

OUTPUT I

DEMODULATOR

ANALOG

OUTPUT Q

DI0-DI13

DQ0-DQ13

CLKOUT

Multiplexed Digital Output Bus Timing

IPI

IPQ

I – 5 Q – 5 I – 4 Q – 4 I – 3 Q – 3 I – 2 Q – 2 I – 1

Q – 5 I – 5 Q – 4 I – 4 Q – 3 I – 3 Q – 2 I – 2 Q – 1

I + 1

Q + 1

I + 2 I + 4

I + 3

Q + 2 Q + 4

Q + 3

9004 TD02

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For more information www.linear.com/LTM9004

Page 9

Typical perForMance characTerisTics

(dB)

AMPLITUDE (dBFS)

9004 G03

AMPLITUDE (dBFS)

LTM9004

AMPLITUDE (dBFS)

LTM9004-AA: 64k Point FFT fIN = 700.5MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

–90 –100 –110 –120

FREQUENCY (MHz)

LTM9004-AB: 64k Point FFT f

= 701.0MHz, –1dBFS

SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

–90 –100 –110 –120

163224

FREQUENCY (MHz)

LTM9004-AC: 64k Point FFT fIN = 702.5MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

–90 –100 –110 –120

FREQUENCY (MHz)

40 50

LTM9004-AA: 64k Point FFT fIN = 1950.5MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110 –120

9004 G01

FREQUENCY (MHz)

9004 G02

LTM9004-AA, Baseband Frequency Response

–5 –10 –15 –20 –25 –30 –35 –40

–45 –50 –55 –60

4 6

BASEBAND FREQUENCY (MHz)

1210 1614

2018

9004 G02a

LTM9004-AB: 64k Point FFT fIN = 1951.0MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110 –120

163224

FREQUENCY (MHz)

9004 G04

LTM9004-AB, Baseband Frequency Response

–5 –10 –15 –20 –25 –30

(dB)

–35 –40

–45 –50 –55 –60

8 12

BASEBAND FREQUENCY (MHz)

2420 3228

4036

9004 G04a

LTM9004-AC: 64k Point FFT

9004 G05

fIN = 1952.5MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110 –120

FREQUENCY (MHz)

40 50

9004 G06

LTM9004-AC, Baseband Frequency Response

–5 –10 –15 –20 –25 –30

(dB)

–35 –40

–45 –50 –55 –60

16 24

BASEBAND FREQUENCY (MHz)

4840 6456

9004 G06a

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8072

For more information www.linear.com/LTM9004

Page 10

LTM9004

AMPLITUDE (dB)

Typical perForMance characTerisTics

LTM9004-AD: 64k Point FFT fIN = 705.0MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110 –120

FREQUENCY (MHz)

40 50

9004 G07

LTM9004-AD: 64k Point FFT fIN = 1955.0MHz, –1dBFS SENSE = V

–10 –20 –30 –40 –50 –60 –70 –80

AMPLITUDE (dBFS)

–90 –100 –110

–120

FREQUENCY (MHz)

40 50

9004 G08

LTM9004-AD, Baseband Frequency Response

–5 –10 –15 –20 –25 –30 –35 –40

–45 –50 –55 –60

32 48

IF FREQUENCY (MHz)

9680 128112

160144

9004 G09

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Page 11

pin FuncTions

Supply Pins

(Pins G5, H2), V

CC1

5V Supply for Mixer and First Amplifiers. The specified operating range is 4.5V to 5.25V. The voltage on this pin provides power for the mixer and amplifier stages only and is internally bypassed to GND.

(Pins C9, C12, K9, K12): Analog Supply for Second

CC3

Amplifiers. The specified operating range is 4.5V to 5.5V for LTM9004-AA and LTM9004-AB. The specified operating range is 2.7V to 3.5V for LTM9004-AC and LTM9004-AD.

is internally bypassed to GND.

CC3

(Pins D14, F13, G13, J14): Analog 3V Supply for the

ADC. The specified operating range is 2.7V to 3.6V. V is internally bypassed to GND.

(Pins D17, J17): Positive Supply for the Digital

Output Drivers. The specified operating range is 0.5V to

3.6V. OV

is internally bypassed to OGND.

GND (See Table for Pin Locations): Analog Ground. OGND (Pins C17, K17): Digital Output Driver Ground.

Analog Inputs RF (Pin E2): RF Input Pin. This is a single-ended 50Ω

terminated input. No external matching network is required for the high frequency band. An external (and/or shunt capacitor) may be required for impedance transformation to 50Ω in the low frequency band from 700MHz to 1.5GHz (see Figure 4). If the RF source is not DC blocked, a series blocking capacitor should be used. Otherwise, damage to the IC may result.

LO (Pin H3): Local Oscillator Input Pin. This is a singleended 50Ω terminated input. No external matching network is required in the high frequency band. An external shunt capacitor (and/or series capacitor) may be required for impedance transformation to 50Ω for the low frequency band from 700MHz to 1.5GHz (see Figure 6). If the LO source is not DC blocked, a series blocking capacitor must be used. Otherwise, damage to the IC may result.

CLKQ (Pin G14): Q-Channel ADC Clock Input. The input sample starts on the positive edge. Tie CLKQ and CLKI together.

CLKI (Pin F14): I-Channel ADC Clock Input. The input sample starts on the positive edge. Tie CLKQ and CLKI together.

(Pins C5, C8, K5, K8): Analog

CC2

series capacitor

LTM9004

_ADJ (Pin B1): DC Offset Adjust Pin for I-Channel, + Line.

Source or sink current through this pin to trim DC offset.

–

_ADJ (Pin C1): DC Offset Adjust Pin for I-Channel, – Line.

Source or sink current through this pin to trim DC offset.

_ADJ (Pin K1): DC Offset Adjust Pin for Q-Channel, + Line.

Source or sink current through this pin to trim DC offset.

–

_ADJ (Pin L1): DC Offset Adjust Pin for Q-Channel, – Line.

Source or sink current through this pin to trim DC offset.

Control Pins MIXENABLE (Pin E4): Mixer Enable Pin. If MIXENABLE =

high (the input voltage is higher than 2.0V), the mixer is enabled. If MIXENABLE = low (the input voltage is less than

1.0V), it is disabled. If the enable function is not needed, then this pin should be tied to V

AMP1ENABLE (Pins D5, L5): First Amplifier Enable Pin. AMP1ENABLE = high or floating results in normal (active) operating mode for the first amplifier in each channel. AMP1ENABLE = low (a minimum of 2.1 results in the first amplifiers being disabled. If the enable function is not needed, then this pin should be tied to V

AMP2ENABLE (Pins C10, L10): Second Amplifier Enable Pin. AMP2ENABLE = high or floating results in normal (active) operating mode

for the second amplifier in each

channel. AMP2ENABLE = low (a minimum of 0.45V below

), results in the second amplifiers being disabled. If

CC3

the enable function is not needed, then this pin should be tied to V

CC3

ADCSHDNQ (Pin J12): Q-Channel ADC Shutdown Mode Selection Pin. Connecting ADCSHDNQ to GND and OEQ to GND results in normal operation with the outputs enabled. Connecting ADCSHDNQ to GND and OEQ to V in normal operation with the outputs at high impedance. Connecting ADCSHDNQ to V

nap mode with the outputs at high impedance. Connecting ADCSHDNQ to V

and OEQ to VDD results in sleep mode

with the outputs at high impedance. ADCSHDNI (Pin D12): I-Channel ADC Shutdown Mode

Selection Pin. Connecting ADCSHDNI to GND and OEI to GND results in normal operation with the outputs enabled. Connecting ADCSHDNI to GND and OEI to V normal operation with the outputs at high impedance.

CC1

V below V

and OEQ to GND results in

results in

CC2

results

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Page 12

LTM9004

pin FuncTions

Connecting ADCSHDNI to VDD and OEI to GND results in nap mode with the outputs at high impedance. Connecting ADCSHDNI to V

and OEI to VDD results in sleep mode

with the outputs at high impedance. SENSEQ (Pin H13), SENSEI (Pin E13): ADC Reference

Programming Pin. Tie to V

for normal operation. An

external reference can be used, see ADC Reference section. MODE (Pin J13): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 V the clock duty cycle stabilizer on. 2/3 V

selects straight binary output format and turns

selects 2’s

complement output format and turns the clock duty cycle stabilizer on. V

selects 2’s complement output format

and turns the clock duty cycle stabilizer off. MUX (Pin D13): Digital Output Multiplexer Control. If MUX

= high, Q-channel comes out on DQ0 to DQ13; I-channel comes out on DI0 to DI13. If MUX = low, the output busses are swapped and Q-channel comes out on DI0 to DI13;

I-channel comes out on DQ0 channels onto

a single output bus, connect MUX, CLKQ

to DQ13. To multiplex both

and CLKI together. OEQ (Pin K13): Q-Channel Output Enable Pin. Refer to

ADCSHDNQ pin function. OEI (Pin C13): I-Channel Output Enable Pin. Refer to

ADCSHDNI pin function.

Digital Outputs CLKOUT (Pin E12): ADC Data Ready Clock Output. Latch

data on the falling edge of CLKOUT. CLKOUT is derived from CLKQ. Tie CLKQ to CLKI for simultaneous operation.

DI0 - DI13 (See Table for Pin Locations): I-Channel (In-Phase) ADC Digital Outputs. DI13 is the MSB.

DQ0 - DQ13 (See Table for Pin Locations): Q-Channel (Quadrature) ADC Digital Outputs. DQ13 is the MSB.

OF (Pin H12): Overflow/Underflow Output. High when an overflow or underflow has occurred on either I-channel or Q-channel.

Pin Configuration

A B C D E F G H J K L M

1 GND I 2 GND GND GND GND RF GND GND V 3 GND GND GND GND GND GND GND LO GND GND GND GND 4 GND GND GND GND MIX_EN GND GND GND GND GND GND GND 5 GND GND V

6 GND GND GND GND GND GND GND GND GND GND GND GND 7 GND GND GND GND GND GND GND GND GND GND GND GND 8 GND GND V 9 GND GND V

10 GND GND AMP2A_ENGND GND GND GND GND GND GND AMP2B_ENGND

11 GND GND GND GND GND GND GND GND GND GND GND GND 12 GND GND V 13 DI3 DI0 OEI MUX SENSEI V 14 DI8 DI4 DI1 V 15 DI7 DI6 DI2 GND GND GND GND GND GND DQ11 DQ4 DQ5 16 GND DI9 DI5 DI10 DI11 GND GND DQ1 DQ3 DQ9 DQ7 GND 17 GND GND OGND OV

Top View of LGA Package (Looking Through Component)

_ADJ I–_ADJ GND GND GND GND GND GND Q+_ADJ Q–_ADJ GND

GND GND GND GND

CC1

AMP1A_ENGND GND V

CC2

GND GND GND GND GND GND V

CC2

GND GND GND GND GND GND V

CC3

SHDNI CLKOUT GND GND OF SHDNQ V

CC3

GND CLKI CLKQ GND V

DI12 DI13 DQ0 DQ2 OV

GND GND V

CC1

SENSEQ MODE OEQ DQ13 DQ10

AMP1B_ENGND

CC2

CC3

DQ12 DQ8 DQ6

OGND GND GND

GND GND GND GND

GND GND

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Page 13

block DiagraM

LTM9004

CC1

ENABLE

LO ADJADJ SENSE

CC2

AMP1

ENABLE

Figure 1. Functional Block Diagram (Only One Channel is Shown)

1 AMP

ADC SHDN

REF

BUFFER

MODECLKMIX

DIFF REF AMP

CC3

AMP2

ENABLE

LPFLPF

2 AMP

1.5V

REFERENCE

RANGE

SELECT

ADCLPF

OUTPUT

DRIVERS

REFLREFH

CLKOUT

OGND

9004 BD

D13

For more information www.linear.com/LTM9004

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Page 14

LTM9004

operaTion

DESCRIPTION

The LTM9004 is a direct conversion receiver targeting high linearity receiver applications, such as wireless infrastructure with RF input frequencies up to 2.7GHz. It is an integrated μModule receiver utilizing system in a package (SiP) technology to combine a dual, high speed 14-bit A/D converter, lowpass filters, two low noise dif ferential amplifiers per channel

with fixed gain, and an I/Q

demodulator with DC offset adjustment. The direct conversion receiver architecture offers several

advantages over the traditional superheterodyne. It eases the requirements for RF front-end bandpass filtering, as it is not susceptible to signals at the image frequency. The RF bandpass filters need only attenuate strong out-of-band signals to prevent them from overloading the front end. Also, direct conversion eliminates the need for IF ampli

fiers and bandpass filters. Instead, the RF input signal is directly converted to baseband.

Direct conversion does, however, come with its own set of implementation issues. Since the receive LO signal is at the same frequency as the RF signal, it can easily radiate from the receive antenna and violate regulatory standards.

CC1

MIXER

LORFOFFSET ADJ

Figure 2. Basic Functional Elements (Only Half Shown)

CC2

1 AMP

CC3

2 AMP

GND

ADC CLK

ADCLPF

OGND

9004 F02

SEMI-CUSTOM OPTIONS

The μModule construction affords a new level of flexibility in application-specific standard products. Standard ADC, amplifier and RF components can be integrated regardless of their process technology and matched with passive components to a particular application. The LTM9004-AA, as the first example, is configured with a dual 14-bit ADC sampling at rates up to 125Msps. The amplifiers provide a

voltage gain of 14dB (including the gain of the mixer).

total The lowpass filter limits the bandwidth to 1.92MHz. The RF and LO inputs of the I/Q demodulator have integrated transformers and present 50Ω single-ended inputs. An external DAC can be used for DC offset cancellation.

Unwanted baseband signals can also be generated by 2nd order nonlinearity of the receiver. A entering the receiver

will give rise to a DC offset in the

tone at any frequency

baseband circuits. The 2nd order nonlinearity of the receiver also allows a modulated signal, even the desired signal, to generate a pseudo-random block of energy centered about DC.

For this reason, the LTM9004 provides for DC offset cor rection immediately following the

I/Q demodulator stage.

Once generated, straightforward elimination of DC offset becomes very problematic. Necessary gain in the baseband amplifiers increases the offset because their frequency response extends to DC.

The following sections describe in further detail the opera

tion of each section. The μModule technology allows the LTM9004 to be

customized and this is described in the first section. The outline of the remaining sections follows the basic functional elements as shown in Figure 2.

However, other options are possible through Linear Technology’s semi-custom development program. Linear Technology has in place a program to deliver other sample

rate, resolution, gain and filter configurations for nearly any specified application. These semi-custom designs

are based on existing components with an appropriately modified passive network. The final subsystem is then tested to the exact parameters defined for the application. The final result is a fully integrated, accurately tested and optimized solution in the same package. For more details on the semi-custom receiver subsystem program, contact

Linear Technology.

MIXER OPERATION

The RF signal is applied to the inputs of the RF trans conductance amplifiers and is

then demodulated into I/Q

baseband signals using quadrature LO signals which are internally generated from an external LO source by preci

sion 90° phase shifters.

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Page 15

operaTion

LTM9004

Broadband transformers are integrated at both the RF and LO inputs to enable single-ended RF and LO interfaces. In the high frequency band (1.5GHz to 2.7GHz), both RF and LO ports are internally matched to 50Ω. No external matching components are needed. For the lower frequency bands (700MHz to 1.5GHz), a simple network with series and/or shunt capacitors can be used as the impedance matching network.

I-CHANNEL AND Q-CHANNEL PHASE RELATIONSHIP

The phase relationship between the I-channel output signal and the Q-channel output signal is fixed. When the LO input frequency is larger (or smaller) than the RF input frequency, the Q-channel outputs (DQ0 to DQ13) lag (or lead) the I-channel outputs (DI0 to DI13) by 90°.

DC OFFSET ADJUSTMENT

Each channel includes provision for adjustment of the DC offset voltage presented at the input of the A/D converter. There are two adjust terminals for each channel, so that the common mode and differential mode DC offset may be independently trimmed. These terminals are designed to accept a source or sink current of up to 0.3mA. If the currents through the two terminals are not equal, then a differential DC offset will be the resulting DC example, sinking 0.1mA from one terminal and 0.11mA from the other terminal will yield a differential DC offset of approximately 5.9mV or 48LSB. A maximum DC offset of approximately 178mV or 1457LSB can be imposed by applying a 5V differential voltage to the adjust terminals.

AMPLIFIER OPERATION

Each channel of the LTM9004 consists of two stages of DC-coupled, low noise and low distortion fully differential op amps/ADC drivers. Each stage implements a 2-pole active lowpass filter using a high speed, high performance operational amplifier and precision passive components. The cascade of two stages is designed to provide maximum gain and phase flatness, along with adjacent channel and blocker rejection. The lowpass response can be configured for different cutoff frequencies within the range of the amplifiers. LTM9004-AA, lowpass filter designed for 1.92MHz.

offset will be common mode only. As an

created. If they are equal, then

for example, implements a

ADC INPUT NETWORK

The passive network between the second amplifier output

stages and the ADC input stages provides a 1st order

topology configured for lowpass response.

CONVERTER OPERATION

The analog-to-digital converter (ADC) shown in Figure 1 is

a dual CMOS pipelined multistep converter. The

has six pipelined

result in a digitized value six cycles later (see the Timing

Diagrams section). The CLK inputs are single ended. The

ADC has two phases of operation, determined by the state

of the CLK input pins.

Each pipelined stage contains an ADC, a reconstruction

DAC and an interstage residue amplifier. In operation, the

ADC quantizes the input to the stage and the quantized

value is subtracted from the input by the DAC to produce a

residue. The residue is amplified and output by the residue

amplifier. Successive stages operate out of phase so that

when the odd stages are outputting their residue, the even

stages are acquiring that residue and visa versa.

When CLK is low, the analog input is sampled differen

tially directly onto the input sample-and-hold capacitors.

At the instant that CLK transitions from low to high, the

sampled input is held. While CLK is high, the held input

voltage is buffered by the S/H amplifier which drives the

first pipelined ADC stage. The first stage acquires the

output of the S/H during this high phase of CLK. When

CLK goes back low, the

which is acquired by the second stage. At the same time,

the input S/H goes back to acquiring the analog input.

When CLK goes back high, the second stage produces its

residue which is acquired by the third stage. An identical

process is repeated for the third, fourth and fifth stages,

resulting in a fifth stage residue that is sent to the sixth

stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

that the results can be properly combined in the correction

logic before being sent to the output buffer.

ADC stages; a sampled analog input will

first stage produces its residue

converter

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Page 16

LTM9004

applicaTions inForMaTion

RF INPUT

Figure 3 shows the mixer’s RF input which consists of an integrated transformer and high linearity transconduc

tance amplifiers. The primary side of the transformer is connected to the RF input pin. The secondary side of the transformer is connected to the differential inputs of the transconductance amplifiers. Under no circumstances should an external DC voltage be applied to the RF input pin. DC current flowing into the primary side of the transformer may cause damage to the integrated transformer. A series blocking capacitor should be used to AC-couple the RF input port to the RF signal source.

EXTERNAL

MATCHING

NETWORK FOR

LOW BAND AND

INPUT

MID BAND

C11

C10

Figure 3. RF Input Interface

–5

–10

–15

–20

RETURN LOSS (dB)

–25

–30

NO MATCHING ELEMENTS

1.95GHz MATCH (2.7nH +

1.8pF) 700MHz MATCH (18pF +

8.2pF)

100 1000 10000

FREQUENCY (MHz)

Figure 4. RF Port Return Loss vs Frequency

TO I MIXER

TO Q MIXER

9004 F05

9004 F04

at lower frequencies, however, the input return loss can be improved with the matching network shown in Figure 3. Shunt capacitor

C10 and

series capacitor C11 can be selected for optimum input impedance matching at the desired frequency as illustrated in Figure 4. For lower fre

quency band operation, the external matching component C11 can serve as a series DC blocking capacitor.

The RF input impedance and S11 parameters (without external matching components) are listed in Table 1.

Table 1. RF Input Impedance

FREQUENCY

(MHz)

500 0.78 –139.7 16.1 –10.7 600 0.69 –166.6 10.1 –3.8 700 0.60 163.7 14.0 3.8 800 0.52 132.6 25.8 6.9

900 0.48 102.7 41.9 3.4 1000 0.45 77.4 58.8 –4.3 1100 0.42 56.6 74.9 –11.4 1200 0.38 40.1 86.4 –12.4 1300 0.31 25.7 87.6 –7.1 1400 0.22 10.9 76.8 –1.4 1500 0.10 –14.5 60.9 0.3 1600 0.06 –132.9 45.9 –0.2 1700 0.19 –170.7 34.6 –0.4 1800 0.30 –177.7 26.8 0.2 1900 0.40 –172.1 21.8 1.1 2000 0.47 –169.4 18.7 1.9 2100 0.51 –168.6 16.7 2.2 2200 0.54 –169.3 15.4 2.3 2300 0.55 –172.0 14.7 1.7 2400 0.55 –176.0 14.4 0.9 2500 0.54 –178.7 14.9 –0.3 2600 0.52 –172.3 15.9 –1.6 2700 0.50 –164.3 17.6 –3.0 2800 0.49 –155.0 19.9 –4.3 2900 0.48 –144.7 22.9 –5.4 3000 0.48 –134.8 26.4 –6.0

MAGNITUDE PHASE (°)

R (Ω)

X (Ω)

The RF input port is internally matched over a wide frequency range from 1.5GHz

to 2.7GHz with input return loss typically better than 10dB. No external matching network is needed for this frequency range. When the part is operated

LO Input Port

The mixer’s LO input interface is shown in Figure 5. The input consists of an integrated transformer and a preci sion quadrature phase shifter which generates 0° and

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Page 17

applicaTions inForMaTion

RETURN LOSS (dB)

LTM9004

90° phase-shifted LO signals for the LO buffer amplifiers driving the I/Q mixers. The primary side of the transformer is connected to the LO input pin. The secondary side of the transformer is connected to the differential inputs of the LO quadrature generator. Under no circumstances should an external DC voltage be applied to the input pin. DC current flowing into the primary side of the transformer may damage the transformer. A series blocking capacitor should be used to AC-couple the LO input port to the LO signal source.

EXTERNAL

MATCHING

NETWORK FOR

INPUT

LOW BAND AND

MID BAND

C13

C12

Figure 5. LO Input Interface

–5

–10

–15

–20

–25

–30

100 1000 10000

Figure 6. LO Return Loss vs Frequency

NO MATCHING ELEMENTS

1.95GHz MATCH (2.7nH + 1.5pF) 700MHz MATCH (15pF + 6.8pF)

FREQUENCY (MHz)

LO QUADRATURE

GENERATOR AND

BUFFER AMPLIFIERS

9004 F05

9004 F06

The LO input impedance and S11 parameters (without external matching components) are listed in Table 2.

Table 2. LO Input Impedance

FREQUENCY

(MHz)

500 0.77 –143.2 14.8 –10.0 600 0.66 –172.6 10.6 –2.0 700 0.55 154.5 17.8 5.1 800 0.46 119.8 33.1 5.5

900 0.41 88.8 50.8 –0.3 1000 0.39 63.9 67.5 –7.4 1100 0.35 44.9 80.2 –10.1 1200 0.30 31.5 83.4 –7.2 1300 0.23 22.7 76.9 –3.1 1400 0.14 20.7 65.2 –0.9 1500 0.05 47.3 53.6 –0.1 1600 0.08 139.3 44.1 0.3 1700 0.17 152.3 36.9 0.9 1800 0.25 154.7 31.7 1.6 1900 0.31 157.5 27.9 2.0 2000 0.35 160.5 25.1 2.2 2100 0.38 164.9 23.1 2.0 2200 0.41 170.3 21.4 1.4 2300 0.42 177.7 20.2 0.4 2400 0.44 –173.8 19.6 –1.0 2500 0.46 –164.6 19.7 –2.6 2600 0.48 –155.7 20.2 –4.1 2700 0.51 –147.1 21.2 –5.6 2800 0.54 –139.2 22.8 –6.8 2900 0.56 –131.5 25.2 –7.6 3000 0.58 –124.9 27.9 –7.9

MAGNITUDE PHASE (°) R (Ω)

X (Ω)

The LO input port is internally matched over a wide frequency range from 1.5

GHz to 2.7GHz with input return loss typically better than 10dB. No external matching network is needed

for this frequency range. When the part is operated at a lower frequency, the input return loss can be improved with the matching network shown in Figure

8. Shunt capacitor C12 and series capacitor C13 can be selected for optimum input impedance matching at the desired frequency as illustrated in Figure 6. For lower frequency operation, external matching component C13

can serve as the series DC blocking capacitor.

ADC Reference

The internal voltage reference can be configured for two pin-selectable ADC input ranges. Tying the SENSE pin to

selects the default range; tying the SENSE pin to 1.5V

selects a 3dB lower range. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. The SENSE pin is internally bypassed to ground with a 1µF ceramic capacitor.

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LTM9004

9004 F07

applicaTions inForMaTion

Enable Interface

The enable voltage necessary to turn on the mixer is 2V. To disable or turn off the mixer, this voltage should be below 1V. If this pin is not connected, the mixer is disabled. However, it is not recommended that the pin be left floating for normal operation.

The AMP1ENABLE and AMP2ENABLE pins are CMOS logic inputs with internal pull-up resistors. If the pin is driven low, the amplifier powers down with Hi-Z outputs. If the pin is left unconnected or driven high, the part is in normal active operation. Some care should be taken to control leakage currents at this pin to prevent inadvertently putting it into shutdown. The turn-on and turn-off time between the shutdown and active states are typically less than 1μs.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting ADCSHDNx to GND results in normal operation. Connecting ADCSHDNx to V OEx to V

results in sleep mode, which powers down

and

all circuitry including the reference and the ADC typically dissipates 1mW. When exiting sleep mode, it will take milliseconds for the output data to become valid

because the reference capacitors have to recharge and stabilize. Connecting ADCSHDNx to V

and OEx to GND results

in nap mode and the ADC typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Channels I and Q have independent ADCSHDN pins (ADCSHDNI, ADCSHDNQ

.) I-Channel is

controlled by ADCSHDNI and OEI, and Q-Channel is controlled by ADCSHDNQ and OEQ. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.

Note that ADCSHDN has the opposite polarity as MIXEN ABLE, AMP1ENA

BLE and AMP2ENABLE. Normal operation

is achieved with a logic low level on the SHDN pins and a high level disables the respective functions.

It is not recommended to enable or shut down individual components separately. These pins are separated for test purposes.

Driving the ADC Clock Inputs

The CLK inputs can be driven level signal.

A sinusoidal clock can also be used along with

directly with a CMOS or TTL

a low-jitter squaring circuit before the CLK pin (Figure 7).

CLEAN

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTM9004

4.7µF

NC7SVU04

SINUSOIDAL

CLOCK

INPUT

Figure 7. Sinusoidal Single-Ended CLK Driver

0.1µF

50Ω

The noise performance of the ADC can depend on the clock signal quality as much as on the analog input. Any noise present on the CLK signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.

It is recommended that CLKI and CLKQ are shorted to gether and driven by the same clock source. If a small time delay is

desired between when the two channels sample the analog inputs, CLKI and CLKQ can be driven by two different signals. If this time delay exceeds 1ns, the performance of the part may degrade. CLKI and CLKQ should not be driven by asynchronous signals.

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applicaTions inForMaTion

CLEAN

LTM9004

Figure 8 and Figure 9 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bear

ing on how much SNR degradation will be experienced. For high crest

factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact.

The transformer in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω series resistor to act as both a lowpass high frequency noise

that may be induced into the clock

filter for

line by neighboring digital signals, as well as a damping mechanism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the ADC is 125Msps. The lower limit of the sample rate is determined by the

droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency

for the LTM9004 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures high

performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V

or 2/3VDD

using external resistors. This circuit uses the rising edge of the CLK pin to sample

the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle for a long

period of time, the duty cycle stabilizer circuit

. If the clock is turned off

will require a hundred clock cycles for the PLL to lock onto the input clock.

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTM9004

4.7µF

100Ω

Figure 8. CLK Driver Using an LVDS or PECL to CMOS Converter

9004 F08

Figure 9. LVDS or PECL CLK Drive Using a Transformer

For more information www.linear.com/LTM9004

DIFFERENTIAL

CLOCK

INPUT

ETC1-1T

5pF-30pF

0.1µF

CLK

FERRITE

BEAD

LTM9004

9004 F09

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LTM9004

applicaTions inForMaTion

For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

Table 3 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Note that OF is high when an overflow or underflow has occurred on either channel I or channel Q.

Table 3. Output Codes vs Input Voltage

INPUT OF D13 – D0

Overvoltage 1 11 1111 1111 1111 Maximum 0 011 1111 1111 1111

Minimum Under

voltage 1 00 0000 0000 0000

(OFFSET BINARY)

11 1111 1111 1110

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

D13 – D0

(2’S COMPLEMENT)

01 1111 1111 1111 01 1111 1111 1111

01 1111 1111 1110 00 0000 0000 0001

00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110

10 0000 0000 0001 10 0000 0000 0000

10 0000 0000 0000

Digital Output Modes

Figure 10 shows an equivalent buffer. Each buffer is powered by OV

circuit for a single output

and OGND, isolated

from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

DATA

FROM

LATCH

PREDRIVER

LOGIC

LTM9004

0.1µF

43Ω

9004 F10

OGND

0.5V TO 3.6V

TYPICAL DATA OUTPUT

Figure 10. Digital Output Buffer

Lower OV

voltages will also help reduce interference

from the digital outputs.

Data Format

Using the MODE pin, the ADC parallel digital output can be selected for offset binary or 2’s complement format. Note that MODE controls MODE

to GND or 1/3 V

format. Connecting MODE to 2/3 V

both I and Q channels. Connecting

selects straight binary output

or VDD selects 2’s

complement output format. An external resistive divider can be used to set the 1/3 V

or 2/3 VDD logic values.

Table 4 shows the logic states for the MODE pin.

Table 4. MODE Pin Function

MODE PIN OUTPUT FORMAT CLOCK DUTY CYCLE

0 Straight Binary Off 1/3V 2/3V

Straight Binary On 2’s Complement On 2’s Complement Off

STABILIZER

As with all high speed/high resolution converters the digi tal output loading can affect the performance. The digital outputs of the

ADC should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For full speed operation, the capacitive load should be kept under 10pF.

Overflow Bit

When OF outputs a logic high the converter is either over-

ranged or

underranged on I-channel or Q-channel. Note that both channels when I-channel is in sleep or nap mode.

For more information www.linear.com/LTM9004

share a common OF pin. OF is disabled

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LTM9004

Output Clock

The ADC has a delayed version of the CLKQ input available as a digital output, CLKOUT. The falling edge of the CLKOUT pin can be used to latch the digital output data. CLKOUT is disabled when channel Q is in sleep or nap mode.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OV to the same supply that powers the logic being driven. For example, if the converter drives a DSP powered by a 1.8V supply, then OV

can be powered with any voltage from 500mV up

to the V volt-age from GND up to 1V and must be less than OV The logic outputs will swing between OGND and OV

Output Enable

The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed during long periods of inactivity. Channels I and Q have independent output enable pins (OEI, OEQ.)

Digital Output Multiplexer

The digital outputs of the ADC can be multiplexed onto a single data bus. The MUX pin is a digital input that swaps the two data busses. If MUX is high, I-channel comes out on DI0 to DI13; Q-channel comes out on DQ0 to DQ13. If MUX is low, the output busses are swapped and I-channel comes out on DQ0 to DQ13; Q-channel comes out on DI0 to DI13. To multiplex both channels onto a single output bus, connect MUX, CLKI and CLKQ together (see the Tim ing Diagrams for the multiplexed mode.) The multiplexed data is available on either data bus – the unused data bus can be disabled with its OE pin.

of the part. OGND can be powered with any

operation. The output Hi-Z state is intended for use

should be tied to that same 1.8V supply.

, should be tied

Design Example – UMTS Uplink FDD System

The LTM9004 can be used with an RF front end to build a complete UMTS band uplink receiver. An RF front end will consist of a diplexer, along with one or more LNAs and bandpass filters. Here is an example of typical performance for such a frontend

Rx frequency range: RF gain: 15dB maximum AGC range: 20dB Noise figure: 1.6dB IIP2: 50dBm IIP3: 0dBm P1dB: –9.5dBm Rejection at 20MHz: 2dB Rejection at Tx band: 95dB Minimum performance of the receiver is detailed in the 3GPP

TS25.104 V7.4.0 specification. We will use the Medium Area Basestation in Operating Band I for this example.

Sensitivity is a primary consideration for the receiver; the requirement is ≤–111dBm, for an input SNR of –19.8dB/5MHz. That means the effective noise floor at the receiver input must be ≤–158.2dBm/Hz. Given the effective noise contribution of the RF frontend, the maxi mum allowable noise due to the LTM9004 must then be –142.2dBm/Hz. Typical input noise for the LTM9004 is –148.3dBm/Hz, which translates to a calculated system sensitivity of –116.7dBm.

Typically such a receiver enjoys the benefits of some DSP filtering of the digitized signal after the ADC. In this case assume the DSP filter is a 64 tap RRC lowpass with alpha

equal to 0.22. To operate in the presence of co-channel in terfering signals range at maximum sensitivity. The UMTS specification calls for a maximum co-channel interferer of –73dBm. Note the the LTM9004 is –15.1dBm for a modulated signal with a 10dB crest factor. The tone interferer amounts to a peak digitized signal level of –42.6dBFS.

input level for –1dBFS within the IF passband of

1920 to 1980 MHz

, the receiver

must have sufficient dynamic

For more information www.linear.com/LTM9004

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LTM9004

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With the RF AGC set for minimum gain, the receiver must be able to demodulate the largest anticipated desired signal from the handset. This requirement ultimately sets the maximum signal the LTM9004 must accommodate at or below –1dBFS. Assuming a handset average power of +28dBm, the minimum path loss called out in the specifi cation is 53dB. The maximum signal level is then –25dBm at the receiver input, or –30dBm at the LTM9004 input. This is equivalent to –14.6dBFS peak.

There are several blocker signals detailed in the UMTS system specification. The sensitivity may degrade to no more than –105dBm in the presence of these signals. The first of these is an adjacent channel 5MHz away, at a level of –42dBm. This amounts to a peak digitized signal level of –11.6dBFS. The resulting sensitivity is then –112.8dBm.

The receiver must also contend with a –35dBm interfer ing channel ≥10MHz away. rejection of this channel, so it amounts to –6.6dBFS peak, and the resulting sensitivity is –109.2dBm.

Out of band blockers must also be accommodated, but these are at the same level as the inband blockers which have already been

In all of of the LTM9004 is well above the maximum anticipated signal levels. Note that the crest factor for the modulated channels will be on the order of 10dB to 12dB, so the largest of these will reach a peak power of approximately –6.5dBFS at the module output.

The largest blocking signal is the –15dBm CW tone ≥20MHz beyond the receive band edges. The RF frontend will offer 37dB rejection of this tone, so it will appear at the input of the LTM9004 at –32dBm. Here again, a signal at this level must not desensitize the baseband module. The equivalent digitized level is only –41.6dBFS peak, so there is no effect upon sensitivity.

Another source of undesired signal power is leakage from the transmitter. Since this is an FDD application, the re ceiver described herein will operating simultaneously. The transmitter output level is assumed to be ≤+38dBm, with a transmit to receive isola tion of 95dB. Leakage appearing at the LTM9004 input is then –42dBm, offset from the receive signal by at least

these cases, the typical input level for –1dBFS

addressed.

The RF frontend will offer no

be coupled with a transmitter

130MHz. The equivalent digitized level is only –76.6dBFS

so there is no desensitization.

peak, One challenge of

order linearity. Insufficient 2nd order linearity will allow any signal, wanted or unwanted, to create DC offset or pseudo-random noise at baseband. The blocking signals detailed above will then degrade sensitivity if this pseudorandom noise approaches the noise level of the receiver. The system specification allows for sensitivity degrada

the presence of these blockers in each case. Per

tion in the system specification, may degrade sensitivity to –105dBm. This is equivalent to increasing the effective input noise of the receiver to –148.2dBm/Hz. The 2nd order distortion produced by the LTM9004 input is about 18dB below this level, and the

resulting predicted sensitivity is –116.6dBm.

The –15dBm CW blocker will also give rise to a 2nd order product; in this case the product is a DC offset. DC offset is undesirable, as it reduces the maximum signal the A/D converter can process. The one sure way to alleviate the effects of DC offset is to ensure the 2nd order linearity of the baseband module is high enough. The predicted DC offset due to this signal is <1mV at the

Note that the system specification, so the sensitivity degradation due to this signal must be held to a minimum. The 2nd order

distortion generated in the LTM9004 is such that the loss

of sensitivity will be <0.1dB.

There is only one requirement for 3rd order linearity in

the specification. In the presence of two interferers, the sensitivity must not degrade below –105dBm. The inter ferers are a CW tone and a WCDMA channel at –44dBm each. These will appear at the LTM9004 input at –29dBm each. Their frequencies are such that they are 10MHz and 20MHz away from the desired channel, so the 3rd order intermodulation product falls at baseband. Here again, this product appears as pseudo-random noise and thus will

reduce signal to noise ratio. For a sensitivity of –105dBm, the allowable 3rd order distortion referred to the receiver input is then –148.2dBm/Hz. The 3rd order distortion produced in the LTM9004 is about 23dB below this level,

and the predicted sensitivity degradation is <0.1dB.

direct conversion architectures is 2nd

the –35dBm blocking channel

ADC input.

transmitter leakage is not included in the

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applicaTions inForMaTion

LTM9004

Supply Sequencing

The V plifiers and the V The mixer, amplifiers and ADC are separate integrated circuits within the LTM9004; however, there are no sup ply sequencing considerations beyond standard practice.

Grounding and Bypassing

The LTM9004 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTM9004 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. A continuous row of ground pads facilitates a layout that ensures that digital and analog signal lines are separated as much as possible.

The LTM9004 is internally bypassed with the ADC (V mixer and amplifier (V ground (GND). The digital output supply (OV to OGND. A 0.1µF bypass capacitor should be placed at each of the two OV is optional and may be required if power supply noise is significant.

Heat Transfer

Most of the heat generated by the LTM9004 is transferred through the bottom-side ground and thermal per are connected to a ground plane of sufficient area with as many vias as possible.

pins provide the supply to the mixer and all am-

pins provide the supply to the ADC.

) supplies returning to a common

) is returned

pins. Additional bypass capacitance

pads. For good electrical

formance, it is critical that all ground pins

• Use large PCB copper areas for ground. This helps to

dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. Common ground (GND) and output ground (OGND) are electrically isolated on the LTM9004, but can be connected on the PCB underneath the part to provide a common return path.

• Use multiple ground vias. Using as many vias as pos

sible helps board and creates and digital traces on the board at high frequencies.

• Separate analog and digital traces as much as possible,

using vias to create high frequency barriers. This will reduce digital feedback that can reduce the signal-tonoise ratio (SNR) and dynamic range of the LTM9004.

Figures 11 through 14 give a good example of the recom mended layout.

quality of

The producing high yield use a type 3 or 4 printing no-clean solder paste. The sol der stencil design should follow the guidelines outlined in Application Note 100.

The LTM9004 employs gold-finished pads for use with Pb-based or tin-based solder paste. It is inherently Pb-free and complies with the JEDEC (e4) standard. The materials declaration is available online at http://www.linear.com/ leadfree/mat_dec.jsp.

to improve the thermal performance of the

necessary barriers separating analog

the paste print is an important factor in

assemblies. It is recommended to

Recommended Layout

The high integration of the LTM9004 makes the PCB board layout simple. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.

For more information www.linear.com/LTM9004

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Figure 11. Layer 1

Figure 12. Layer 2

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applicaTions inForMaTion

LTM9004

Figure 13. Layer 3

Figure 14. Layer 4

For more information www.linear.com/LTM9004

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LTM9004

LGA Package

204-Lead (22mm × 15mm × 2.91mm)

(Reference LTC DWG # 05-08-1822 Rev C)

SEE NOTES

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LGA Package

204-Lead (22mm × 15mm × 2.91mm)

(Reference LTC DWG # 05-08-1822 Rev C)

PAD “A1” CORNER

10.1600

8.8900

7.6200

6.3500

5.0800

3.8100

2.5400

1.2700

0.0000

1.2700

2.5400

3.8100

5.0800

6.3500

7.6200

8.8900

10.1600

aaa Z

6.9850

5.7150

4.4450

3.1750

SUGGESTED PCB LAYOUT

PACKAGE TOP VIEW

1.9050

0.6350

0.0000

TOP VIEW

1.9050

aaa Z

6.9850

0.630 ±0.025 SQ. 204x

5.7150

4.4450

3.1750

SYMBOL

MOLD

SUBSTRATE

CAP

// bbb Z

DETAIL B

YXeee

DETAIL A

DIMENSIONS

A b

E e F

G H1 H2

aaa bbb eee

2.81

0.60

0.36

2.45

2.91

0.63

22.0

15.0

1.27

20.32

13.97

0.41

2.50

NOM

MIN

TOTAL NUMBER OF LGA PADS: 204

MAX

3.01

0.66

0.46

2.55

0.15

0.10

0.05

DETAIL B

SEE NOTES

L K J H G F E D C BM A

PADS

PACKAGE BOTTOM VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

Ø(0.630) PAD 1

2. ALL DIMENSIONS ARE IN MILLIMETERS

LAND DESIGNATION PER JESD MO-222, SPP-010

DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

5. PRIMARY DATUM -Z- IS SEATING PLANE

6. THE TOTAL NUMBER OF PADS: 204

NOTES

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY

LTMXXXXXX

µModule

COMPONENT

PIN “A1”

TRAY PIN 1

BEVEL

PACKAGE IN TRAY LOADING ORIENTATION

LGA 204 0113 REV C

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Page 27

LTM9004

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 05/14 Updated package drawing, height changed to 2.91mm 2, 26

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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LTM9004

Typical applicaTion

= 5V

CC1

LTM9004

0°

90°

_ADJ

I–_ADJQ+_ADJ Q–_ADJ

LTC2634-12 (OR LTC2654-16)

VCC = 5V

0.1µF

CS/LD SDI SCK SDO

REF

0.1µF

9004 TA02

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTC2295 Dual 14-Bit, 10Msps ADC 120mW, 74.4dB SNR, 9mm x 9mm QFN LTC2296 Dual 14-Bit, 25Msps ADC 150mW, 74dB SNR, 9mm x 9mm QFN LTC2297 Dual 14-Bit, 40Msps ADC 240mW, 74dB SNR, 9mm x 9mm QFN LTC2298 Dual 14-Bit, 65Msps ADC 410mW, 74dB SNR, 9mm x 9mm QFN LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm x 9mm QFN LTC2284 Dual 14-Bit, 105Msps ADC 540mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN LTC2285 Dual 14-Bit, 125Msps ADC 790mW, 72.4dB SNR, 88dB SFDR, 64-pin QFN LT5575 800MHz to 2.7GHz High Linearity Direct

Conversion Quadrature Demodulator

LTC6404-1/ LTC6404-2

600MHz, Low Noise, AC Precision Fully Differential Input/Output Ampliﬁer/Driver

LTC6406 3GHz Low Noise, Rail-to-Rail Input

Differential ADC Driver

LTM9001 16-Bit IF/Baseband Receiver Subsystem Integrated 16-Bit, 130Msps ADC, Passive Filter and Fixed Gain Differential Amplifier,

LTM9002 14-Bit Dual-Channel IF/Baseband

Receiver Subsystem

60dBm IIP2 at 1.9GHz, NF = 12.7dB, Low DC Offsets

3V or 5V, 1.5nV/√Hz, Very Low Distortion –92dBc at 10MHz

Low Noise: 1.6nV/√Hz, Low Power: 18μA

11.25mm × 11.25mm LGA Package Integrated, Dual 14-Bit 125Msps ADCs, Passive Filters and Fixed Gain Differential

Amplifiers, Up to 300MHz IF Range, 15mm × 11.25mm LGA Package

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com/LTM9004

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LT 0514 • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2011