LINEAR TECHNOLOGY LTM8032 Technical data
OUTPUT
V
REG
IC REGULATOR
REF
GND
VINSWITCH PIN
SWITCH
CONTROL
FEEDBACK NODE
+V
OUTPUT
V
REG
IC REGULATOR
REF
GND
V
IN
SWITCH
PIN
SWITCH
CONTROL
FEEDBACK NODE
+V
STEP-UP STEP-DOWN
AN122 F02
DIODE TURN-ON TIME
DIODE ON VOLTAGE
IC BREAKDOWN LIMIT
AN122 F03
DIODE
UNDER
TEST
5Ω
MEASUREMENT POINT
PULSE IN
t
RISE
≤ 2ns
AMPLITUDE = 5V + V
FWD
L DESIGN IDEAS
Diode Turn-On Time Induced
Failures in Switching Regulators
Never Has So Much Trouble Been Had
by So Many with So Few Terminals
by Jim Williams and David Beebe
This article is excerpted from the Linear
Technology Application Note AN122
with the same title.
Introduction
Most circuit designers are familiar with
diode dynamic characteristics such
as charge storage, voltage dependent
capacitance and reverse recovery
time. Less commonly acknowledged
and manufacturer specified is diode
forward turn-on time. This parameter
describes the time required for a diode
to turn on and clamp at its forward voltage drop. Historically, this extremely
short time, units of nanoseconds, has
been so small that user and vendor
alike have essentially ignored it. It
is rarely discussed and almost never
specified. Recently, switching regulator clock rate and transition time have
become faster, making diode turn-on
time a critical issue. Increased clock
rates are mandated to achieve smaller
magnetics size; decreased transition
times somewhat aid overall efficiency
but are principally needed to minimize
IC heat rise. At clock speeds beyond
about 1MHz, transition time losses are
the primary source of die heating.
A potential difficulty due to diode
turn-on time is that the resultant
Figure 2. Diode forward turn-on time permits transient excursion above
nominal diode clamp voltage, potentially exceeding IC breakdown limit.
34
34
transitory “overshoot” voltage across
the diode, even when restricted to
nanoseconds, can induce overvoltage
stress, causing switching regulator
IC failure. As such, careful testing is
required to qualify a given diode for a
particular application to insure reliability. This testing, which assumes
low loss surrounding components
and layout in the final application,
measures turn-on overshoot voltage
due to diode parasitics only. Improper
Figure 1. Typical voltage step-up/step-down converters. Assumption
is diode clamps switch pin voltage excursion to safe limits.
associated component selection and
layout will contribute additional overstress terms.
Diode Turn-On Time
Perspectives
Figure 1 shows typical step-up and
step-down voltage converters. In both
cases, the assumption is that the diode
clamps switch pin voltage excursions
to safe limits. In the step-up case, this
limit is defined by the switch pins
Figure 3. Conceptual method tests diode turn-on time at 1A. Input
step must have exceptionally fast, high fidelity transition.
Linear Technology Magazine • March 2009
DESIGN IDEAS L
AN122 F05
LT1086
22µF22µF
120Ω
1k
1k
+V ADJUST (RISE TIME TRIM)
+V TYPICAL 17VVIN = 20V
*
+V
Q1
Q4
+V
Q2
Q5
+V
Q3
Q6
1Ω
1Ω
1Ω
5Ω**
OUTPUT
62Ω50Ω
2pF TO 12pF
EDGE
PURITY
EDGE PURITY
100Ω
PULSE
INPUT
MINIMIZE INDUCTANCE IN ALL PATHS
= 2N3866
= 2N3375
** = TEN PARALLELED 50Ω RESISTORS
* = BYPASS EVERY TRANSISTOR WITH
22µF SANYO OSCON PARALLELED WITH
2.2µF MYLAR
+
+
*
*
1V/DIV
2ns/DIV
AN122 F06
AN122 F04
DIODE
UNDER
TEST
5Ω
OSCILLOSCOPE
1GHz BANDWIDTH
t
RISE
= 350ps
PULSE CURRENT
AMPLIFIER
t
RISE
= 2ns
PULSE GENERATOR
t
RISE
< 1ns
Z0 PROBE
≈1A
TYPICALLY
5V TO 6V, 30ns
WIDE
Figure 4. Detailed measurement scheme indicates necessary performance parameters for various elements. Subnanosecond rise time pulse
generator, 1A, 2ns rise time amplifier and 1GHz oscilloscope are required.
maximum allowable forward voltage.
The step-down case limit is set by
the switch pins maximum allowable
reverse voltage.
a finite length of time to clamp at its
forward voltage. This forward turnon time permits transient excursions
above the nominal diode clamp voltage, potentially exceeding the IC’s
breakdown limit. The turn-on time is
typically measured in nanoseconds,
making observation difficult. A further
complication is that the turn-on overshoot occurs at the amplitude extreme
of a pulse waveform, precluding high
resolution amplitude measurement.
These factors must be considered
when designing a diode turn-on test
method.
Linear Technology Magazine • March 2009
Figure 5. Pulse amplifier includes paralleled, darlington driven RF transistor output stage. Collector voltage adjustment
(“rise time trim”) peaks Q4 to Q6 FT, input RC network optimizes output pulse purity. Low inductance layout is mandatory.
Figure 2 indicates the diode requires
Figure 3 shows a conceptual method
for testing diode turn-on time. Here,
the test is performed at 1A although
other currents could be used. A pulse
Figure 6. Pulse amplifier output into 5Ω. Rise time is 2ns with minimal pulse-top aberrations.
steps 1A into the diode under test via
the 5Ω resistor. Turn-on time voltage excursion is measured directly
at the diode under test. The figure
3535
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