LINEAR TECHNOLOGY LTM4601, LTM4601-1 Technical data

FEATURES

LTM4601/LTM4601-1

12A DC/DC µModules

with PLL, Output Tracking

and Margining

U

DESCRIPTIO

■

Complete Switch Mode Power Supply

■

Wide Input Voltage Range: 4.5V to 20V

■

12A DC Typical, 14A Peak Output Current

■

0.6V to 5V Output Voltage

■

Output Voltage Tracking and Margining

■

Parallel Multiple µModules for Current Sharing

■

Differential Remote Sensing for Precision

Regulation (LTM4601 Only)

■

PLL Frequency Synchronization

■

±1.5% Regulation

■

Current Foldback Protection (Disabled at Start-Up)

■

Pb-Free (e4) RoHS Compliant Package with Gold

Finish Pads

■

Ultrafast Transient Response

■

Current Mode Control

■

Up to 95% Effi ciency at 5VIN, 3.3V

■

Programmable Soft-Start

■

Output Overvoltage Protection

■

Small Footprint, Low Profi le (15mm × 15mm ×

OUT

2.8mm) Surface Mount LGA Package

U

APPLICATIO S

■

Telecom and Networking Equipment

■

Servers

■

Industrial Equipment

■

Point of Load Regulation

The LTM®4601 is a complete 12A step-down switch mode
DC/DC power supply with onboard switching controller,
MOSFETs, inductor and all support components. The

TM

µModule

is housed in a small surface mount 15mm
×15mm × 2.8mm LGA package. Operating over an input
voltage range of 4.5 to 20V, the LTM4601 supports an
output voltage range of 0.6V to 5V as well as output voltage
tracking and margining. The high effi ciency design delivers
12A continuous current (14A peak). Only bulk input and
output capacitors are needed to complete the design.

The low profi le (2.8mm) and light weight (1.7g) pack­age easily mounts in unused space on the back side of
PC boards for high density point of load regulation. The
µModule can be synchronized with an external clock for
reducing undesirable frequency harmonics and allows

®

PolyPhase

operation for high load currents.

A high switching frequency and adaptive on-time current
mode architecture deliver a very fast transient response
to line and load changes without sacrifi cing stability. An
onboard differential remote sense amplifi er can be used
to accurately regulate an output voltage independent of
load current. The onboard remote sense amplifi er is not
available in the LTM4601-1.

, LTC, LT and PolyPhase are registered trademarks of Linear Technology Corporation.
µModule is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589,
6774611, 6677210

TYPICAL APPLICATIO

1.5V/12A Power Supply with 4.5V to 20V Input

V

IN

4.5V TO 20V

ON/OFF

C

IN

R1
392k

5% MARGIN

PGOOD

RUN
COMP
INTV
DRV
MPGM

V

IN

CC

CC

TRACK/SSPLLIN

LTM4601

V

OUT_LCL

DIFFV

f

SETPGNDSGND

MARG0
MARG1

V

OSNS

V

OSNS

U

CLOCK SYNC
TRACK/SS CONTROL

V

OUT

V

FB

MARGIN
CONTROL

OUT

+

–

100pF

R

SET

40.2k

4601 TA01a

C

V

1.5V
12A

OUT

OUT

Effi ciency and Power Loss

vs Load Current

95

EFFICIENCY

90

85

80

75

70

EFFICIENCY (%)

65

60

55

50

0

5V

IN

12V

IN

12V

IN

POWER LOSS

24 681012 14

OUTPUT CURRENT (A)

4.0

3.5

3.0

POWER LOSS (W)

2.5

5V

IN

2.0

1.5

1.0

0.5

4601 TA01b

4601f

1

LTM4601/LTM4601-1

WW

W

U

ABSOLUTE AXI U RATI GS

(Note 1)

INTVCC, DRVCC, V
DIFFV

) .................................................... –0.3V to 6V

OUT

OUT_LCL

PLLIN, TRACK/SS, MPGM, MARG0, MARG1,
PGOOD, f

..............................–0.3V to INTVCC + 0.3V

SET

RUN ............................................................. –0.3V to 5V

, COMP ................................................ –0.3V to 2.7V

V

FB

............................................................. –0.3V to 20V

V

IN

V

OSNS

+

, V

–

.............................–0.3V to INTVCC – 1V

OSNS

Operating Temperature Range (Note 2) ... –40°C to 85°C

Junction Temperature ........................................... 125°C

Storage Temperature Range ...................–55°C to 125°C

, V

OUT

(V

OUT

≤ 3.3V with

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

RUN

COMP

PLLIN

INTVCCTRACK/SS

V

IN

PGND

V

OUT

118-LEAD (15mm ´ 15mm ´ 2.8mm)

T

JMAX

DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS

θ

JA

LGA PACKAGE

= 125°C, θJA = 15°C/W, θJC = 6°C/W,

WEIGHT = 1.7g

*LTM4601-1 ONLY

ORDER PART NUMBER LGA PART MARKING*

MPGM

f

SET

MARG0
MARG1
DRV
V

FB

PGOOD
SGND
V

OSNS

DIFFV
V

OUT_LCL

V

OSNS

CC

+

OUT

–

/NC2*

/NC3*

/NC1*

LTM4601EV#PBF
LTM4601IV#PBF
LTM4601EV-1#PBF
LTM4601IV-1#PBF

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
*The temperature grade is identifi ed by a label on the shipping container.

The

ELECTRICAL CHARACTERISTICS

● denotes the specifi cations which apply over the –40°C to 85°C

LTM4601V
LTM4601V
LTM4601V-1
LTM4601V-1

temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN(DC)

V

OUT(DC)

Input Specifi cations

V

IN(UVLO)

I

INRUSH(VIN)

I

Q(VIN,NOLOAD)

I

S(VIN)

Input DC Voltage

Output Voltage CIN = 10µF ×3, C

Undervoltage Lockout Threshold I

Input Inrush Current at Startup I

Input Supply Bias Current VIN = 12V, V

Input Supply Current VIN = 12V, V

V

= 5V, V

IN

V

IN

= 0A 3.2 4 V

OUT

= 0A. V

OUT

V

IN

V

IN

V

= 12V, V

IN

Continuous
V

= 5V, V

IN

V

= 5V, V

IN

Shutdown, RUN = 0, VIN = 12V

V

= 12V, V

IN

V

= 5V, V

IN

OUT

= 12V, V

OUT

= 5V
= 12V

OUT
OUT

= 1.5V, No Switching

OUT

= 1.5V, Switching Continuous

OUT

OUT
OUT

= 1.5V, I

OUT

= 200µF

OUT

= 1.5V, I

= 1.5V, I

OUT

= 1.5V

= 1.5V, No Switching
= 1.5V, Switching

= 1.5V, I
= 3.3V, I

OUT
OUT

OUT

= 0A

OUT

OUT

= 12A
= 12A

= 12A

= 0A

●

4.5 20 V

●

1.478

●

1.478

1.5

1.5

0.6

0.7

3.8
38

2.5
42
22

1.81

3.63

4.29

1.522

1.522

mA
mA

mA
mA

µA

4601f

V
V

A
A

A
A
A

2

LTM4601/LTM4601-1

The ● denotes the specifi cations which apply over the –40°C to 85°C

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

INTV

CC

Output Specifi cations

I

OUTDC

ΔV

OUT(LINE)

V

ΔV
V

V

OUT(AC)

f

S

ΔV

t

START

ΔV

t

SETTLE

I

OUTPK

OUT(MIN)

OUT(0A-12A)

OUT(MIN)

OUT(START)

OUTLS

Remote Sense Amp (Note 3) (LTM4601 Only, Not Supported in the LTM4601-1)

+

, V

V

OSNS

OSNS

CM Range

DIFFV

V

A

Range Output Voltage Range VIN = 12V, DIFF OUT Load = 100k 0 INTV

OUT

OS

V

GBP Gain Bandwidth Product 3MHz

SR Slew Rate 2 V/µs

R

IN

CMRR Common Mode Rejection Mode 100 dB

Control Stage

V

FB

V

RUN

I

SS/TRACK

t

ON(MIN)

VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V

Output Continuous Current Range
(See Output Current Derating Curves
for Different V

, V

and TA)

IN

OUT

Line Regulation Accuracy V

Load Regulation Accuracy V

Output Ripple Voltage I

Output Ripple Voltage Frequency I

Turn-On Overshoot,
TRACK/SS = 10nF

Turn-On Time, TRACK/SS = Open C

Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load,

Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load

Output Current Limit C

–

Common Mode Input Voltage Range VIN = 12V, RUN > 2V 0 INTV

Input Offset Voltage Magnitude 1.25 mV

Differential Gain 1V/V

Input Resistance V

Error Amplifi er Input Voltage
Accuracy

RUN Pin On/Off Threshold 1 1.5 1.9 V

Soft-Start Charging Current V

Minimum On Time (Note 4) 50 100 ns

= 25°C, VIN = 12V. Per typical application (front page) confi guration.

A

= 12V, V

V

IN

= 1.5V, I

OUT

= 1.5V, 0A to 12A

OUT

V

IN

V

IN

= 0A, C

OUT

V

= 12V, V

IN

V

= 5V, V

IN

= 5A, VIN = 12V, V

OUT

C

= 200µF, V

OUT

V

= 12V

IN

V

= 5V

IN

= 200µF, V

OUT

= 1.5V 0 12 A

OUT

= 0A, VIN from 4.5V to 20V

OUT

= 12V, Remote Sense Amplifi er
= 12V (LTM4601-1)

= 2×, 100µF/X5R/Ceramic

OUT

= 1.5V

OUT

= 1.5V

OUT

= 1.5V 850 kHz

OUT

OUT

= 1.5V, I

OUT

= 0A

●

●

●

20
18

20
20

OUT

= 1.5V, I

OUT

= 1A

0.3 %

0.25
1

Resisitive Load
V

= 12V

IN

V

= 5V

IN

C

= 2 × 22µF/Ceramic, 470µF, 4V Sanyo

OUT

0.5

0.7

POSCAP
V

= 12V

IN

V

= 5V

IN

V

= 12V 25 µs

IN

= 200µF, Table 2

OUT

V

= 12V, V

IN

V

= 5V, V

IN

+

to GND 20 kΩ

OSNS

I

= 0A, V

OUT

SS/TRACK

= 1.5V

OUT

= 1.5V

OUT

OUT

= 1.5V

●

0.594 0.6 0.606 V

= 0V –1.0 –1.5 –2.0 µA

35
35

17
17

CC

mV
mV

– 1 V

CC

4601f

%
%

P-P
P-P

mV
mV

ms
ms

mV
mV

A
A

V

3

LTM4601/LTM4601-1

The ● denotes the specifi cations which apply over the –40°C to 85°C

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

OFF(MIN)

R

PLLIN

I

DRVCC

R

FBHI

V

MPGM

, V

V

MARG0

MARG1

PGOOD Output

ΔV

FBH

ΔV

FBL

ΔV

FB(HYS)

Minimum Off Time (Note 4) 250 400 ns

PLLIN Input Resistance 50 kΩ

Current into DRVCC Pin V

Resistor Between V

Margin Reference Voltage 1.18 V

MARG0, MARG1 Voltage Thresholds 1.4 V

PGOOD Upper Threshold VFB Rising 7 10 13 %

PGOOD Lower Threshold VFB Falling –7 –10 –13 %

PGOOD Hysteresis VFB Returning 1.5 %

OUT

and V

FB

= 25°C, VIN = 12V. Per typical application (front page) confi guration.

A

OUT

DRV

= 1.5V, I

= 5V

CC

= 1A, Frequency = 850kHz,

OUT

18 25 mA

60.098 60.4 60.702 kΩ

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTM4601E/LTM4601E-1 are guaranteed to meet performance
specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTM4601I/LTM4601I-1
are guaranteed and tested over the –40°C to 85°C temperature range.

Note 3: Remote sense amplifi er recommended for ≤3.3V output.
Note 4: 100% tested at wafer level only.

4

4601f

w

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTM4601/LTM4601-1

(See Figure 18 for all curves)

Effi ciency vs Load Current

ith 5V

IN

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

0.6V

1.2V

1.5V

2.5V

3.3V

OUTPUT CURRENT (A)

1.2V Transient Response 1.5V Transient Response

V

OUT

50mV/DIV

I

OUT

5A/DIV

OUT
OUT
OUT
OUT
OUT

510

4601 G01

Effi ciency vs Load Current
with 12V

100

95

90

85

80

75

70

EFFICIENCY (%)

65

60

55

50

15

0

0.6V

OUT

1.2V

OUT

1.5V

OUT

2.5V

OUT

3.3V

OUT

5V

OUT

5

OUTPUT CURRENT (A)

10

15

4601 G02

Effi ciency vs Load Current
with 20V

100

95

90

85

80

75

EFFICIENCY (%)

70

65

60

0

IN

5

OUTPUT CURRENT (A)

1.2V

OUT

1.5V

OUT

2.5V

OUT

3.3V

OUT

5.0V

OUT

10 15

4601 G03

1.8V Transient Response

V

OUT

50mV/DIV

I

OUT

5A/DIV

V

OUT

50mV/DIV

I

OUT

5A/DIV

1.2V AT 6A/µs LOAD STEP
= 3 • 22µF 6.3V CERAMICS

C

OUT

470µF 4V SANYO POSCAP
C3 = 100pF

20µs/DIV

2.5V Transient Response 3.3V Transient Response

V

OUT

50mV/DIV

I

OUT

5A/DIV

2.5V AT 6A/µs LOAD STEP
C

OUT

470µF 4V SANYO POSCAP
C3 = 100pF

4601 G04

20µs/DIV

= 3 • 22µF 6.3V CERAMICS

1.5V AT 6A/µs LOAD STEP
C

= 3 • 22µF 6.3V CERAMICS

OUT

470µF 4V SANYO POSCAP
C3 = 100pF

4601 G07

20µs/DIV

V

OUT

50mV/DIV

I

OUT

5A/DIV

4601 G05

3.3V AT 6A/µs LOAD STEP
= 3 • 22µF 6.3V CERAMICS

C

OUT

470µF 4V SANYO POSCAP
C3 = 100pF

20µs/DIV

1.8V AT 6A/µs LOAD STEP
= 3 • 22µF 6.3V CERAMICS

C

OUT

470µF 4V SANYO POSCAP
C3 = 100pF

20µs/DIV

4601 G08

4601 G06

4601f

5

LTM4601/LTM4601-1

A

UW

TYPICAL PERFOR A CE CHARACTERISTICS

(See Figure 18 for all curves)

Start-Up, I

V

OUT

0.5V/DIV

I

IN

0.5A/DIV

= 12V

V

IN

V

OUT

C

OUT

3 × 22
SOFT-START = 10nF

VIN to V

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

OUTPUT VOLTAGE (V)

1.5

1.0

0.5

0

0

OUT

42

= 0A

OUT

5ms/DIV

= 1.5V
= 470µF

µF

Step-Down Ratio

12 14 18

86

10

INPUT VOLTAGE (V)

Start-Up, I

OUT

= 12A

(Resistive Load)

V

OUT

0.5V/DIV

I

IN

1A/DIV

4601 G09

= 12V

V

IN

= 1.5V

V

OUT

= 470µF

C

OUT

µF

3 × 22
SOFT-START = 10nF

3.3V OUTPUT WITH
130k FROM V
TO I

ON

5V OUTPUT WITH
100k RESISTOR
ADDED FROM f
TO GND

5V OUTPUT WITH
NO RESISTOR ADDED
FROM f

2.5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

16

20

4601 G11

SET

OUT

SET

TO GND

TRACK/SS

0.5V/DIV

0.5V/DIV

V

1V/DIV

2ms/DIV

Track, I

V

FB

OUT

V

= 12V

IN

= 1.5V

V

OUT

= 470mF

C

OUT

m

3 ´ 22
SOFT-START = 10nF

= 12A

OUT

F

2ms/DIV

4601 G10

4601 G12

6

Short-Circuit Protection, I

V

OUT

0.5V/DIV

I

IN

1A/DIV

V

= 12V

IN

= 1.5V

V

OUT

= 470µF

C

OUT

µF

3 × 22
SOFT-START = 10nF

50µs/DIV

OUT

= 0

4601 G13

Short-Circuit Protection, I

V

OUT

0.5V/DIV

I

IN

1A/DIV

= 12V

V

IN

= 1.5V

V

OUT

= 470µF

C

OUT

µF

3 × 22
SOFT-START = 10nF

50µs/DIV

OUT

= 12A

4601 G14

4601f

PI FU CTIO S

LTM4601/LTM4601-1

UUU

(See Package Description for Pin Assignment)

VIN (Bank 1): Power Input Pins. Apply input voltage be-

tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V

pins

IN

and PGND pins.

(Bank 3): Power Output Pins. Apply output load

V

OUT

between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. Review the fi gure below.

PGND (Bank 2): Power ground pins for both input and
output returns.

–

V

(Pin M12): (–) Input to the Remote Sense Amplifi er.

OSNS

This pin connects to the ground remote sense point. The
remote sense amplifi er is used for V

OUT

≤3.3V.

NC1 (Pin M12): No Connect On the LTM4601-1.

+

V

(Pin J12): (+) Input to the Remote Sense Amplifi er.

OSNS

This pin connects to the output remote sense point. The
remote sense amplifi er is used for V

OUT

≤3.3V.

NC2 (Pin J12): No Connect On the LTM4601-1.

DIFFV

fi er. This pin connects to the V

(Pin K12): Output of the Remote Sense Ampli-

OUT

OUT_LCL

pin.

NC3 (Pin K12): No Connect On the LTM4601-1.

DRVCC (Pin E12): This pin normally connects to INTVCC

for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure 16.
This improves effi ciency at the higher input voltages by
reducing power dissipation in the module.

INTV

(Pin A7): This pin is for additional decoupling of

CC

the 5V internal regulator.

PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock above 2V and
below INTV

. See Applications Information.

CC

TRACK/SS (Pin A9): Output Voltage Tracking and Soft­Start Pin. When the module is confi gured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to the ground,
and connecting the center point of the divider to this pin.
See Applications Information.

MPGM (Pin A12): Programmable Margining Input. A re­sistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kΩ will equal a
value in millivolts that is a percentage of the 0.6V refer­ence voltage. See Applications Information. To parallel
LTM4601s, each requires an individual MPGM resistor.
Do not tie MPGM pins together.

(Pin B12): Frequency Set Internally to 850kHz. An

f

SET

external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See Applications Information for fre­quency adjustment.

(Pin F12): The Negative Input of the Error Amplifi er.

V

FB

Internally, this pin is connected to V

OUT_LCL

pin with a

60.4k precision resistor. Different output voltages can be
programmed with an additional resistor between V

FB

and

SGND pins. See Applications Information.

BANK 1

PGND

BANK 2

V

OUT

BANK 3

V

IN

M

A
B
C
D
E

F
G
H

J
K
L

1234567

*LTM4601-1 ONLY

TOP VIEW

RUN

PLLIN

INTVCCTRACK/SS

8 9 10 11 12

COMP

MPGM

f

SET

MARG0
MARG1
DRV
V

FB

PGOOD
SGND
V

OSNS

DIFFV
V

OUT_LCL

V

OSNS

CC

+

/NC2*

/NC3*

OUT

–

/NC1*

4601f

7

LTM4601/LTM4601-1

UUU

PI FU CTIO S

(See Package Description for Pin Assignment)

MARG0 (Pin C12): This pin is the LSB logic input for the

margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.

MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.

SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.

COMP (Pin A11): Current Control Threshold and Error
Amplifi er Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).

W

SI PLIFIEDWBLOCK DIAGRA

PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25µs power bad mask timer expires.

RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1.9V, will turn
off the module. A programmable UVLO function can be
accomplished with a resistor from V

to this pin that has

IN

a 5.1V zener to ground. Maximum pin voltage is 5V. Limit
current into the RUN pin to less than 1mA.

V

OUT_LCL

(Pin L12): V

to bypass the remote sense amplifi er, or DIFFV

connects directly to this pin

OUT

OUT

con­nects to this pin when remote sense amplifi er is used.
V

OUT_LCL

V

OUT

can be connected to V

is internally connected to V

on the LTM4601-1,

OUT

OUT_LCL

with 50Ω in the

LTM4601-1.

>2V = ON

<0.9V = OFF

MAX = 5V

R

SET

40.2k

C

SS

V

OUT_LCL

RUN

PGOOD

COMP

SGND

MARG1

MARG0

V

f

SET

MPGM

TRACK/SS

PLLIN

INTV

DRV

V

1M

(50Ω, LTM4601-1)

60.4k

INTERNAL

COMP

FB

39.2k

4.7µF

CC

CC

50k

OUT

5.1V
ZENER

POWER CONTROL

50k

50k

10k

INTV

V

IN

4.5V TO 20V

+

1.5µF

Q1

22µF

Q2

CC

10k

–
+

10k

10k

C

OUT

PGND

V

OSNS

V

OSNS

DIFFV

OUT

C

IN

V

OUT

1.5V
12A

+

–

+

NOT INCLUDED
IN THE LTM4601-1

–

= NC1

V

OSNS

+

= NC2

V

OSNS

= NC3

DIFFV

OUT

8

4601 F01

Figure 1. Simplifi ed LTM4601/LTM4601-1 Block Diagram

4601f

LTM4601/LTM4601-1

U

DECOUPLI G REQUIRE E TS

T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

C

IN

C

OUT

External Input Capacitor Requirement
(V

= 4.5V to 20V, V

IN

External Output Capacitor Requirement
(V

= 4.5V to 20V, V

IN

OUT

OUT

= 1.5V)

= 1.5V)

WU

= 25°C, VIN = 12V. Use Figure 1 confi guration.

A

= 12A, 3× 10µF Ceramics 20 30 µF

I

OUT

= 12A 100 200 µF

I

OUT

U

OPERATIO

Power Module Description

The LTM4601 is a standalone nonisolated switching mode
DC/DC power supply. It can deliver up to 12A of DC output
current with some external input and output capacitors.
This module provides precisely regulated output voltage
programmable via one external resistor from 0.6V

5.0V

over a 4.5V to 20V wide input voltage. The typical

DC

DC

application schematic is shown in Figure 18.

The LTM4601 has an integrated constant on-time current
mode regulator, ultralow R

FETs with fast switch-

DS(ON)

ing speed and integrated Schottky diodes. The typical
switching frequency is 850kHz at full load. With current
mode control and internal feedback loop compensation,
the LTM4601 module has suffi cient stability margins and
good transient performance under a wide range of operat­ing conditions and with a wide range of output capacitors,
even all ceramic output capacitors.

Current mode control provides cycle-by-cycle fast current
limit. Besides, foldback current limiting is provided in an
overcurrent condition while V

drops. Internal overvoltage

FB

and undervoltage comparators pull the open-drain PGOOD
output low if the output feedback voltage exits a ±10%
window around the regulation point. Furthermore, in an
overvoltage condition, internal top FET Q1 is turned off

and bottom FET Q2 is turned on and held on until the
overvoltage condition clears.

Pulling the RUN pin below 1V forces the controller into its
shutdown state, turning off both Q1 and Q2. At low load
current, the module works in continuous current mode by

to

default to achieve minimum output voltage ripple.

When DRV

pin is connected to INTVCC an integrated

CC

5V linear regulator powers the internal gate drivers. If a
5V external bias supply is applied on the DRV

CC

an effi ciency improvement will occur due to the reduced
power loss in the internal linear regulator. This is especially
true at the higher input voltage range.

The LTM4601 has a very accurate differential remote
sense amplifi er with very low offset. This provides for
very accurate remote sense voltage measurement. The
MPGM pin, MARG0 pin and MARG1 pin are used to sup­port voltage margining, where the percentage of margin
is programmed by the MPGM pin, and the MARG0 and
MARG1 select margining.

The PLLIN pin provides frequency synchronization of the
device to an external clock. The TRACK/SS pin is used for
power supply tracking and soft-start programming.

pin, then

4601f

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LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

The typical LTM4601 application circuit is shown in
Figure 18. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for specifi c external capacitor
requirements for a particular application.

to V

V

IN

There are restrictions in the maximum V
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristics curves labeled V
Ratio. Note that additional thermal derating may apply. See
the Thermal Considerations and Output Current Derating
section of this data sheet.

Output Voltage Programming and Margining

The PWM controller has an internal 0.6V reference voltage.
As shown in the Block Diagram, a 1M and a 60.4k 0.5%
internal feedback resistor connects V
together. The V
and the 60.4k resistor. The 1M resistor is used to protect
against an output overvoltage condition if the V
pin is not connected to the output, or if the remote sense
amplifi er output is not connected to V
voltage will default to 0.6V. Adding a resistor R
the V

VV

OUT

Table 1. Standard 1% Resistor Values

R

SET

(kΩ)

V

OUT

(V)

Step-Down Ratios

OUT

and V

IN

to V

IN

OUT_LCL

pin to SGND pin programs the output voltage:

FB

60 4..

=+06

Open 60.4 40.2 30.1 25.5 19.1 13.3 8.25

0.6 1.2 1.5 1.8 2 2.5 3.3 5

pin is connected between the 1M

kR

SET

R

SET

OUT

OUT

OUT_LCL

OUT

Step-Down

and VFB pins

OUT_LCL

. The output

SET

step

from

The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
offset for margining. A 1.18V reference divided by the
RPGM resistor on the MPGM pin programs the current.
Calculate V

V

OUT MARGIN

where %V
and V

R

OUT

OUT(MARGIN)

=

PGM

OUT(MARGIN)

is the percentage of V

V

OUT

VVV

06

.

:

V

%

OUT

V

•=

100

OUT()

you want to margin,

OUT

is the margin quantity in volts:

118

.

•

()

OUT MARGIN

k

10

•

where RPGM is the resistor value to place on the MPGM
pin to ground.

The output margining will be ± margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:

MARG0 MARG1 MODE

LOW LOW NO MARGIN

LOW HIGH MARGIN UP

HIGH LOW MARGIN DOWN

HIGH HIGH NO MARGIN

Input Capacitors

LTM4601 module should be connected to a low AC imped­ance DC source. Input capacitors are required to be placed
adjacent to the module. In Figure 18, the 10µF ceramic
input capacitors are selected for their ability to handle
the large RMS current into the converter. An input bulk
capacitor of 100µF is optional. This 100µF capacitor is only
needed if the input source impedance is compromised by
long inductive leads or traces.

10

4601f

LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

For a buck converter, the switching duty-cycle can be
estimated as:

V

OUT

D

=

V

I

CIN RMS

()

IN

I

OUT MAX

()

%

η

DD

••–=

can be a switcher-rated electrolytic

IN

1

()

Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:

In the above equation, η% is the estimated effi ciency of
the power module. C
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitor. Note the capacitor ripple current rat­ings are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.

In Figure 18, the 10µF ceramic capacitors are together
used as a high frequency input decoupling capacitor. In a
typical 12A output application, three very low ESR, X5R or
X7R, 10µF ceramic capacitors are recommended. These
decoupling capacitors should be placed directly adjacent
to the module input pins in the PCB layout to minimize
the trace inductance and high frequency AC noise. Each
10µF ceramic is typically good for 2A to 3A of RMS ripple
current. Refer to your ceramics capacitor catalog for the
RMS current ratings.

Multiphase operation with multiple LTM4601 devices in
parallel will lower the effective input RMS ripple current due
to the interleaving operation of the regulators. Application
Note 77 provides a detailed explanation. Refer to Figure 2
for the input capacitor ripple current requirement as a
function of the number of phases. The fi gure provides a
ratio of RMS ripple current to DC load current as function
of duty cycle and the number of paralleled phases. Pick

the corresponding duty cycle and the number of phases
to arrive at the correct ripple current value. For example,
the 2-phase parallel LTM4601 design provides 24A at 2.5V
output from a 12V input. The duty cycle is DC = 2.5V/12V
= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty
cycle of 0.21. This 0.25 ratio of RMS ripple current to a
DC load current of 24A equals ~6A of input RMS ripple
current for the external input capacitors.

Output Capacitors

The LTM4601 is designed for low output voltage ripple.
The bulk output capacitors defi ned as C

are chosen

OUT

with low enough effective series resistance (ESR) to meet
the output voltage ripple and transient requirements. C

OUT

can be a low ESR tantalum capacitor, a low ESR polymer
capacitor or a ceramic capacitor. The typical capacitance is
200µF if all ceramic output capacitors are used. Additional
output fi ltering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spike is required. Table 2 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRENT

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 2. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Modules (Phases)

DUTY FACTOR (V

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE

OUT/VIN

0.9

)

4601 F02

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11

LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

Multiphase operation with multiple LTM4601 devices in
parallel will lower the effective output ripple current due to
the interleaving operation of the regulators. For example,
each LTM4601’s inductor current of a 12V to 2.5V multi­phase design can be read from the Inductor Ripple Current
verses Duty Cycle graph (Figure 3). The large ripple current
at low duty cycle and high output voltage can be reduced

12

2.5V OUTPUT

10

8

6

(A)

L

I

4

2

0

0

20 40 60 80

DUTY CYCLE (V

OUT/VIN

)

4601 F03

Figure 3. Inductor Ripple Current vs Duty Cycle

5V OUTPUT

1.8V OUTPUT

1.5V OUTPUT

1.2V OUTPUT

3.3V OUTPUT WITH
130k ADDED FROM
V

TO f

OUT

SET

5V OUTPUT WITH
100k ADDED FROM

TO GND

f

SET

by adding an external resistor from f

to ground which

SET

increases the frequency. If the duty cycle is DC = 2.5V/12V
= 0.21, the inductor ripple current for 2.5V output at 21%
duty cycle is ~6A in Figure 3.

Figure 4 provides a ratio of peak-to-peak output ripple cur­rent to the inductor current as a function of duty cycle and
the number of paralleled phases. Pick the corresponding
duty cycle and the number of phases to arrive at the correct
output ripple current ratio value. If a 2-phase operation is
chosen at a duty cycle of 21%, then 0.6 is the ratio. This

0.6 ratio of output ripple current to inductor ripple of 6A
equals 3.6A of effective output ripple current. Refer to Ap­plication Note 77 for a detailed explanation of output ripple
current reduction as a function of paralleled phases.

The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output voltage ripple can be calculated with
the known effective output ripple current. The equation:
ΔV

OUT(P-P)

≈ (ΔIL/(8 • f • m • C

) + ESR • ΔIL), where f

OUT

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

DIr

0.50

0.45

0.40

0.35

PEAK-TO-PEAK OUTPUT RIPPLE CURRENT

0.30

0.25

RATIO =

0.20

0.15

0.10

0.05

0

0.1 0.15 0.2 0.25 0.350.3 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

DUTY CYCLE (VO/VIN)

1-PHASE
2-PHASE
3-PHASE
4-PHASE

6-PHASE

4601 F04

Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI, Dlr = Each Phase’s Inductor Current

4601f

12

LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

is frequency and m is the number of parallel phases. This
calculation process can be easily fulfi lled using our Linear
Technology µModule Design Tool.

Fault Conditions: Current Limit and Overcurrent
Foldback

LTM4601 has a current mode controller, which inher­ently limits the cycle-by-cycle inductor current not only
in steady-state operation, but also in transient.

To further limit current in the event of an overload condi­tion, the LTM4601 provides foldback current limiting. If the
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.

Soft-Start and Tracking

The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.5µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltage reference minus any margin delta. This will control
the ramp of the internal reference and the output voltage.
The total soft-start time can be calculated as:

C

tVVV

SOFTSTART OUT MARGIN

=

08 06

.•.– •

()

()

15

.

SS

µ

AA

down with another regulator. The master regulator’s output
is divided down with an external resistor divider that is the
same as the slave regulator’s feedback divider. Figure 5
shows an example of coincident tracking. Ratiometric
modes of tracking can be achieved by selecting different
resistor values to change the output tracking ratio. The
master output must be greater than the slave output for
the tracking to work. Figure 6 shows the coincident output
tracking characteristics.

MASTER

OUTPUT

R2

FB

SLAVE OUTPUT

C

60.4k

R1

40.2k

OUT

V

IN

100k

PGOOD

MPGM
RUN

C

IN

COMP
INTV
DRV

PLLIN

V

IN

LTM4601

CC

CC

TRACK CONTROL

TRACK/SS

V

MARG0
MARG1

V

OUT_LCL

DIFFV

V

OSNS

V

OSNS

f

SETPGNDSGND

OUT

V

OUT

FB

+

–

60.4k FROM
TO V

V

OUT

R

SET

40.2k

4601 F05

Figure 5

When the RUN pin falls below 1.5V, then the SS pin is reset
to allow for proper soft-start control when the regulator
is enabled again. Current foldback and force continuous
mode are disabled during the soft-start process. The
soft-start function can also be used to control the output
ramp up time, so that another regulator can be easily
tracked to it.

Output Voltage Tracking

Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up and

OUTPUT

VOLTAGE

MASTER OUTPUT

TIME

Figure 6

SLAVE OUTPUT

4601 F06

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APPLICATIO S I FOR ATIO

Run Enable

The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with a logic input not to exceed 5V.

The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:

RR

=

+12

R

2

15•.

V

V

UVLO

Power Good

The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.

COMP Pin

This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application require­ments. A spice model will be provided for other control
loop optimization.

through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:

P

LDO_LOSS

= 20mA • (VIN – 5V)

The LTM4601 also provides the external gate driver volt­age pin DRV
recommended to connect DRV

. If there is a 5V rail in the system, it is

CC

pin to the external 5V

CC

rail. This is especially true for higher input voltages. Do
not apply more than 6V to the DRV
be used to power the DRV

pin with an external circuit

CC

pin. A 5V output can

CC

as shown in Figure 16.

Parallel Operation of the Module

The LTM4601 device is an inherently current mode con­trolled device. Parallel modules will have very good current
sharing. This will balance the thermals on the design.
Figure 19 shows a schematic of the parallel design. The
voltage feedback equation changes with the variable n as
modules are paralleled:

k

60 4..

VV

=+06

OUT

R

n

FB

R

FB

η is the number of paralleled modules.

PLLIN

The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows the internal top MOSFET turn-on
to be locked to the rising edge of the external clock. The
frequency range is ±30% around the operating frequency
of 850kHz. A pulse detection circuit is used to detect a
clock on the PLLIN pin to turn on the phase lock loop.
The pulse width of the clock has to be at least 400ns and
2V in amplitude. During the start-up of the regulator, the
phase-lock loop function is disabled.

INTV

and DRVCC Connection

CC

An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRV

CC

for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4601
can be directly powered by V

. The gate driver current

IN

Figure 19 shows an LTM4601 and an LTM4601-1 used in a
parallel design. The 2nd LTM4601 device does not require
the remote sense amplifi er, therefore, the LTM4601-1 de­vice is used. An LTM4601 device can be used without the
diff amp. V

OSNS

be tied to INTV

+

can be tied to ground and the V
. DIFFV

CC

can fl oat. When using multiple

OUT

OSNS

–

can

LTM4601-1 devices in parallel with an LTM4601, limit the
number to fi ve for a total of six modules in parallel.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 14 for calculating an approximate θ

for the

JA

module with various heat sinking methods. Thermal models
are derived from several temperature measurements at
the bench and thermal modeling analysis. Thermal Ap­plication Note 103 provides a detailed explanation of the
analysis for the thermal models and the derating curves.
Tables 3 and 4 provide a summary of the equivalent θ

JA

4601f

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LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

5.0

4.5

4.0

3.5

3.0

2.5

2.0

POWER LOSS (W)

1.5

1.0

0.5

0

2

0

Figure 7. 1.5V Power Loss Figure 8. 3.3V Power Loss

12

10

8

OUTPUT CURRENT (A)

12V LOSS

4

20V LOSS

5V LOSS

68

12

10

4601 F07

6

5

4

3

2

POWER LOSS (W)

1

0

0

2

12

10

8

20V LOSS

468

OUTPUT CURRENT (A)

12V LOSS

10 12

4601 F08

6

4

MAXIMUM LOAD CURRENT (A)

5VIN, 1.5V

2

0

50

, 1.5V

5V

IN

, 1.5V

5V

IN

60 70 80 90

AMBIENT TEMPERATURE (°C)

OUT
OUT
OUT

0LFM
200LFM
400LFM

Figure 9. No Heat Sink 5V

4600 F09

IN

100

6

4

MAXIMUM LOAD CURRENT (A)

5VIN, 1.5V

2

0

50

, 1.5V

5V

IN

, 1.5V

5V

IN

60 70 80 90

AMBIENT TEMPERATURE (°C)

OUT
OUT
OUT

0LFM
200LFM
400LFM

Figure 10. BGA Heat Sink 5V

100

4601 F10

IN

4601f

15

LTM4601/LTM4601-1

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APPLICATIO S I FOR ATIO

12

10

8

6

4

MAXIMUM LOAD CURRENT (A)

12

5VIN, 1.5V

2

5V

IN

5V

0

IN

50

60 70 80 90

AMBIENT TEMPERATURE (°C)

, 1.5V
, 1.5V

OUT
OUT
OUT

0LFM
200LFM
400LFM

Figure 11. No Heat Sink 12V

100

4601 F11

IN

12

10

8

6

4

MAXIMUM LOAD CURRENT (A)

5VIN, 1.5V

2

0

50

, 1.5V

5V

IN

, 1.5V

5V

IN

60 70 80 90

AMBIENT TEMPERATURE (°C)

OUT
OUT
OUT

0LFM
200LFM
400LFM

Figure 12. BGA Heat Sink 12V

12

100

4601 F12

IN

10

8

6

4

MAXIMUM LOAD CURRENT (A)

0LFM

2

200LFM
400LFM

0

40

60 80

AMBIENT TEMPERATURE (°C)

Figure 13. 12VIN, 3.3V

, No Heat Sink

OUT

4601 F13

100

10

8

6

4

MAXIMUM LOAD CURRENT (A)

0LFM

2

200LFM
400LFM

0

40

60 80

AMBIENT TEMPERATURE (°C)

Figure 14. 12VIN, 3.3V

, BGA Heat Sink

OUT

100

4601 F14

16

4601f

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APPLICATIO S I FOR ATIO

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18), 0A to 6A Load Step

TYPICAL MEASURED VALUES

VENDORS PART NUMBER C

C

OUT1

TDK C4532X5R0J107MZ (100UF,6.3V) SANYO POS CAP 6TPE330MIL (330µF, 6.3V)
TAIYO YUDEN JMK432BJ107MU-T ( 100µF, 6.3V) SANYO POS CAP 2R5TPE470M9 (470µF, 2.5V)
TAIYO YUDEN JMK316BJ226ML-T501 ( 22µF, 6.3V) SANYO POS CAP 4TPE470MCL (470µF, 4V)

V

OUT

(V)

1.2 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 47pF 5 70 140 30 6 60.4

1.2 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 5 35 70 20 6 60.4

1.2 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 22pF 5 70 140 20 6 60.4

1.2 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 40 93 30 6 60.4

1.2 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 12 70 140 30 6 60.4

1.2 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 12 35 70 20 6 60.4

1.2 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 22pF 12 70 140 20 6 60.4

1.2 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 12 49 98 20 6 60.4

1.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 5 48 100 35 6 40.2

1.5 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 33pF 5 54 109 30 6 40.2

1.5 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 5 44 84 30 6 40.2

1.5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 61 118 30 6 40.2

1.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 12 48 100 35 6 40.2

1.5 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 33pF 12 54 109 30 6 40.2

1.5 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 12 44 89 25 6 40.2

1.5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 12 54 108 25 6 40.2

1.8 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 47pF 5 48 100 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 5 44 90 20 6 30.1

1.8 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 5 68 140 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 65 130 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 12 60 120 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 2.5V NONE 100pF 12 60 120 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 12 68 140 30 6 30.1

1.8 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 12 65 130 20 6 30.1

2.5 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 4V NONE 100pF 5 48 103 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 220pF 5 56 113 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 5 57 116 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 5 60 115 25 6 19.1

2.5 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 4V NONE 100pF 12 48 103 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE NONE 12 51 102 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 220pF 12 56 113 30 6 19.1

2.5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 220pF 12 70 140 25 6 19.1

3.3 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 7 120 240 30 6 13.3

3.3 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 4V NONE 100pF 7 110 214 30 6 13.3

3.3 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 100pF 7 110 214 30 6 13.3

3.3 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 7 114 230 30 6 13.3

3.3 2 × 10µF 25V 150µF 35V 1 × 100µF 6.3V 470µF 4V NONE 100pF 12 110 214 30 6 13.3

3.3 2 × 10µF 25V 150µF 35V 3 × 22µF 6.3V 470µF 4V NONE 150pF 12 110 214 35 6 13.3

3.3 2 × 10µF 25V 150µF 35V 2 × 100µF 6.3V 330µF 6.3V NONE 100pF 12 110 214 35 6 13.3

3.3 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 100pF 12 114 230 30 6 13.3
5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 15 188 375 25 6 8.25
5 2 × 10µF 25V 150µF 35V 4 × 100µF 6.3V NONE NONE 22pF 20 159 320 25 6 8.25

C

IN

(CERAMIC)

C

IN

(BULK)

C

OUT1

(CERAMIC)

C

OUT2

(BULK) C

COMP

VENDORS PART NUMBER

OUT2

V

C3

(V)

DROOP

IN

(mV)

PEAK TO

PEAK (mV)

RECOVERY

TIME (µs)

LOAD STEP

(A/µs)

R

SET

(kΩ)

4601f

17

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

Table 3. 1.5V Output at 12A

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)

Figures 9, 11 5, 12 Figure 7 0 None 15.2

Figures 9, 11 5, 12 Figure 7 200 None 14

Figures 9, 11 5, 12 Figure 7 400 None 12

Figures 10, 12 5, 12 Figure 7 0 BGA Heat Sink 13.9

Figures 10, 12 5, 12 Figure 7 200 BGA Heat Sink 11.3

Figures 10, 12 5, 12 Figure 7 400 BGA Heat Sink 10.25

Table 4. 3.3V Output at 12A

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)

Figure 13 12 Figure 8 0 None 15.2

Figure 13 12 Figure 8 200 None 14.6

Figure 13 12 Figure 8 400 None 13.4

Figure 14 12 Figure 8 0 BGA Heat Sink 13.9

Figure 14 12 Figure 8 200 BGA Heat Sink 11.1

Figure 14 12 Figure 8 400 BGA Heat Sink 10.5

Heat Sink Manufacturer

Wakefi eld Engineering Part No: 20069 Phone: [phone]

18

4601f

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

for the noted conditions. These equivalent θJA parameters
are correlated to the measured values, and are improved
with air fl ow. The case temperature is maintained at 100°C
or below for the derating curves. The maximum case
temperature of 100°C is to allow for a rise of about 13°C
to 25°C inside the µModule with a thermal resistance θ
from junction to case between 6°C/W to 9°C/W. This will
maintain the maximum junction temperature inside the
µModule below 125°C.

Safety Considerations

The LTM4601 modules do not provide isolation from
V

to V

IN

. There is no internal fuse. If required, a

OUT

slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.

Layout Checklist/Example

The high integration of LTM4601 makes the PCB board
layout very simple and easy. However, to optimize its electri­cal and thermal performance, some layout considerations
are still necessary.

JC

• Use large PCB copper areas for high current path, in­cluding V

, PGND and V

IN

. It helps to minimize the

OUT

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci­tors next to the V

, PGND and V

IN

pins to minimize

OUT

high frequency noise.

• Place a dedicated power ground layer underneath the
unit. Refer frequency synchronization source to power
ground.

• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.

• Do not put vias directly on pads.

• Use a separated SGND ground copper area for com­ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.

Figure 15 gives a good example of the recommended
layout.

V

GND

V

OUT

IN

CINC

IN

SIGNAL
GND

C

C

OUT

OUT

Figure 15. Recommended Layout

4601 F15

4601f

19

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

Frequency Adjustment

The LTM4601 is designed to typically operate at 850kHz
across most input conditions. The f
open or decoupled with an optional 1000pF capacitor. The
switching frequency has been optimized for maintaining
constant output ripple noise over most operating ranges.
The 850kHz switching frequency and the 400ns minimum
off time can limit operation at higher duty cycles like 5V to

3.3V, and produce excessive inductor ripple currents for
lower duty cycle applications like 20V to 5V. The 5V and

3.3V drop out curves are modifi ed by adding an external
resistor on the f

pin to allow for lower input voltage

SET

operation, or higher input voltage operation.

Example for 5V Output

LTM4601 minimum on-time = 100ns;

= ((4.8 • 10pf)/I

t

ON

fSET

)

LTM4601 minimum off-time = 400ns; t
where t = 1/Frequency

Duty Cycle = t

ON

/t or V

OUT/VIN

Equations for setting frequency:

= (VIN/(3 • R

I

fSET

= ((4.8 • 10pF)/I

t

ON

is 39.2k. Frequency = (V

R

fSET

)), for 20V operation, I

fSET

), tON = 282ns, where the internal

fSET

OUT

282ns)) ~ 886kHz. The inductor ripple current begins to
get high at the higher input voltages due to a larger voltage
across the inductor. This is noted in the Typical Inductor
Ripple Current verses Duty Cycle graph (Figure 3) where

≈ 10A at 25% duty cycle. The inductor ripple current

I

L

can be lowered at the higher input voltages by adding an
external resistor from f

to ground to increase the switch-

SET

ing frequency. An 8A ripple current is chosen, and the total
peak current is equal to 1/2 of the 8A ripple current plus
the output current. The 5V output current is limited to 8A,
so the total peak current is less than 12A. This is below the

pin is normally left

SET

= t – tON,

OFF

= 170µA,

SET

/(VIN • tON)) = (5V/(20 •

14A peak specifi ed value. A 100k resistor is placed from

to ground, and the parallel combination of 100k and

f

SET

39.2k equates to 28k. The I

20V input voltage equals 238µA. This equates to a t

calculation with 28k and

fSET

ON

of
200ns. This will increase the switching frequency from
~886kHz to ~1.25MHz for the 20V to 5V conversion. The
minimum on time is above 100ns at 20V input. Since
the switching frequency is approximately constant over
input and output conditions, then the lower input voltage
range is limited to 10V for the 1.25MHz operation due to
the 400ns minimum off time. Equation: t

ON

= (V

OUT/VIN

)

• (1/Frequency) equates to a 400ns on time, and a 400ns
off time. The “V

IN

to V

Step Ratio Curve” refl ects an

OUT

operating range of 10V to 20V for 1.25MHz operation with
a 100k resistor to ground, and an 8V to 16V operation for

fl oating. These modifi cations are made to provide

f

SET

wider input voltage ranges for the 5V output designs while
limiting the inductor ripple current, and maintaining the
400ns minimum off time.

Example for 3.3V Output

LTM4601 minimum on-time = 100ns;

= ((3.3 • 10pF)/I

t

ON

fSET

)

LTM4601 minimum off-time = 400ns;

= t – tON, where t = 1/Frequency

t

OFF

Duty Cycle (DC) = t

ON

/t or V

OUT/VIN

Equations for setting frequency:

= (VIN/(3 • R

I

fSET

= ((3.3 • 10pf)/I

t

ON

is 39.2k. Frequency = (V

R

fSET

)), for 20V operation, I

fSET

), tON = 195ns, where the internal

fSET

/(VIN • tON)) = (3.3V/(20

OUT

fSET

= 170µA,

• 195ns)) ~ 846kHz. The minimum on-time and minimum­off time are within specifi cation at 195ns and 980ns. The

4.5V minimum input for converting 3.3V output will not
meet the minimum off-time specifi cation of 400ns. t
868ns, Frequency = 850kHz, t

= 315ns.

OFF

ON

=

20

4601f

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

Solution

Lower the switching frequency at lower input voltages to
allow for higher duty cycles, and meet the 400ns mini­mum off-time at 4.5V input voltage. The off-time should
be about 500ns with 100ns guard band. The duty cycle

V

CC

CC

SGND

OFF

IN

LTM4601-1

, or

TRACK/SSPLLIN

for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/t
(1 – 0.73)/500ns = 540kHz. The switching frequency needs
to be lowered to 540kHz at 4.5V input. t
or 1.35µs. The f
the I

current equates to 38µA with the internal 39.2k.

fSET

pin voltage compliance is 1/3 of VIN, and

SET

V

IN

10V TO 20V

C2

10µF

25V

R2

100k

5% MARGIN

392k

1%
C1
10µF
25V

= DC/frequency,

ON

V

OUT

R4

100k

R1

PGOOD

MPGM
RUN
COMP
INTV
DRV

The I
A resistor can be placed from V
effective I
f

SET

will source 14µA into the f

current needs to be 24µA for 540kHz operation.

fSET

current out of the f

fSET

pin is 4.5V/3 =1.5V and V

SET

to f

OUT

SET

= 3.3V, therefore 130k

OUT

node and lower the I

to lower the

SET

pin to 24µA. The

fSET

current to 24µA. This enables the 540kHz operation and
the 4.5V to 20V input operation for down converting to

3.3V output. The frequency will scale from 540kHz to 1.1
MHz over this input range. This provides for an effective
output current of 8A over the input range.

TRACK/SS CONTROL

REVIEW TEMPERATURE

MARG0
MARG1

V

OUT_LCL

f

SETPGND

V

R

fSET

100k

OUT

V

NC3
NC1
NC2

FB

DERATING CURVE

C6 100pF

R

SET

8.25k

+

V

OUT

5V

C3

8A

100µF

6.3V
SANYO POSCAP

REFER TO

TABLE 2

IMPROVE

EFFICIENCY

FOR ≥12V INPUT

MARGIN CONTROL

SOT-323

DUAL

CMSSH-3C3

4601 F16

Figure 16. 5V at 8A Design Without Differential Amplifi er

4601f

21

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

V

R2

100k

PGOOD

OUT

R4

100k

R1

392k

5% MARGIN

PGOOD

MPGM
RUN
COMP
INTV
DRV

V

4.5V TO 16V

10µF

25V

IN

C2

×3

TRACK/SS CONTROL

REVIEW TEMPERATURE

V

OUT

V

FB

MARG0
MARG1

OUT

+

V

OSNS

–

V

OSNS

DERATING CURVE

C6 100pF

R
130k

LTM4601

MARGIN CONTROL

TRACK/SSPLLIN

V

OUT_LCL

DIFFV

f

SETPGNDSGND

V

IN

CC

CC

Figure 17. 3.3V at 10A Design

fSET

4601 F17

R

SET

13.3k

C3

+

100µF

6.3V
SANYO POSCAP

V

OUT

3.3V
10A

V

4.5V TO 20V

BULK

OPT

CLOCK SYNC

MARG0
MARG1

V

OUT_LCL

DIFFV

V

OSNS

V

OSNS

SETPGNDSGND

C5

0.01µF

REVIEW TEMPERATURE

OUT

V

OUT

FB

+

–

DERATING CURVE

C3 100pF

MARGIN
CONTROL

V

4601 F18

R

SET

40.2k

C

OUT1

100µF

6.3V

REFER TO

TABLE 2 FOR

DIFFERENT

OUTPUT

VOLTAGE

V

OUT

1.5V

C

OUT2

470µF

6.3V

12A

+

V

R2

100k

PGOOD

C

IN

10µF
25V
×3 CER

OUT

R4

100k

ON/OFF

R1
392k

5% MARGIN

PGOOD

MPGM
RUN
COMP
INTV
DRV

CC

V

IN

CC

TRACK/SSPLLIN

LTM4601

f

IN

+

C

IN

Figure 18. Typical 4.5V-20VIN, 1.5V at 12A Design

22

4601f

LTM4601/LTM4601-1

U

WUU

APPLICATIO S I FOR ATIO

V

V

IN

4.5V TO 20V

+

C5*
100µF
25V

C2

10µF

25V

×2

4.5V TO 20V

PGOOD

C8
10µF
25V
×2

0.1µF

118k
1%

C1

LTC6908-1

1

+

V

2

GND

3

SET

2-PHASE

OSCILLATOR

OUT1

OUT2

MOD

6

5

4

OUT

R2
100k

392k

MARGIN

392k

R1

100k

5%

60.4k
+ R

SET

= 0.6V

+

C4

TABLE 2

N

R

SET

V

OUT

1.5V
24A

+

C4
470µF

6.3V

V

CLOCK SYNC
0° PHASE

R4

PGOOD

MPGM
RUN
COMP
INTV
DRV

PGOOD

MPGM
RUN
COMP
INTV
DRV

V

IN

CC

CC

V

IN

CC

CC

TRACK/SSPLLIN

LTM4601

MARGIN CONTROL

TRACK/SSPLLIN

LTM4601-1

MARG0
MARG1

V

OUT_LCL

DIFFV

V

OSNS

V

OSNS

f

SETPGNDSGND

CLOCK SYNC
180° PHASE

TRACK/SS CONTROL

MARG0
MARG1

V

OUT_LCL

f

SETPGNDSGND

V

V

OUT

V

OUT

OUT

V

NC3
NC2
NC1

FB

+

–

FB

TRACK/SS CONTROL

C6 220pF

R

SET

20k

C7

0.033µF

4601 F19

OUT

N = NUMBER OF PHASES

C3
22µF

6.3V

470µF

6.3V

REFER TO

TABLE 2

100pF

C3
22µF

6.3V

REFER TO

*C5 OPTIONAL TO REDUCE ANY LC RINGING.
NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTION

Figure 19. 2-Phase Parallel, 1.5V at 24A Design

4601f

23

LTM4601/LTM4601-1

U

TYPICAL APPLICATIO S

3.3V

R23

60.4k

R24

19.1k

C15

+

C16

2.5V AT 12A

C18 100pF

OUT

V

TRACK/SSPLLIN

FB

V

470µF

22µF

6.3V

MARGIN

MARG0

6.3V

CONTROL

MARG1

TABLE 2

REFER TO

OUT

OUT_LCL

V

DIFFV

C15

470µF

6.3V

+

C16

22µF

6.3V

MARGIN

CONTROL

MARG0

MARG1

TABLE 2

REFER TO

OUT

OUT_LCL

V

DIFFV

+

OSNS

V

R13

40.2k

–

OSNS

V

SETPGNDSGND

f

1.5V AT 12A

3.3V

R18

19.1k
R25

60.4k

R26

40.2k

C24 100pF

+

OSNS

V

–

OSNS

V

SETPGNDSGND

f

TRACK/SSPLLIN

FB

V

OUT

V

4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Tracking

8V TO 16V

C26

R17

0.1µF

59k

SET

LTC6902

V+DIVPHOUT1

4-PHASE

GND

MOD

OUT4

OSCILLATOR

CLOCK SYNC 1

CLOCK SYNC 2

3.3V

OUT3

OUT2

TRACK/SS

8V TO 16V

R11

R10

C7

CONTROL

IN

V

PGOOD

100k

100k

3.3V AT 10A

0.15µF

OUT

V

TRACK/SSPLLIN

IN

V

PGOOD

MPGM

RUN

PGOOD

C10

470µF

+

C9

22µF

MARGIN

C12 100pF

FB

V

MARG0

MPGM

RUN

LTM4601

COMP

ON/OFF

6.3V

6.3V

CONTROL

MARG1

LTM4601

COMP

CC

INTVCCDRV

C14

TABLE 2

REFER TO

OUT

OUT_LCL

V

DIFFV

CC

INTVCCDRV

+

R9

10µF

OSNS

V

392k

25V

–

OSNS

V

×3

f

R8

SETPGNDSGND

13.3k

CLOCK SYNC 4

5% MARGIN

CLOCK SYNC 3

8V TO 16V

3.3V

R21

60.4k

TRACK 2.5V

3.3V

R19

R16

R15

30.1k

IN

V

PGOOD

100k

100k

1.8V AT 12A

C8 100pF

OUT

V

TRACK/SSPLLIN

IN

V

PGOOD

MPGM

PGOOD

C4

+

C3

22µF

FB

V

MPGM

RUN

ON/OFF

470µF

6.3V

6.3V

MARGIN

MARG0

RUN

LTM4601

COMP

INTVCCDRV

REFER TO

CONTROL

MARG1

OUT_LCL

V

LTM4601

COMP

INTVCCDRV

CC

R14

C14

10µF

TABLE 2

+

OUT

OSNS

V

DIFFV

CC

392k

25V

–

V

OSNS

×3

f

R12

SETPGNDSGND

5% MARGIN

30.1k

24

BUS

INTERMEDIATE

–48V

INPUT

8V TO 16V

3.3V

R1

R27

C11

392k

C8

100µF

35V

OPT

5% MARGIN

10µF

25V

×3

8V TO 16V

3.3V

R3

100k

R2

100k

R7

100k

R6

100k

ON/OFF

PGOOD

ON/OFF

PGOOD

392k

5% MARGIN

C2

10µF

25V

×3

+

4601f

PACKAGE DESCRIPTIO

LTM4601/LTM4601-1

U

aaa Z

Y

X

15

BSC

aaa Z

2.72 – 2.92

LGA Package

118-Lead (15mm × 15mm)

(Reference LTM DWG # 05-05-1801, Rev Ø)

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

0.0000

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

PAD 1

4

CORNER

15

BSC

MOLD

SUBSTRATE

CAP

0.27 – 0.37

DETAIL B

2.45 – 2.55

TOP VIEW

LGA 118 0306 REV Ø

0.10

0.10

0.03

TOLERANCE

DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE

4

NOTES:

DETAIL B

Z

DETAIL A

13.97

0.60 – 0.66

BSC

bbb Z

3

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS

LAND DESIGNATION PER JESD MO-222, SPP-010

YXeee

M

0.60 – 0.66

L

M

5. PRIMARY DATUM -Z- IS SEATING PLANE

DETAIL A

G

HKJ

TOP VIEW

aaa

eee

bbb

SYMBOL

6. THE TOTAL NUMBER OF PADS: 118

3

PADS

SEE NOTES

A

B

C

D

E

F

12

BOTTOM VIEW

SUGGESTED SOLDER PAD LAYOUT

234567891011

1

6.9850

5.7150

4.4450

3.1750

1.9050

0.6350

0.0000

0.6350

1.9050

3.1750

4.4450

5.7150

6.9850

0.12 – 0.28

13.97

BSC

1.27

BSC

PAD 1

C(0.30)

4601f

25

LTM4601/LTM4601-1

PACKAGE DESCRIPTIO

PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME

A1 V

IN

A2 V

IN

A3 V

IN

A4 V

IN

A5 V

IN

A6 V

IN

A7 INTV
A8 PLLIN B8 - C8 - D8 - E8 - F8 PGND
A9 TRACK/SS B9 - C9 - D9 - E9 - F9 PGND
A10 RUN B10 - C10 - D10 - E10 - F10 ­A11 COMP B11 - C11 - D11 - E11 - F11 ­A12 MPGM B12 f

G1 PGND H1 PGND J1 V
G2 PGND H2 PGND J2 V
G3 PGND H3 PGND J3 V
G4 PGND H4 PGND J4 V
G5 PGND H5 PGND J5 V
G6 PGND H6 PGND J6 V
G7 PGND H7 PGND J7 V
G8 PGND H8 PGND J8 V
G9 PGND H9 PGND J9 V
G10 - H10 - J10 V
G11 - H11 - J11 - K11 V
G12 PGOOD H12 SGND J12 V

CC

PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME

U

Pin Assignment Tables

(Arranged by Pin Number)

B1 V

IN

B2 V

IN

B3 V

IN

B4 V

IN

B5 V

IN

B6 V

IN

B7 - C7 - D7 - E7 PGND F7 PGND

SET

C1 V
C2 V
C3 V
C4 V
C5 V
C6 V

IN

IN

IN

IN

IN

IN

D1 PGND E1 PGND F1 PGND
D2 PGND E2 PGND F2 PGND
D3 PGND E3 PGND F3 PGND
D4 PGND E4 PGND F4 PGND
D5 PGND E5 PGND F5 PGND
D6 PGND E6 PGND F6 PGND

C12 MARG0 D12 MARG1 E12 DRV

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OSNS

+

K1 V

OUT

K2 V

OUT

K3 V

OUT

K4 V

OUT

K5 V

OUT

K6 V

OUT

K7 V

OUT

K8 V

OUT

K9 V

OUT

K10 V

OUT

OUT

K12 DIFFV

OUT

L1 V
L2 V
L3 V
L4 V
L5 V
L6 V
L7 V
L8 V
L9 V
L10 V
L11 V
L12 V

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT_LCL

F12 V

CC

M1 V
M2 V
M3 V
M4 V
M5 V
M6 V
M7 V
M8 V
M9 V
M10 V
M11 V
M12 V

FB

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OSNS

–

26

4601f

PACKAGE DESCRIPTIO

LTM4601/LTM4601-1

U

Pin Assignment Tables

(Arranged by Pin Function)

A1
A2
A3
A4
A5
A6

B1
B2
B3
B4
B5
B6

C1
C2
C3
C4
C5
C6

PIN NAME

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

V

IN

D1
D2
D3
D4
D5
D6

E1
E2
E3
E4
E5
E6
E7

F1
F2
F3
F4
F5
F6
F7
F8
F9

G1
G2
G3
G4
G5
G6
G7
G8
G9

H1
H2
H3
H4
H5
H6
H7
H8
H9

PIN NAME

PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND

J1
J2
J3
J4
J5
J6
J7
J8
J9
J10

K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11

L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11

M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11

PIN NAME

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

PIN NAME

A7
A8
A9
A10
A11
A12

B12 f

INTVCC
PLLIN
TRACK/SS
RUN
COMP
MPGM

SET

C12 MARG0

D12 MARG1

E12 DRV

F12 V

CC

FB

G12 PGOOD

H12 SGND

J12 V

OSNS

K12 DIFFV

L12 V

M12 V

OUT_LCL

OSNS

+

OUT

–

PIN NAME

B7
B8
B9
B10
B11

C7
C8
C9
C10
C11

D7
D8
D9
D10
D11

E8
E9
E10
E11

F10
F11

G10
G11

H10
H11

J11 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4601f

27

LTM4601/LTM4601-1

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC2923 Power Supply Tracking Controller Tracks Both Up and Down; Power Supply Sequencing

LT3825/LT3837 Synchronous Isolated Flyback Controllers No Optocoupler Required; 3.3V, 12A Output; Simple Design

LTM4600 10A DC/DC µModule Basic 10A DC/DC µModule

LTM4601 12A DC/DC µModule with PLL, Output Tracking/

Margining and Remote Sensing

LTM4602 6A DC/DC µModule Pin Compatible with the LTM4600

LTM4603 6A DC/DC µModule with PLL and Outpupt Tracking/

Margining and Remote Sensing

Synchronizable, PolyPhase Operation to 48A, LTM4601-1 Version has no
Remote Sensing

Synchronizable, PolyPhase Operation to 48A, LTM4601-1 Version has no
Remote Sensing, Pin Compatible with the LTM4601

28

This product contains technology licensed from Silicon Semiconductor Corporation.

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

®

4601f

LT 0107 • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2007