Voltage Monitor for Power Fail or
Low Battery Warning
■
Thermal Limiting
■
Performance Specified Over Temperature
■
Superior Upgrade for MAX690 Family
U
O
PPLICATI
A
■
Critical µP Power Monitoring
■
Intelligent Instruments
■
Battery-Powered Computers and Controllers
■
Automotive Systems
S
DUESCRIPTIO
The LTC692/LTC693 provide complete power supply monitoring and battery control functions for microprocessor
reset, battery backup, CMOS RAM write protection, power
failure warning and watchdog timing. A precise internal
voltage reference and comparator circuit monitor the
power supply line. When an out-of-tolerance condition
occurs, the reset outputs are forced to active states and the
Chip Enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed
to remain logic low even with VCC as low as 1V.
The LTC692/LTC693 power the active CMOS RAMs with a
charge pumped NMOS power switch to achieve low dropout and low supply current. When primary power is lost,
auxiliary power, connected to the battery input pin, powers
the RAMs in standby through an efficient PMOS switch.
For an early warning of impending power failure, the
LTC692/LTC963 provide an internal comparator with a
user-defined threshold. An internal watchdog timer is
also available, which forces the reset pins to active states
when the watchdog input is not toggled prior to a preset
time-out period.
O
A
PPLICATITYPICAL
≥ 7.5V
V
IN
+
10µF
51k
10k
MICROPROCESSOR RESET, BATTERY BACKUP, POWER FAILURE
WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR MICROPROCESSOR SYSTEMS.
LT1086-5
V
IN
ADJ
5V
V
OUT
+
100µF
U
0.1µF
3V
RESET Output Voltage vs
Supply Voltage
5
TA = 25°C
EXTERNAL PULL-UP = 10µA
= 0V
V
4
BATT
3
2
RESET OUTPUT VOLTAGE (V)
1
0
1
0
2
SUPPLY VOLTAGE (V)
3
4
5
LTC692/3 • TA02
µP
SYSTEM
µP
POWER
LTC692/3 • TA01
0.1µF
POWER TO
CMOS RAM
µP RESET
µP NMI
I/O LINE
100Ω
V
CC
V
BATT
PFI
LTC692
LTC693
GND
V
OUT
RESET
PFO
WDI
0.1µF
1
LTC692/LTC693
A
W
O
LUTEXI T
S
A
WUW
ARB
I
Terminal Voltage
VCC.................................................... –0.3V to 6.0V
V
................................................. –0.3V to 6.0V
PFO Short Circuit Source CurrentPFI = HIGH, PFO = 0V1325µA
(Note 4)PFI = LOW, PFO = V
PFI Comparator Response Time (falling)∆VIN = –20mV, VOD = 15mV2µs
PFI Comparator Response Time (rising)∆VIN = 20mV, VOD = 15mV40µs
(Note 4) with 10kΩ Pull-Up8µs
Chip Enable Gating
CE IN ThresholdV
CE IN Pullup Current (Note 7)3µA
CE OUT Output VoltageI
CE Propagation DelayVCC = 5V, CL = 20pF2035ns
CE OUT Output Short Circuit CurrentOutput Source Current30mA
Oscillator
OSC IN Input Current (Note 7)±2µA
OSC SEL Input Pull-Up Current (Note 7)5µA
OSC IN Frequency RangeOSC SEL = 0V●0250kHz
OSC IN Frequency with External CapacitorOSC SEL = 0V, C
= 2.8V, TA = 25°C, unless otherwise noted.
BATT
ICS
Logic High3.5V
OUT
WDI = 0V
= 3.2mA0.4V
SINK
= 1µA3.5V
I
SOURCE
OUT
IL
V
IH
= 3.2mA0.4V
SINK
= 3.0mAV
I
SOURCE
= 1µA, VCC = 0VV
I
SOURCE
Output Sink Current35mA
= 47pF4kHz
OSC
●450µA
●–50–8µA
25mA
0.8V
2.0V
– 1.50V
OUT
– 0.05V
OUT
●2045ns
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute maximum ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: For military temperature range, consult the factory.
Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pull-ups of typically 3µA. However, external
pull-up resistors may be used when higher speed is required.
4
Note 5: The LTC692/LTC693 have minimum reset active times of 140ms
(200ms typically). The reset active time of the LTC693 can be adjusted
(see Table 2 in Applications Information Section).
Note 6: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer (See BLOCK DIAGRAM).
Variation in the time-out period is caused by phase errors which occur
when the oscillator divides the external clock by 64. The resulting variation
in the time-out period is 64 clocks plus one clock of jitter.
Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.
LPER
TIME (µs)
0
4
5
6
4
LTC692/3 • TPC06
3
2
0
123
5
1
1.305V
1.285V
87
6
VCC = 5V
T
A
= 25°C
+
–
V
PFI
1.3V
PFO
30pF
V
PFI
= 20mV STEP
PFO OUTPUT VOLTAGE (V)
V
vs I
OUT
5.00
4.95
4.90
4.85
OUTPUT VOLTAGE (V)
4.80
OUT
SLOPE = 5Ω
F
O
R
VCC = 5V
V
BATT
= 25°C
T
A
ATYPICA
= 2.8V
UW
CCHARA TERIST
E
C
V
vs I
OUT
2.80
2.78
SLOPE = 125Ω
2.76
OUTPUT VOLTAGE (V)
2.74
OUT
ICS
VCC = 0V
V
BATT
= 25°C
T
A
= 2.8V
LTC692/LTC693
Power Failure Input Threshold
vs Temperature
1.308
VCC = 5V
1.306
1.304
1.302
1.300
1.298
PFI INPUT THRESHOLD (V)
1.296
4.75
232
224
216
208
200
RESET ACTIVE TIME
192
184
–50
10
0
20
LOAD CURRENT (mA)
Reset Active Time vs
Temperature
VCC = 5V
50100 125
–250
2575
TEMPERATURE (°C)
Power Fail Comparator
Response Time
6
VCC = 5V
5
T
A
4
3
2
1
PFO OUTPUT VOLTAGE (V)
0
1.315V
1.295V
0
30
= 25°C
40
LTC692/3 • TPC01
LTC692/3 • TPC04
V
PFI
40
20
50
V
PFI
1.3V
= 20mV STEP
60
10080
TIME (µs)
2.72
100
0
Reset Voltage Threshold
vs Temperature
4.41
4.40
4.39
4.38
4.37
RESET VOLTAGE THRESHOLD (V)
4.36
4.35
–50
–250
+
PFO
140
120
LTC692/3 • TPC07
30pF
180160
–
300
200
LOAD CURRENT (µA)
50100 125
2575
TEMPERATURE (°C)
1.315V
1.295V
1.294
400
LTC692/3 • TPC02
500
–50
–250
Power Fail Comparator
Response Time
LTC692/3 • TPC05
Power Fail Comparator Response
Time with Pull-Up Resistor
6
VCC = 5V
5
= 25°C
T
A
4
3
2
1
PFO OUTPUT VOLTAGE (V)
0
0
2
V
= 20mV STEP
PFI
4
V
PFI
1.3V
6
TIME (µs)
108
+
PFO
–
12
LTC692/3 • TPC08
2575
TEMPERATURE (°C)
5V
10k
30pF
14
1816
50100 125
LTC692/3 • TPC03
5
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