FEATURES
LTC6800
Rail-to-Rail
Input and Output,
Instrumentation Amplifier
U
DESCRIPTIO
■
116dB CMRR Independent of Gain
■
Maximum Offset Voltage: 100µV
■
Maximum Offset Voltage Drift: 250nV/°C
■
–40°C to 125°C Operation
■
Rail-to-Rail Input Range
■
Rail-to-Rail Output Swing
■
Supply Operation: 2.7V to 5.5V
■
Available in an MS8 and 3mm × 3mm × 0.8mm
DFN Packages
U
APPLICATIO S
■
Thermocouple Amplifiers
■
Electronic Scales
■
Medical Instrumentation
■
Strain Gauge Amplifiers
■
High Resolution Data Acquisition
U
TYPICAL APPLICATIO
The LTC®6800 is a precision instrumentation amplifier.
The CMRR is typically 116dB with a single 5V supply and
is independent of gain. The input offset voltage is guaranteed below 100µV with a temperature drift of less than
250nV/°C. The LTC6800 is easy to use; the gain is adjustable with two external resistors, like a traditional op amp.
The LTC6800 uses charge balanced sampled data techniques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift
operational amplifier.
The differential inputs operate from rail-to-rail and the
single ended output swings from rail-to-rail. The LTC6800
is available in an MS8 surface mount package. For space
limited applications, the LTC6800 is available in a
3mm × 3mm × 0.8mm dual fine pitch leadless package
(DFN).
, LTC and LT are registered trademarks of Linear Technology Corporation.
V
REGULATOR
High Side Power Supply Current Sense Typical Input Referred Offset vs
Input Common Mode Voltage (VS = 3V)
1.5mΩ
2
3
–
LTC6800
+
4
8
7
6
10k
5
0.1µF
150Ω
OUT
100mV/A
OF LOAD
CURRENT
I
LOAD
LOAD
6800 TA01
15
VS = 3V
= 0V
V
REF
10
= 25°C
T
A
5
(µV)
0
OS
V
–5
–10
–15
0
1 1.5 2
0.5
INPUT COMMON MODE VOLTAGE (V)
G = 1000
G = 100
G = 10
G = 1
2.5 3
6800 TA02
sn6800 6800fas
1
LTC6800
WW
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
Total Supply Voltage (V+ to V–) .............................. 5.5V
Input Current ...................................................... ±10mA
+
V
V
IN
IN
– V
–
– V
........................................................ 5.5V
REF
........................................................ 5.5V
REF
Output Short Circuit Duration .......................... Indefinite
UUW
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
LTC6800HMS8
TOP VIEW
NC
1
–IN
2
+IN
3
4
–
V
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
= 150°C, θJA = 200°C/W
JMAX
+
8
V
7
OUT
6
RG
5
REF
MS8 PART MARKING
LTADE
Operating Temperature Range
(Note 7) ................................................ – 40°C to 125°C
Storage Temperature Range
MS8 Package ................................... – 65°C to 150°C
DD Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)..................300°C
TOP VIEW
NC
1
–IN
2
+IN
3
–
V
4
8-LEAD (3mm × 3mm) PLASTIC DFN
DD PACKAGE
T
= 125°C, θJA = 160°C/W
JMAX
UNDERSIDE METAL INTERNALLY
CONNECTED TO V
(PCB CONNECTION OPTIONAL)
+
V
8
OUT
7
RG
6
REF
5
–
ORDER PART NUMBER
LTC6800HDD
DD PART MARKING
LAEP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, REF = 200mV. Output voltage swing is referenced
to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Offset Voltage (Note 2) VCM = 200mV ±100 µV
Average Input Offset Drift (Note 2) TA = –40°C to 85°C ● ±250 nV/°C
= 85°C to 125°C ● –1 –2.5 µV/°C
T
A
Common Mode Rejection Ratio AV = 1, VCM = 0V to 3V ● 85 113 dB
(Notes 4, 5)
Integrated Input Bias Current (Note 3) VCM = 1.2V 4 10 nA
Integrated Input Offset Current (Note 3) VCM = 1.2V 1 3 nA
Input Noise Voltage DC to 10Hz 2.5 µV
Power Supply Rejection Ratio (Note 6) VS = 2.7V to 5.5V ● 110 116 dB
Output Voltage Swing High RL = 2k to V
= 10k to V
R
L
Output Voltage Swing Low ● 20 mV
Gain Error AV = 1 0.1 %
Gain Nonlinearity AV = 1 100 ppm
–
–
● 2.85 2.94 V
● 2.95 2.98 V
P-P
2
sn6800 6800fas
LTC6800
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, REF = 200mV. Output voltage swing is referenced
to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Current No Load ● 1.2 mA
Internal Op Amp Gain Bandwidth 200 kHz
Slew Rate 0.2 V/µs
Internal Sampling Frequency 3kHz
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V,
V– = 0V, REF = 200mV. Output voltage swing is referenced to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Offset Voltage (Note 2) VCM = 200mV ±100 µV
Average Input Offset Drift (Note 2) TA = –40°C to 85°C ● ±250 nV/°C
= 85°C to 125°C ● –1 –2.5 µV/°C
T
A
Common Mode Rejection Ratio AV = 1, VCM = 0V to 5V ● 85 116 dB
(Notes 4, 5)
Integrated Input Bias Current (Note 3) VCM = 1.2V 4 10 nA
Integrated Input Offset Current (Note 3) VCM = 1.2V 1 3 nA
Power Supply Rejection Ratio (Note 6) VS = 2.7V to 5.5V ● 110 116 dB
Output Voltage Swing High RL = 2k to V
R
= 10k to V
L
Output Voltage Swing Low ● 20 mV
Gain Error AV = 1 0.1 %
Gain Nonlinearity AV = 1 100 ppm
Supply Current No Load ● 1.3 mA
Internal Op Amp Gain Bandwidth 200 kHz
Slew Rate 0.2 V/µs
Internal Sampling Frequency 3kHz
–
–
● 4.85 4.94 V
● 4.95 4.98 V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
systems. V
capability.
Note 3: If the total source resistance is less than 10k, no DC errors result
from the input bias currents or the mismatch of the input bias currents or
the mismatch of the resistances connected to –IN and +IN.
Note 4: The CMRR with a voltage gain, AV, larger than 10 is 120dB (typ).
Note 5: At temperatures above 70°C, the common mode rejection ratio
lowers when the common mode input voltage is within 100mV of the
supply rails.
is measured to a limit determined by test equipment
OS
Note 6: The power supply rejection ratio (PSRR) measurement accuracy
depends on the proximity of the power supply bypass capacitor to the
device under test. Because of this, the PSRR is 100% tested to relaxed
limits at final test. However, their values are guaranteed by design to meet
the data sheet limits.
Note 7: The LTC6800H is guaranteed functional over the operating
temperature range of –40°C to 125°C. Specifications over the –40°C to
125°C range (denoted by
but are not tested or QA sampled at these temperatures.
●) are assured by design and characterization
sn6800 6800fas
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LTC6800
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Input Offset Voltage
vs Input Common Mode Voltage
15
VS = 3V
= 0V
V
REF
= 25°C
T
10
A
5
0
–5
INPUT OFFSET VOLTAGE (µV)
–10
–15
0
1.0 1.5 2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
G = 1000
Input Offset Voltage
vs Input Common Mode Voltage
20
VS = 5V
= 0V
V
REF
15
G = 10
10
5
0
–5
–10
INPUT OFFSET VOLTAGE (µV)
–15
–20
0
TA = 25°C
TA = –55°C
234
1
INPUT COMMON MODE VOLTAGE (V)
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
60
VS = 3V
= 0V
V
REF
+
= R– = R
R
–20
–40
ADDITIONAL OFFSET ERROR (µV)
–60
40
20
0
0
CIN < 100pF
G = 10
T
SMALL C
S
= 25°C
A
R
S
IN
R
S
1.0 1.5 2.0
0.5
INPUT COMMON MODE VOLTAGE (V)
RS = 10k
+
–
RS = 5k
RS = 15k
RS = 20k
G = 10
2.5 3.0
TA = 70°C
2.5 3.0
G = 100
G = 1
6800 G01
6800 G04
RS = 0k
6800 G07
Input Offset Voltage
vs Input Common Mode Voltage
15
VS = 5V
= 0V
V
REF
= 25°C
T
10
A
G = 10
G = 1000
G = 100
G = 1
5
2053 G02
5
0
–5
INPUT OFFSET VOLTAGE (µV)
–10
–15
0
INPUT COMMON MODE VOLTAGE (V)
234
1
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
60
VS = 3V
V
= 0V
REF
G = 10
40
20
0
–20
INPUT OFFSET VOLTAGE (µV)
–40
5
–60
0
1.0 1.5 2.0 2.5 3.0
0.5
INPUT COMMON MODE VOLTAGE (V)
TA = 85°C
TA = 125°C
6800 G05
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
30
VS = 5V
= 0V
–10
–20
ADDITIONAL OFFSET ERROR (µV)
–30
V
REF
+
–
= R
= R
R
20
IN
CIN < 100pF
G = 10
10
= 25°C
T
A
0
SMALL C
0
INPUT COMMON MODE VOLTAGE (V)
S
IN
R
S
+
IN
R
1
–
S
234
RS = 20k
RS = 15k
RS = 10k
RS = 5k
5
6800 G08
Input Offset Voltage
vs Input Common Mode Voltage
20
VS = 3V
= 0V
V
REF
15
G = 10
10
5
0
–5
–10
INPUT OFFSET VOLTAGE (µV)
–15
–20
TA = 25°C
TA = –55°C
0
1.0 1.5 2.0 2.5 3.0
0.5
INPUT COMMON MODE VOLTAGE (V)
TA = 70°C
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
60
VS = 5V
V
= 0V
REF
G = 10
40
20
0
–20
INPUT OFFSET VOLTAGE (µV)
–40
–60
0
0
TA = 125°C
2345
1
INPUT COMMON MODE VOLTAGE (V)
Additional Input Offset Due to Input
RS Mismatch vs Input Common
Mode (CIN < 100pF)
50
VS = 3V
= 0V
V
40
REF
< 100pF
C
IN
30
G = 10
= 25°C
T
A
20
10
0
–10
–20
–30
SMALL C
ADDITIONAL OFFSET ERROR (µV)
–40
–50
0
R+ = 0k, R– = 5k
R+ = 5k, R– = 0k
R+ = 10k, R– = 0k
+
R
IN
–
R
0.5
INPUT COMMON MODE VOLTAGE (V)
R+ = 0k, R– = 15k
R+ = 0k, R– = 10k
+
–
R+ =15k, R– = 0k
1.0 1.5 2.0
sn6800 6800fas
6800 G03
TA = 85°C
6800 G06
2.5 3.0
6800 G09
4
UW
OUTPUT VOLTAGE (V)
–2.4
NONLINEARITY (ppm)
10
8
6
4
2
0
–2
–4
–6
–8
–10
–1.4
–0.4
6800 G18
0.6
1.6
2.6
VS = ±2.5V
V
REF
= 0V
G = 10
R
L
= 10k
T
A
= 25°C
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6800
Additional Input Offset Due to Input
RS Mismatch vs Input Common
Mode (CIN < 100pF)
40
VS = 5V
= 0V
V
REF
30
< 100pF
C
IN
G = 10
20
= 25°C
T
A
10
0
+
R
= 15k, R
SMALL C
0
IN
+
R
IN
–
R
1
–10
–20
ADDITIONAL OFFSET ERROR (µV)
–30
–40
INPUT COMMON MODE VOLTAGE (V)
+
R
= 0k, R
IN
IN
+
= 0k, R
= 0k
–
IN
–
= 10k
IN
–
= 0k
IN
–
= 0k
IN
R
R
+
IN
R
IN
R
IN
+
= 0k, R
IN
= 10k, R
–
IN
+
= 20k, R
+
–
234
–
= 20k
= 15k
5
6800 G10
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF) Offset Voltage vs Temperature
200
VS = 3V
= 0V
V
REF
150
100
–50
–100
ADDITIONAL OFFSET ERROR (µV)
–150
–200
= 25°C
T
A
G = 10
R
50
0
0
R+ = 0Ω, R– = 100Ω
+
R
= 100Ω, R– = 0Ω
R+ = 500Ω, R– = 0Ω
+
R
+
CINBIG
–
–
R
1.0 1.5 2.0 2.5 3.0
0.5
INPUT COMMON MODE VOLTAGE (V)
+
= 0Ω, R– = 1k
R
+
= 0Ω, R– = 500Ω
+
= 1k, R– = 0Ω
R
6800 G13
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
40
VS = 3V
V
= 0V
REF
30
+
R
= R– = R
= 25°C
A
S
20
10
CIN > 1µF
G = 10
T
0
–10
R
0
BIG C
S
IN
R
S
0.5
+
–
1.0 1.5 2.0
–20
ADDITIONAL OFFSET ERROR (µV)
–30
–40
INPUT COMMON MODE VOLTAGE (V)
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
200
VS = 5V
= 0V
V
REF
150
= 25°C
T
100
–50
–100
ADDITIONAL OFFSET ERROR (µV)
–150
–200
A
G = 10
50
0
R+ = 100Ω, R– = 0Ω
+
R
+
CINBIG
–
–
R
12 4
0
INPUT COMMON MODE VOLTAGE (V)
R+ = 0Ω, R– = 1k
+
R
= 0Ω, R– = 500Ω
R+ = 0Ω, R– = 100Ω
R+ = 500Ω, R– = 0Ω
R+ = 1k, R– = 0Ω
3
RS = 15k
RS = 10k
RS = 5k
2.5 3.0
6800 G11
6800 G14
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
70
50
30
10
–10
R
–30
ADDITIONAL OFFSET ERROR (µV)
–50
–70
0
BIG C
S
IN
R
S
1
INPUT COMMON MODE VOLTAGE (V)
80
60
40
20
0
VS = 3V
–20
–40
INPUT OFFSET VOLTAGE (µV)
–60
–80
5
–50
RS = 10k
RS = 5k
+
–
234
050–25 25 75 125
TEMPERATURE (°C)
RS = 1k
RS = 500Ω
VS = 5V
V
REF
+
= R– = R
R
CIN > 1µF
G = 10
= 25°C
T
A
VS = 5V
= 0V
S
5
6800 G12
100
6800 G15
30
20
10
(µV)
V
0
OS
–10
–20
–30
VOS vs V
+
V
= V
IN
G = 10
= 25°C
T
A
0
REF
= REF
IN–
VS = 3V
1
Gain Nonlinearity, G = 1 Gain Nonlinearity, G = 10
10
VS = ±2.5V
8
V
= 0V
REF
G = 1
6
R
= 10k
L
T
= 25°C
4
A
2
VS = 5V
2
V
REF
34
(V)
6800 G16
0
–2
–4
NONLINEARITY (ppm)
–6
–8
–10
–2.4
–1.4
–1.9 –0.9
OUTPUT VOLTAGE (V)
–0.4
0.1
0.6
1.1
1.6
6800 G17
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LTC6800
UW
TYPICAL PERFOR A CE CHARACTERISTICS
CMRR vs Frequency
120
VS = 3V, 5V
V
= 1V
IN
P-P
TA = 25°C
120
110
100
CMRR (db)
90
80
70
1
+
= 10k, R– = 0Ω
R
+
= 0Ω, R– = 10k
R
+
R
+
–
R
–
R+ = R– = 1k
10 100 1000
FREQUENCY (Hz)
Input Referred Noise in 10Hz
Bandwidth
3
VS = 5V
= 25°C
T
A
2
1
0
–1
–2
INPUT REFFERED NOISE VOLTAGE (µV)
–3
–5
–3 –1 1 3
TIME (s)
+
= R– = 10k
R
6800 G19
6800 G22
Input Voltage Noise Density
vs Frequency
300
G = 10
T
= 25°C
A
250
INPUT REFERRED NOISE DENSITY (nV/√Hz)
200
150
100
50
0
1
VS = 5V
VS = 3V
10 100 1000 10000
FREQUENCY (Hz)
6800 G20
Input Referred Noise in 10Hz
Bandwidth
3
VS = 3V
T
= 25°C
A
2
1
0
–1
–2
INPUT REFFERED NOISE VOLTAGE (µV)
–3
–3 –1 1 3
–5
TIME (s)
5
6800 G21
Output Voltage Swing
vs Output Current Supply Current vs Supply Voltage
5.0
T
= 25°C
A
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
OUTPUT VOLTAGE SWING (V)
0.5
5
0
0.01
VS = 5V, SOURCING
VS = 3V, SOURCING
VS = 3V, SINKING
VS = 5V, SINKING
0.1
OUTPUT CURRENT (mA)
110
6800 G23
1.00
0.95
0.90
0.85
0.80
0.75
SUPPLY CURRENT (mA)
0.70
0.65
0.60
TA = 85°C
TA = –55°C
2.5
SUPPLY VOLTAGE (V)
TA = 125°C
TA = 0°C
4.53.5
5.5 6
6800 G24
Low Gain Settling Time
vs Settling Accuracy
8
7
6
5
4
3
SETTLING TIME (ms)
2
1
0
0.0001
0.001
SETTLING ACCURACY (%)
6
0.01
VS = 5V
dV
OUT
G < 100
= 25°C
T
A
= 1V
6800 G25
0.1
Settling Time vs Gain
35
VS = 5V
= 1V
dV
OUT
30
0.1% ACCURACY
= 25°C
T
A
25
20
15
SETTLING TIME (ms)
10
5
0
1
10 100 1000 10000
GAIN (V/V)
6800 G26
Internal Clock Frequency
vs Supply Voltage
3.40
3.35
3.30
3.25
3.20
CLOCK FREQUENCY (kHz)
3.15
3.10
TA = 125°C
TA = 25°C
2.5
SUPPLY VOLTAGE (V)
TA = 85°C
TA = –55°C
4.5 5.5 63.5
6800 G27
sn6800 6800fas
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PI FU CTIO S
LTC6800
NC (Pin 1): Not Connected.
–IN (Pin 2): Inverting Input.
+IN (Pin 3): Noninverting Input.
V– (Pin 4): Negative Supply.
REF (Pin 5): Voltage Reference (V
W
BLOCK DIAGRA
) for Amplifier Output.
REF
+IN
3
–IN
2
C
RG (Pin 6): Inverting Input of Internal Op Amp. With a
resistor, R2, connected between the OUT pin and the RG
pin and a resistor, R1, between the RG pin and the REF pin,
the DC gain is given by 1 + R2 / R1.
OUT (Pin 7): Amplifier Output.
V
= GAIN (V
OUT
+IN
– V
–IN
) + V
REF
V+ (Pin 8): Positive Supply.
8
+
V
+
C
S
H
REF6RG
5
–
–
V
4
OUT
7
6800 BD
sn6800 6800fas
7
LTC6800
U
WUU
APPLICATIO S I FOR ATIO
Theory of Operation
The LTC6800 uses an internal capacitor (CS) to sample a
differential input signal riding on a DC common mode
voltage (see Block Diagram). This capacitor’s charge is
transferred to a second internal hold capacitor (CH) translating the common mode of the input differential signal to
that of the REF pin. The resulting signal is amplified by a
zero-drift op amp in the noninverting configuration. The
RG pin is the negative input of this op amp and allows
external programmability of the DC gain. Simple filtering
can be realized by using an external capacitor across the
feedback resistor.
Input Voltage Range
The input common mode voltage range of the LTC6800 is
rail-to-rail. However, the following equation limits the size
of the differential input voltage:
V– ≤ (V
+IN
– V
–IN
) + V
≤ V+ – 1.3
REF
where V
pins respectively, V
+IN
and V
are the voltages of the +IN and –IN
–IN
is the voltage at the REF pin and V
REF
+
is the positive supply voltage.
For example, with a 3V single supply and a 0V to 100mV
differential input voltage, V
must be between 0V and
REF
1.6V.
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage
VIN is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to N
bits of accuracy at the op amp noninverting input after N
clock cycles or 333µs(N). The settling time at the OUT pin
is also affected by the settling of the internal op amp.
Since the gain bandwidth of the internal op amp is
typically 200kHz, the settling time is dominated by the
switched capacitor front end for gains below 100 (see
Typical Performance Characteristics).
SINGLE SUPPLY, UNITY GAIN
5V
8
3
+
V
D
–
+
2
–
4
0V < V
0V < V
0V < V
V
OUT
Figure 1
= V
+IN
–IN
D
5
6800 F01
< 5V
< 5V
< 3.7V
D
V
+IN
V
–IN
7
6
8
sn6800 6800fas
LTC6800
U
WUU
APPLICATIO S I FOR ATIO
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results in
an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the –IN pin every cycle. The resulting input
charging current decays exponentially during each input
sampling period with a time constant equal to RSCS. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors
due to source resistance or the source resistance mismatch between –IN and +IN. With RS less than 10k, no
DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from nonzero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is less
sensitive to source resistance and source resistance mismatch. When large capacitors are placed across the inputs, the input charging currents described above result in
larger DC errors, especially with source resistor mismatches.
Power Supply Bypassing
The LTC6800 uses a sampled data technique and therefore
contains some clocked digital circuitry. It is therefore sensitive to supply bypassing. A 0.1µF ceramic capacitor must
be connected between Pin␣ 8 (V+) and Pin 4 (V–) with leads
as short as possible.
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9
LTC6800
TYPICAL APPLICATIO S
U
Precision ÷2
5V
0.1µF
V
IN
0.1µF
3
2
+
LTC6800
–
1k
8
7
V
6
5
4
6800 TA03
OUT
V
IN
V
=
OUT
2
Precision Doubler (General Purpose)
2.5V
0.1µF
V
IN
3
2
0.1µF
+
LTC6800
–
–2.5V
4
8
5
0.1µF
7
V
V
OUT
6800 TA04
= 2V
OUT
IN
6
10
Precision Inversion (General Purpose)
2.5V
0.1µF
3
2
V
IN
+
LTC6800
–
–2.5V
4
8
5
0.1µF
7
V
V
OUT
6800 TA05
= –V
OUT
IN
6
sn6800 6800fas
U
PACKAGE DESCRIPTIO
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
DETAIL “A”
0.254
(.010)
GAUGE PLANE
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
° – 6° TYP
0
DETAIL “A”
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
(.043)
0.22 – 0.38
(.009 – .015)
TYP
1.10
MAX
0.65
(.0256)
BSC
MS8 Package
3.00 ± 0.102
0.86
(.034)
REF
0.127 ± 0.076
(.005 ± .003)
(.118 ± .004)
4.90
(.193 ± .006)
(NOTE 3)
± 0.152
8
7
12
LTC6800
0.52
(.0205)
6
5
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4
3
5.23
(.206)
MIN
0.42 ± 0.038
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.889
(.035 ± .005)
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
MSOP (MS8) 0603
± 0.127
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
TYP
3.00 ±0.10
PIN 1
TOP MARK
0.200 REF
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
(4 SIDES)
0.75 ±0.05
1.65 ± 0.10
(2 SIDES)
0.00 – 0.05
0.28 ± 0.05
BOTTOM VIEW—EXPOSED PAD
DD Package
85
14
2.38 ±0.10
(2 SIDES)
0.50 BSC
0.38 ± 0.10
3.5 ±0.05
0.675 ±0.05
1.65 ±0.05
(2 SIDES)2.15 ±0.05
PACKAGE
OUTLINE
0.28 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
2.38 ±0.05
(2 SIDES)
0.50
BSC
(DD8) DFN 0203
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
sn6800 6800fas
11
LTC6800
TYPICAL APPLICATIO
U
Differential Bridge Amplifier
3V
0.1µF
R < 10k
2
3
8
–
LTC6800
+
4
7
6
R2 10k
5
OUT
0.1µF
R1
10Ω
6800 TA06
GAIN = 1 +
R2
R1
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12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
sn6800 6800fas
LT/TP 0903 1K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORAT ION 2002
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