LTC6084/LTC6085
Dual/Quad 1.5MHz,
Rail-to-Rail, CMOS
Amplifi ers
FEATURES
n
Low Offset Voltage: 750μV Maximum
n
Low Offset Drift: 5μV/°C Maximum
n
Low Input Bias Current:
1pA (Typical at 25°C)
40pA (≤85°C)
n
Rail-to-Rail Inputs and Outputs
n
2.5V to 5.5V Operation Voltage
n
Gain Bandwidth Product: 1.5MHz
n
CMRR: 70dB Minimum
n
PSRR: 94dB Minimum
n
Supply Current: 110µA per Amplifi er
n
Shutdown Current: 1.1µA per Amplifi er
n
Available in 8-Lead MSOP and 10-Lead DFN
Packages (LTC6084) and 16-Lead SSOP and DFN
Packages (LTC6085)
APPLICATIONS
n
Portable Test Equipment
n
Medical Equipment
n
Consumer Electronics
n
Data Acquisition
DESCRIPTION
The LTC®6084/LTC6085 are dual/quad, low cost, low offset,
rail-to-rail input/output, unity-gain stable CMOS operational
amplifi ers that feature 1pA of input bias current.
A 1.5MHz gain bandwidth, and 0.5V/s slew rate, along
with the wide supply range and a low 0.75mV offset, make
the LTC6084/LTC6085 useful in an extensive variety of applications from data acquisition to medical equipment and
consumer electronics. The 110A supply current and the
shutdown mode are ideal for signal processing applications
which demand performance with minimal power.
The LTC6084/LTC6085 have an output stage which swings
within 5mV of either supply rail to maximize signal dynamic
range in low supply applications. The input common
mode range includes the entire supply voltage. These op
amps are specifi ed on power supply voltages of 2.5V and
5V from –40°C to 125°C. The dual amplifi er LTC6084 is
available in 8-lead MSOP and 10-lead DFN packages. The
quad amplifi er LTC6085 is available in 16-lead SSOP and
DFN packages.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Shock Sensor Amplifi er
20M
20M
2k *
100k
3V
100k
*SHOCK SENSOR MURATA ERIE PKGS-OOMX1
www.murata.com
0.22µF
470pF
–
LTC6084
+
7Hz TO 5kHz
3V
1/2
200k
V
60845 TA01
= 120mV/g
OUT
Input Bias Current
vs Common Mode Voltage
10000
VS = 5V
1000
100
10
1
INPUT BIAS CURRENT (pA)
0.1
0.01
0 0.5 1 4.5 541.5 2 2.5 3 3.5
COMMON MODE VOLTAGE (V)
TA = 125°C
TA = 85°CTA = 85°C
TA = 25°C
60845 TA01b
60845fa
1
LTC6084/LTC6085
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Total Supply Voltage (V+ to V–) ...................................6V
–
Input Voltage ......................................................V
to V
Input Current ........................................................±10mA
–
SHDNA/SHDNB Voltage .....................................V
to V
Output Short-Circuit Duration (Note 2) ............ Indefi nite
Operating Temperature Range (Note 3)
LTC6084C/LTC6085C ...........................–40°C to 85°C
LTC6084H/LTC6085H .........................–40°C to 125°C
PIN CONFIGURATION
TOP VIEW
OUTA
1
–INA
+INA
–
2
+
A
3
–
V
4
MS8 PACKAGE
8-LEAD PLASTIC MSOP
T
= 150°C, θJA = 200°C/W
JMAX
+
8
V
7
OUTB
–
6
–INB
+
B
5
+INB
Specifi ed Temperature Range (Note 4)
+
LTC6084C/LTC6085C ...............................0°C to 70°C
LTC6084H/LTC6085H ........................... –40°C to 125°
+
Junction Temperature ........................................... 150°C
Storage Temperature Range ...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
MS8, GN Only ................................................... 300°C
TOP VIEW
+
10
OUTA
1
–INA
+INA
SHDNA
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 11) IS V
–
2
+
A
3
–
4
V
5
DD PACKAGE
T
= 150°C, θJA = 43°C/W
JMAX
11
–
, MUST BE SOLDERED TO PCB
V
OUTB
9
–
–INB
8
+
B
7
+INB
6
SHDNB
TOP VIEW
1
OUTA
–
2
–INA
+INA
V
+INB
–INB
OUTB
NC
16-LEAD PLASTIC SSOP NARROW
+
A
3
+
4
5
+
BC
–
6
7
8
GN PACKAGE
T
= 150°C, θJA = 110°C/W
JMAX
16
–
15
+
D
14
13
12
+
–
11
10
9
OUTD
–IND
+IND
–
V
+INC
–INC
OUTC
NC
OUTA
–INA
+INA
+INB
–INB
OUTB
NC
16-LEAD (5mm × 3mm) PLASTIC DFN
EXPOSED PAD (PIN 17) IS V
TOP VIEW
1
–
2
+
A
3
+
4
V
5
+
BC
–
6
7
8
DHC PACKAGE
T
= 150°C, θJA = 43°C/W
JMAX
16
OUTD
–
15
–IND
+
D
14
+IND
–
13
17
–
, MUST BE SOLDERED TO PCB
V
12
+INC
+
–
11
–INC
10
OUTC
9
NC
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6084CMS8#PBF LTC6084CMS8#TRPBF LTDNG 8-Lead Plastic MSOP 0°C to 70°C
LTC6084HMS8#PBF LTC6084HMS8#TRPBF LTDNG 8-Lead Plastic MSOP –40°C to 125°C
LTC6084CDD#PBF LTC6084CDD#TRPBF LDNH
LTC6084HDD#PBF LTC6084HDD#TRPBF LDNH
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
–40°C to 125°C
2
60845fa
LTC6084/LTC6085
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LTC6085CGN#PBF LTC6085CGN#TRPBF 6085 16-Lead Plastic SSOP 0°C to 70°C
LTC6085HGN#PBF LTC6085HGN#TRPBF 6085 16-Lead Plastic SSOP –40°C to 125°C
LTC6085CDHC#PBF LTC6085CDHC#TRPBF 6085
LTC6085HDHC#PBF LTC6085HDHC#TRPBF 6085
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. Test conditions are V+ = 2.5V, V– = 0V, VCM = 0.5V unless otherwise noted.
C SUFFIX H SUFFIX
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
ΔV
I
OS
OS
B
Offset Voltage (Note 5) LTC6084MS8, LTC6085GN
Input Offset Voltage Drift
/ΔT
(Note 6)
Input Bias Current
(Notes 5, 7)
I
OS
Input Offset Current
(Notes 5, 7)
e
n
Input Noise Voltage
Density
Input Noise Voltage 0.1Hz to 10Hz 3 3 µV
i
n
Input Noise Current
Density (Note 8)
Input Common Mode
Range
C
IN
Input Capacitance
Differential Mode
Common Mode
CMRR Common Mode Rejection
Ratio
PSRR Power Supply Rejection
Ratio
V
A
OUT
VOL
Output Voltage, High,
(Referred to V
Output Voltage, Low,
(Referred to V
+
)
–
)
Large-Signal Voltage Gain R
LTC6084DD, LTC6085DHC
LTC6084MS8, LTC6085GN
LTC6084DD, LTC6085DHC
Guaranteed by 5V Test
Guaranteed by 5V Test
f = 1kHz
f = 10kHz
f = 100kHz
0 ≤ V
≤ 2.5V
CM
VS = 2.5V to 5.5V
No Load
I
= 1mA
SOURCE
I
= 5mA
SOURCE
No Load
I
= 1mA
SINK
I
= 5mA
SINK
= 10k, 0.4V ≤ V
LOAD
OUT
≤ 2.1V
l
l
l
l
l
l
V
64
l
63
94
l
91
l
l
l
l
l
l
400
l
200
300
300
750
1100
900
1350
25 25
1
40
0.5
30
31
27
0.56 0.56 fA/√Hz
–
+
V
5
9
80 64
115 94
0.5
39
220
0.5
36
200
5
85
460
5
85
460
2000 400
0°C to 70°C
–40°C to 125°C
300
300
1
0.5
31
27
–
V
5
9
80 dB
61
115 dB
89
0.5
39
220
0.5
36
200
2000 V/mV
150
750
1100
1100
1600
750
150
+
V
10
100
10
100
µV
µV
µV
µV
µV/°C
pA
pA
pA
pA
nV/√Hz
nV/√Hz
P-P
pF
pF
dB
dB
mV
mV
mV
mV
mV
mV
V/mV
V
60845fa
3
LTC6084/LTC6085
The l denotes the specifi cations which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
I
SC
Output Short-Circuit
Current
SR Slew Rate AV = 1 0.5 0.5 V/µs
GBW Gain Bandwidth Product
(f
= 10kHz)
TEST
Φ
0
t
S
I
S
Phase Margin RL = 10k, CL = 150pF, AV = 1 45 45 Deg
Settling Time 0.1% V
Supply Current
(Per Amplifi er)
Shutdown Current
(Per Amplifi er)
V
S
Supply Voltage Range Guaranteed by the PSRR Test
Channel Separation f
Shutdown Logic SHDNx High
t
t
ON
OFF
Turn On Time V
Turn Off Time V
Leakage of SHDN Pin V
Source and Sink
= 50k, VCM = 1.25V
R
LOAD
= 1V, AV = 1 6 6 µs
STEP
No Load
Shutdown, V
= 10kHz –120 –120 dB
S
SHDNx Low
= 0.5V to 1.8V 7 7 µs
SHDNx
= 1.8V to 0.5V 1 1 µs
SHDNx
= 0V
SHDNx
= 25°C. Test conditions are V+ = 2.5V, V– = 0V, VCM = 0.5V unless otherwise noted.
A
C SUFFIX H SUFFIX
SHDNx
≤ 0.5V
7.7
l
6
0.9
l
0.7
l
l
l
2.5 5.5 2.5 5.5 V
1.8
12.5 7.7
12.5 mA
4.5
1.5 0.9
1.5 MHz
0.6
110 130
110 130
140
0.2 0.3 0.2 0.5 µA
1.8
0.5
l
0.2 0.3 0.2 0.5 µA
145
0.5
mA
µA
µA
V
V
The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. Test
conditions are V+ = 5V, V– = 0V, VCM = 0.5V unless otherwise noted.
C SUFFIX H SUFFIX
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V
ΔV
I
I
e
i
C
B
OS
n
OS
Offset Voltage (Note 5) LTC6084MS8, LTC6085GN
LTC6084DD, LTC6085DHC
l
l
l
OS
Input Offset Voltage Drift
/ΔT
(Note 6)
LTC6084MS8, LTC6085GN
LTC6084DD, LTC6085DHC
Input Bias Current
(Notes 5, 7)
l
Input Offset Current
(Notes 5, 7)
n
Input Noise Voltage
Density
f = 1kHz
f = 10kHz
l
Input Noise Voltage 0.1Hz to 10Hz 3 3 µV
Input Noise Current
Density (Note 8)
Input Common Mode
l
V
Range
IN
Input Capacitance
f = 100kHz
Differential Mode
Common Mode
300
300
750
1100
300
300
900
1350
25 25
1
1
40
0.5
0.5
30
31
27
31
27
0.56 0.56 fA/√Hz
–
5
9
+
V
–
V
5
9
750
1100
1100
1600
750
150
+
V
µV
µV
µV
µV
µV/°C
pA
pA
pA
pA
nV/√Hz
nV/√Hz
P-P
pF
pF
V
4
60845fa
LTC6084/LTC6085
The l denotes the specifi cations which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
CMRR Common Mode Rejection
Ratio
PSRR Power Supply Rejection
Ratio
V
A
I
OUT
VOL
SC
Output Voltage, High,
(Referred to V
Output Voltage, Low,
(Referred to V
+
)
–
)
Large-Signal Voltage Gain R
Output Short-Circuit
Current
SR Slew Rate AV = 1 0.5 0.5 V/µs
GBW Gain Bandwidth Product
(f
= 10kHz)
TEST
Φ
0
t
S
I
S
Phase Margin RL = 10k, CL = 150pF, AV = 1 45 45 Deg
Settling Time 0.1% V
Supply Current
(Per Amplifi er)
Shutdown Current
(Per Amplifi er)
V
S
Supply Voltage Range Guaranteed by the PSRR Test
Channel Separation f
Shutdown Logic SHDNx High
t
t
ON
OFF
Turn On Time V
Turn Off Time V
Leakage of SHDN Pin V
≤ 5V
0 ≤ V
CM
VS = 2.5V to 5.5V
No Load
I
= 1mA
SOURCE
I
= 5mA
SOURCE
No Load
I
= 1mA
SINK
I
= 5mA
SINK
= 10k, 0.5V ≤ V
LOAD
Source and Sink
= 50k, VCM = 2.5V
R
LOAD
= 1V, AV = 1 5 5 µs
STEP
No Load
Shutdown, V
= 10kHz –120 –120 dB
S
SHDNx Low
= 1.2V to 3.5V 7 7 µs
SHDNx
= 3.5V to 1.2V 1 1 µs
SHDNx
= 0V
SHDNx
= 25°C. Test conditions are V+ = 5V, V– = 0V, VCM = 0.5V unless otherwise noted.
A
C SUFFIX H SUFFIX
SHDNx
OUT
≤ 1.2V
≤ 4.5V
70
l
68
94
l
91
l
l
l
l
l
l
1000
l
400
7.7
l
6
0.9
l
0.7
l
l
l
2.5 5.5 2.5 5.5 V
3.5
84 70
84 dB
66
115 94
115 dB
89
0.5
39
220
0.5
36
200
5000 1000
5
85
460
5
85
460
0.5
39
220
0.5
36
200
5000 V/mV
300
12.5 7.7
12.5 mA
4.5
1.5 0.9
1.5 MHz
0.6
110 130
110 130
140
1.1 1.8 1.1 2 µA
3.5
1.2
l
0.5 0.9 0.5 1.2 µA
10
100
10
100
145
1.2
dB
dB
mV
mV
mV
mV
mV
mV
V/mV
mA
µA
µA
V
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum. This depends on the power supply voltage
and the total output current.
Note 3: The LTC6084C/LTC6085C are guaranteed functional over the
operating temperature range of –40°C to 85°C. The LTC6084H/LTC6085H
are guaranteed functional over the operating temperature range of –40°C
to 125°C.
Note 4: The LTC6084C/LTC6085C are guaranteed to meet specifi ed
performance from 0°C to 70°C. The LTC6084C/LTC6085C are designed,
characterized and expected to meet specifi ed performance from –40°C
to 85°C but are not tested or QA sampled at these temperatures. The
LTC6084H/LTC6085H are guaranteed to meet specifi ed performance from
–40°C to 125°C.
Note 5: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6084/LTC6085; however,
high electrostatic discharge can damage or degrade the device. Use proper
ESD handling precautions.
Note 6: This parameter is not 100% tested.
Note 7: This specifi cation is limited by high speed automated test
capability. See Typical Performance Characteristic curves for actual
performance.
Note 8: Current noise is calculated from i
= √2qIB, where q = 1.6 • 10
n
–19
coulombs.
60845fa
5
LTC6084/LTC6085
TYPICAL PERFORMANCE CHARACTERISTICS
VOS Distribution VOS vs V
20
LTC6084 MS8
18
= 5V
V
S
= 0.5V
V
CM
16
= 25°C
T
A
100 UNITS
14
12
10
8
6
PERCENTAGE OF UNITS (%)
4
2
0
–1
–0.4 0.4–0.8 0 0.8
VOS (mV)
1–0.6 0.2–0.2 0.6
60845 G01
(mV)
OS
V
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
0.0
Input Bias vs Temperature
1000
VS = 5V
= 2.5V
V
CM
100
10
INPUT BIAS CURRENT (pA)
1
25 115 13010085705540
TEMPERATURE (°C)
60845 G04
10000
1000
100
10
INPUT BIAS CURRENT (pA)
0.1
0.01
CM
VS = 5V
= 25°C
T
A
REPRESENTATIVE PARTS
0
1.5 3.50.5 2.5 4.5
VCM (V)
51324
60845 G02
VOS Drift Distribution
30
28
26
24
22
20
18
16
14
12
10
8
PERCENT OF UNITS (%)
6
4
2
0
–1
0.5 2.5–0.5 1.5 3.5
DISTRIBUTION (µV/°C)
LTC6084 MS8
V
CM
= –40°C TO 125°C
T
A
78 UNITS
V
= 2.5V
Input Bias Current
vs Common Mode Voltage Input Noise Voltage vs Frequency
VS = 5V
TA = 125°C
TA = 85°CTA = 85°C
TA = 25°C
1
0 0.5 1 4.5 541.5 2 2.5 3 3.5
COMMON MODE VOLTAGE (V)
60845 G05
100
90
80
70
60
50
40
30
20
INPUT NOISE VOLTAGE (nV/√Hz)
10
0
10 10k 100k1k100
FREQUENCY (Hz)
V
CM
T
VS = 5V
= 2.5V
= 25°C
A
= 5V
S
4.502134
60845 G03
60845 G06
0.1Hz to 10Hz Output Voltage
Noise Input Noise Current vs Frequency
600
500
400
300
200
NOISE CURRENT (fA/√Hz)
100
0
1 10 10k 100k1k100
FREQUENCY (Hz)
INPUT NOISE VOLTAGE (2µV/DIV)
VS = 5V
= 2.5V
V
CM
TIME (1s/DIV)
60845 G07
6
60845 G08
Output Saturation Voltage
vs Load Current (Output High)
5.0
VS = 5V
4.5
= 2.5V
V
CM
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
OUTPUT HIGH SATURATION VOLTAGE (V)
0.0
TA = –55°C
= 25°C
T
A
= 125°C
T
A
0.1 10 1001
LOAD CURRENT (mA)
SOURCE
SINK
60845 G09
60845fa
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage Supply Current vs Temperature
140
120
100
80
60
40
SUPPLY CURRENT (µA)
20
0
0
PER AMPLIFIER
1.5 3.50.5 2.5 4.5
TOTAL SUPPLY VOLTAGE (V)
V
CM
T
= 25°C
A
= 0.5V
51324
60845 G10
140
PER AMPLIFIER
V
130
120
110
SUPPLY CURRENT (µA)
100
90
–55
LTC6084/LTC6085
= 0.5V
CM
VS = 5V
VS = 2.5V
–10 50–40 20 110
TEMPERATURE (°C)
125–25 355658095
60845 G11
Open-Loop Gain vs Frequency
100
90
80
70
60
50
40
30
20
GAIN (dB)
10
0
–10
–20
–30
–40
1k 1M 10M100k10k
VS = 5V
= 2.5V
V
S
PHASE
GAIN
FREQUENCY (Hz)
Output Impedance vs Frequency
10000
VS = 5V
= 2.5V
V
CM
1000
= 25°C
T
A
100
10
1
0.1
OUTPUT IMPEDANCE (Ω)
0.01
0.001
100 1k 1M 10M 100M100k10k
AV = 10
AV = 1
FREQUENCY (Hz)
AV = 2
CL = 5pF
R
V
CM
T
A
= 10k
L
= VS/2
= 25°C
60845 G12
60845 G15
CMRR vs Frequency
120
100
110
80
100
60
40
20
0
–20
–40
90
80
PHASE (DEG)
70
60
50
CMRR (dB)
40
30
20
10
0
–10
1k 1M 10M100k10k
Disabled Output Impedance
vs Frequency
1000
100
10
1
OUTPUT IMPEDANCE (kΩ)
0.1
100 1k 1M 10M100k10k
FREQUENCY (Hz)
FREQUENCY (Hz)
VS = 5V
V
CM
T
A
VS = 5V
V
CM
A
V
T
A
= 2.5V
= 1k
R
L
= 25°C
60845 G13
= 1V
= 1
= 25°C
60845 G16
PSRR vs Frequency
100
90
80
70
60
50
40
PSRR (dB)
30
20
10
0
–10
100 1k 1M 10M100k10k
FREQUENCY (Hz)
Capacitive Load Handling
40
VS = 5V
= 2.5V
V
CM
35
= 1
A
V
30
–
25
+
20
15
OVERSHOOT (%)
10
5
0
10 100 1000
CAPACITIVE LOAD (pF)
RS = 10Ω
R
S
RS = 50Ω
C
L
V
VS = 5V
CM
T
A
= 2.5V
= 25°C
60845 G14
60845 G17
60845fa
7
LTC6084/LTC6085
TYPICAL PERFORMANCE CHARACTERISTICS
Capacitive Load Handling Channel Separation vs Frequency
50
VS = 5V
45
= 2.5V
V
CM
= –1
A
V
40
35
30
25
20
OVERSHOOT (%)
15
10
5
0
10 100 1000 10000
RS = 10Ω
RS = 50Ω
1k
–
1k
+
CAPACITIVE LOAD (pF)
R
S
C
L
60845 G18
–90
–95
–100
–105
–110
–115
–120
–125
CHANNEL SEPARATION (dB)
–130
–135
0.001 1 100.10.01
VS = 5V
= 2.5V
V
CM
= 25°C
T
A
FREQUENCY (MHz)
60845 G19
Total Harmonic Distortion and
Noise vs Frequency
1
VS = 3V
= 1.5V
V
CM
= 10k
R
L
0.1
AV = –2, VIN = 1V
AV = 2, VIN = 1V
0.01
THD AND NOISE (%)
AV = 1, VIN = 2V
0.001
0.01 10 10010.1
P-P
P-P
FREQUENCY (kHz)
P-P
AV = 1,
= 1V
V
IN
P-P
60845 G20
Total Harmonic Distortion and
Noise vs Frequency
1
VS = 5V
= 2.5V
V
CM
= 10k
R
L
0.1
AV = 2, VIN = 1V
0.01
AV = –2, VIN = 1V
THD AND NOISE (%)
0.001
AV = 1, VIN = 2V
0.0001
0.01 10 10010.1
P-P
P-P
FREQUENCY (kHz)
Small Signal Response Small Signal Response Large Signal Response
100mV/DIV
P-P
AV = 1, VIN = 1V
P-P
60845 G21
Total Harmonic Distortion and
Noise vs Output Voltage
10
RL = 10k
= VS/2
V
CM
= 1
A
V
1
VS= 3V AT 20kHz
0.1
0.01
THD AND NOISE (%)
0.001
0.0001
010.5 1.5 2.5 3.5 4.54532
100mV/DIV
VS= 3V AT 1kHz
OUTPUT VOLTAGE (V
VS= 5V AT 20kHz
VS= 5V AT 1kHz
)
P-P
60845 G22
Total Harmonic Distortion and
Noise vs Load Resistance
0.1
0.01
0.001
THD AND NOISE (%)
0.0001
0.1 10 1001
LOAD RESISTANCE TO GROUND (kΩ)
1V/DIV
= VS/2 AT 1kHz
V
CM
VS = 3V, VIN = 1V
VS = 5V, VIN = 2V
AV = 1
P-P
P-P
60845 G23
8
VS = 5V
= 1
A
V
= ∞
R
L
2µs/DIV
60845 G24
VS = 5V
= 1
A
V
= ∞
R
L
= 220pF
C
L
2µs/DIV
60845 G25
VS = 5V
= 1
A
V
= ∞
R
L
20µs/DIV
60845 G26
60845fa
LTC6084/LTC6085
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Response Large Signal Response Large Signal Response
1V/DIV
VS = 5V
= –1
A
V
= 1k
R
L
20µs/DIV
60845 G27
1V/DIV
VS = 5V
= 1
A
V
= ∞
R
L
PIN FUNCTIONS
OUT: Amplifi er Output.
–IN: Inverting Input.
+IN: Noninverting Input.
+
: Positive Supply.
V
–
: Negative Supply.
V
SHDNA: Shutdown Pin of Amplifi er A, active low and only
available with the LTC6084DD. An internal current source
pulls the pin to V
+
when fl oating.
1V/DIV
20µs/DIV
60845 G28
VS = 5V
= –1
A
V
= 1k
R
L
20µs/DIV
60845 G29
SHDNB: Shutdown Pin of Amplifi er B, active low and only
available with the LTC6084DD. An internal current source
+
pulls the pin to V
when fl oating.
NC: Not Internally Connected.
–
Exposed Pad: Connected to V
.
60845fa
9
LTC6084/LTC6085
APPLICATIONS INFORMATION
NO SOLDER MASK
OVER THE GUARD RING
LEAKAGE
CURRENT
NO LEAKAGE
R
CURRENT
GUARD
RING
OUT
LTC6084
–
IN
+
IN
–
V
60845 F01
OUT
R
R
V
IN
GND
–
IN
+
IN
–
V
LTC6084
60845 F02
Figure 1. Sample Layout. Unity-Gain Confi guration. Using Guard
Ring to Shield High Impedance Input from Board Leakage
Rail-to-Rail Input
The input stage of LTC6084/LTC6085 combines both PMOS
and NMOS differential pairs, extending its input common
mode voltage to both positive and negative supply voltages. At high input common mode range, NMOS pair is
on. At low common mode range, the PMOS pair is on. The
transition happens when the common voltage is between
1.3 and 0.9V below the positive supply.
Achieving Low Input Bias Current
The DD and DHC packages are leadless and make contact
to the PCB beneath the package. Solder fl ux used during
the attachment of the part to the PCB can create leakage
current paths and can degrade the input bias current performance of the part. All inputs are susceptible because
–
the backside paddle is connected to V
–
input voltage or V
changes, a leakage path can be formed
internally. As the
and alter the observed input bias current. For lowest bias
current use the LTC6084/LTC6085 in the leaded MSOP/GN
package. With fi ne PCB design rules, you can also provide
a guard ring around the inputs.
Figure 2. Sample Layout. Inverting Gain Confi guration. Using
Guard Ring to Shield High Impedance Input from Board Leakage
than the bias current of the operational amplifi er. A guard
ring around the high impedance input traces driven by a
low impedance source equal to the input voltage prevents
such leakage problems. The guard ring should extend
as far as necessary to shield the high impedance signal
from any and all leakage paths. Figure 1 shows the use
of a guard ring in a unity-gain confi guration. In this case
the guard ring is connected to the output and is shielding
–
the high impedance noninverting input from V
. Figure 2
shows the inverting gain confi guration.
Rail-to-Rail Output
The output stage of the LTC6084/LTC6085 swings within
5mV of the supply rails when driving high impedance
loads, in other words when no DC load current is present.
See the Typical Performance Characteristics for curves of
output swing versus load current. The class AB design of
the output stage enables the op amp to supply load currents which are much greater than the quiescent supply
current. For example, the room temperature short-circuit
current is typically 12.5mA.
For example, in high source impedance applications such as
pH probes, photo diodes, strain gauges, etc., the low input
bias current of these parts requires a clean board layout to
minimize additional leakage current into a high impedance
signal node. A mere 100G of PC board resistance between
a 5V supply trace and input trace near ground potential
adds 50pA of leakage current. This leakage is far greater
10
Capacitive Load
LTC6084/LTC6085 can drive a capacitive load up to 300pF in
unity gain. The capacitive load driving capability increases
as the amplifi er is used in higher gain confi gurations. A
small series resistance between the output and the load
further increases the amount of capacitance the amplifi er
can drive.
60845fa
APPLICATIONS INFORMATION
LTC6084/LTC6085
SHDN Pins
Pins 5 and 6 are used for power shutdown of the LTC6084
in the DD package. If they are fl oating, internal current
+
sources pull pins 5 and 6 to V
and the amplifi ers operate
normally. In shutdown the amplifi er output is high impedance, and each amplifi er draws less than 1µA current.
This feature allows the part to be used in muxed output
applications as shown in Figure 3.
10k 10k
5V
5V
+
10k
INA
10k
5V
10k
10k
INB
SEL
Figure 3. Inverting Amplifi er with Muxed Output
–
+
–
5V
FAIRCHILD
NC7SZ04 OR
EQUIVALENT
A
B
10k
SHDN
A
10k
SHDN
B
60845 F03
LTC6084
(DD PACKAGE)
OUT
SEL = 5V, OUT = –INA
SEL = 0V, OUT = –INB
ESD
The LTC6084/LTC6085 has reverse-biased ESD protection
diodes on all inputs and outputs as shown in the Simplifi ed Schematic. If these pins are forced beyond either
supply, unlimited current will fl ow through these diodes.
If the current is transient and limited to 100mA or less,
no damage to the device will occur.
The amplifi er input bias current is the leakage current of
these ESD diodes. This leakage is a function of the temperature and common mode voltage of the amplifi er, as
shown in the Typical Performance Characteristics.
Noise
In the frequency region above 1kHz, the LTC6084/LTC6085
shows good noise voltage performance. In this region,
noise can be dominated by the total source resistance of the
particular application. Specifi cally, these amplifi ers exhibit
the noise of a 58k resistor, meaning it is desirable to keep
the source and feedback resistance at or below this value,
+ RG||RFB ≤ 58k. Above this total source impedance,
i.e., R
S
the noise voltage is dominated by the resistors.
At low frequency, noise current can be estimated from the
expression i
= √2qIB, where q = 1.6 • 10
n
Equating √4kTRΔf and R√2qI
Δf shows that for a source
B
–19
coulombs.
resistor below 50G the amplifi er noise is dominated by
the source resistance. Noise current rises with frequency.
See the curve Input Noise Current vs Frequency in the
Typical Performance Characteristics section.
60845fa
11
LTC6084/LTC6085
SIMPLIFIED SCHEMATIC
+
V
M11M10
Simplifi ed Schematic of the Amplifi er
R1 R2
M8
SHDN
1µA
+
V
D2
BIAS
GENERATION
D1
NOTE: SHDN IS ONLY AVAILABLE
–
IN THE DFN PACKAGE
V
–
V
–
V
+IN
–IN
+
I2
V
D4
D3
D6
–
V
D5
TYPICAL APPLICATIONS
I1
V
BIAS
+
V
–
V
M1 M2
M3
M5
M4
M6
M7
R3
+
–
A1
OUTPUT
CONTROL
A2
+
–
R4
C1
+
V
D7
OUT
D8
–
V
C2
M9
60845 SS
Gain Selectable Amplifi er
12
5V
10k
10k
+
–
1k
B
SHDNB
24.3k
5V
+
A
–
SHDNA
4.02k
1k
SEL = 5V, GAIN = 25
SEL = 0V, GAIN = 5
A, B: LTC6084 in DFN10
FAIRCHILD NC7SZ04 OR EQUIVALENT
V
OUT
60845 TA02
60845fa
V
IN
SEL
PACKAGE DESCRIPTION
LTC6084/LTC6085
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05
TOP MARK
(SEE NOTE 6)
1.65 ±0.05
(2 SIDES)
0.25 ± 0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
PIN 1
0.200 REF
0.50
BSC
(2 SIDES)
3.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
106
15
0.25 ± 0.05
0.50 BSC
0.38 ± 0.10
(DD) DFN 1103
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
60845fa
13
LTC6084/LTC6085
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 ±0.05
3.50 ±0.05
1.65 ±0.05
(2 SIDES)2.20 ± 0.05
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
5.00 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
PACKAGE
OUTLINE
3.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.20
1.65 ± 0.10
(2 SIDES)
0.00 – 0.05
TYP
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
4.40 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
169
18
0.40 ± 0.10
PIN 1
NOTCH
(DHC16) DFN 1103
14
60845fa
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.
889 ± 0.127
(.035 ± .005)
LTC6084/LTC6085
5.23
(.206)
MIN
0.42 ± 0.038
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
GAUGE PLANE
0.18
(.007)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
DETAIL “A”
DETAIL “A”
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
° – 6° TYP
0
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
4.90
± 0.152
(.193 ± .006)
0.22 – 0.38
(.009 – .015)
TYP
1.10
(.043)
MAX
12
0.65
(.0256)
BSC
8
7
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 ±.005
16
15
6
5
4
3
.189 – .196*
(4.801 – 4.978)
14
12 11 10
13
0.52
(.0205)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8) 0307 REV F
9
.009
(0.229)
REF
.254 MIN
± .0015
RECOMMENDED SOLDER PAD LAYOUT
.007 – .009
8
(0.178 – 0.249)
.016 – .050
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
(0.406 – 1.270)
(MILLIMETERS)
INCHES
.150 – .165
.0250 BSC.0165
.015
(0.38 ± 0.10)
0° – 8° TYP
± .004
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
× 45°
.229 – .244
(5.817 – 6.198)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
12
.150 – .157**
(3.810 – 3.988)
5
4
678
3
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
GN16 (SSOP) 0204
BSC
60845fa
15
LTC6084/LTC6085
TYPICAL APPLICATION
1M
1%
V
IN
1M
1%
OC1
OC2
GNDA
Bipolar Analog Isolation Amplifi er
V
CC
10pF
V
CC
–
+
1/2 LTC6084
10pF
1/2 LTC6084
–
+
OC1
2k
OC1
2k
OC2
BW ≈ 40kHz, EITHER POLARITY
LARGE SIGNAL TRANSITION DELAY ≈ 50µs
SMALL SIGNAL DEAD ZONE: |V
OC2
GNDB
1M
–
+
3pF
+5V
LTC6240HV
–5V
| ≤ 10mV
IN
V
= V
OUT
IN
VCC = 5V,
= ±5V
V
IN
RELATIVE TO GNDA
OC1, OC2: AVAGO TECHNOLOGIES HCNR201
www.avagotech.com
V
OUT
RELATIVE TO GNDB
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC6078/LTC6079 Dual/Quad Micropower Precision Rail-to-Rail Op Amps
LTC6081/LTC6082 Dual/Quad Precision Rail-to-Rail Input/Output Amps
LTC6087/LTC6088 Dual/Quad 14MHz Rail-to-Rail Input/Output Amps
LTC6240/LTC6241/
Single/Dual/Quad Low Noise Rail-to-Rail Output Op Amps 7nV/√Hz Noise, 0.2pA I
LTC6242
LTC6244 Dual Low Noise Rail-to-Rail Output Op Amps 8nV/√Hz Noise, 1pA I
25µV V
70µV V
750µV V
, 0.7µV/°C VOS Drift(MAX), 1pA I
OS(MAX)
, 0.8µV/°C VOS Drift(MAX), 1pA I
OS(MAX)
, 5µV/°C VOS Drift(MAX), 1pA I
OS(MAX)
= ±5V,
60845 TA03
, 18MHz Gain Bandwidth
BIAS
, 50MHz Gain Bandwidth
BIAS
BIAS(MAX)
BIAS(MAX)
BIAS
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
60845fa
LT 0209 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2008
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