FEATURES
LTC4307
Low Offset Hot Swappable
2-Wire Bus Buffer with Stuck
Bus Recovery
U
DESCRIPTIO
■
Bidirectional Buffer with Stuck Bus Recovery
■
60mV Buffer Offset Independent of Load
■
30ms Stuck Bus Timeout
■
Compatible with Non-Compliant VOL I2C Devices
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■
±5kV Human Body Model ESD Protection
■
Isolates Input SDA and SCL Line from Output
■
Compatible with I2CTM, I2C Fast Mode and SMBus
■
READY Open-Drain Output
■
1V Precharge on All SDA and SCL Lines
■
High Impedance SDA, SCL Pins for VCC = 0V
■
Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP
Packages
U
APPLICATIO S
■
Live Board Insertion
■
Servers
■
Capacitance Buffer/Bus Extender
■
RAID Systems
■
ATCA
The LTC®4307 hot swappable, 2-wire bus buffer allows
I/O card insertion into a live backplane without corruption of the data and clock busses. The LTC4307 provides
bidirectional buffering, keeping the backplane and card
capacitances isolated. Low offset and high V
tolerance
OL
allows multiple devices to be cascaded on the clock and
data busses. If SDAOUT or SCLOUT are low for 30ms, the
LTC4307 will automatically break the bus connection. At
this time the LTC4307 automatically generates up to 16
clock pulses on SCLOUT in an attempt to free the bus. A
connection will resume if the stuck bus is cleared.
During insertion, the SDA and SCL lines are pre-charged
to 1V to minimize bus disturbances. When driven high,
the ENABLE input allows the LTC4307 to connect after a
stop bit or bus idle. Driving ENABLE low breaks the connection between SDAIN and SDAOUT, SCLIN and SCLOUT.
READY is an open-drain output which indicates that the
backplane and card sides are connected.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7032051, 6356140, 6650174
TYPICAL APPLICATIO
3.3V
0.01μF
MICRO-
CONTROLLER
10k 2.7k 10k 10k 0.01μF
10k
ENABLE
SCLIN
SDAIN
V
CC
LTC4307
SCLOUT
SDAOUT
GND
3.3V
10k
READY
U
2.7k
BACKPLANE
CONNECTOR
CARD
CONNECTOR
100k
ENABLE
SCLIN
SDAIN
V
CC
LTC4307
SCLOUT
SDAOUT
GND
CARD
READY
3.3V
4307 TA01a
10k
CARD_SCL
CARD_SDA
Rising Edge from Asserted Low
1000
800
600
LOW
OFFSET
200mV/DIV
400
200
0
SDAOUT
SDAIN
0 100 200 300 400 600500
100ns/DIV
4307 TA01b
4307f
1
LTC4307
WW
W
ABSOLUTE AXI U RATI GS
U
(Notes 1, 7)
VCC to GND ................................................. – 0.3V to 6V
SDAIN, SCLIN, SDAOUT, SCLOUT,
READY, ENABLE .......................................... –0.3V to 6V
Maximum Sink Current (SDAIN, SCLIN, SDAOUT,
SCLOUT, READY) .............................................. 50mA
Operating Temperature Range
LTC4307C ................................................ 0°C to 70°C
LTC4307I ............................................. – 40°C to 85°C
UUW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
1ENABLE
SCLOUT
2
SCLIN
3
GND
4
8-LEAD (3mm × 3mm) PLASTIC DFN
T
EXPOSED PAD (PIN 9) CONNECTION TO GND IS OPTIONAL
JMAX
9
DD PACKAGE
= 125°C, θJA = 43°C/W
8
7
6
5
V
CC
SDAOUT
SDAIN
READY
ORDER PART
NUMBER
LTC4307CDD
LTC4307IDD
DD PART*
MARKING
LBTW
LBTW
Storage Temperature Range
DFN ....................................................– 65°C to 125°C
MSOP ................................................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP ............................................................... 300°C
ORDER PART
NUMBER
ENABLE
1
SCLOUT
2
SCLIN
3
GND
4
8-LEAD PLASTIC MSOP
T
= 125°C, θJA = 200°C/W
JMAX
TOP VIEW
MS8 PACKAGE
8
V
7
SDAOUT
6
SDAIN
5
READY
CC
LTC4307CMS8
LTC4307IMS8
MS8 PART*
MARKING
LTBTV
LTBTV
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
The
ELECTRICAL CHARACTERISTICS
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
I
CC
I
SD
V
PRE
t
IDLE
V
THR_ENABLE
I
ENABLE
t
PLH_EN
t
PHL_EN
t
PLH_READY
t
PHL_READY
V
OL_READY
I
OFF_READY
Positive Supply Voltage
Supply Current VCC = 5.5V, V
Shutdown Supply Current VCC = 5.5V, ENABLE = GND, SDA, SCL = 5.5V
Precharge Voltage SDA, SCL Floating
Bus Idle Time
ENABLE Threshold 0.8 1.4 2 V
ENABLE Input Current ENABLE from 0V to V
ENABLE Delay Off-On VCC = 3.3V (Figure 1) 95 μs
ENABLE Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
READY Delay Off-On VCC = 3.3V (Note 3) (Figure 1) 10 ns
READY Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
READY Output Low Voltage I
READY Off Leakage Current VCC = READY = 5.5V
= 3mA, VCC = 2.3V
PULLUP
SCLOUT
= V
CC
SDAOUT
= 0V (Note 6)
●
2.3 5.5 V
●
●
●
0.8 1 1.2 V
●
55 95 175 μs
●
●
●
811 mA
900 1200 μA
0.1 ±5 μA
0.1 ±5 μA
0.4 V
2
4307f
LTC4307
The ● denotes the specifi cations which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Propagation Delay and Rise-Time Accelerators
t
PHL
t
PLH
t
RISE
t
FALL
I
PULLUPAC
Input-Output Connection
V
OS
V
THR
V
HYS
C
IN
I
LEAK
V
OL
V
ILMAX
Bus Stuck Low Timeout
t
TIMEOUT
Timing Characteristics
f
I2C,MAX
t
BUF
t
HD,STA
t
SU,STA
t
SU,STO
t
HD,DATI
t
SU,DAT
SDA/SCL Propagation Delay High to Low C
SDA/SCL Propagation Delay Low to High C
SDA/SCL Transition Time Low to High C
SDA/SCL Transition Time High to Low C
Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 3.3V
Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V,
SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC0.55VCC0.65V
SDA, SCL Logic Input Threshold Voltage
Hysteresis
Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
Input Leakage Current SDA, SCL, Pins
Output Low Voltage SDA, SCL Pins, I
Buffer Input Logic Low Voltage VCC = 3.3V
Bus Stuck Low Timer VCC = 3.3V, SDAOUT, SCLOUT = 0V
I2C Maximum Operating Frequency (Note 3) 400 600 kHz
Bus Free Time Between Stop and Start
Condition
Hold Time After (Repeated) Start Condition (Note 3) 100 ns
Repeated Start Condition Set-Up Time (Note 3) 0 ns
Stop Condition Set-Up Time (Note 3) 0 ns
Data Hold Time Input (Note 3) 0 ns
Data Set-Up Time (Note 3) 100 ns
= 25°C. VCC = 3.3V, unless otherwise noted.
A
= 50pF, 2.7k to VCC on SDA, SCL,
LOAD
V
= 3.3V (Notes 2, 3) (Figure 1)
CC
= 50pF, 2.7k to VCC on SDA, SCL,
LOAD
V
= 3.3V (Notes 2, 3) (Figure 1)
CC
= 100pF, 10k to VCC on SDA, SCL, VCC
LOAD
70 ns
10 ns
30 300 ns
= 3.3V (See Notes 3, 4) (Figure 1)
= 100pF, 10k to VCC on SDA, SCL, VCC
LOAD
30 300 ns
= 3.3V (See Notes 3, 4) (Figure 1)
58 mA
(Note 5)
●
20 60 100 mV
Driven SDA/SCL = 0.2V
CC
(Note 3) 50 mV
(Note 3) 10 pF
= 4mA,
Driven SDA/SCL = 0.2V, V
SINK
= 2.7V
CC
2.7k to VCC on SDA, SCL, VCC = 3.3V,
●
●
0 0.4 V
●
120 160 205 mV
±5 μA
Driven SDA/SCL = 0.1V
●
●
25 30 35 ms
1.2 V
(Note 3) 1.3 μs
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See “Propagation Delays” in the Operations section for a
discussion of t
PHL
and t
as a function of pull-up resistance and bus
PLH
capacitance.
Note 3: Determined by design, not tested in production.
Note 4: Measure points are 0.3 • V
Note 5: I
varies with temperature and VCC voltage as shown in the
PULLUP
and 0.7 • VCC.
CC
Typical Performance Characteristics section.
Note 6: I
test performed with connection circuitry active.
CC
Note 7: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specifi ed.
4307f
3
LTC4307
TIMING DIAGRAMS
ENABLE, CONNECT, READY Timing
t
PHL_EN
t
PHL_READY
4307 TD01
ENABLE
CONNECT
READY
t
PLH_READY
t
PLH_EN
Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
SDAIN/SCLIN
SDAOUT/SCLOUT
t
PLH
t
PHLtRISE
t
RISE
t
FALL
t
FALL
4307 TD02
Figure 1. Timing Diagrams
4307f
4
C
V
V
(V)
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC4307
TA = 25°C, VCC = 3.3V, unless otherwise indicated.
ICC vs Temperature I
8.3
8.0
7.7
7.4
7.1
(mA)
CC
I
6.8
6.5
6.2
5.9
–50
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
–25 0 50
25
TEMPERATURE (°C)
75
100
4307 G01
Input-Output High to Low
Propagation Delay vs Temperature
100
VCC = 5.5V
= 50pF
OUT
= R
PULLUPOUT
02550
TEMPERATURE (°C)
VCC = 3.3V
= 10k
(ns)
PHL
t
80
60
40
20
0
VCC = 2.3V
CIN = C
R
PULLUPIN
–50
–25
20
16
12
(mA)
8
PULLUPAC
I
4
0
–50
75 100
4307 G04
PULLUPAC
–25
vs Temperature
VCC = 5.5V
VCC = 3.3V
25 50
0
TEMPERATURE (°C)
(ns)
PHL
t
950
900
850
(μA)
SD
I
800
750
100
75
4307 G02
700
–50
Input-Output High to Low
Propagation Delay vs C
130
CIN = 50pF
= R
R
120
110
100
90
80
70
60
PULLUPIN
0
PULLUPOUT
VCC = 5.5V
VCC = 3.3V
200 400 600 1000
C
(pF)
OUT
ISD vs Temperature
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
–25
OUT
= 10k
800
25 50
0
TEMPERATURE (°C)
4307 G07
100
75
4307 G02
onnection Circuitry
85
75
(mV)
IN
65
– V
OUT
V
55
45
2345
1
R
PULLUP
(kΩ)
–
IN
4307 G05
OUT
678910
Bus Stuck Low Timeout vs V
34
32
(ms)
30
TIMEOUT
t
28
26
2
2.5
3.5
3
VCC (V)
CC
4
4.5
5
5.5
4307 G06
4307f
5
LTC4307
PI FU CTIO S
UUU
ENABLE (Pin 1): Connection Enable Input. This is a 1.4V
digital threshold input pin. For normal operation pull or tie
ENABLE high. Driving ENABLE below 0.8V isolates SDAIN
from SDAOUT, SCLIN from SCLOUT and asserts READY
low. A rising edge on ENABLE after a fault has occurred
forces a connection between SDAIN, SDAOUT and SCLIN,
SCLOUT. Connect to V
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
an SCL bus segment where stuck bus recovery is needed.
A pull-up resistor should be connected between this pin
CC
.
and V
SCLIN (Pin 3): Serial Clock Input. Connect this pin to an
SCL bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
between this pin and V
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
READY (Pin 5): Connection READY Status Output. The
READY pin is an open-drain N-channel MOSFET output that
pulls low when ENABLE is low, or when the start-up and
if unused.
CC
.
CC
connection sequence described in the Operation section
has not been completed. READY also goes low when the
LTC4307 disconnects the inputs from the outputs due to
the bus being stuck low for at least 30ms. READY goes high
when ENABLE is high and a connection is made. Connect
a pull-up resistor, typically 10k, from this pin to V
provide the pull-up. This pin can be fl oated if unused.
SDAIN (Pin 6): Serial Data Input. Connect this pin to an
SDA bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
between this pin and V
SDAOUT (Pin 7): Serial Data Output. Connect this pin
to the SDA bus segment where stuck bus recovery is
needed. A pull-up resistor should be connected between
this pin and V
(Pin 8): Supply Voltage Input. Place a bypass capacitor
V
CC
of at least 0.01μF close to V
Exposed Pad (Pin 9, DFN Package Only): Exposed Pad
may be left open or connected to device ground.
CC
.
CC
.
for best results.
CC
CC
to
6
4307f
BLOCK DIAGRA
LTC4307
W
Low Offset 2-Wire Bus Buffer with Stuck Low Timeout
8mA
PRECHARGE
30ms
TIMER
CONNECT
PC_CONNECT
CONNECT
I
BOOSTSDA
I
BOOSTSCL
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
I
BOOSTSDA
SDAIN
6
SLEW RATE
DETECTOR
100k
CONNECT
100k
SCLIN
3
8mA
SLEW RATE
DETECTOR
I
BOOSTSCL
PC_CONNECT
CONNECT
+
8mA
8mA
+
–
0.55V
V
8
CC
SDAOUT
7
100k
100k
SCLOUT
2
CC
+
1
0.55V
0.55V
ENABLE
–
CC
0.55V
I
BOOSTSCL
I
+
LOGIC
–
CC
BOOSTSDA
PC_CONNECT
–
CONNECT
CC
READY
5
+
1.4V
–
UVLO
95μs
DELAY
OPERATION
Start-Up
When the LTC4307 fi rst receives power on its V
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until V
rises above 2V (typ).
CC
This is to ensure that the LTC4307 does not try to function
until it has enough voltage to do so.
CC
pin,
CONNECT
GND
4307 BD
4
During this time, the 1V precharge circuitry is active and
forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and V
CC
.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
4307f
7
LTC4307
OPERATION
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4307 comes out of UVLO, it monitors both
the backplane and card sides for either a stop bit or bus idle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit condition while the other is idle, the input-to-output connection
circuitry is activated, joining the SDA and SCL busses on
the I/O card with those on the backplane. In addition, the
precharge circuitry is deactivated and will not be reactivated
unless the V
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages being low. The LTC4307 is tolerant of I
voltages up to the 0.3V
When the LTC4307 senses a rising edge on the bus, it
deactivates its pull-down devices for bus voltages as low
as 0.48V and activates its accelerators. This methodology
maximizes the effectiveness of the rise time accelerator
circuitry and maintains compatibility with the other devices
in the LTC4300 bus buffer family. Care must be taken to
ensure that devices participating in clock stretching or
arbitration force logic low voltages below 0.48V at the
LTC4307 inputs.
SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT release high.
The same is true for SCLIN and SCLOUT. This important
feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always
work, regardless of how the devices in the system are
tied to the LTC4307.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
voltage falls below the UVLO threshold.
CC
2
C bus DC logic low
I2C specifi cation.
CC VIL
Input to Output Offset Voltage
When a logic low voltage, V
LTC4307’s data or clock pins, the LTC4307 regulates the
voltage on the opposite data or clock pins to a slightly
higher voltage, typically 60mV above V
practically independent of pull-up current (see the Typical
Performance curves).
Propagation Delays
During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 2 for
= 5.5V and a 10k pull-up resistor on each side (50pF
V
CC
on one side and 150pF on the other). Since the output
side has less capacitance than the input, it rises faster
and the effective propagation delay is negative.
There is a fi nite propagation delay through the connection circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2.
An external N-channel MOSFET device pulls down the
voltage on the side with 150pF capacitance; the LTC4307
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function
of supply voltage, temperature and the pull-up resistors
and equivalent bus capacitances on both sides of the bus.
The Typical Performance Characteristics section shows
propagation delay as a function of temperature and voltage
for 10k pull-up resistors and 50pF equivalent capacitance
on both sides of the part. Also, the t
= 5.5V shows that increasing the capacitance from
V
CC
50pF to 150pF results in a t
Larger output capacitances translate to longer delays (up
to 125ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
PHL
, is driven on any of the
LOW1
. This offset is
LOW1
vs C
PHL
increase from 81ns to 91ns.
curve for
OUT
8
4307f
OPERATION
LTC4307
OUTPUT SIDE
50pF
1V/DIV
200ns/DIV
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms
INPUT SIDE
150pF
1V/DIV
4307 F02
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by that respective input
going high. If it does not go high within 30ms (typical)
the connection between SDAIN and SDAOUT, and between
SCLIN and SCLOUT is broken. After at least 40μs, the
LTC4307 automatically generates up to 16 clock pulses
at 8.5kHz (typical) on SCLOUT in an attempt to unstick
the bus. When the clock pulses are completed, a stop bit
will be generated on SCLOUT and SDAOUT to reset any
circuity on that bus. When the low SDAOUT or SCLOUT
pin goes high, a connection is enabled waiting for a stop
bit or a bus idle to make a connection.
INPUT SIDE
150pF
1V/DIV
200ns/DIV
OUTPUT SIDE
50pF
1V/DIV
4307 F03
low. When the pin is driven above 2V, the part waits for
data transactions on both the backplane and card sides to
be complete (as described in the Start-Up section) before
connecting the two sides. At this time the internal pulldown on READY releases. When ENABLE is low, automatic
clocking is disabled.
A rising edge on ENABLE after a bus stuck low condition
has occurred forces a connection between SDAIN, SDAOUT,
and SCLIN, SCLOUT even if the bus stuck low condition
has not been cleared. At this time the 30ms timer is reset
but not disabled.
Rise Time Accelerators
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated
and is only reset when SDAOUT and SCLOUT are high.
30ms after UVLO, automatic clocking takes place as
described above.
READY Digital Output
This pin provides a digital fl ag which is low when either
ENABLE is low, the start-up sequence described earlier in
this section has not been completed, or the LTC4307 has
disconnected due to a stuck bus condition. READY goes
high when ENABLE is high and the backplane and card
sides are connected. The pin is driven by an open-drain
pull-down capable of sinking 3mA while holding 0.4V on
the pin. Connect a resistor to V
to provide the pull-up.
CC
ENABLE
When the ENABLE pin is driven below 0.8V with respect to
the LTC4307’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
Once connection has been established, rise time accelerator
circuits on all four SDA and SCL pins are enabled. During
positive bus transitions, the rise time accelerators provide
strong, slew-limited pull-up currents that make the bus
voltage rise at a rate of 100V/μs. The rise time accelerators
signifi cantly improve system reliability in two ways. First,
they provide smooth, controlled transitions during rising
edges for both small and large systems. Because the accelerator pull-up impedance is signifi cantly lower than the
bus pull-up resistance, the system is much less susceptible
to noise on rising edges. Second, the accelerators allow
users to choose large bus pull-up resistors, reducing power
consumption and improving logic low noise margin.
For these reasons, it is strongly recommended that users
choose bus pull-up resistors so that the bus will rise on its
own at a rate of at least 0.8V/μs to guarantee activation of
the accelerators. The rise time accelerators are disabled
until the sequence of events described in the start-up section has been completed. They are also disabled during
automatic clocking.
4307f
9
LTC4307
APPLICATIONS INFORMATION
Live Insertion and Capacitance Buffering Application
Figures 4 and 5 illustrate applications of the LTC4307 that
TM
take advantage of the LTC4307’s Hot Swap
, capacitance
buffering and precharge features. If the I/O cards were
plugged directly into the backplane without the LTC4307
buffer, all of the backplane and card capacitances would
add directly together, making rise-time and fall-time requirements diffi cult to meet. Placing an LTC4307 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4307
drives the capacitance of everything on the card and the
backplane must drive only the capacitance of the LTC4307,
which is less than 10pF.
Hot Swap is a trademark of Linear Technology Corporation.
CARD
CONNECTORS
V
SDA
SCL
ENA1
READY
CC
BACKPLANE
R2
R1
10k
10k
BACKPLANE
CONNECTOR
R3
10k
In most applications the LTC4307 will be used with a
staggered connector where V
and GND will be long
CC
pins. SDA and SCL are medium length pins to ensure that
the V
and GND pins make contact fi rst. This will allow
CC
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that
the connection between the backplane and the card’s data
and clock busses is not is not enabled until the transients
associated with live insertion have settled.
Figure 4 shows the LTC4307 in an application with a staggered connector. The LTC4307 receives its V
voltage
CC
from one of the long “early power” pins. Establishing
early power V
ensures that the 1V precharge voltage is
CC
present at SDAIN and SCLIN before they make contact.
I/O PERIPHERAL CARD 1
C1
R4
10k
SDAIN
SCLIN
ENABLE
READY
V
CC
LTC4307
GND
0.01μF
SDAOUT
SCLOUT
R5
10k
R6
10k
CARD1_SDA
CARD1_SCL
10
ENAn
•
•
•
I/O PERIPHERAL CARD N
C2
0.01μF
R8
10k
R7
10k
SDAIN
SCLIN
ENABLE
READY
V
CC
LTC4307
GND
SDAOUT
SCLOUT
Figure 4. The LTC4307 in an Application with a Staggered Connector
R9
10k
CARDn_SDA
CARDn_SCL
4307 F04
4307f
APPLICATIONS INFORMATION
LTC4307
The ENABLE pin is driven using a short pin. This is to
ensure that a connection is not enabled until the transients
associated with live insertion have settled.
Figure 5 shows the LTC4307 in an application where all
of the pins have the same length. In this application a
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Repeater/Bus Extender Applications
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4307s back-
2
to-back, as shown in Figure 6. The I
C specifi cation allows
for 400pF maximum bus capacitance, severely limiting
the length of the bus. The SMBus specifi cation places no
restriction on bus capacitance, but the limited impedances
of devices connected to the bus require systems to remain
small if rise time and fall time specifi cations are to be met.
In this situation, the differential ground voltage between
the two systems may limit the allowed distance, because
a valid logic-low voltage with respect to the ground at one
end of the system may violate the allowed V
specifi cation
OL
with respect to the ground at the other end. In addition, the
connection circuitry offset voltages of the back-to-back
LTC4307s add together, directly contributing to the same
problem.
Figure 7 further illustrates a repeater application. This circuit
could be used in an AdvancedTCA system. In AdvancedTCA
applications, the bus pull-up resistance on the backplane
is quite small. Since there is no effect on the offset due
to the pull-up impedance, multiple LTC4307 buffers can
be used in a single system. This allows the user to divide
the line and device capacitances into more sections with
buffering and meet rise and fall times.
The LTC4307 disconnects when both bus I/Os are above
0.48V and rising. In systems with large ground bounce,
if many devices are cascaded, the 0.48V threshold can be
exceeded and the transients associated with the ground
bounce can appear to be a rising edge. Under this condition,
the LTC4307 with inputs above 0.48V may disconnect.
V
SDA
SCL
ENA1
READY
ENAn
CC
BACKPLANE
R2
R1
10k
10k
R3
10k
BACKPLANE
CONNECTOR
CARD
CONNECTORS
I/O PERIPHERAL CARD 1
SDAIN
SCLIN
LTC4307
ENABLE
READY
R4
10k
I/O PERIPHERAL CARD N
SDAIN
SCLIN
LTC4307
ENABLE
READY
R7
10k
V
CC
GND
•
•
•
V
CC
GND
SDAOUT
SCLOUT
SDAOUT
SCLOUT
C1
0.01μF
C2
0.01μF
R5
10k
R8
10k
R6
10k
CARD1_SDA
CARD1_SCL
R9
10k
CARDn_SDA
CARDn_SCL
Figure 5. The LTC4307 in an Application Where All the Pins Have the Same Length
4307 F05
4307f
11
LTC4307
APPLICATIONS INFORMATION
Systems with Supply Voltage Droop
In large 2-wire systems, the V
voltages seen by devices
CC
at various points in the system can differ by a few hundred
3.3V
R1
R2
10k
R3
10k
LTC4307
ENABLE
READY
SDAIN
SCLIN
10k
SDA1
SCL1
Figure 6. The LTC4307 in a Repeater/Bus Extender Application Where Two 2-Wire Systems are Separated by a Distance
V
SDA1
SCL1
CC
R1
R2
2.7k
2.7k
LTC4307
SDAOUT
SCLOUT
V
GND
CC
ENABLE
READY
SDAIN
SCLIN
C1
0.01mF
10k
R3
R4
2.7k
V
CC
SDAOUT
SCLOUT
GND
R5
2.7k
C1
0.01μF
R6
10k
R4
10k
LTC4307
ENABLE
READY
SDAIN
SCLIN
millivolts or more
resistor in the V
. This situation is modeled by a series
line, as shown in Figure 8. For proper
CC
operation, make sure that the V
C2
0.01μF
R5
10k
V
CC
SDAOUT
SCLOUT
GND
R6
10k
C2
0.01mF
LTC4307
ENABLE
READY
SDAIN
SCLIN
R7
2.7k
V
CC
SDAOUT
SCLOUT
GND
R8
2.7k
4307 F06
R7
10k
R9
10k
ENABLE
READY
SDAIN
SCLIN
CC(LTC4307)
R8
10k
SDA2
SCL2
C3
0.01mF
V
CC
LTC4307
SDAOUT
SCLOUT
GND
4307 F07
is ≥ 2.3V.
R11
R10
2.7k
2.7k
SDA2
SCL2
12
Figure 7. The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices
V
CC(BUS)
READY
SDA1
SCL1
R1
10k
DROOP
R2
10k
R3
10k
LTC4307
ENABLE
READY
SDAIN
SCLIN
V
CC
SDAOUT
SCLOUT
GND
4307 F08
C1
0.01μF
R4
10k
R5
10k
V
CC(LTC4307)
SDA2
SCL2
R
Figure 8. System with Voltage Droop
4307f
TYPICAL APPLICATIONS
TEMPERATURE
SENSOR
R3
200Ω
R4
200Ω
High VIL Application
5V
R2
R1
1.8k
1.8k
ENABLE
SCLIN
LTC4307
SDAIN
V
GND
CC
SCLOUT
SDAOUT
READY
4307 TA02
C1
0.01μF
LTC4307
R5
10kR610k
SCL
SDA
5V
R7
10k
READY
Simplifi ed ATCA IPMB Application
SHELF MANAGER
3.3V 3.3V
R1
V
ShMC
10kR210k
CC
ENABLE
SDAIN
SCLIN
DC/DC
V
CC
LTC4307
C1
0.01μF
SDAOUT
SCLOUT
R3
2.7k
R4
2.7k
–48V
IPM
BUS
(1 OF 2)
ATCA BOARD
C2
0.01μF
SDAIN
SCLIN
–48V–48V
V
CC
LTC4307
DC/DC
R5
10kR610k
ENABLE
SDAOUT
SCLOUT
V
IPMC
CC
4307 TA03
4307f
13
LTC4307
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.5 ±0.05
0.675 ±0.05
1.65 ±0.05
(2 SIDES)2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.50
BSC
2.38 ±0.05
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 ±0.10
(4 SIDES)
0.75 ±0.05
1.65 ± 0.10
0.00 – 0.05
(2 SIDES)
R = 0.115
TYP
0.25 ± 0.05
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.38 ± 0.10
85
14
0.50 BSC
(DD8) DFN 1203
14
4307f
PACKAGE DESCRIPTION
LTC4307
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
0.889 ± 0.127
(.035 ± .005)
GAUGE PLANE
5.23
(.206)
MIN
0.42 ± 0.038
(.0165 ± .0015)
TYP
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3.20 – 3.45
(.126 – .136)
0.65
(.0256)
BSC
0.18
(.007)
0.254
(.010)
DETAIL “A”
DETAIL “A”
0° – 6° TYP
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
4.90 ± 0.152
(.193 ± .006)
0.22 – 0.38
(.009 – .015)
TYP
1.10
(.043)
MAX
8
12
0.65
(.0256)
BSC
0.52
5
4
(.0205)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8) 0307 REV F
7
6
3
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4307f
15
LTC4307
TYPICAL APPLICATION
The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices
V
SDA1
SCL1
CC
R1
R2
2.7k
2.7k
LTC4307
SDAOUT
SCLOUT
V
GND
CC
ENABLE
READY
SDAIN
SCLIN
C1
0.01mF
R3
10k
R4
2.7k
R5
2.7k
R6
10k
LTC4307
ENABLE
READY
SDAIN
SCLIN
V
CC
SDAOUT
GND
SCLOUT
C2
0.01mF
R7
2.7k
R8
2.7k
R9
10k
LTC4307
ENABLE
READY
SDAIN
SCLIN
V
CC
SDAOUT
SCLOUT
GND
C3
0.01mF
4307 F07
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ThinSOT is a trademark of Linear Technology Corporation
: 35Ω Single Ended/70Ω Differential, Expandable to 32 Single
ON
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R10
2.7k
R11
2.7k
SDA2
SCL2
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
4307f
LT 0507 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2007
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