LINEAR TECHNOLOGY LTC4265 Technical data
DETECTION V1
ON
UVLO
UVLO UVLOON
T = R
LOAD
C1
TRACKS
V
IN
DETECTION V2
TIME
PD CURRENT
50
40
30
GND (V)
20
10
40mA
50
40
30
20
10
TIME
GND – V
OUT
(V)
–10
TIME
–20
–30
GND – T2PSE (V)
–40
–50
dV
dt
INRUSH
C1
=
INRUSH = 100mA R
CLASS
= 30.9Ω
I
LOAD
=
V
IN
R
LOAD
GND
PSE
I
IN
R
LOAD
R
CLASS
V
OUT
C1
GND
R
CLASS
T2PSE
LTC4265
V
OUT
V
IN
1st CLASS
1st MARK 2nd MARK
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
2nd CLASS
1st CLASS
2nd CLASS
LOAD, I
LOAD
INRUSH
L DESIGN FEATURES
PD Interface for PoE+ Includes 25.5W
Classification and Protection Features
in a Low Profile 4mm × 3mm DFN
by Kirk Su
Introduction
The third generation Power over Ethernet standard increases the power
available to PDs to 25.5W, up from
the earlier standard’s 12.95W (see
sidebar). In the new standard, a Type-2
(high power) PD must communicate via
handshake with Type-2 power sourcing equipment (PSE) to determine that
the PSE is capable of providing high
power. Type-2 PSEs are backwards
compatible to the old standard.
The LTC4265 is a PoE PD interface
that can identify 2-event classification
(see sidebar) protocol and present an
active signal as required for operation
in an IEEE 802.3at-compliant PD. In
addition, the LTC4265 may be configured for a variety of auxiliary power
options with the aid of the shutdown
and signature corrupt features.
The LTC4265 is highly integrated
and easy to apply, requiring only one
classification programming resistor.
The LTC4265 is a PoE PD
interface that can identify
2-event classification
protocol and present an
active signal as required
for operation in an IEEE
802.3at-compliant PD. In
addition, the LTC4265 may
be configured for a variety of
auxiliary power options with
the aid of the shutdown and
signature corrupt features.
No additional external components
are required to program the LTC4265
since all features (signature resistance, UVLO, OVLO, inrush current,
and thermal protection) are built in
and programmed into the LTC4265
Overview of the Third Generation
Power over Ethernet System (PoE+)
The Power over Ethernet (PoE) standard specifies how DC power can be
distributed alongside high speed data through a single RJ45 connector. The
second generation standard (IEEE 802.3af) allows Powered Devices (PDs) to
draw 12.95W from Power Sourcing Equipment (PSEs). The popularity of the
standard has PD equipment vendors running up against the 12.95W power
limit. To answer the call for more power, the newer IEEE 802.3at standard
(also called PoE+) establishes a high power allocation while maintaining
compatibility with the existing IEEE 802.3af systems.
In the new standard, PSEs and PDs are distinguished as Type-1 if they
comply with the IEEE 802.3af power levels, or Type-2 if they comply with
the IEEE 802.3at power levels. The maximum available power to a Type-2
PD is 25.5W.
The IEEE 802.3at standard also establishes a new method for Type-2
equipment to mutually identify each other while maintaining compatibility
with the existing PoE systems. A Type-2 PSE has the option of declaring
the presence of high power by performing 2-event classification (Layer 1)
or by communicating with the PD over the data line (Layer 2). In turn, a
Type-2 PD must recognize both layers of communications and identify a
Type-2 PSE before beginning 25.5W operations. L
26
to guarantee a smooth power-up
transition and PD operation with any
Power Sourcing Equipment (PSE). This
eliminates additional component costs
and cumbersome calculations that
Figure 1. Example of 2-event
classification waveform
Linear Technology Magazine • January 2009
DESIGN FEATURES L
GND
R
S
10k
R10
100k
PWRGD
D9
MMBD4148
Q1
FMMT2222
–54V
4265 F08
TO
PSE
LTC4265
ACTIVE-LOW ENABLE
V
IN
V
OUT
V
+
PD
LOAD
GND
R
S
10k
R9
100k
PWRGD
D9
5.1V
MMBZ5231B
–54V
TO
PSE
LTC4265
ACTIVE-LOW ENABLE
V
IN
V
OUT
PD
LOAD
–54V
TO
PSE
ACTIVE-HIGH ENABLE
PD
LOAD
RUN
SHDN
GND
PWRGD
LTC4265
V
IN
V
OUT
OPTION 1: SERIES CONFIGURATION FOR
ACTIVE LOW/LOW IMPEDANCE OUTPUT
–54V
TO
PSE
R
P
TO PD
LOAD
GND
LTC4265
V
IN
T2PSE
V
+
OPTION 2: SHUNT CONFIGURATION FOR
ACTIVE HIGH/OPEN COLLECTOR OUTPUT
–54V
TO
PSE
R
P
TO PD
LOAD
GND
LTC4265
V
IN
V
OUT
T2PSE
V
+
T1
T1 = COILCRAFT ETHI-230LD
BR1, BR2 = DF1501S
TVS
TO PHY
36V
100k
10k
10k
D1
BR1
+
–
BR2
+
–
0.1µF
100V
C1
GND
LTC4265
V
IN
SHDN
V
OUT
+
–
ISOLATED
WALL
ADAPTER
PD
LOAD
RX
–
6
RX
+
3
TX
–
2
TX
+
RJ45
1
7
8
5
4
SPARE
–
SPARE
+
are required in other power interface
products to set thresholds, signature
resistance, and current limits. The
LTC4265 comes in a low profile,
thermally enhanced, 4mm × 3mm
DFN package.
What is 2-Event
Classification?
The IEEE 802.3at establishes two
ways to communicate the presence of
a Type-2 PSE. The Layer 1 approach
requires a PSE to perform 2-event
classification, where classification
probing is performed twice. The Layer
2 approach requires the PSE to communicate over the high speed data line.
A Type-2 PD is required to recognize a
Type-2 PSE using either layer of communication. Layer 1 communication
using 2-event classification is included
in the IEEE 802.3at standard for the
benefit of PSEs/power injectors which
do not have access to the high speed
data line.
Since Layer 2 communications
takes place directly between the PSE
and the LTC4265 load, the LTC4265
concerns itself only with recognizing
2-event classification. Figure 1 shows
an example of a 2-event classification.
The 1st classification event occurs
when the PSE presents an input
voltage between 14.5V to 20.5V and
the LTC4265 presents a class 4 load
current. A Type-2 PSE then drops the
input voltage into the Mark voltage
range of 6.9V to 10V, signaling the
1st Mark event. The PD in the Mark
voltage range presents a load current
between 0.25mA to 4mA. A Type-2
PSE repeats this sequence, signaling
the 2nd Classification and 2nd Mark
event occurrence.
The Type-2 PSE then applies power
to the PD and the LTC4265 charges
up the reservoir capacitor C1 with a
controlled inrush current. When C1
is fully charged, and the LTC4265
Figure 3. Examples of enabling/disabling the PD load via the complementary power good pins
Figure 2. Interfacing with the
Type-2 PSE via the T2PSE pin
Linear Technology Magazine • January 2009
Figure 4. Auxiliary power supply. Auxiliary power takes
precedence over PoE power (using the SHDN pin).
27
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