LINEAR TECHNOLOGY LTC4258 Technical data

FEATURES

LTC4258

Quad IEEE 802.3af

Power over Ethernet Controller

with Integrated Detection

U

DESCRIPTIO

■

Controls Four Independent – 48V Powered
Ethernet Ports

■

Each Port Includes:
– IEEE 802

®

.3af Compliant PD Detection and

Classification
– Output Current Limit with Foldback
– Short-Circuit Protection with Fast Gate Pull-Down
– PD Disconnect Using DC Sensing
– Power Good Indication

■

Operates Autonomously or by I2C

■

4-Bit Programmable Digital Address Allows Control

TM

Control

of Up to 64 Ports

■

Programmable INT Pin Eliminates Software Polling

■

Current and Duty Cycle Limits Protect External FETs

■

Available in a 36-Pin SSOP Package

U

APPLICATIO S

■

IEEE 802.3af Compliant Endpoint and Midspan
Power Sources

■

IP Phone Systems

■

DTE Power Distribution

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Hot Swap is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

The LTC

®

4258 is a quad –48V Hot SwapTM controller de­signed for use in IEEE 802.3af compliant Power
Sourcing Equipment (PSE). It consists of four independent
ports, each with output current limit, short-circuit protec­tion, complete Powered Device (PD) detection and classi­fication capability, and programmable PD disconnect using
DC sensing. Used with power MOSFETs and passives as
in Figure 1, the LTC4258 can implement a complete IEEE

802.3af-compliant PSE.

The LTC4258 can operate autonomously or be controlled by

2

an I

C serial interface. Up to 16 LTC4258s may coexist on
the same data bus, allowing up to 64 powered Ethernet ports
to be controlled with only two digital lines. Fault conditions
are optionally signaled with the INT pin to eliminate software
polling.

External power MOSFETs, current sense resistors and di­odes allow easy scaling of current and power dissipation
levels and provide protection against voltage and current
spikes and ESD events.

The LTC4258 is available in a 36-pin SSOP package.

Linear Technology also provides solutions for 802.3af PD
applications with the LTC4257, LTC4257-1, and LTC4267.

TYPICAL APPLICATIO

INT

SHDN1

SHDN2 SHDN3 SHDN4 V

V

EE

SENSE1

R

S1

RS1 TO RS4: 0.5Ω
Q1 TO Q4: IRFM120A

GATE1

Q1

OUT1 SENSE2 GATE2

–48V

SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3

DGND

0.1µF

AGND

U

3.3V

0.1µF

DD

LTC4258

OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4

10k

R

S2

10k 10k 10k

Q2

R

S3

Figure 1. Complete 4-Port Powered Ethernet Power Source

0.1µF

100V X7R

AUTO BYP RESET

Q3

R

S4

DETECT1
DETECT2
DETECT3

DETECT4

Q4

CMPD3003

×4

0.1µF 100V
×4

SMAJ58A

×4

4258 F01

PORT1

PORT2

PORT3

PORT4

4258fb

1

LTC4258

PACKAGE/ORDER I FOR ATIO

UU

W

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TOP VIEW

GW PACKAGE

36-LEAD PLASTIC SSOP

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

RESET

BYP

INT

SCL

SDAOUT

SDAIN

AD3

AD2

AD1

AD0

DETECT1

DETECT2

DETECT3

DETECT4

DGND

V

DD

SHDN1

SHDN2

NC

AUTO

OUT1

GATE1

SENSE1

OUT2

GATE2

SENSE2

V

EE

OUT3

GATE3

SENSE3

OUT4

GATE4

SENSE4

AGND

SHDN4

SHDN3

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltages

to DGND .......................................... – 0.3V to 5V

V

DD

V

to AGND ......................................... 0.3V to – 70V

EE

DGND to AGND (Note 2) ................................. ±0.3V

Digital Pins

SCL, SDAIN, SDAOUT, INT, AUTO, RESET

n

, AD

SHDN

n .................

Analog Pins

GATE

n

(Note 3) ................... VEE – 0.3V to VEE + 12V

n

DETECT
SENSE
OUT

.................... DGND – 21V to DGND + 0.3V

n .................................

n ....................................

BYP Current ................................................. ±0.1mA

Operating Ambient Temperature Range ...... 0°C to 70°C

Junction Temperature (Note 4)............................ 150°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

DGND – 0.3V to DGND + 5V

VEE – 0.3V to VEE + 1V

VEE – 70V to VEE + 70V

ORDER PART

NUMBER

LTC4258CGW

T

= 150°C, θJA = 80°C/W

JMAX

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T
(Note 5).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supplies

V

DD

V

EE

I

DD

I

EE

V

DDMIN

V

EEMINONVEE

V

EEMINOFFVEE

Detection

I

DET

V

DET

R

DETMIN

R

DETMAX

Classification

V

CLASS

I

CLASS

2

VDD Supply Voltage
VEE Supply Voltage To Maintain IEEE Compliant Output (Note 6)
VDD Supply Current
VEE Supply Current Normal Operation

VDD UVLO Voltage 2.7 V

UVLO Voltage (Turning On) VEE – AGND –31 V
UVLO Voltage (Turning Off) VEE – AGND –28 V

Detection Current First Point, V

Detection Voltage Compliance Open Circuit, Measured at DETECTn Pin
Minimum Valid Signature Resistance
Maximum Valid Signature Resistance

Classification Voltage 0mA < I
Classification Current Compliance Into Short (V

The ● denotes the specifications which apply over the full operating

= 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted

A

●

3 3.3 4 V

●

–47 –57 V

Classification Into a Short (V

= –10V

DETECT

Second Point, V

CLASS

DETECT

< 31mA

DETECT

n

n

= 0V)

= –3.5V

DETECT

= 0V) (Note 8)

n

●

●

●

●

235 300 µA

●

145 190 µA

●

●

15.2 17 19 kΩ

●

26.7 29 33 kΩ

●

–16.4 –21 V

●

55 75 mA

2.5 5 mA
–2 –5 mA

100 mA

–20 –23 V

4258fb

LTC4258

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted

A

(Note 5).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

TCLASS

Gate Driver

I

GON

I

GOFF

I

GPD

∆V

GATE

Output Voltage Sense

V

PG

I

VOUT

Current Sense

V

CUT

V

LIM

V

MIN

V

SC

I

SENSE

Digital Interface

V

OLD

V

ILD

V

IHD

R

PU

R

PD

AC Characteristics

t

DETDLY

t

DET

t

CLSDLY

t

CLASS

t

PON

Classification Threshold Current Class 0-1

Class 1-2
Class 2-3
Class 3-4
Class 4-Overcurrent

GATE Pin Current Gate On, V
GATE Pin Current Gate Off, V
GATE Pin Short-Circuit Pull-Down V
External Gate Voltage (V

– VEE)I

GATE

n

Power Good Threshold Voltage V
Out Pin Bias Current 0V > V

Overcurrent Detection Sense Voltage V
Current Limit Sense Voltage V

DC Disconnect Sense Voltage V

= VEE + 2V 50 mA

GATE

n

= –1µA (Note 3)

GATE

n

– V

OUT

n

OUT

–10V > V
V

V
V

OUT

= –48V –20 µA

OUT

n

– VEE, V

SENSE

n

– VEE, V

SENSE

n

– VEE, V

SENSE

n

– VEE, V

SENSE

n

– V

SENSE

n

GATE

GATE

EE

> –10V

n

> –30V

n

EE

= V

n

EE

= VEE + 5V

n

= V

OUT

OUT
OUT
OUT

(Note 7) 166 187.5 199 mV

EE

= V

n

EE

= AGND – 30V 201 224 mV

n

= AGND – 10V 30.2 mV

n

●

5.5 6.5 7.5 mA

●

13 14.5 16 mA

●

21 23 25 mA

●

31 33 35 mA

●

45 48 51 mA

●

–20 –50 –70 µA

●

30 300 µA

●

10 13 15 V

●

123 V

●

●

–6 µA

–18 µA

201 212.5 224 mV

2.52 3.75 4.97 mV
Short-Circuit Sense Voltage 275 mV
SENSE Pin Bias Current V

Digital Output Low Voltage I

Digital Input Low Voltage SCL, SDAIN, RESET, SHDNn, AUTO, AD
Digital Input High Voltage SCL, SDAIN, RESET, SHDNn, AUTO, AD
Pull-Up Resistor to V

DD

= V

SENSE

n

EE

= 3mA, I

SDAOUT

I

SDAOUT

= 5mA, I

INT
INT

ADn, RESET, SHDN

= 3mA
= 5mA

n

–50 µA

●

●

n
n

●

●

2.4 V

0.4 V

0.7 V

0.8 V

50 kΩ

Pull-Down Resistor to DGND AUTO 50 kΩ

Detection Delay From Detect Command or Application of PD to Port

●

170 590 ms

to Detect Complete (Figure 2)
Detection Duration Time to Measure PD Signature Resistance (Figure 2)
Classification Delay From Successful Detect in Auto or Semiauto Mode

●

170 230 ms

●

10.1 52 ms

to Class Complete

●

From Classify Command in Manual Mode (Figure 2)
Classification Duration (Figure 2)
Power On Delay, Auto Mode From Valid Detect to Port On in Auto Mode (Figure 2)

From Port On Command to GATE Pin Current = I

GON

10.1 420 ms

●

10.1 13 ms

●

●

130 ms

1ms

(Note 9)

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3

LTC4258

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted

A

(Note 5).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

START

t

ICUT

DC

CLMAX

t

DIS

t

VMIN

I2C Timing

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

r

t

f

t

FLTINT

t

STOPINT

t

ARAINT

Maximum Current Limit Duration During t
Port Start-Up t

Maximum Current Limit Duration After t
Port Start-Up t

START1
START1

t

START1

t

START1

ICUT1
ICUT1

t

ICUT1

t

ICUT1

= 0, t
= 0, t
= 1, t
= 1, t

= 0, t
= 0, t
= 1, t
= 1, t

START0
START0
START0
START0

= 0 (Figure 3)

ICUT0

= 1 (Figure 3)

ICUT0

= 0 (Figure 3)

ICUT0

= 1 (Figure 3)

ICUT0

= 0 (Figure 3)
= 1 (Figure 3)
= 0 (Figure 3)
= 1 (Figure 3)

Maximum Current Limit Duty Cycle Reg16h = 00h
Disconnect Delay t

DC Disconnect Minimum Pulse V

DIS1

t

DIS1

t

DIS1

t

DIS1

SENSE

= 0, t
= 0, t
= 1, t
= 1, t

= 0 (Figure 4)

DIS0

= 1 (Figure 4)

DIS0

= 0 (Figure 4)

DIS0

= 1 (Figure 4)

DIS0

– VEE > 5mV, V

n

Width Sensitivity (Note 9)

Clock Frequency (Note 9)
Bus Free Time Figure 5 (Notes 9, 10)
Start Hold Time Figure 5 (Notes 9, 10)
SCL Low Time Figure 5 (Notes 9, 10)
SCL High Time Figure 5 (Notes 9, 10)
Data Hold Time Figure 5 (Notes 9, 10)
Data Set-Up Time Figure 5 (Notes 9, 10)
Start Set-Up Time Figure 5 (Notes 9, 10)
Stop Set-Up Time Figure 5 (Notes 9, 10)
SCL, SDAIN Rise Time Figure 5 (Notes 9, 10)
SCL, SDAIN Fall Time Figure 5 (Notes 9, 10)
Fault Present to INT Pin Low (Notes 9, 10, 11)
Stop Condition to INT Pin Low (Notes 9, 10, 11)
ARA to INT Pin High Time (Notes 9, 10)

= –48V (Figure 4)

OUT

n

●

50 60 70 ms

●

25 30 35 ms

●

100 120 140 ms

●

200 240 280 ms

●

50 60 70 ms

●

25 30 35 ms

●

100 120 140 ms

●

200 240 280 ms

●

5.8 6.3 6.7 %

●

300 360 400 ms

●

75 90 100 ms

●

150 180 200 ms

●

600 720 800 ms

●

●

●

1.3 µs

●

600 ns

●

1.3 µs

●

600 ns

●

150 ns

●

200 ns

●

600 ns

●

600 ns

●

20 300 ns

●

20 150 ns

●

20 150 ns

●

60 200 ns

●

20 300 ns

0.02 1 ms

400 kHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: DGND and AGND should be tied together in normal operation.
Note 3: An internal clamp limits the GATE pins to a minimum of 12V above

. Driving this pin beyond the clamp may damage the part.

V

EE

Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

Note 5: All currents into device pins are positive; all currents out of device

4

pins are negative. All voltages are referenced to ground (AGND and DGND)
unless otherwise specified.

Note 6: The LTC4258 is designed to maintain a port voltage of –46.6V to
–57V. The V

supply voltage range accounts for the drop across the

EE

MOSFET and sense resistor.
Note 7: The LTC4258 implements overload current detection per IEEE

802.3af. The minimum overload current (I
voltage; I

CUT_MIN

= 15.4W/V

PORT_MIN

) is dependent on port

CUT

. An IEEE compliant system using the

LTC4258 should maintain port voltage above –46.6V.
Note 8: V

by measuring the DETECT

supply current while classifying a short is measured indirectly

EE

n

pin current while classifying a short.

Note 9: Guaranteed by design, not subject to test.
Note 10: Values measured at V
Note 11: If fault occurs during an I2C transaction, the INT pin will not be

pulled down until a stop condition is present on the I

ILD

and V

IHD

.

2

C bus.

4258fb

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TYPICAL PERFOR A CE CHARACTERISTICS

LTC4258

PORT

VOLTAGE

10V/DIV

Power On Sequence in Auto Mode

GND

V

EE

PORT 1

= 3.3V

V

DD

= –48V

V

EE

DETECTION

PHASE 1

DETECTION

PHASE 2

CLASSIFICATION

50ms/DIV

POWER ON

Current Limit Foldback

225

200

175

150

125

(mV)

n

100

SENSE

V

75

50

VDD = 3.3V

= –48V

V

EE

25

= 25°C

T

A

0

–48 0

–40

–24–32 –16 –8

V

OUTn-AGND

(V)

4258 G01

4258 G03

450

400

350

300

250

200

150

100

50

0

I

LIMIT

WITH R

SENSE

= 0.5Ω (mA)

PORT

VOLTAGE

20V/DIV

GATE

VOLTAGE

10V/DIV

PORT

CURRENT

500mA/DIV

Powering On a 180µF Load

GND

V

EE

V

EE

+14V

V

0mA

EE

FET ON

FOLDBACK

CURRENT LIMIT

5ms/DIV

INT and SDAOUT Pull Down
Voltage vs Load Current

2.0
VDD = 3.3V

1.8

= 25°C

T

A

1.6

1.4

1.2

1.0

0.8

0.6

PULL-DOWN VOLTAGE (V)

0.4

0.2

0

5

0

10

LOAD CURRENT (mA)

425mA

15

VDD = 3.3V

= –48V

V

EE

LOAD
FULLY

CHARGED

4258 G02

20

4258 G06

25

PORT

VOLTAGE

1V/DIV

PORT
CURRENT
20mA/DIV

Classification Transient Response
to 40mA Load Step Classification Current Compliance

0

VDD = 3.3V

–2

= –48V

V

EE

= 25°C

T

A

–4

–6

–8

–10

–12

–14

PORT VOLTAGE WITH

TYPICAL CMPD3003

–16

CLASSIFICATION VOLTAGE (V)

–18

–20

0 10203040506070

CLASSIFICATION CURRENT (mA)

PIN VOLTAGE

–18V

40mA

0mA

50µs/DIV

VDD = 3.3V

= –48V

V

EE

= 25°C

T

A

4258 G07

DETECT

n

4258 G08

VEE DC Supply Current vs
Supply Voltage

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5
VDD = 3.3V

REG 12h = 00h

0

–70

–60 –50

–40 –20

VEE SUPPLY VOLTAGE (V)

–30 –10 0

4258 G09

4258fb

5

LTC4258

WU

TEST TI I G

PORT

n

PD

INSERTED

0VV

t

DET

V

SENSE

PORT
TURN ON
(AUTO MODE)

V

GATE

V

CLASS

V

n

EE

V

T

INT

t

DETDLY

t

CLSDLY

t

PON

t

CLASS

4258 F02

Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes

V

TO V

n

LIM

EE

0V

INT

V

CUT

t

START

, t

ICUT

V

SENSE

TO V

n

V

EE

MIN

INT

t

4258 F03

VMIN

Figure 3. Current Limit Timing Figure 4. DC Disconnect Timing

SCL

SDA

t

3

t

4

t

2

t

1

t

r

t

f

t

5

t

6

t

7

t

8

4258 F05

Figure 5. I2C Interface Timing

t

DIS

4258 F04

WUW

TI I G DIAGRA S

SCL

SCL

SDA

SDA

001

START BY
MASTER

AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0

SERIAL BUS ADDRESS BYTE

FRAME 1

001

START BY
MASTER

AD3 AD2 AD1 AD0 A7 A6 A5 A4 A3 A2 A1 A0

SERIAL BUS ADDRESS BYTE

ACK

R/W

6

FRAME 1

ACK BY
SLAVE

REGISTER ADDRESS BYTE

ACK

R/W

ACK BY
SLAVE

FRAME 2

REGISTER ADDRESS BYTE

ACK BY

SLAVE

Figure 6. Writing to a Register

ACK

001

REPEATED
START BY
MASTER

SERIAL BUS ADDRESS BYTE

FRAME 2

ACK BY

SLAVE

Figure 7. Reading from a Register

ACK ACK

D7 D6 D5 D4 D3 D2 D1 D0

4258 F06

FRAME 2

DATA BYTE

STOP BY

MASTER

NO ACK BY

MASTER

ACK BY

SLAVE

FRAME 3

DATA BYTE

AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

R/W

ACK

ACK BY
SLAVE

ACK

4258 F07

STOP BY
MASTER

4258fb

WUW

TI I G DIAGRA S

SCL

LTC4258

SDA

01

START BY
MASTER

AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0

0

SERIAL BUS ADDRESS BYTE

FRAME 1

R/W

ACK

Figure 8. Reading the Interrupt Register (Short Form)

SCL

SDA

00 11

0

START BY
MASTER

FRAME 1

ALERT RESPONSE ADDRESS BYTE

R/W

ACK

Figure 9. Reading from Alert Response Address

U

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PI FU CTIO S

RESET (Pin 1): Chip Reset, Active Low. When the RESET
pin is low, the LTC4258 is held inactive with all ports off
and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4258 begins normal
operation. RESET can be connected to an external capaci­tor or RC network to provide a power turn-on delay.
Internal filtering of the RESET pin prevents glitches less
than 1µs wide from resetting the LTC4258. Pull RESET
high with ≤10k or tie to V

BYP (Pin 2): Bypass Output. The BYP pin is used to
connect the internally generated –20V supply to an exter­nal 0.1µF bypass capacitor. Use a 100V rated 0.1µF, X7R
capacitor. Do not connect the BYP pin to any other external
circuitry.

INT (Pin 3): Interrupt Output, Open Drain. INT will pull low
when any one of several events occur in the LTC4258. It
will return to a high impedance state when bits 6 or 7 are
set in the Reset PB register (1Ah). The INT signal can be
used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See Register Functions and Applications
Information for more information. The INT pin is only

2

updated between I

C transactions.

DD

.

ACK

ACK BY
SLAVE

ACK BY
SLAVE

FRAME 2

DATA BYTE

AD30000 1 AD2 AD1 AD0

FRAME 2

SERIAL BUS ADDRESS BYTE

NO ACK BY

MASTER

NO ACK BY

MASTER

STOP BY
MASTER

4258 F08

ACK1

STOP BY
MASTER

4258 F09

SCL (Pin 4): Serial Clock Input. High impedance clock
input for the I
be connected directly to the I

2

C serial interface bus. The SCL pin should

2

C SCL bus line.

SDAOUT (Pin 5): Serial Data Output, Open Drain Data
Output for the I

2

C Serial Interface Bus. The LTC4258 uses

two pins to implement the bidirectional SDA function to

2

simplify optoisolation of the I

C bus. To implement a stan­dard bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.

SDAIN (Pin 6): Serial Data Input. High impedance data input

2

for the I

C serial interface bus. The LTC4258 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I

2

C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
See Applications Information for more information.

AD3 (Pin 7): Address Bit 3. Tie the address pins high or low

2

to set the I
sponds. This address will be (010A

C serial address to which the LTC4258 re-

3A2A1A0)b

. Pull AD3

high or low with ≤10k or tie to VDD or DGND.

AD2 (Pin 8): Address Bit 2. See AD3.

AD1 (Pin 9): Address Bit 1. See AD3.

AD0 (Pin 10): Address Bit 0. See AD3.

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7

LTC4258

U

UU

PI FU CTIO S

DETECT1 (Pin 11): Detect Sense, Port 1. The LTC4258
Powered Device (PD) detection and classification hard­ware monitors port 1 with this pin. Connect DETECT1 to
the output port via a low leakage diode (see Figure 1). If the
port is unused, the DETECT1 pin can be tied to AGND or
allowed to float.

DETECT2 (Pin 12): Detection Sense, Port 2. See DETECT1.

DETECT3 (Pin 13): Detection Sense, Port 3. See DETECT1.

DETECT4 (Pin 14): Detection Sense, Port 4. See DETECT1.

DGND (Pin 15): Digital Ground. DGND should be con-

nected to the return from the 3.3V supply. DGND and
AGND should be tied together.

V

(Pin 16): Logic Power Supply. Connect to a 3.3V

DD

power supply relative to DGND. VDD must be bypassed to
DGND near the LTC4258 with at least a 0.1µF capacitor.

SHDN1 (Pin 17): Shutdown Port 1, Active Low. When
pulled low, SHDN1 shuts down port 1, regardless of the
state of the internal registers. Pulling SHDN1 low is
equivalent to setting the Reset Port 1 bit in the Reset
Pushbutton register (1Ah). Internal filtering of the SHDN1
pin prevents glitches less than 1µs wide from reseting the
LTC4258. Pull SHDN1 high with ≤10k or tie to V

SHDN2 (Pin 18): Shutdown Port 2, Active Low. See
SHDN1.

DD

.

GATE4 (Pin 23): Port 4 Gate Drive. GATE4 should be
connected to the gate of the external MOSFET for port 4.
When the MOSFET is turned on, a 50µA pull-up current
source is connected to the pin. The gate voltage is clamped
to 13V (typ) above V
the voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down with 50µA, turning the
MOSFET off and recording a t
port is unused, float the GATE4 pin or tie it to V

OUT4 (Pin 24): Port 4 Output Voltage Monitor. OUT4
should be connected to the output port through a 10k
series resistor. A current limit foldback circuit limits the
power dissipation in the external MOSFET by reducing the
current limit threshold when the port voltage is within 18V
of AGND. The port 4 Power Good bit is set when the voltage
from OUT4 to V
is connected internally from OUT4 to AGND. If the port is
unused, the OUT4 pin can be tied to AGND or allowed to
float.

SENSE3 (Pin 25): Port 3 Current Sense Input. See SENSE4.
GATE3 (Pin 26): Port 3 Gate Drive. See GATE4.
OUT3 (Pin 27): Port 3 Output Voltage Monitor. See OUT4.

(Pin 28): –48V Supply Input. Connect to a –48V to

V

EE

–57V supply, relative to AGND.

EE

. During a current limit condition,

EE

or t

ICUT

drops below 2V (typ). A 2.5MΩ resistor

event. If the

START

EE

.

SHDN3 (Pin 19): Shutdown Port 3, Active Low. See
SHDN1.

SHDN4 (Pin 20): Shutdown Port 4, Active Low. See
SHDN1.

AGND (Pin 21): Analog Ground. AGND should be con­nected to the return from the – 48V supply. AGND and
DGND should be tied together.

SENSE4 (Pin 22): Port 4 Current Sense Input. SENSE4
monitors the external MOSFET current via a 0.5Ω sense
resistor between SENSE4 and V
across the sense resistor exceeds the overcurrent detec­tion threshold V
If the voltage across the sense resistor reaches the current
limit threshold V
GATE4 pin voltage is lowered to maintain constant current
in the external MOSFET. See Applications Information for
further details. If the port is unused, the SENSE4 pin must
be tied to VEE.

, the current limit fault timer counts up.

CUT

(typically 25mV/50mA higher), the

LIM

. Whenever the voltage

EE

SENSE2 (Pin 29): Port 2 Current Sense Input. See SENSE4.
GATE2 (Pin 30): Port 2 Gate Drive. See GATE4.
OUT2 (Pin 31): Port 2 Output Voltage Monitor. See OUT4.
SENSE1 (Pin 32): Port 1 Current Sense Input. See SENSE4.
GATE1 (Pin 33): Port 1 Gate Drive. See GATE 4.
OUT1 (Pin 34): Port 1 Output Voltage Monitor. See OUT4.
AUTO (Pin 35): Auto Mode Input. Auto mode allows the

LTC4258 to detect and power up a PD even if there is no
host controller present on the I2C bus. The voltage of the
AUTO pin determines the state of the internal registers
when the LTC4258 is reset or comes out of V
the Register map in Table 1). The states of these register
bits can subsequently be changed via the I
The real-time state of the AUTO pin is read at bit 0 in the
Pin Status register (11h). Pull AUTO high or low with ≤10k
or tie to V

NC (Pin 36): No Internal Connection.

or DGND.

DD

UVLO (see

DD

2

C interface.

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8

W

TABLE 1. REGISTER AP

Fault 1 0000,0000 0000,0000

Fault 1 0000,0000 0000,0000

ICUT

START

Fault 2 t

Fault 2 t

ICUT

START

Fault 3 t

Fault 3 t

ICUT

START

01

0

A

1

,A

2

A

3

00 00A

0

A

1

,A

2

A

3

0000,0000 0000,0000

DIS0

t

DIS1

t

ICUT0

t

LTC4258

UVLO

EE

supplies are brought up.

EE

UVLO is not set by RESET pin or

and V

DD

DD

reset all pushbutton.

V

V

bit depends on the order in which the

* The start-up state of the V

WO = Write Only

CoR = Clear on Read

R/W = Read/Write

RO = Read Only

Key:

Fault Class Complete Detect Complete Disconnect Pwr Good Event Pwr Enable Event 1000,0000 1000,0000

ICUT

Fault t

START

Fault 4 t

ICUT

Fault 4 t

START

UVLO Reserved Reserved Reserved Reserved 0011,0000* 0011,0000*

EE

UVLO V

DD

ICUT1

t

START0

t

START1

Enable

Interrupts

00h Interrupt RO Global Supply Event t

Interrupts Auto Pin Low Auto Pin High

ADDRESS REGISTER NAME R/W PORT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET STATE RESET STATE

02h Power Event RO 4321 Pwr Good Pwr Good Pwr Good Pwr Good Pwr Enable Pwr Enable Pwr Enable Pwr Enable 0000,0000 0000,0000

01h Int Mask R/W Global Mask 7 Mask 6 Mask 5 Mask 4 Mask 3 Mask 2 Mask 1 Mask 0 1000,0000 1110,0100

Events

04h Detect Event RO 4321 Class Complete 4 Class Complete 3 Class Complete 2 Class Complete 1 Detect Complete 4 Detect Complete 3 Detect Complete 2 Detect Complete 1 0000,0000 0000,0000

03h Power Event CoR CoR Change 4 Change 3 Change 2 Change 1 Change 4 Change 3 Change 2 Change 1

05h Detect Event CoR CoR

Event CoR CoR

Event RO 4321 Reserved Reserved Reserved Reserved t

START

START

111 Overcurrent 111 Reserved

110 Class 0 110 Open Circuit

101 Undefined—Read as Class 0 101 RHIGH

100 Class 4 100 Detect Good

011 Class 3 011 RLOW 11 Auto Detect, Class and Power Automatically

010 Class 2 010 Reserved 10 Semiauto Detect and Class But Wait to Turn On Power

001 Class 1 001 Short Circuit (<1V) 01 Manual Will Not Advance Between States

0Fh Port 4 Status RO 4 Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Detect Status 0 0000,0000 0000,0000

11h Pin Status RO Global Reserved Reserved AD3 Pin Status AD2 Pin Status AD1 Pin Status AD0 Pin Status Reserved Auto Pin Status 00A

10h Power Status RO 4321 Power Good 4 Power Good 3 Power Good 2 Power Good 1 Power Enable 4 Power Enable 3 Power Enable 2 Power Enable 1 0000,0000 0000,0000

06h Fault Event RO 4321 Disconnect 4 Disconnect 3 Disconnect 2 Disconnect 1 t

0Bh Supply Event CoR CoR

0Ah Supply Event RO 4321 Over Temp Reserved V

Status

09h t

08h t

07h Fault Event CoR CoR

0Eh Port 3 Status RO 3 Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Detect Status 0 0000,0000 0000,0000

0Ch Port 1 Status RO 1 Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Detect Status 0 0000,0000 0000,0000

0Dh Port 2 Status RO 2 Reserved Class Status 2 Class Status 1 Class Status 0 Reserved Detect Status 2 Detect Status 1 Detect Status 0 0000,0000 0000,0000

Configuration

13h Disconnect Enable R/W 4321 Reserved Reserved Reserved Reserved DC Discon En 4 DC Discon En 3 DC Discon En 2 DC Discon En 1 0000,0000 0000,1111

12h Operating Mode R/W 4321 Port 4 Mode 1 Port 4 Mode 0 Port 3 Mode 1 Port 3 Mode 0 Port 2 Mode 1 Port 2 Mode 0 Port 1 Mode 1 Port 1 Mode 0 0000,0000 1111,1111

14h Detect/Class Enable R/W 4321 Class Enable 4 Class Enable 3 Class Enable 2 Class Enable 1 Detect Enable 4 Detect Enable 3 Detect Enable 2 Detect Enable 1 0000,0000 1111,1111

16h Timing Config R/W Global Reserved Reserved t

15h Reserved R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0000,0000 0000,0000

17h Misc Config R/W Global Interrupt Pin Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1000,0000 1000,0000

19h Power Enable PB WO 4321 Power Off 4 Power Off 3 Power Off 2 Power Off 1 Power On 4 Power On 3 Power On 2 Power On 1 0000,0000 0000,0000

18h Det/Class Restart PB WO 4321 Restart Class 4 Restart Class 3 Restart Class 2 Restart Class 1 Restart Detect 4 Restart Detect 3 Restart Detect 2 Restart Detect 1 0000,0000 0000,0000

Pushbuttons

1Ah Reset PB WO Global Clear All Clear Interrupt Pin Reserved Reset All Reset Port 4 Reset Port 3 Reset Port 2 Reset Port 1 0000,0000 0000,0000

000 Class Status Unknown 000 Detect Status Unknown 00 Shutdown Power Off, Detection and Class Off

CLASS STATUS DETECT STATUS MODE BIT ENCODING

Encoding

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