LINEAR TECHNOLOGY LTC4257 Technical data

FEATURES

LTC4257

IEEE 802.3af PD

Power over Ethernet

Interface Controller

U

DESCRIPTIO

■

Complete Power Interface Port for IEEE 802.3af
Powered Devices (PDs)

■

Onboard 100V, 400mA Power MOSFET

■

Precision Input Current Limit

■

Onboard 25k Signature Resistor

■

Programmable Classification Current (Class 0-4)

■

Undervoltage Lockout

■

Smart Thermal Protection

■

Power Good Signal

■

Available in 8-Pin SO and Low Profile (3mm × 3mm)
DFN Packages

U

APPLICATIO S

■

IP Phone Power Management

■

Wireless Access Points

■

Telecom Power Control

®

The LTC®4257 provides complete signature and power
interface functions for a device operating in an IEEE

802.3af Power over Ethernet (PoE) system. The LTC4257
simplifies Powered Device (PD) design by incorporating
the 25k signature resistor, the classification current source,
input current limit with thermal foldback, undervoltage
lockout and power good signalling, all in a single 8-pin
package. By incorporating a high voltage power MOSFET
onboard, the LTC4257 provides the system designer with
reduced cost while also saving board space.

The LTC4257 can interface directly with a variety of Linear
Technology DC/DC converter products to provide a cost
effective power solution for IP phones, wireless access
points and other PDs. Linear Technology also provides
solutions for Power Sourcing Equipment (PSE) applica­tions with quad network power controllers.

The LTC4257 is available in the 8-pin SO and low profile
(3mm × 3mm) DFN packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO

Powered Device (PD)

–48V FROM

POWER SOURCING

EQUIPMENT

(PSE)

~~+

DF01SA

0.1µF

–

SMAJ58A

R

CLASS

U

R

V

CLASS

IN

LTC4257

PWRGD

GND

V

OUT

100k

5µF

MIN

+

V

IN

SWITCHING

POWER SUPPLY

SHDN

RTN

4257 TA01

+

3.3V

TO LOGIC

–

V

50V/DIV

V

OUT

20V/DIV

200mA/DIV

PWRGD
50V/DIV

LTC4257 Charging 300µF

Load Capacitor

IN

I

IN

5ms/DIV

4225 TA02

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1

LTC4257

WWWU

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

VIN Voltage ............................................. 0.3V to –100V

, PWRGD Voltage ............. VIN + 100V to VIN – 0.3V

V

OUT

R

PWRGD Current .................................................. 10mA

R

Voltage ............................ VIN + 7V to VIN – 0.3V

CLASS

Current .................................................. 100mA

CLASS

Operating Ambient Temperature Range

LTC4257C ............................................... 0°C to 70°C

LTC4257I............................................. –40°C to 85°C

Storage Temperature Range

S8 Package....................................... – 65°C to 150°C

DD Package ...................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec).................. 300°C

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

TOP VIEW

1

NC

R

2

CLASS

NC

3

V

4

IN

S8 PACKAGE

8-LEAD PLASTIC SO

T

= 150°C, θJA = 150°C/W

JMAX

ORDER PART NUMBER S8 PART MARKING

LTC4257CS8
LTC4257IS8

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF
Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container.

8

7

6

5

GND

NC

PWRGD

V

OUT

4257
4257I

ORDER PART NUMBER DD PART MARKING*

LTC4257IDD

1NC

R

2

CLASS

NC

3

V

4

IN

8-LEAD (3mm × 3mm) PLASTIC DFN

ELECTRICALLY ISOLATED PCB HEATSINK

DD PACKAGE

T

= 125°C, θJA = 43°C/W

JMAX

EXPOSED PAD TO BE SOLDERED TO

8

7

6

5

GND

NC

PWRGD

V

OUT

LACTLTC4257CDD

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

I

IN_ON

I

IN_CLASS

∆I

CLASS

Supply Voltage Voltage with Respect to GND Pin (Notes 4, 5, 6)

Maximum Operating Voltage
Signature Range
Classification Range
UVLO Turn-On Voltage

UVLO Turn-Off Voltage
IC Supply Current when ON VIN = –48V, Pins 5, 6 Floating
IC Supply Current During Classification VIN = –17.5V, Pin 2 Floating, V

Current Accuracy During Classification 10mA < I

The ● denotes the specifications which apply over the full operating

= 25°C. (Note 3)

A

●

●

–1.5 –9.5 V

●

–12.5 – 21 V

●

–37.7 –39.2 –40.2 V

●

–29.3 –30.5 –31.5 V

●

(Note 7)

CLASS

(Notes 8, 9)

Tied to GND

OUT

< 40mA, –12.5V ≤ VIN ≤ – 21V,

●

0.35 0.50 0.65 mA

●

–57 V

3mA

±3.5 %

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2

LTC4257

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes the specifications which apply over the full operating

= 25°C. (Note 3)

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

R

SIGNATURE

Signature Resistance –1.5V ≤ VIN ≤ –9.5V, V

Tied to GND,

OUT

●

23.25 26.00 kΩ

IEEE 802.3af 2-Point Measurement (Notes 4, 5)

V

PG_OUT

V

PG_THRES_FALL

V

PG_THRES_RISE

I

PG_LEAK

R

ON

I

OUT_LEAK

I

LIMIT

I

LIMIT_WARM

T

OVERTEMP

T

SHUTDOWN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltages are with respect to GND pin.
Note 3: The LTC4257 operates with a negative supply voltage in the range

of –1.5V to –57V. To avoid confusion, voltages in this data sheet are
always referred to in terms of absolute magnitude. Terms such as
“maximum negative voltage” refer to the largest negative voltage and a
“rising negative voltage” refers to a voltage that is becoming more
negative.

Note 4: The LTC4257 is designed to work with two polarity protection
diodes between the PSE and PD. Parameter ranges specified in the
Electrical Characteristics are with respect to LTC4257 pins and are
designed to meet IEEE 802.3af specifications when these diode drops are
included. See Applications Information.

Note 5: Signature resistance is measured via the 2-point ∆V/∆I method as
defined by IEEE 802.3af. The LTC4257 signature resistance is offset from
25k to account for diode resistance. With two series diodes, the total PD
resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4257
pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and
–9.5V.

Note 6: The LTC4257 includes hysteresis in the UVLO voltages to preclude

Power Good Output Low Voltage I = 1mA, VIN = –48V, PWRGD Referenced to V
Power Good Trip Point VIN = –48V, Voltage Between VIN and V

V

Falling

OUT

V

Rising

OUT

Power Good Leakage VIN = 0V, PWRGD FET Off, V

PWRGD

OUT

= 57V

(Note 9)

On-Resistance I = 300mA, VIN = – 48V, Measured from VIN to V

(Note 9)

V

Leakage VIN = 0V, Power MOSFET Off, V

OUT

Input Current Limit VIN = –48V, V

= –43V (Note 11)

OUT

= 57V (Note 10)

OUT

●

IN

●

1.3 1.5 1.7 V

●

2.7 3.0 3.3 V

●

OUT

●

●

●

300 350 400 mA

1.0 1.6 Ω

0.5 V

1 µA

2.0 Ω

150 µA

Overtemperature Input Current Limit (Note 11) 188 mA

Overtemperature Trip Temperature (Note 11) 120 °C

Thermal Shutdown Trip Temperature (Note 11) 140 °C

power up from a voltage source with 20Ω series resistance on the first
trial.

Note 7: I
Pin 2. Total supply current in classification mode will be I

does not include classification current programmed at

IN_CLASS

IN_CLASS

+ I

CLASS

(see Note 8).
Note 8: I

∆I

CLASS

I

CLASS

include variations in R
a PD also includes the IC quiescent current (I

is the measured current flowing through R

CLASS

accuracy is with respect to the ideal current defined as

= 1.237/R

. The current accuracy specification does not

CLASS

resistance. The total classification current for

CLASS

IN_CLASS

). See Applications

CLASS

.

Information.
Note 9: For the DD package, this parameter is assured by design and

wafer level testing.
Note 10: I

OUT_LEAK

includes current drawn at the V

pin by the power

OUT

good status circuit. This current is compensated for in the 25kΩ signature
resistance and does not affect PD operation.

Note 11: The LTC4257 includes smart thermal protection. In the event of
an overtemperature condition, the LTC4257 will reduce the input current
limit by 50% to reduce the power dissipation in the package. If the part
continues heating and reaches the shutdown temperature, the current is
reduced to zero until the part cools below the overtemperature limit. The
LTC4257 is also protected against thermal damage from incorrect
classification probing by the PSE. If the LTC4257 exceeds the
overtemperature trip point, the classification load current is disabled.

any start-up oscillation. Per IEEE 802.3af requirements, the LTC4257 will

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3

LTC4257

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Input Current vs Input Voltage
25k Detection Range Input Current vs Input Voltage

0.5
TA = 25°C

0.4

0.3

0.2

INPUT CURRENT (mA)

0.1

0

0

–4 –6 –8

–2

INPUT VOLTAGE (V)

–10

4357 G02

Input Current vs Input Voltage

50

TA = 25°C

40

30

20

INPUT CURRENT (mA)

10

0

0

CLASS 4

CLASS 3

CLASS 2

CLASS 1

CLASS 0

–20 –30 –40

–10

INPUT VOLTAGE (V)

–50 –60

4257 G01

12.0
CLASS 1 OPERATION

11.5

11.0

10.5

10.0

INPUT CURRENT (mA)

9.5

9.0
–12

85°C

–40°C

–14

–16

INPUT VOLTAGE (V)

–18

–20 –22

4257 G03

Input Current vs Input Voltage

3

EXCLUDES ANY LOAD CURRENT

= 25°C

T

A

2

1

INPUT CURRENT (mA)

0

–45 –55

INPUT VOLTAGE (V)

Power Good Output Low Voltage
vs Current

4

TA = 25°C

3

(V)

2

PG_OUT

V

1

4257 G04

Signature Resistance
vs Input Voltage

28

RESISTANCE =

27

DIODES: S1B

= 25°C

T

A

26

25

24

LTC4257 ONLY

SIGNATURE RESISTANCE (kΩ)

23

CURRENT (µA)

V

V1:
V2:

OUT

22

120

90

60

30

–1

–2 –4

V

OUT

= 0V

V

IN

= 25°C

T

A

–60–40 –50

∆V∆IV2 – V1

=

– I

I

2

1

IEEE UPPER LIMIT

LTC4257 + 2 DIODES

IEEE LOWER LIMIT

–3

–5
–6 –10

INPUT VOLTAGE (V)

Leakage Current

–9

–7

–8

4257 G05

Normalized UVLO Threshold
vs Temperature

2

APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS

1

0

–1

NORMALIZED UVLO THRESHOLD (%)

–2

–40

–20 0 20 40

TEMPERATURE (°C)

Current Limit vs Input Voltage

375

V

= VIN + 5V

OUT

365

355

345

CURRENT LIMIT (mA)

335

85°C

25°C

–40°C

60 80

4257 G06

4

0

2

0

CURRENT (mA)

6

8

4

10

4257 G07

0

0

20 40

V

PIN VOLTAGE (V)

OUT

60

42571 G09

325

–40

–45

–50

INPUT VOLTAGE (V)

–55

–60

4257 G09

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LTC4257

U

UU

PI FU CTIO S

NC (Pin 1): No Connect.

R

(Pin 2): External Class Select Input. Used to set the

CLASS

current the LTC4257 maintains during classification. Con­nect a resistor between R

and VIN (see Table 2).

CLASS

NC (Pin 3): No Connect.

(Pin 4): Power Input. Tie to system –48V through the

V

IN

input diode bridge.

(Pin 5): Power Output. Supplies – 48V to the PD load

V

OUT

through an internal power MOSFET that limits input cur­rent. V

is high impedance until the input voltage rises

OUT

above the turn-on UVLO threshold. Above the UVLO
threshold the output is current limited to 350mA.

W

BLOCK DIAGRA

PWRGD (Pin 6): Power Good Output, Open-Drain. Signals
that the LTC4257 MOSFET is fully on. Low impedance
indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to V

IN

.

NC (Pin 7): No Connect

GND (Pin 8): Ground. Tie to system ground and to power

return through the input diode bridge.

R

NC

CLASS

NC

V

CLASSIFICATION

1

2

3

IN

1.237V

CONTROL
CIRCUITS

350mA

0.3Ω

CURRENT SOURCE

+

–

+

–

EN

EN

INPUT

CURRENT

LIMIT

25k SIGNATURE

RESISTOR

POWER GOOD

BOLD LINE INDICATES HIGH CURRENT PATH

8

7

6

54

GND

NC

PWRGD

V

OUT

4257 BD

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5

LTC4257

WUUU

APPLICATIO S I FOR ATIO

The LTC4257 is intended for use as the front end of a
Powered Device (PD) designed to IEEE 802.3af draft
standard. The LTC4257 includes a trimmed 25k signature
resistor, classification current source, and an inrush cur­rent limit circuit. With these functions integrated into the
LTC4257, the signature and power interface for a PD that
meets all the requirements of IEEE 802.3af can be built
with a minimum of external components.

Using an LTC4257 for the power and signature interface
functions of a PD provides several advantages. The
LTC4257 current limit circuit includes an onboard, 100V,
400mA power MOSFET with low leakage. This onboard
low leakage MOSFET avoids the possibility of corrupting
the 25k signature resistor while also saving board space
and cost. In addition, the IEEE 802.3af inrush current limit
requirement causes large transient power dissipation in
the PD; the LTC4257 manages this turn-on sequence
through the use of smart thermal protection circuitry. The
LTC4257 is designed to allow multiple turn-on sequences
without overheating the miniature 8-lead package. In the
event of excessive power cycling, the LTC4257 provides
thermally activated current-limit reduction to keep the
onboard power MOSFET within its safe operating area.

Operation

The LTC4257 has several modes of operation depending
on the applied input voltage as shown in Figure 1 and
summarized in Table 1. These various modes satisfy the
requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the VIN pin and is with
reference to the GND pin. This input voltage is always
negative. To avoid confusion, voltages in this data sheet
are always referred to in terms of absolute magnitude.
Terms such as
largest negative voltage and a

maximum negative voltage

refer to the

rising negative voltage

refers to a voltage that is becoming more negative. Refer­ences to electrical parameters in this applications section
use the nominal value. Refer to the Electrical Characteris­tics section for the range of values a particular parameter
will have.

PSE

–10

–20

(V)

IN

V

–30

–40

–50

–10

–20

(V)

OUT

–30

V

–40

–50

–10

–20

–30

PWRGD (V)

–40

–50

I

LIMIT

I

CLASS

PD CURRENT

V

IN

R

CLASS

UVLO

V1 – 2 DIODE DROPS

I

=

1

V2 – 2 DIODE DROPS

I2 =

I

CLASS

I

= 350mA (NOMINAL)

LIMIT

I

=

LOAD

2

I

IN

4

DETECTION V1

DETECTION V2

CLASSIFICATION

UVLO
TURN-ON

OFF

dV

=

dt

POWER

DEPENDENT ON R

V

R

LOAD

LTC4257

R

CLASS

V

IN

UVLO

I

LIMIT

C1

BAD

CLASSIFICATION
I

CLASS

DETECTION I

DETECTION I

25kΩ

25kΩ

IN

GND

PWRGD

V

OUT

ON

POWER

GOOD

2

1

CLASS

8

6

5

SELECTION

R9 R

TIME

UVLO
TURN-OFF

TIME

τ = R

LOAD

UVLO

OFF

TIME

POWER

BAD

PWRGD TRACKS
V

IN

CURRENT
LIMIT, I

LOAD CURRENT, I

LOAD

C1

Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage

LIMIT

C1

V

4257 F01

LOAD

GND

OUT

6

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