LINEAR TECHNOLOGY LTC4110 Technical data

LTC4110

Battery Backup

System Manager

FEATURES

n

Complete Backup Battery Manager for Li-Ion/

Polymer, Lead Acid, NiMH/NiCd Batteries and
Super Capacitors

n

Charge and Discharge Battery with Voltages Above

and Below the Input Supply Voltage

n

“No Heat” Battery Calibration Discharge Using

System Load

n

Automatic Battery Backup with Input Supply

Removal Using PowerPath™ Control

n

Standalone for Li-Ion/Polymer, SLA, and Supercaps

n

Optional SMBus/I2C Support Allows Battery

Capacity Calibration Operation with Host

n

Over- and Under-Battery Voltage Protection

n

Adjustable Battery Float Voltage

n

Precision Charge Voltage ±0.5%

n

Programmable Charge/Calibration Current Up to

3A with ±3% Accuracy

n

Optional Temperature Qualifi ed Charging

n

Wide Backup Battery Supply Range: 2.7V to 19V

n

Wide Input Supply Range: 4.5V to 19V

n

38-Lead (5mm × 7mm) QFN Package

APPLICATIONS

n

Backup Battery Systems

n

Server Memory Backup

n

Medical Equipment

n

High Reliability Systems

DESCRIPTION

The LTC®4110 is a complete single chip, high effi ciency,
fl yback battery charge and discharge manager with auto­matic switchover between the input supply and the backup
battery or super capacitor. The IC provides four modes of
operation: battery backup, battery charge, battery calibra­tion and shutdown. Battery backup and battery charge are
automatic standalone modes, while the optional calibration
mode requires a CPU host to communicate over an SMBus.
During calibration the fl yback charger is used in reverse
to discharge the battery with a programmable constant
current into the system load eliminating heat generation.
Three status outputs can be individually reconfi gured over
the SMBus to become GPIOs. User programmable over­discharge protection is provided. The SHDN pin isolates
the battery to support shipping the product with a charged
battery installed.

Multiple LTC4110s can be combined to form a redundant
battery backup system or increase the number of battery
packs to achieve longer backup run times.

The LTC4110 is available in a low profi le (0.75mm), 38-pin

5mm × 7mm QFN package. The QFN features an exposed

metal die mount pad for optimum thermal performance.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.

TYPICAL APPLICATION

Battery Backup System Manager Server Backup System (In Backup Mode)

SYSTEM LOAD

DCIN

0V

UVLO

SET POINT

BACKUP LOAD (DCOUT)

INID BATID

LTC4110

DCDIV

CURRENT FLOW

ON ONOFF

CHGFET

DCHFET

4110 F01

BATTERY

HOST CPU

LTC4110
BATTERY
BACKUP
SYSTEM

MANAGER

CURRENT FLOW

2

I

C BUS

SYSTEM LOAD

(DC/DC, ETC.)

BACKUP LOAD

(MEMORY, ETC.)

BATTERY

4110 TA01b

4110fa

1

LTC4110

(Note 1)

DCIN, BAT, DCOUT, DCDIV, SHDN

to GND ....................................................... –0.3V to 20V

Input Voltage (CLP, CLN) ...............–0.3V to DCIN + 0.3V

Input Voltage (CSP, CSN) ................–0.3V to BAT + 0.3V

Input Voltage

(GPIO1, GPIO2, GPIO3, SELC, SELA, TYPE, V
THA, THB, I

Input Voltage (V

, ACPDLY, SDA, SCL) .... – 0.3V to 7V

SENSE

, V

CAL

) ....................... – 0.3V to 1.35V

DIS

Output Voltage

(ACPb, GPIO1, GPIO2, GPIO3) ................–0.3V to 7V

CLP-CLN, CSP-CSN ..................................................±1V

Operating Temperature Range (Note 2)....–40°C to 85°C

Junction Temperature (Note 3) ............................. 105°C

Storage Temperature Range

QFN Package ......................................–65°C to 125°C

CHG

,

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

TOP VIEW

INID

DCOUTNCBATID

38 37 36 35 34 33 32

1DCIN

CLN

2

CLP

3

ACPDLY

4

DCDIV

5

SHDN

6

SDA

7

SCL

8

GPI01

9

GPI02

10

GPI03

11

SELA

12

13 14 15 16

DIS

V

ACPb

38-LEAD (5mm s 7mm) PLASTIC QFN

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

UHF PACKAGE

T

= 100°C, θJA = 34°C/W

JMAX

V

CAL

39

CHG

V

VDDCHGFET

17 18 19

REF

V

TIMER

DCHFET

31

30

29

28

27

26

25

24

23

22

21

20

TYPE

BAT

SELC

I

SENSE

SGND

CSN

CSP

I

TH

I

CHG

I

CAL

I

PCC

THB

THA

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4110EUHF#PBF LTC4110EUHF#TRPBF 4110

38-Lead (5mm × 7mm) Plastic QFN

LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4110EUHF LTC4110EUHF#TR 4110

38-Lead (5mm × 7mm) Plastic QFN

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

–40°C to 85°C

–40°C to 85°C

2

4110fa

LTC4110

ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
GND = SGND = CLP = CLN = SHDN = 0V and R

VREF

= 25°C. Unless otherwise specifi ed, V

A

= 49.9k. All currents into device pins are positive and all currents out of device pins

are negative. All voltages are referenced to GND, unless otherwise specifi ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Input

DCIN Operating Voltage Range Charge or Calibration Modes

DCOUT Operating Voltage Range Charge or Calibration Modes

Backup Mode

V

BAT

I

SPLY

I

BIDL

I

BBU

I

BSD

V

UVI

V

UVD

V

UVH

Regulator

V

DD

V

DD

V

DD(MIN)

Charging Performance

V

FTO L

V

FATOL

I

BTOL

I

PTO L

I

SKVA

I

SRCA

I

SKCA

I

VCHG

V

BC

V

BCH

V

AR

V

ARH

Operating Voltage Range Backup Mode

Supply Current (I

DCIN

+ I

) in Idle Mode

DCOUT

(Note 4)

Battery Current in Idle Mode (Notes 4 and 5) 30 45 µA

Battery Current in Backup Mode (Note 5) V

Battery Current in Shutdown (Note 5) V

Undervoltage Lockout Exit Threshold V

Undervoltage Lockout Entry Threshold V

= 0 2 3 mA

DCIN

= V

, V

SHDN

Increasing

DCIN

Decreasing

DCIN

BAT

= 0 20 45 µA

DCIN

Undervoltage Lockout Hysteresis 400 mV

Output Voltage No Load

Output Voltage IDD = –10mA

Charge Float Voltage Accuracy 4.20V for Li-Ion. 2.35V for Lead Acid (Note 8)

V

= GND

CHG

–5°C < T
–40°C < T

< 85°C (Note10)

A

< 85°C

A

Charge Float Voltage Adjust Accuracy 0.3V and –0.3V for Li-Ion Batteries,

0.15V and –0.15V for Lead Acid Batteries
(Note 8)

Bulk Charge Current Accuracy (Note 7) V

Preconditioning and Wake-Up Current
Accuracy (Note 7)

– V

CSP

V

BAT

–40°C < T

V

BAT

=100mV

CSN

≥ 3.1V

< 85°C

A

≥ 3.3V (Note 8), V

CSP

– V

= 10mV;

CSN

Li-Ion and NiMH/NiCd Batteries Only

V

≤ 3.3 (Note 8), V

BAT

CSP

– V

= 10mV;

CSN

Li-Ion and NiMH/NiCd Batteries Only

Voltage Error Amplifi er Sink Current at ITH Pin V

Current Error Amplifi er Source Current at ITH

= 2V 96 µA

ITH

V

= 2V –24 µA

ITH

Pin

Current Error Amplifi er Sink Current at ITH Pin V

V

Pin Bias Current V

CHG

Bulk Charge Threshold Voltage;
V

Increasing (Note 8)

BAT

Bulk Charge Threshold Voltage Hysteresis;
V

Decreasing (Note 8)

BAT

Auto Recharge Threshold Voltage;
V

Decreasing

BAT

Auto Recharge Threshold Hysteresis Voltage;
V

Increasing

BAT

= 2V 24 µA

ITH

= 1.25V –100 100 nA

CHG

CHG

= GND

Li-Ion, V
NiMH/NiCd

CHG

= GND

Li-Ion, V
NiMH/NiCd

Standard Li-Ion Only;
Specifi ed as Percentage of Float Voltage 93 95 97 %

Standard Li-Ion Only; Specifi ed as
Percentage of Float Voltage

DCIN

= V

l

l

l

l

DCOUT

= V

DCDIV

= 12V, V

4.5 19 V

4.5 19 V

2.7 19 V

2.7 19 V

23 mA

l

3.7 4 4.45 V

l

3.4 3.7 4.1 V

l

4.5 4.75 5 V

l

4.25 V

–0.5

–0.8

l

–1

l

–2 2 %

–3

l

–5

0.5

0.8
1

3

5

–30 30 %

–40 40 %

2.80

0.84

3.00

0.90

3.20

0.96

85
40

2%

= 8.4V,

BAT

%

%
%

%

%

mV
mV

4110fa

V
V

3

LTC4110

ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
GND = SGND = CLP = CLN = SHDN = 0V and R

VREF

= 25°C. Unless otherwise specifi ed, V

A

= 49.9k. All currents into device pins are positive and all currents out of device pins

are negative. All voltages are referenced to GND, unless otherwise specifi ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

BOV

V

BOVH

V

REF

F

TMR

t

TIMEOUT

Calibration Performance

V

CTOL

V

CTOLH

V

CATOL

I

FTO L

I

VCAL

I

BDT

I

BDH

V

OVP

V

OVPH

AC Present and Discharge Cut-Off Comparators

V

AC

V

ACH

I

AC

t

AC

V

DTOL

V

DTOLH

V

DATOL

I

VDIS

Battery Overvoltage Threshold;
V

Increasing

BAT

All Li-Ion, Lead Acid as Percentage of
Float Voltage
NiMH/NiCd (Note 8)

Battery Overvoltage Threshold Hysteresis;
V

Increasing.

BAT

All Li-Ion, Lead Acid as Percentage of
Float Voltage
NiMH/NiCd (Note 8)

Reference Pin Voltage Range

Programmed Timer Accuracy C

TIMER

= 47nF

Time Between Receiving Valid
ChargingCurrent() and ChargingVoltage()
Commands. Wake-Up Timer.

Calibration Cut-Off Default Voltage Accuracy;
V

Decreasing

BAT

Calibration Cut-Off Default Voltage Hysteresis;
V

Increasing. (Note 8)

BAT

2.75V for Li-Ion, 1.93V for Lead Acid,
V

= GND (Note 8), 0.95V for NiMH/NiCd l

CAL

Li-Ion
Lead Acid
NiMH/NiCd

Calibration Cut-Off Voltage Adjust Accuracy ±400mV for Li-Ion, ±300mV for Lead Acid,

±200mV for NiMH/NiCd (Note 8)

Calibration Current Accuracy (Note 7) V

V

Pin Leakage Current V

CAL

Back-Drive Current Limit Threshold V

Back-Drive Current Limit Threshold Hysteresis V

Calibration Mode Input Overvoltage

– V

CSP

CAL

CLP

V

CLN

CLP

V

CLN

V

DCDIV

= –100mV

CSN

= 1.25V –100 100 nA

– V

Decreasing

CLN

= V

DCIN

– V

Increasing

CLN

= V

DCIN

Rising

Comparator DCDIV Pin Threshold

Calibration Mode Input Overvoltage

V

Falling 100 mV

DCDIV

Comparator DCDIV Pin Hysteresis

AC Present Comparator DCDIV Pin Threshold V

AC Present Comparator DCDIV Pin Hysteresis V

AC Present Comparator DCDIV Pin Input Bias

Falling

DCDIV

Rising 50 mV

DCDIV

V

= 1.25V 100 nA

DCDIV

Current

ACPb Pin Externally Programmed Falling Delay C

Discharge Cut-Off Default Voltage Accuracy;
V

Decreasing

BAT

Discharge Cut-Off Default Voltage Hysteresis;
V

Increasing (Note 8)

BAT

= 100nF, R

ACPDLY

V

Stepped From 1.17V to 1.30V 8 10 12 ms

DCDIV

VREF

= 49.9k,

2.75V for Li-Ion, 1.93V for Lead Acid,
V

= GND, 0.95V for NiMH/NiCd

DIS

Li-Ion
Lead acid
NiMH/NiCd

Discharge Cut-Off Voltage Adjust Accuracy ±400mV for Li-Ion, ±300mV for Lead Acid,

±200mV for NiMH/NiCd

V

Pin Bias Current V

DIS

= 1.25V –100 100 nA

DIS

DCIN

= V

l

l

l

l

l

l

DCOUT

105

1.80

= V

DCDIV

107.5

1.85

2

40

= 12V, V

110

1.90

= 8.4V,

BAT

%

%

mV

1.208 1.220 1.232 V

–15 0 15 %

140 175 210 sec

–1.1
–1.3

85
50
40

1.1

1.3

%
%

mV
mV
mV

–1.5 1.5 %

–5 5 %

71013 mV

1mV

l

1.4 1.5 1.6 V

l

1.196 1.22 1.244 V

l

–1.5 1.5 %

85
50
40

l

22%

mV
mV
mV

V

4

4110fa

LTC4110

ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
GND = SGND = CLP = CLN = SHDN = 0V and R

VREF

= 25°C. Unless otherwise specifi ed, V

A

= 49.9k. All currents into device pins are positive and all currents out of device pins

are negative. All voltages are referenced to GND, unless otherwise specifi ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input and Battery Ideal Diodes and Switches

V

V

V

V

V

FR

REV

GON

GOFF

FO

Forward Regulation Voltage (V
V

BAT-VDCOUT

)

DCIN-VDCOUT

Reverse Voltage Turn-Off Voltage
(V

DCIN-VDCOUT

“ON” Gate Clamping Voltage (V
V

BAT-VBATID

“OFF” Gate Voltage (V

, V

)

BAT-VDCOUT

DCIN-VINID

)

DCIN-VINID

, V

BATID Fast-On Voltage Comparator Threshold I

INID Pin Delay Times

t

IIDON

t

IIDOFF

Turn “ON”
Turn “OFF”

BATID Pin Delay Times

t

BIDON

t

BIDOFF

Turn “ON”
Turn “OFF”

PWM Flyback Converter

V

V

V

OHF

OLF

OLFX

CHGFET, DCHFET High I

CHGFET, DCHFET Low I

CHGFET, DCHFET in Shutdown and Backup
Modes

CHGFET, DCHFET Transition Times

t

R

t

F

F

PWM

Rise Time
Fall Time

PWM Oscillator Switching Frequency

SafetySignal Decoder and Thermistor Interface

SS

OR

SafetySignal Decoder
SafetySignal Trip
(RES_COLD/RES_OR)

SS

CLD

SafetySignal Decoder
SafetySignal Trip
(RES_IDEAL/RES_COLD)

SS

IDL

SafetySignal Decoder
SafetySignal Trip
(RES_HOT/RES_IDEAL)

SS

HOT

SafetySignal Decoder
SafetySignal Trip
(RES_UR/RES_HOT)

V

HOT

V

HOTH

V

REM

THB Pin Hot Threshold Voltage V

THB Pin Hot Threshold Hysteresis Voltage V

THB Pin Battery Removal Threshold Voltage V

,

,

BAT-VBATID

2.7V ≤ V

2.7V ≤ V

I

INID

)I

INID

V

BATID

C

SHDN

INID

≤ 19V

DCIN

≤ 19V

DCIN

, I

= 1μA 7 8.3 9.7 V

BATID

, I

= –10μA

BATID

= 0V and V

(Shutdown)

DCIN

> 500µA 45 100 mV

= 10nF
DCIN is Switched Between 12.2V and 11.8V
From DCOUT – V
From DCOUT – V

C

= 2.5nF

BATID

to DCOUT –6V

GOFF

to DCOUT –1.5V

GON

BAT is Switched Between 12.2V and 11.8V
From DCOUT – V
From DCOUT – V

, I

CHGFET

DCHFET

, I

CHGFET

DCHFET

V

= V

DCIN

Mode), V
I

CHGFET

C
C

R

DCDIV

DCIN

, I

DCHFET

= 1.6nF, 10% to 90%

LOAD

= 1.6nF, 10% to 90%

LOAD

= 1130Ω ±1%, CTH = 1nF (Note 6) R

THA

to DCOUT –6V

GOFF

to DCOUT –1.5V

GON

= –1mA 4.5 4.75 5.25 V

= 1mA 50 mV

= V

= V

= 0V (Shutdown

DCOUT

= 0V (Backup Mode)

DCDIV

= 1µA

= 54.9k ±1%.
Smart Batteries and Li-Ion Only

R

= 1130Ω ±1%, CTH = 1nF (Note 6) R

THA

= 54.9k ±1%
Smart Batteries and Li-Ion Only

R

= 1130Ω ±1%, CTH = 1nF (Note 6) R

THA

= 54.9k ±1%
Smart Batteries and Li-Ion Only

R

= 1130Ω ±1%, CTH = 1nF (Note 6) R

THA

= 54.9k ±1%
Smart Batteries and Li-Ion Only

Decreasing; Lead Acid Only

THB

Increasing; Lead Acid Only 50 mV

THB

Increasing; Lead Acid Only

THB

THB

THB

THB

THB

DCIN

= V

l

l

DCOUT

= V

DCDIV

= 12V, V

10 20 32 mV

–30 –18 –8 mV

0.25 V

450

8

15

8

700

20

60
20

100 mV

35
15

l

255 300 340 kHz

l

95 100 105 k

l

28.5 30 31.5 k

l

2.85 3 3.15 k

l

425 500 575 Ω

l

0.28 •
V

l

0.90 •
V

THA

THA

0.30 •
V

THA

0.94 •
V

THA

65
65

0.36 •
V

THA

0.96 •
V

THA

= 8.4V,

BAT

µs
µs

µs
µs

ns
ns

V

V

4110fa

5

LTC4110

ELECTRICAL CHARACTERISTICS

The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
GND = SGND = CLP = CLN = SHDN = 0V and R

VREF

= 25°C. Unless otherwise specifi ed, V

A

= 49.9k. All currents into device pins are positive and all currents out of device pins

are negative. All voltages are referenced to GND, unless otherwise specifi ed.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

REMH

Logic and Status Output Levels

V

ILS

V

IHS

V

OLS

V

OLG

I

OHG

V

ILG

V

IHG

V

ILSD

V

IHSD

I

ISD

T

LR

SMBus Timing (Note 9)

t

HIGH

t

LOW

t

TO

t

F

t

SU-STA

t

HD-STA

t

HD-DAT

THB Pin Battery Removal Threshold

V

Decreasing; Lead Acid Only 25 mV

THB

Hysteresis Voltage

SCL/SDA Input Pins Low Voltage

SCL/SDA Input Pins High Voltage

SDA Output Pin Low Voltage I

ACPb, GPIO1,2,3 Output Pins Low Voltage I

PULL-UP

, I

ACPb

= 350µA

, I

GPIO1

GPIO2

, I

= 10mA 1 V

GPIO3

ACPb, GPIO1,2,3 Output Pins Open
Leakage Current Outputs Open, V

ACPb

, V

GPIO1,2,3

= 5V –2 2 µA

GPIO Input Low Voltage

GPIO Input High Voltage

SHDN Input Pin Low Voltage 0.5 V

SHDN Input Pin High Voltage 2.4 V

SHDN Input Pin Pull-Up Current V

Logic Reset Duration After Power-Up
From Zero

SCL Serial Clock High Period I

SCL Serial Clock Low Period I

= 2.4V –3.5 –2 –1 µA

SHDN

V

Transition From 0V to 5V in <1ms;

DCIN

V

= 0

BAT

PULL-UP

R

= 9.31k

PU

PULL-UP

R

= 9.31k

PU

= 350µA, C

= 350µA, C

LOAD

LOAD

= 250pF,

= 250pF,

Timeout Period

SDA/SCL Fall Time C

= 250pF, RPU = 9.31k

LOAD

Start Condition Set-Up Time

Start Condition Hold Time

SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data

DCIN

= V

l

l

l

l

l

DCOUT

= V

DCDIV

= 12V, V

= 8.4V,

BAT

0.8 V

2.1 V

0.4 V

1V

1.5 V

1s

l

4µs

l

4.7 µs

l

25 ms

l

l

4.7 µs

l

4µs

l

300 ns

300 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Specifi c functionality or parametric performance
of the device beyond the limits expressly given in the Electrical
Characteristics table is not implied by these maximum ratings.

Note 2: The LTC4110E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Overtemperature protection will become active at a junction temperature
greater than the maximum operating junction temperature. Continuous
operation above the specifi ed maximum operation temperature may result
in device degradation or failure. Operating junction temperature T
°C) is calculated from the ambient temperature T
dissipation P

(in watts) by the formula TJ = TA + θ

D

and the average power

A

• PD.

JA

J

(in

6

Note 4: The LTC4110 is idle with no application load. It is not charging
or calibrating the battery and is not in backup or shutdown mode. The
internal clock is running and the SMBus is functional.

Note 5: Combined current of CSP, CSN and BAT pins set to V

with no

BAT

application load.
Note 6: C

is defi ned as the sum of capacitance on THA, THB

TH

SafetySignal.
Note 7: Does not include tolerance of current sense or current

programming resistors.
Note 8: Given as a per cell voltage referred to the BAT pin (V

/number of

BAT

series cells).
Note 9: Refer to System Management Bus Specifi cation, Revision 1.1,

section 2.1 for Timing Diagrams and section 8.1, for t

LOW

and t

TIMEOUT

requirements.
Note 10: Specifi cations over the –5°C to 85°C operating ambient

temperature range are assured by design, characterization and correlation
with statistical process controls.

4110fa

TYPICAL PERFORMANCE CHARACTERISTICS

Output Charging Characteristics
Typical CHGFET and DCHFET
Waveforms

Showing Constant Current and

Constant Voltage Operation

1200

1000

CC

LTC4110

Supply Current vs DCIN Voltage in
Idle Mode

2.5

2.0

5V/DIV

0V

= 12V

V

IN

= 12V (NiMH)

V

BAT

500ns/DIV

Battery Leakage in Idle
Mode – IBIDL

140

120

100

80

(µA)

60

BAT

I

40

20

0

–20

0 5 10 15 2520

V

BAT

(V)

4110 G01

4110 G04

800

(mA)

600

BAT

I

400

PRE-CHARGE

200

0

042 6 8 101214

Battery Current in Backup

Mode – IBBU

1.8

1.6

1.4

1.2

1.0

(mA)

0.8

BAT

I

0.6

0.4

0.2

0

0 5 10 15 2520

Charging Effi ciency/Power Loss,
12VIN and 12.6V

(Xfmr = BH

OUT

510-1019) Soft-Start Waveform

100

90

80

70

60

50

40

EFFICIENCY (%)

30

20

10

0

0.05 0.20.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00

EFFICIENCY

I

POWER LOSS

(A)

LOAD

4110 G07

2.5

2.0

POWER LOSS (W)

1.5

1.0

0.5

0

0.2A/DIV

0A

V

V

BAT

BAT

(V)

(V)

2ms/DIV

CV

4110 G02

4110 G05

4110 G08

1.5

(mA)

DCIN

I

1.0

0.5

0

0 5 10 15 20

DCIN (V)

Battery Leakage in Shutdown
Mode vs Battery Voltage

40

35

30

25

(µA)

20

BAT

I

15

10

5

0

0

15

V

(V)

BAT

Backup Mode On and Off
Waveform

V

BACKUP

2V/DIV

V

BATTERY

3V/DIV

0V

NiMH BATTERY (12V)

= 3A

I

LOAD

= 15V FALLING

V

IN

10ms/DIV

4110 G03

2520105

4110 G06

4110 G09

4110fa

7

LTC4110

PIN FUNCTIONS

DCIN (Pin 1): External DC Power Sense Input. Provides a
control input and supply for the main supply ideal diode
function.

CLN (Pin 2): Current Limit Sense Negative Input. See
CLP pin.

CLP (Pin 3): Current Limit Sense Positive Input. This pin
and the CLN pin form a differential input that senses volt­age on an external resistor for reverse current entering the
power source while in low loss calibration mode. Should
the current approach reversal, this function will terminate
calibration. An RC fi lter may be required to fi lter out system
load noise. Connect both CLP and CLN pins to GND to
disable this function. A differential voltage of >1V between
the CLP and CLN pins may damage the device.

ACPDLY (Pin 4): ACPb Delay Control Pin. A capacitor
connected from ACPDLY to GND and a resistor from

to GND programs delay in the ACPb pin high-to-low

V

REF

transition. Open if minimum delay is desired.

DCDIV (Pin 5): AC Present Detection Input. Backup
operation is invoked when the system power voltage,
divided by an external resistor divider, falls below the
threshold of this pin.

SHDN (Pin 6): Active High Shutdown/Reset Control Logic
Input. Forces micropower shutdown mode if high when
DCIN supply is removed. Forces all registers to reset if high
when DCIN supply is present. Normally tied to ground.
Internal pin pull-up current.

SDA (Pin 7): SMBus Bidirectional Data Signal. Connect

when not in use.

to V

DD

SCL (Pin 8): SMBus Clock Signal Input From SMBus Host.
Connect to V

GPIO1 (Pin 9): General Purpose I/O or Charge Status Pin. A
logic-level I/O bit port that is confi gurable as a host-driven
input/output port or as a battery charge status output (CHGb)
with an open-drain N-MOSFET that is asserted low when any

when not in use.

DD

smart battery or Li-Ion battery is in any phase of charging
or when lead acid battery charge current is >C/x where:

C

x

= •5

I

(See C/x Charge Termination section for more details).
If the No SMBus option is selected with the SELA pin,
the GPIO1 pin defaults as battery charge status. Refer
to Table 5a.

GPIO2 (Pin 10): General Purpose I/O Pin. A logic-level I/O bit
port that is confi gurable as a host-driven input/output port
or as a battery undervoltage status output (BKUP_FLTb)
with an open-drain N-MOSFET that is asserted low only
while in backup mode if the battery’s average cell voltage
drops below voltage programmed by the V
No SMBus option is selected with the SELA pin, then the
GPIO2 pin defaults as battery undervoltage status. Refer
to Table 5c.

GPIO3 (Pin 11): General Purpose I/O Pin. A logic-level I/O
bit port that is confi gurable as a host-driven input/output
port or as a calibration complete status output (CAL_COM­PLETEb) with an open-drain N-MOSFET that is asserted
low when calibration has been completed. If the SELA pin
is programmed for no SMBus use then the status output
is charge fault (CHGFLTb) instead of calibration complete.
Refer to Table 5e.

SELA (Pin 12): SMBus Address Selection Input. Selects
the LTC4110 SMBus address to facilitate redundant backup
systems when standard batteries are used. Connect to
GND for 12h, V
a smart battery is selected by the TYPE pin, the SELA pin
must be connected to GND to select address 12h. If the
SMBus is not used or to force all GPIOs to status mode
upon power-up, connect pin to a typically 0.5 • V
age from V
if used, will be 12h.

CHG

DIS

for 28h and the V

DD

pin resistor divider. The SMBus address,

REF

pin for 20h. When

REF

pin. If the

volt-

REF

8

4110fa

PIN FUNCTIONS

LTC4110

ACPb (Pin 13): AC Present Status Digital Output. Open­Drain N-MOSFET output is asserted low when the main
supply is present as detected by the DCDIV pin and internal
DCIN UVLO.

(Pin 14): Battery Discharge Voltage Limit During

V

DIS

Backup Program Input. Battery threshold voltage at which
backup mode will terminate by turning off the isolation
P-MOSFET with the BATID pin. Adjustable from external
resistor string biased from V

pin. For default threshold

REF

connect to GND pin.

(Pin 15): Battery Voltage Limit During Calibra-

V

CAL

tion Program Input. Battery threshold voltage at which
calibration will terminate. Adjustable from external resistor
string biased from V

pin. For default threshold connect

REF

to GND pin.

(Pin 16): Battery Float Voltage Program Input. Trims

V

CHG

the fl oat voltage during charging. Programmed from
external resistor string biased from V

pin. Connect to

REF

GND for default fl oat voltage.

(Pin 17): Voltage Reference Output and Timing Pro-

V

REF

gramming Input. Provides a typical virtual reference of 1.220V
(V

) for an external resistor divider tied between this pin and

REF

GND that programs the V
Total resistance from V

, V

CAL

and V

CHG

to GND, along with the capacitor

REF

pin functions.

DIS

on the timer pin, programs the charge time. Voltage refer­ence output remains active in all modes except shutdown.
Load current must be between 10µA and 25µA.

TIMER (Pin 18): Charge Timing Input. A capacitor con­nected between TIMER and GND along with the resistance
connected from V

to GND programs the charge time

REF

intervals.

TYPE (Pin 19): Refer to Table 8.

THA (Pin 20): SafetySignal Force/Sense Pin to Smart

Battery and Force Pin to Lead Acid Battery Thermistor.
See description of operation for more detail. The maxi­mum allowed combined capacitance on THA, THB and
SafetySignal is 1nF. For lead acid battery applications the
maximum capacitance on the THA pin is 50pF.

THB (Pin 21): SafetySignal Force/Sense Pin to Smart
Battery and Sense Pin to Lead Acid Battery Thermistor.
See description of operation for more detail. The maxi­mum allowed combined capacitance on THA, THB and
SafetySignal is 1nF.

I

(Pin 22): Battery Preconditioning Charge Current

PCC

Program Input. Programs the battery current during
preconditioning or wakeup charging. Programmed from
external resistor to GND.

(Pin 23): Battery Discharge Current During Calibration

I

CAL

Program Input. Programs the constant discharge current at
the battery during calibration. Programmed from external
resistor to GND.

(Pin 24): Battery Current During Charge Program Input.

I

CHG

Programs the battery current while constant-current bulk
charging. Programmed from external resistor to GND.

(Pin 25): Control Signal of the Current Mode PWM. AC

I

TH

compensates control loop. Higher I

voltage corresponds

TH

to higher charging current.

CSP (Pin 26): Current Sense Positive Input. This pin and
the CSN pin measure voltage across the external current
sense resistor to control battery current during charging
and calibration.

CSN (Pin 27): Current Sense Negative Input. This pin and
the CSP pin measure voltage across the external current
sense resistor to control battery current during charging
and calibration.

SGND (Pin 28): Signal Ground Reference Input. This pin
should be Kelvin connected to the fl yback current sense
resistor and to the battery return.

(Pin 29): Current Sense Input. Senses current in

I

SENSE

the fl yback transformer by monitoring voltage across the
external current sense resistor. This pin should be Kelvin­connected to the resistor.

SELC (Pin 30): Refer to Table 8.

4110fa

9

LTC4110

PIN FUNCTIONS

BAT (Pin 31): Battery Voltage Sense Input. This pin is used
to monitor the battery and control charging voltage through
an internal resistor divider connected to this pin that is
disconnected in shutdown mode. Also provides a control
input for battery ideal diode functions. Pin should be Kelvin­connected to battery to avoid voltage drop errors.

DCHFET (Pin 32): Drives the Gate of an External N-MOSFET.
Used to drive energy into the battery side of the high ef­fi ciency switch mode converter during low loss calibration
discharge of the battery. Provides synchronous rectifi cation
during battery charging.

CHGFET (Pin 33): Drives the Gate of an External N­MOSFET. Used to drive energy into the supply side of
the high effi ciency switch mode converter during battery
charging. Provides synchronous rectifi cation during low
loss calibration mode.

(Pin 34): Bypass Capacitor Connection for Internal

V

DD

VDD Regulator. Bypass at pin with 100nF low ESR capaci­tor to GND.

BATID (Pin 35): Drives the Gate of the Battery P-MOSFET
Ideal Diode. Controls low loss ideal diode between the
battery and backup load when in backup mode. When not
in backup mode, the P-MOSFET is turned off to prevent
battery power from back driving into main power.

NC (Pin 36): No Connect.

DCOUT (Pin 37): System Power Output Voltage Monitor

Input. Provides a control input for supply input ideal diode
and battery ideal diode functions. Also supplies power to the
IC. Bypass at pin with 100nF low ESR capacitor to GND.

INID (Pin 38): Drives the Gate of the Supply Input P-MOSFET
Ideal Diode. Controls low loss ideal diode between the sup­ply input and backup load when not in backup mode.

Exposed Pad (Pin 39): Ground. The Exposed Pad must
be soldered to the PCB.

10

4110fa

BLOCK DIAGRAM

38INID

1DCIN

39GND

34V

DD

3CLP

2CLN

5DCDIV

17V

REF

16V

CHG

15V

CAL

14V

DIS

30SELC

SUPPLY INPUT BATTERY

PowerPath CONTROLLER

V

DD

REGULATOR

VOLTAGE REFERENCE

ANALOG COMPARATORS

AND SWITCHES

OF CELLS

NUMBER

PRECISION

VOLTAGE DIVIDER

–

EA

+

–

÷10

+

PROGRAMMING CURRENT

CURRENT

SELECTION

1.220

CA

CURRENT

SWITCH

PWM

LOGIC

–
+

CHG/DCH

SWITCH

37 DCOUT

36 NC

35 BATID

31 BAT

27 CSN

26 CSP

22 I

PCC

24 I

CHG

23 I

CAL

25 I

TH

33 CHGFET

32 DCHFET

29 I

SENSE

28 SGND

LTC4110

19TYPE

6SHDN

7SDA

8SCL

12SELA

20THA

21THB

SMBus

INTERFACE

AND CONTROL

THERMISTOR

INTERFACE

TIMER/

CONTROLLER

OSC

UVLO

18 TIMER

4 ACPDLY

13 ACPb

9 GPIO1

10 GPIO2

11 GPIO3

4110 BD

4110fa

11

LTC4110

OPERATION

OVERVIEW

In the typical application, the LTC4110 is placed in series
with main power supply that powers all or part of the
system, which must include the device(s) or system that
needs battery backup.

The LTC4110 has four modes of operation:

• Battery Backup Mode

• Battery Charge Mode

• Battery Calibration Mode

• Shutdown Mode

The LTC4110 provides complete PowerPath control for
the battery backed up load switching automatically from
the main power supply to the battery when battery backup
mode is required. Low loss ideal diode FET switches are
used to connect the main supply or the battery to the
backup load which permit multiple LTC4110’s to work
together in a scalable fashion to permit longer backup
times, redundancy and/or higher load currents. In battery
charge mode, power is drawn from the main supply by a
high effi ciency synchronous fl yback charger. The LTC4110
maintains the state of charge (SOC) of the battery at all
times so the battery is ready at all times. Use of a fl yback
converter permits charging of batteries who’s termination
voltage can be greater than the main supply voltage, while
at the same time providing high DC isolation to minimize
parasitic drain on the battery. Testing, maintenance support
and capacity verifi cation of the battery is supported through
the LTC4110’s calibration mode. In calibration mode, the
same synchronous fl yback used to charge the battery is

also used in reverse to allow safe controlled discharge of
the battery back into the main supply eliminating wasted
heat and energy. The product will not need to provide any
additional thermal management to support this mode.
Shutdown mode disconnects the battery from the load to
preserve capacity and permits shipping the product with
an energized battery installed at the factory, eliminating
battery installation at the site. The LTC4110 supports
optional control and monitoring of all activities by a host
including faults over the industry standard SMBus, which

2

is a variation of the I

C bus. However no host is required
as the LTC4110 is fully functional in a standalone mode.
Combining all these functions into a single IC reduces
circuit area compared to presently available solutions.

The LTC4110 is designed to work with both standard
battery and smart battery confi gurations. Smart batteries
are standard batteries with industry standard gas gauge
electronics built in offering accurate SOC information for
the host. Furthermore, being intimate with all aspects of
the battery, it also has the ability to control the charge
process. Smart batteries use the SMBus as the com­munication bus for data exchange and charge control.
For more information about smart batteries, see www.
sbs-forum.org for specifi cations or contact Linear Tech­nology Applications.

It is important to know that the LTC4110 uses the TYPE
pin to learn what type of battery it will be working with.
The TYPE pin setting globally affects all of the operating
modes, options including GPIO and control ranges. Table 1
and Table 2 give you a complete breakdown of all the
battery types supported relative to the TYPE pin settings

Table 1. LTC4110 Battery Pack Charge Mode Capabilities

BATTERY TYPE CHEMISTRY MAXIMUM CHARGE TIME (SLA EXCLUDED)

Li-Ion/Polymer Nickel SLA/Lead Acid

Standard Battery Yes No Yes Adj. Up to 12 Hours

Smart Battery Yes Yes Yes Unlimited

Table 2. LTC4110 Battery Pack Charge Voltage Capabilities

CHEMISTRY V

Lead Acid 2.35V ±0.15V 2, 3, 5 and 6 4, 6, 10 and 12

Li-Ion/Polymer 4.2V ±0.3V 1, 2, 3 and 4 3.6, 7.2, 10.8 and 14.4

NiMH/NiCd N/A N/A 4, 6, 9 and 10 4.8, 7.2, 10.8 and 12

Super Caps 2.5V, 2.7V or 3V Yes 2 to 7 5 to 18

FULL CHARGE V

CELL

ADJ. RANGE SERIES CELL COUNT NOMINAL STACK VOLTAGE (V)

CELL

4110fa

12

OPERATION

LTC4110

and ranges. It should be noted that even if the LTC4110
TYPE pin is not set to a smart battery mode, any SMBus
commands sent by a host or a smart battery are still
acted upon. For SuperCap support, see the Applications
Information section.

BATTERY BACKUP MODE

Figure 1 shows the LTC4110 in backup mode and the
corresponding PowerPath enabled. The LTC4110 use the
DCDIV pin to typically monitor the DCIN voltage through
an external resistor divider. The DCDIV pin sets the backup
mode threshold voltage and senses the need to enter
backup mode. DCDIV can alternately be driven with other
signals such as logic. When the DCDIV pin voltage drops
below the AC present threshold voltage (see V

) backup

AC

mode is entered. Backup mode is also entered whenever
the internal undervoltage lockout, UVLO, senses that DCIN

) or DCOUT has fallen to excessively low voltages.

(V

UVD

In backup mode the battery P-MOSFET ideal diode is
enabled to backup the load from the battery. The supply
input P-MOSFET ideal diode isolates the main supply
input from the load and the fl yback switcher N-MOSFETs
are inhibited from turning on. Also, after the threshold is
passed, hysteresis (V

) is switched in. When the supply

ACH

is returning and the AC present threshold voltage plus the
hysteresis voltage is reached on the DCDIV pin, both of the
battery P-MOSFETs are rapidly switched off (t

dDOFF

) and
the supply input P-MOSFET ideal diode provides the load
current. When forward biased, the ideal diodes regulate
their forward voltage drop to 20mV typical (V

SYSTEM LOAD

DCIN

0V

UVLO

SET POINT

BACKUP LOAD (DCOUT)

CURRENT FLOW

ON ONOFF

INID BATID

DCDIV

LTC4110

Figure 1. Backup Mode Operation

CHGFET

DCHFET

) when the

FR

BATTERY

4110 F01

MOSFET is suffi ciently sized. If the voltage input falls and
results in a forward voltage below 20mV, then the ideal
diode will begin turning off at a slow rate. Should the ideal
diode see a –18mV typical (V
the ideal diode will turn off quickly (t

) or lower reverse voltage,

REV

).

dDOFF

While in backup, the battery’s average cell voltage is moni­tored to protect the battery from excessive discharge. If
the cell voltage drops below the value programmed by the

pin (Li-Ion default = 2.75V/cell, NiMH/NiCd default

V

DIS

= 0.95V/cell, lead acid default = 1.93V/cell), the battery
P-MOSFETs are rapidly turned off and the battery is dis­connected from the load. If DCIN is above UVLO, the load
and the LTC4110 will be powered from the supply input. If
DCIN is below UVLO, the LTC4110 enters the micropower
shutdown mode (see the Shutdown Mode section for more
details). Also, the SMBus accessible BKUP_FLT fault bit
is set and maintained as long as suffi cient battery voltage
is present (V

≥ 2.7V). This fault bit can be read after

BAT

DCIN returns to a voltage level exceeding the internal
UVLO threshold (see V

) and DCOUT has regained suf-

UVI

fi cient voltage (see DCOUT) to provide internal power. If
the GPIO2 port is programmed as the BKUP_FLTb status
output after DCIN returns, it will be forced low to repre­sent an inverted BKUP_FLT bit. When DCIN returns, as
sensed by the UVLO, the shutdown mode is automatically
cancelled and normal operation can resume, however, the
BKUP_FLT bit remains set until either the SHDN pin is set
high (all registers reset) or register bits POR_RESET or
BUFLT_RST are set. See the Shutdown Mode section for
details. During backup, the external thermistor network
is monitored for battery presence.

BATTERY CHARGE MODE

Figure 2 shows the charge path to charge a battery. Cur­rent is pulled from the supply input to charge the battery.
At the same time, the input supply provides power to
both the system load and the backup load. The battery
is isolated from the load at all times so it cannot affect
charger terminations algorithms.

If we ignore battery chemistry for a moment, as far as the
LTC4110 charger is concerned, there are only two basic
charge modes. When the TYPE pin selects a standard bat­tery mode, charge termination is controlled by the LTC4110

4110fa

13

LTC4110

OPERATION

BACKUP LOADSYSTEM LOAD

DCIN

OFF OFFON

CURRENT FLOW

INID BATID

LTC4110

Figure 2. Charge Mode Operation

CHGFET

DCHFET

BATTERY

4110 F02

for the battery chemistry selected. Specifi cally the TIMER
pin becomes active and used to detect faults conditions or
terminate the charge cycle itself as needed. Smart battery
SMBus charge control commands are still honored if any
are sent at any time. A smart battery can safely function
in a standard battery mode if identical in chemistry and
voltage confi guration as the standard battery. When the
TYPE pin selects a smart battery mode, this simply disables
the TIMER pin and its function in charge termination. The
smart battery is able to restart or terminate a charge cycle
at any time using charge commands over the SMBus. This
mode also enables smart battery wake-up and watchdog
functions based on t

TIMEOUT

per the smart battery stan­dards. However it is not recommended to use a standard
battery with a LTC4110 confi gured for smart battery mode
operation. You can shorten battery life, damage or destroy
the battery. In the extreme case this can cause an explosion
since no charge termination mechanisms are active.

The following sections explain detailed operation for each
charge mode as selected by the TYPE pin.

STANDARD LI-ION/POLYMER BATTERY CHARGE MODE

The charger is programmed for standard Li-Ion batteries by
connecting the TYPE pin to GND. During Li-Ion charging,
the LTC4110 operates as a high effi ciency, synchronous,
PWM fl yback battery charger with constant-current and
constant fl oat voltage regions of operation. The constant­charge current is programmed by the combination of a
resistor (R

) from the I

CHG

pin to ground, a battery

CHG

current sense resistor (R

SNS(BAT)

) and CSP/CSN pin resis­tors. The constant voltage (fl oat voltage) is programmed
to one of four values (4.2V, 8.4V, 12.6V, 16.8V) depending
on the number of series cells using the SELC pin and can
be adjusted ±0.3V/cell with the V

pin. If adjusted, the

CHG

auto recharge threshold and overvoltage threshold will
track proportionally.

The charge cycle begins when the supply input is present
as sensed by the DCDIV pin and DCIN above UVLO, the
battery cell voltage is below the auto recharge threshold
(95% of the programmed fl oat voltage; see V

), thermis-

AR

tor temperature is within ideal limits, COLD, under range
(see SafetySignal Decoder section) or is optioned out and
the register bit CHARGE_INHIBIT is cleared (see Tables 6
and 7 for register details).

Soft-start ramps the charge current at a rate set by the
capacitor on the I

pin. When charging begins, the pro-

TH

grammable timer initiates timing and the CHGb (GPIO1
pin) status output is pulled LOW. An external capacitor
on the TIMER pin, along with the current set by the total
series resistance connected to the V

pin, sets the total

REF

charge time.

If the battery voltage is less than the 3.0V/cell bulk charge
threshold (V

), the charger will begin with a precondition-

BC

ing trickle charge current. The trickle current is programmed
by the resistor (R

) from the I

PCC

pin to ground. During

PCC

preconditioning trickle charging, if the battery voltage
stays below the bulk charge threshold (V

) 25% of the

BC

programmed bulk charge time, the battery may be defective
and the charge sequence will be terminated immediately.
To indicate this fault, the CHGb (GPIO1 pin) becomes high
impedance, the CHG_STATE_0 and CHG_STATE_1 register
bits will be set low and CHG_FLT register bit will be set
high. Charge is terminated and the timer reset until the
fault is cleared by the RESET_TO_ZERO or POR_RESET
SMBus write commands, SHDN pin toggle or the battery
removed and replaced. Removing the supply input will
not clear the fault if the battery is present.

If the battery voltage exceeds 107.5% (V

) of the

BOV

programmed fl oat voltage during any stage of charge,
the charger pauses until the voltage drops below the
hysteresis (V

). The timer is not stopped and no fault

BOVH

is indicated.

4110fa

14

OPERATION

LTC4110

14

ANY

CHARGE

STAT E

8

PWM

STOPPED

(BATTERY OVP)

STOP

CHARGE

(OVERTEMPERATURE)

RESUME

CHARGE

STAT E

RESET

15

9

1

PRE-CONDITIONING

CHARGE

5 (PRE-CONDITIONING FAULT)

23

ANY

CHARGE

STAT E

11 (BATTERY NEEDS RECHARGE)

6 (BULK TIME FAULT)

BULK

CHARGE

Figure 3. Standard Li-Ion Charge State Diagram (Does Not Include Calibration)

# Logic Event (T = True, F = False) [Notes] Notes and/or Actions (T = True, F = False)

I

1

RES_OR = F & DCDIV pin = T & SHDN pin = F &
CHARGE_INHIBITED = F & CHG_FLT = F & V

Or

RES_OR = F & DCDIV pin = T & SHDN pin = F &

BAT

< V

BC

CHARGE_INHIBITED = F & CHG_FLT=F &
ChargingVoltage() ≠ 0 & ChargingCurrent() ≠ 0

2V

BAT

> V

BC

3 C/5 = T Timer(Bulk) = Stopped & Timer/4(Top Off) = Started

4 Timer/4(Top Off = done [Battery is full] I

5 Timer/4(PreCond) = done before V

BAT

> V

BC

6 Timer(Bulk) = done before C/5 = T I

7

RESET_TO_ZERO = T [See ChargeMode()]

Or

CHARGE_INHIBIT=T [See ChargeMode()]

8 RES_HOT = T & RES_UR = F [See ChargeStatus()] I

9 RES_HOT = F [See ChargeStatus()] I

10

11

12

DCDIV pin = F

Or

RES_OR = T [Bat Removed, See ChargeStatus()]

Or

SHDN pin = T

Or

V

= T

UVD

Or

POR_RESET = T [See ChargeMode()]

V

= T [AutoRestart]

AR

Or

ChargingVoltage() & ChargingCurrent() ≠ 0

AlarmWarning() command is sent by Smart Battery over
SMBus with any of the following bits set to True:
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM

Or

Reserved ALARM

Or

OVER_TEMPERATURE_ALARM

Or

13 ChargingVoltage() or ChargingCurrent() = 0 sent I

14 V

15 V

Note: For all charge states, V

= T [Battery Overvoltage] PWM stopped. Timers remain running.

BOV

= F PWM restarted.

BOV

is always active.

CHG

& Timer/4(PreCond) = Started & CHG = T & ALARM_INHIBITED = F

PPC

(RES_OR = F = Bat Inserted -> See ChargeStatus() )
(POR_RESET -> See ChargeMode()

I

= Off & I

PPC

= Off & CHG = F (Typical Full State)

CHG

I

= Off & CHG_FLT = T & CHG = F

PPC

= Off & CHG_FLT = T & CHG = F

CHG

or IPPC = Off & All Timers = Reset & CHG_FLT = F & CHG = F

I

CHG

or I

CHG

or I

CHG

or I

I

CHG

= On & Timer/4(PreCond) = Stopped & Timer(Bulk) = Started.

CHG

= Off & CHG_FLT = T, Timers paused.

PPC

= On & CHG_FLT = F, Timers resume.

PPC

= Off & All Timers = Reset & ALARM_INHIBITED = F & CHG_FLT =

PPC

F & CHG = F & CHARGE_INHIBITED = F

(The battery needs another charge cycle or Smart Battery has requested to
start another cycle.)

I

or I

CHG

= Off & All Timers = Reset & CHG = F & ALARM_INHIBITED = T

PPC

(ALARM_INHIBITED bit is found in ChargeStatus())

or I

CHG

= Off & CHG = F

PPC

7, 12, 1310

STOP

CHARGE

4 (BATTERY FULL)

TOP-OFF

CHARGE

4110 F03

4110fa

15

LTC4110

OPERATION

When the battery voltage exceeds the bulk charge threshold

), the charger begins the bulk charge portion of the

(V

BC

charge cycle. As the battery accepts charge, the voltage
increases. Constant-current charge continues until the
battery approaches the constant voltage. At this time, the
charge current will begin to drop, signaling the beginning
of the constant-voltage portion of the charge cycle.

The charger will maintain the constant voltage across the bat­tery until either C/x is reached or 100% of the programmed
bulk charge time has elapsed during bulk charge. When
the current drops to approximately 20% of the full-scale
charge current, an internal C/x comparator will initiate the
start of the top-off stage. The top-off stage charges for
25% of the total programmed bulk charge time. When the
time elapses, charge is terminated and CHGb (GPIO1 pin)
is forced to a high impedance state and CHG_STATE_0 and
CHG_STATE_1 register bits will be set low. Should the total
bulk charge time elapse before C/x is reached, charge is
terminated and a CHG_FLT fault is indicated until cleared
by the RESET_TO_ZERO or POR_RESET SMBus write
commands, SHDN pin toggle or the battery removed and
replaced. Fault conditions are not cleared when the supply
input is removed if the battery has suffi cient voltage.

An optional external thermistor network is sampled at
regular intervals to monitor battery temperature and to
detect battery presence. If the thermistor temperature is
hot (see the SafetySignal Decoder section), the charge
timer is paused, charge current is halted, CHG_FLTb (GPIO3
pin) is forced low and the CHG_FLT bit will be set high.
CHGb (GPIO1 pin) , CHG_STATE_0 and CHG_STATE_1
register bits will not be affected. When the thermistor
value returns to an acceptable value, charging resumes,
CHG_FLTb (GPIO3 pin) returns to high impedance and the
CHG_FLT bit will be reset low. An open thermistor indicates
absence of a battery. To defeat the temperature monitoring
function, replace the thermistor with a resistor to indicate
ideal battery temperature. When a thermistor is not used,
the resistor circuit must be routed through the battery
connector if battery presence detection is required.

After a charge cycle has ended without fault, the charge
cycle is automatically restarted if the average battery cell
voltage falls below the auto recharge threshold. At any

time charging can be forced to stop by pulling the SHDN
pin high or setting the CHARGE_INHIBIT bit high through
the SMBus.

SMART BATTERY CHARGE MODE

This section explains operation for smart batteries with a
SMBus interface. Smart Li-Ion is selected by connecting
the TYPE pin to the V
is selected by connecting the TYPE pin to the V
The LTC4110 only implements a subset of smart battery
charger commands; the actual charging algorithm is
determined by LTC4110 through external resistors even
if the battery is “smart.”

The LTC4110 operates as a high effi ciency, synchronous,
PWM fl yback battery charger with constant current and
constant fl oat voltage regions of operation. The constant­charge current is programmed by the combination of a
resistor (R
current sense resistor (R
resistors. For Li-Ion the constant voltage (fl oat voltage)
is programmed to one of four values (4.2V, 8.4V, 12.6V,

16.8V) depending on the number of series cells using the
SELC pin and can be adjusted ±0.3V/cell with the V
pin. For nickel batteries the constant-voltage function is
not used, however, a non-zero value is still required to be
written to the ChargingVoltage() register. The internal auto
recharge function is inhibited for smart batteries.

If the battery voltage exceeds 107.5% (V
programmed fl oat voltage during any stage of charge,
the charger pauses until the voltage drops below the
hysteresis (V
is indicated. This function is disabled when nickel based
smart batteries are used.

There are four states associated with smart battery charge
mode, namely:

• SMBus Wake-Up Charge State

• SMBus Preconditioning Charge State

• SMBus Bulk Charge State

• SMBus OFF State
These states are explained in the following four sections.

) from the I

CHG

BOVH

pin and smart Nickel (NiMH/NiCd)

DD

pin.

REF

pin to ground, a battery

CHG

SNS(BAT)

). The timer is not stopped and no fault

) and CSP/CSN pin

CHG

) of the

BOV

16

4110fa

OPERATION

LTC4110

11

ANY

CHARGE

STAT E

8

PWM

STOPPED

(BATTERY OVP)

OFF

(OVERTEMPERATURE)

RESUME

CURRENT

STAT E

WAKE UP

CHARGE

12

9

2 4, 7, 13, 14

PRE-CONDITIONING

CHARGE

1

3

6 (BATTERY RECHARGE REQUEST)

RESET

BULK

CHARGE

5 (BAD BATTERY)

10

4

(BATTERY

FULL)

ANY

CHARGE

STAT E

OFF

Figure 4. Smart Battery Charge State Diagram (Does Not Include Calibration)

# Logic Event (T = True, F = False) [Notes] Notes and/or Actions (T = True, F = False)

I

1

RES_OR = F & DCDIV pin = T & SHDN pin = F &
CHARGE_INHIBITED = F & CHG_FLT = F & RES_HOT = F

Or

RES_OR = F & DCDIV pin = T & SHDN pin = F &
CHARGE_INHIBITED = F & CHG_FLT = F & RES_HOT = T &
RES_UR = T

2 ChargingVoltage() & ChargingCurrent() ≠ 0 sent Timer/4(Pre-Charge) = Started & TTIMEOUT disabled & ALARM_

3V

BAT

> V

BC

4 ChargingVoltage() or ChargingCurrent() = 0 sent I

5 Timer/4(Pre-Charge) = Done before V

BAT

> V

BC

6 ChargingVoltage() & ChargingCurrent() ≠ 0 sent & RES_OR = F

& DCDIV pin = T & SHDN pin = F & CHARGE_INHIBITED = F &
CHG_FLT = F

7 TTIMEOUT = Done (Dead Battery or Loss of SMBus) I

8 RES_HOT = T & RES_UR = F [See ChargeStatus()] I

9 RES_HOT = F [See ChargeStatus()] I

10

11 V

12 V

13

14

DCDIV pin = F

Or

RES_OR = T [Bat Removed, See ChargeStatus()]

Or

SHDN pin = T

Or

V

= T

UVD

Or

POR_RESET = T [See ChargeMode()]

= T [Battery Overvoltage] PWM stopped. Timers remain running.

BOV

= F PWM restarted.

BOV

RESET_TO_ZERO = T [See ChargeMode()]

Or

CHARGE_INHIBIT = T [See ChargeMode()]

AlarmWarning() command is sent by Smart Battery over SMBus
with any of the following bits set to True:
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM

Or

Reserved ALARM

Or

OVER_TEMPERATURE_ALARM

Or

Note: V

is active in all charge states except for nickel batteries which operate in constant current mode.

CHG

= On (Constant Current only) & TTIMEOUT = Started & CHG = T

PPC

INHIBITED = F

I

PPC

= Off, I

= On, Timer/4(Pre-Charge) = Stopped & Timer(SMBus)

CHG

= Started

= Off & All Timers = Reset & CHG = F

CHG

I

= Off & All Timers = Reset & CHG = F

PPC

= On & Timer/4(Pre-Charge) = Started & CHG = T &

I

PPC

ALARM_INHIBITED = F

= Off & All Timers Reset & CHG = F

CHG

or I

CHG

CHG

I

CHG

= Off & CHG_FLT = T, Timer = Paused.

PPC

or I

= On & CHG_FLT = F, Timer = Resume.

PPC

or I

= Off & All Timers = Reset & CHG_FLT = F & CHG = F &

PPC

ALARM_INHIBITED = F & CHARGE_INHIBITED = F

or I

I

CHG

I

CHG

= Off & All Timers = Reset & CHG_FLT = F & CHG = F

PPC

or I

= Off. & All Timers = Reset & CHG = F &

PPC

ALARM_INHIBITED = T

(ALARM_INHIBITED bit is found in ChargeStatus())

4110 F04

4110fa

17

LTC4110

OPERATION

SMBUS WAKE-UP CHARGE STATE

The battery will be charged with a fi xed “wake-up” current
regardless of previous ChargingCurrent() and Charging­Voltage() register values during wake-up charging. The cur­rent is identical to the preconditioning charge current which
is programmed with an external resistor through the I
pin. The wake-up timer has the same period as t
typically 175sec (see t

TIMEOUT

).

TIMEOUT

PCC

,

The following conditions must be met to allow wake-up
charge of the battery:

• The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.

• AC must be present. This is qualifi ed by DCDIV > V
+ V

and DCIN above UVLO.

ACH

AC

• Wake-up charge initiates if a battery does not write
non-zero values to ChargingCurrent() and Chargin­Voltage() registers when AC power is applied and a
battery is present or when AC is present and a battery
is subsequently connected.

• CHARGE_INHIBIT is set in the BBuControl() register.
Charge is stopped, however, the wake-up timer is not
paused. Clearing CHARGE_INHIBIT will enable the
LTC4110 to resume charging.

• There is insuffi cient DCIN voltage to charge the battery
as determined by the internal UVLO. This causes the
state machine to enter the reset state and stop all charge
activity. The LTC4110 will resume wake-up charging when
there is suffi cient DCIN voltage to charge the battery.

• The CAL_START bit in the BBuControl() register is set.
Charge is stopped and the LTC4110 enters the calibra­tion state.

• Writing a zero value to either the ChargingVoltage() or
ChargingCurrent() register. The state machine will go
to the SMBus OFF state.

• RESET_TO_ZERO is set in the BBuControl() register.
Charge is stopped; the SMBus OFF State is entered.

SMBUS PRECONDITIONING CHARGE STATE

The following conditions will terminate the wake-up charge
state and end charge attempts, unless otherwise noted.

• The t

TIMEOUT

period is reached (see t

TIMEOUT

) when
the SafetySignal is RES_COLD or RES_UR. The state
machine will go to the SMBus OFF state. The CHG_FLT
bit is not set.

• The SafetySignal is registering RES_HOT. The state
machine will go to the SMBus OFF state.

• The SafetySignal is registering RES_OR. The state
machine will go to the reset state.

• The LTC4110 will leave the wake-up charge state and
go into the SMBus preconditioning charge state if the
ChargingCurrent() AND ChargingVoltage() registers
have been written to non-zero values.

• The AC power is no longer present (DCDIV < V

AC

or
DCIN below UVLO). The state machine will go to the
reset state.

• The ALARM_INHIBITED becomes set in the
ChargerStatus() register. The state machine will go to
the SMBus OFF state.

During the SMBus preconditioning charge state, the charger
will be operating in the preconditioning charge current
limit. The following conditions must be met in order to
allow SMBus preconditioning charge to start:

• The ChargingVoltage() AND ChargingCurrent() registers
must be written to non-zero values. The LTC4110 will
not directly report the status of these registers. The
battery needs only write one pair of ChargingVoltage()
and ChargingCurrent() registers to stay in this state. The
t

TIMEOUT

timer is not operational in SMBus precondition-

ing charge state.

• The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.

• AC must be present and suffi cient. This is qualifi ed by
DCDIV > V

AC

+ V

and DCIN > UVLO.

ACH

The following conditions will affect the SMBus precondi­tioning charge state as specifi ed below:

• The SafetySignal is registering RES_HOT. Charge is

stopped; the SMBus OFF state is entered.

18

4110fa

OPERATION

LTC4110

• The SafetySignal is registering RES_OR. Charge is
stopped. The LTC4110 enters the reset state.

• The AC power is no longer present (DCDIV < V
DCIN < UVLO). The LTC4110 enters the reset state.

• ALARM_INHIBITED is set in the ChargerStatus()
register. Charge is stopped. The LTC4110 enters the
SMBus OFF state.

• CHARGE_INHIBIT is set in the BBuControl() register.
Charge is stopped, however, the T/4 timer is not paused.
Clearing CHARGE_INHIBIT will enable the LTC4110 to
resume charge.

• RESET_TO_ZERO is set in the BBuControl() register.
Charge is stopped. The LTC4110 enters the SMBus
OFF state.

• Writing a zero value to ChargeVoltage() or ChargeCur­rent() register. Charge is stopped. The LTC4110 enters
the SMBus OFF state.

• If the batter y voltage exceeds the bulk charge threshold,
the LTC4110 will enter the SMBus bulk charge state.

• If the T/4 timeout occurs, charge is stopped and the
LTC4110 enters the SMBus OFF state.

• The CAL_START bit in the BBuControl() register is
set. Charge is stopped and the LTC4110 enters the
calibration mode.

SMBus BULK CHARGE STATE

AC

or

• The ChargeCurrent() AND ChargeVoltage() registers
have not been written for t
and the LTC4110 enters the SMBus OFF state.

• The SafetySignal is registering RES_OR. Charge is
stopped and the LTC4110 enters the reset state.

• The SafetySignal is registering RES_HOT. Charge
is stopped and the LTC4110 enters the SMBus OFF
state.

• The AC power is no longer present (DCDIV < V
DCIN < UVLO). Charge is stopped and the LTC4110
enters the reset state.

• ALARM_INHIBITED is set in the ChargerStatus() register.
Charge is stopped and the LTC4110 enters the SMBus
OFF state.

• CHARGE_INHIBIT is set in the BBuControl() register.
Charge is stopped. Clearing CHARGE_INHIBIT will en­able the LTC4110 to resume charge. The t
does not pause when CHARGE_INHIBIT is set.

• RESET_TO_ZERO is set in the BBuControl() register.
The LTC4110 enters the SMBus OFF state.

• Writing a zero value to the ChargeVoltage() or to the
ChargeCurrent() register. Charge is stopped and the
LTC4110 enters the SMBus OFF state.

• The CAL_START bit in the BBuControl() register is set.
Charge is stopped and the LTC4110 enters the calibra­tion mode.

TIMEOUT

. Charge is stopped

or

AC

TIMEOUT

timer

The charger will be operating in the bulk charge current
limit during the SMBus bulk charge state. The following
conditions must be met in order to allow SMBus bulk
charge to start:

• The ChargeVoltage() AND ChargeCurrent() registers
must be written to non-zero values. The LTC4110 will
not directly report the status of these registers.

• The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.

• AC must be present and suffi cient. This is qualifi ed by
DCDIV > V

The following conditions will affect the SMBus bulk charge
state as specifi ed below:

AC

+ V

and DCIN > UVLO.

ACH

SMBus OFF STATE

This state is different from the reset state in that all charge
is disallowed regardless of the value of the thermistor. The
following conditions will affect the SMBus OFF state as
specifi ed below:

• The ChargeCurrent() AND ChargeVoltage() regis­ters have both been written to non-zero values, the
battery thermistor is registering RES_COLD, RES_
IDEAL or RES_UR and CHARGE_INHIBT is clear. The
LTC4110 enters the SMBus preconditioning charge
state.

4110fa

19

LTC4110

OPERATION

• The CAL_START bit in the BBuControl() register is set.
The LTC4110 enters the calibration state.

• The battery thermistor is registering RES_OR. The
LTC4110 enters the reset state.

LEAD ACID BATTERY CHARGE MODE

The charger is programmed for lead acid batteries by con­necting the TYPE pin to a voltage derived from the V
pin resistor divider of nominally 0.5 • V

. During charge,

REF

REF

the LTC4110 operates as a high effi ciency, synchronous,
PWM fl yback battery charger with constant current and
constant fl oat voltage regions of operation. The constant­charge current is programmed by the combination of a
resistor (R
current sense resistor (R

) from the I

CHG

pin to ground, a battery

CHG

) and CSP/CSN pin resistors.

SNS

The fl oat voltage is programmed to one of four values
(4.7V, 7.05V, 11.75V, 14.1V) depending on the number of
series cells (2, 3, 5 or 6) using the SELC pin and can be
adjusted ±0.15V/cell with the V

CHG

pin.

A new charge cycle begins with the charger in the bulk
charge current limited state. In this state, the charger is
a current source providing a constant charge rate and the
CHGb (GPIO1 pin) is forced low. No time limits are placed
upon lead acid battery charge. The charger monitors the
battery voltage and as it reaches the fl oat voltage the
charger begins its fl oat charge. While in fl oat, the charge
current diminishes as the battery accepts charge. Float
voltage temperature compensation and temperature fault
monitoring, if desired, are accomplished with an external
thermistor network.

Charge is active when the supply input is present as sensed
by the DCDIV pin and DCIN above UVLO, thermistor
temperature is ideal according to the thermistor monitor
circuit (see SafetySignal Decoder) and the charge register
bit CHARGE_INHIBIT is cleared. Soft-start ramps the charge
current at a rate set by the capacitor on the I

pin. When

TH

charge begins, the CHGb (GPIO1 pin) status output is
forced to GND. At any time charge can be forced to stop by
pulling the SHDN pin high or setting the CHARGE_INHIBIT
bit high through the SMBus.

If the battery voltage exceeds 107.5% (V

) of the pro-

BOV

grammed fl oat voltage during any stage of charge, the

charger pauses until the voltage drops below the hysteresis
(V

). No fault is indicated.

BOVH

An optional external NTC thermistor network can be used
to provide an adjustable negative TC for the fl oat voltage,
monitor battery temperature and to detect battery pres­ence. If the thermistor value indicates a hot temperature,
voltage falling to V

on THB pin, charge current is halted,

HOT

CHG_FLTb (GPIO3 pin) is forced low and the CHG_FLT bit
will be set high. CHGb (GPIO1 pin) and CHG_STATE_0 and
CHG_STATE_1 register bits will not be affected. When the
thermistor value returns to ideal when the voltage exceeds
V

HOT

+V

on THB pin, charge resumes CHG_FLTb

HOTH

(GPIO3 pin) returns to high impedance and the CHG_FLT
bit will be reset low. An open thermistor indicates an
over-range which is considered absence of a battery.
Low temperature is not monitored. However, since bat­tery removal detection looks at the thermistor for a high
resistance (V

on THB pin), extremely cold temperatures

REM

may result in an indication of battery absence. To defeat
the temperature monitoring register, replace the thermis­tor with a resistor to indicate normal battery temperature.
When a thermistor is not used the resistor circuit must be
routed through the battery connector if battery presence
detection is required.

BATTERY CALIBRATION MODE

Figure 6 shows the LTC4110 in battery calibration mode and
the corresponding PowerPath enabled. During calibration,
the host CPU can calibrate a gas gauge or verify the battery’s
ability to support a load by use of a low heat producing
method. Calibration requires a host to communicate over
a SMBus. In the low heat method, a synchronous PWM
fl yback charger is used in reverse to discharge the battery
with a programmable constant-current into the system
load thereby saving space and eliminating heat generation
compared with resistive loads. Protection circuits prevent
accidental overdrive back into the power source if the
system load is insuffi cient. The constant-charge current
is programmed by the combination of a resistor (R
from the I
tor (R

SNS(BAT)

pin to ground, a battery current sense resis-

CAL

) and CSP/CSN pin resistors. Calibration is

CAL

)

initiated by setting the CAL_START bit in the BBuControl()
register. The CAL_ON bit in the BBuStatus() register will

20

4110fa

OPERATION

LTC4110

7

ANY

CHARGE

STAT E

5

PWM

STOPPED

(BATTERY OVP)

STOP

(OVERTEMPERATURE)

RESUME

CHARGE

STAT E

RESET

8

6

19

CHARGE

4

2

3

ANY

CHARGE

STAT E

STOP

Figure 5. SLA Charge State Diagram (Does Not Include Calibration)

# Logic Event (T = True, F = False) [Notes] Notes and/or Actions (T = True, F = False)

1 RES_OR = F & DCDIV pin = T & SHDN pin = F & CHARGE_INHIBITED = F &

2

3

4

5 RES_HOT = T & RES_UR = F [See ChargeStatus()] I

6 RES_HOT = F [See ChargeStatus()] I

7V

8V

9

Note: For all charge states, V

CHG_FLT = F

VAR = T [AutoRestart]

Or

ChargingVoltage() & ChargingCurrent() ≠ 0 sent

ChargingVoltage() or ChargingCurrent() = 0 sent

Or

RESET_TO_ZERO = T [See ChargeMode()]

Or

CHARGE_INHIBIT = T [See ChargeMode()]

DCDIV pin = F

Or

RES_OR = T [Bat Removed, See ChargeStatus()]

Or

SHDN pin = T

Or

V

= T

UVD

Or

POR_RESET = T [See ChargeMode()]

= T PWM stopped. Timers remain running.

BOV

= F PWM restarted.

BOV

AlarmWarning() command is sent by Smart Battery over SMBus with any of
the following bits set to True:
OVER_CHARGED_ALARM
TERMINATE_CHARGE_ALARM

Or

Reserved ALARM

Or

OVER_TEMPERATURE_ALARM

Or

is always active

CHG

= On & CHG = T

I

CHG

ALARM_INHIBITED = F

= Off & CHG = F

I

CHG

= Off & CHG = F & CHARGE_INHIBITED = F &

I

CHG

ALARM_INHIBITED = F

= Off & CHG_FLT = T

CHG

= On & CHG_FLT = F

CHG

I

= Off & CHG = F & ALARM_INHIBITED = T

CHG

(ALARM_INHIBITED bit is found in ChargeStatus())

4110 F05

be set to indicate calibration in progress. Soft-start ramps
the discharge current at a rate set by the capacitor on the
ITH pin (typically 10ms with 0.1F capacitor). A limit to
how far the battery cell voltage will be discharged during
calibration can be programmed with the V

pin (Li-Ion

CAL

default = 2.75V/cell, lead acid default = 1.93V/cell, Smart
NiMH/NiCd default = 0.95V/cell). When the limit is reached
calibration is terminated, the CAL_COMPLETE bit in the
BBuStatus() register is set, the CAL_ON bit in the BBuS­tatus() register will be cleared and the charge mode is

automatically entered to begin recharging the battery. If
the GPIO3 is confi gured as a calibration complete status
output (CAL_COMPLETEb), it will be forced low until reset
by the CAL_RESET write bit. Calibration is inhibited during
backup or shutdown modes. Calibration is also inhibited
when a thermistor is sensed absent.

During calibration, user-programmable supply back-drive
protections are provided. These protections prevent a
reversal of current into the main supply and/or possibly
raising the supply voltage to unsafe levels should the

4110fa

21

LTC4110

OPERATION

system load not be adequate to absorb the current. The
primary protection is accomplished with an external current
sense resistor (R

), connected between the CLP and CLN

CL

pins, through which the system load current fl ows. When
the voltage across the resistor reaches 10mV (I

BDT

) or
less, representing a low forward current, calibration mode
is terminated. The current protection can be completely
disabled by connecting both CLP and CLN pins to GND.
As an alternative where R

sensing is not an option for

CL

the application, a secondary method is accomplished by
monitoring the supply voltage through the DCDIV pin.
Once the DCDIV pin voltage goes above V

, calibration

OVP

mode is terminated. In either case, the CAL_FLT register is
set high and the charge mode is automatically entered to
begin recharging the battery. Both of these protections are
automatically disabled when not in calibration. However,
in calibration, one or the other of these two protective
methods should be used. You can optionally do both.
Failure to implement any form of protection can result in
destructive voltages being generated in the application.

If the calibration cycle fails due to loss of the main power
source a fault condition results that sets the CAL_FLT
register bit and backup mode is entered.

An optional external thermistor network is sampled at
regular intervals to monitor battery temperature and to
detect battery presence. If the thermistor value indicates
a temperature outside of ideal limits (hot or over-range)
the calibration current is halted and the CAL_FLT bit will
be set high. When the thermistor value returns to an ac­ceptable value (under-range, cold or ideal), charge mode
is automatically entered to begin recharging the battery.
Calibration can be restarted by clearing the CAL_FLT bit
and sending another CAL_START command.

An open thermistor (over-range) indicates absence of a
battery. To defeat the temperature monitoring function, re­place the thermistor with a resistor to indicate ideal battery
temperature. When a thermistor is not used, the resistor
circuit must be routed through the battery connector if
battery presence detection is required. If the battery should
be removed during calibration, calibration will terminate
and the CAL_FLT read bit will be set high.

SYSTEM LOAD

DCIN

CURRENT FLOW

BACKUP LOAD

OFF OFFON

INID BATID

LTC4110

Figure 6. Calibration Mode Operation

CHGFET

DCHFET

4110 F06

BATTERY

The CAL_FLT bit can be cleared by writing a one to the
CAL_RESET or POR_RESET registers, or by forcing the
SHDN pin high. The CAL_FLT bit is not cleared by remov­ing and reapplying the supply input if the battery has
maintained suffi cient voltage (V

≥ 2.7V).

BAT

Calibration can start only if the CAL_FLT bit in the
BBuStatus() register is clear. Once the LTC4110 is in cali­bration state, the following events will stop calibration:

• BKDRV is sensed. The CAL_FLT bit is set.

• A HOT thermistor is sensed. The CAL_FLT bit is set.

• Loss of battery presence is sensed. The CAL_FLT bit is
set.

• The calibration cutoff threshold has been reached.
The CAL_COMPLETE bit is set. The LTC4110 will start
charging based upon the TYPE and SELA pins.

• An OVER_TEMP_ALARM, RESERVED_ALARM, or
TERMINATE_DISCHARGE_ALARM bit in the Alarm­Warning() register is set. The CAL_FLT bit is set. The
LTC4110 will start charging.

• Loss of AC presence. The CAL_FLT bit is set.

SHUTDOWN MODE

The LTC4110 can be forced into either a micropower
shutdown state or an all logic register reset state with
the SHDN pin.

22

4110fa

OPERATION

LTC4110

RESUME

STAT E

NO

7

CALIBRATION

MODE?

YES

(CALIBRATION FAULT)

8

ANY

STAT E

RESET

(CALIBRATION

COMPLETED)

6, 9

1

5 (BATTERY IS DEAD)

4

CALIBRATION

RUNNING

2

CALIBRATION

START

Figure 7. Calibration State Diagram

# Logic Event (T = True, F = False) [Notes] Notes and/or Actions (T = True, F = False)

1 RES_OR = F & DCDIV pin = T & SHDN pin = F & CAL_FLT = F &

2 RES_OR = F & DCDIV pin = T & SHDN pin = F & CAL_FLT = F &

3 [Calibration Automatically Started] I

4V

5V

6 AlarmWarning() command is sent by Smart Battery over SMBus

7 CAL_RESET = T I

8

9

CAL_START = T

CAL_START = T

< V

BAT

BAT

with any of the following bits set to True:
OVER_TEMP_ALARM or Reserved ALARM or
TERMINATED_DISCHARGE_ALARM]

RES_HOT = T & RES_UR = F [See ChargeStatus()]

Or

RES_OR = T [Bat Removed, See ChargeStatus()]

Or

V

OVP

Or

I

BDT

DCDIV pin = F

Or

SHDN pin = T

Or

V

UVD

Or

POR_RESET = T [See ChargeMode()]

[Battery has reached Discharge] I

CAL

< V

[Battery is Discharged] CAL_COMPLETE = T

CAL

= T [Output Over-Voltage condition sensed)]

= T [Output Back Drive Current condition sensed)]

= T

CAL_COMPLETE = F
(Calibration started while in Reset {Idle or Cold Power-Up})

or IPPC = Off & All Timers = Reset & CAL_COMPLETE = F

I

CHG

(Calibration was initiated while in any mode other than Reset.)

= ON & CAL_ON = T

CAL

= Off & CAL_ON = F & CAL_COMPLETE = T

CAL

(Normal Calibration Cycle)

(Battery is already discharged. Cancel Calibration.)

I

= Off & CAL_ON = F & ALARM_INHIBITED = T

CAL

(ALARM_INHIBITED bit is found in ChargeStatus())

= Off & CAL_ON = F & CAL_COMPLETE = F & CAL_FLT = F

CAL

= Off & CAL_ON = F & CAL_FLT = T

I

CAL

= Off & CAL_ON = F & ALARM_INHIBITED = F &

I

CAL

CHARGE_INHIBITED = F

3

4110 F07

REGISTER RESET STATE

The SHDN pin will reset all logic registers when taken high,
but only if DCIN is present as determined by DCDIV > V
+ V

and DCIN above UVLO. Micropower shutdown

ACH

AC

state will not be entered, but the LTC4110 will be idle and
not able to enter charge or calibration modes. If SHDN is
switched low then normal operation will resume.

While in register reset state, charge and calibration modes
are inhibited, and all registers including the backup fault bit
register are set to their default states and the internal timer
is reset. The status pin ACPb is active, but GPIO1, GPIO2

and GPIO3 are reset to their default states. The SMBus is
enabled, however, it is not able to communicate with the
LTC4110. The DCIN to DCOUT PowerPath controller is
functional and the V

DD

and V

pin voltages remain.

REF

MICROPOWER SHUTDOWN STATE

If the SHDN pin remains high when DCIN is removed as
detected by the undervoltage lockout UVLO (see V

UVD

),
micropower shutdown is entered, battery backup mode is
inhibited and all registers are reset. During this condition,
the level of the SHDN pin is ignored and has no effect.

4110fa

23

LTC4110

OPERATION

The micropower shutdown state will be maintained if the
DCIN supply is removed and suffi cient battery voltage is
present (V
by the UVLO (see V

≥ 2.7V). When DCIN is reapplied as detected

BAT

), regardless of the level of the

UVI

SHDN pin, the shutdown state is automatically cancelled.
Register reset state is cancelled until DCIN is reapplied as
determined by the DCDIV pin.

5V

I

ISD

SHDN

Figure 8. Shutdown Control Input

LTC4110

SHUTDOWN

4110 F08

In shutdown; charge, calibration and backup modes are
inhibited, all registers are set to their default states (with
exception of the backup fault bit register), the internal
timer is reset and oscillator disabled, the status pins;
ACPb, GPIO1, GPIO2 and GPIO3 are a high impedance
and the LTC4110 is put into a micropower state. While
in shutdown the SMBus is disabled and the SDA and
SCL pins are high impedance. In addition, the shutdown
state will disconnect loads from the battery to prevent its
discharge as follows:

• The BATID pin is forced to the battery voltage to turn
off the battery P-MOSFETs for isolation of the load from
the battery

+

R

R

CSP2

CSP1

+

R

V

SNS(BAT)

SNS

–

R

CSN1

+

–

CSP

R

CSN2

CSN

+

BAT

+

=

V

ICHG

/(R

+ R

CSP1

CSP2

CURRENT

LOOP EA

BANDGAP

)*V

SNS

I

CHG

–

R

ICHG

+

+
–

4110 F09

R

REFERENCE

VOLTAGE

PIN

V

CHG

ICHG

I

TH

+

–

INPUT

CURRENT

AMPLIFIER

V

FB

–

VOLTAGE
LOOP EA

+

+
–

ADJUSTED BY

Figure 9. LTC4110 PWM Engine

The voltage across the external current programming
resistor R

SNS(BAT)

is averaged by the RC network con­nected to the CSP and CSN pins and then amplifi ed by a
ratio of R

ICHG

/(R

CSP1

+ R

). This amplifi ed voltage is

CSP2

compared with the bandgap reference through the cur­rent loop error amplifi er to adjust the ITH pin which sets
the current comparator threshold to maintain a constant
charging current. Once the battery voltage rises to close
to the programmed fl oat voltage, the voltage loop error
amplifi er gradually pulls the ITH pin low, reduces the charg­ing current and maintain a constant voltage charging.

• The CHGFET and DCHFET pins are forced to GND to
turn off the fl yback switcher N-MOSFETs

• Current into the BAT pin is minimized. Also the V

pin voltages will fall to zero.

V

REF

DD

and

While in shutdown, the LTC4110 will draw a small current
from battery (I
pin is open an internal weak pull-up current (I

) if the DCIN supply is absent. If the SHDN

BSD

) pulls the

ISD

pin voltage up thereby entering the shutdown state.

PWM OPERATION

A conceptual diagram of the LTC4110 PWM engine is
shown in Figure 9.

24

C/x CHARGE TERMINATION

LTC4110 monitors the charging current through the volt­age on the I

pin, once the current drops below 20% of

CHG

the bulk charging current, an internal C/x comparator is
tripped, and the LTC4110 will enter top-off charge stage
if standard Li-Ion battery mode is selected or release the
GPI01 pin if no-host SLA battery mode is selected. The
actual x value depends on the programmed charging cur­rent and the C rate of the battery.

C

x

= •5

I

CHG

4110fa

OPERATION

LTC4110

Where:

C = C rate of the battery

I

= Programmed charging current

CHG

For Example, if we charge a 3Ah battery with 1A current,
then x = 15.

SAFETYSIGNAL DECODER

Table 3. SafetySignal State Ranges (Except SLA)

SafetySignal
CHARGE
RESISTANCE CHARGE STATUS BITS DESCRIPTION

0 to 500 RES_UR, RES_HOT,

500 to 3k RES_HOT, BATTERY_PRESENT Hot

3k to 30k BATTERY_PRESENT Ideal

30k to 100k RES_COLD, BATTERY_PRESENT Cold

Above 100k RES_OR, RES_COLD Overrange

Note: The under range detection scheme is a very important feature of the
LTC4110. The R
is well above the 0.047 • V
pull-up. A system using a 10k pull-up would not be able to resolve the
important under range to a hot transition point with a modest 100mV of
ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.

BATTERY_PRESENT

THA/RSafetySignal

= 140mV threshold of a system using a 10k

DD

divider trip point of 0.307 • 4.75V = 1.46V

Under range

Table 4. SafetySignal for SLA (7.256k Between THA and THB)

SafetySignal
CHARGE
RESISTANCE CHARGE STATUS BITS DESCRIPTION

0Ω to 3.1k RES_HOT,

BATTERY_PRESENT

3.1k to 114k BATTERY_PRESENT Ideal

114k RES_COLD, RES_OR Battery Removal

Hot

This decoder measures the resistance of the SafetySignal
and features high noise immunity at critical trip points.
The SafetySignal decoder is shown in Figure 10.

The value of R

is 1.13k and R

THA

is 54.9k. SafetySignal

THB

sensing is accomplished by a state machine that reconfi gures
the switches of Figure 10 using THA_SELB and THB_SELB,
a selectable reference generator, and two comparators.
The state machine successively samples the SafetySignal
value starting with the RES_OR ≥ RES_COLD threshold,

V

INT

R

THA

1.13k

THA

R

THB

54.9k

R

SafetySignal

THB

C

SS

THA_SELB

TH_HI

MUX

HI_REF

REF

LATCH

LO_REF

RES_OR

RES_COLD

RES_HOT

RES_UR

V

INT

SafetySignal

THB_SELB

CONTROL

+
–

TH_LO

+
–

4110 F10

Figure 10. Battery Safety Decoder (Except SLA)

then RES_C0LD ≥ RES_IDEAL threshold, RES_IDEAL ≥
RES_HOT threshold, and fi nally the RES_HOT ≥ RES_UR
threshold. Once the SafetySignal range is determined, the
lower value thresholds are not sampled. The SafetySignal
decoder block uses the previously determined SafetySignal
value to provide the appropriate adjustment in threshold to
add hysteresis. The R

resistor value is used to measure

THB

the RES_OR ≥ RES_COLD and RES_COLD ≥ RES_IDEAL
thresholds by connecting the THB pin to an internal voltage
and measuring the voltage resultant on the THA pin. The

resistor value is used to measure the RES_IDEAL ≥

R

THA

RES_HOT and RES_HOT ≥ RES_UR thresholds by con­necting the THA pin to the internal voltage and measuring
the resultant voltage on the THB pin. The SafetySignal
impedance is interpreted according to Table 3.

When the DCIN supply is present, a full sampling of the
SafetySignal is performed every 27ms. When the supply is
absent, a low power limited sampling of the SafetySignal is
performed every 218ms. A full sampling of the thermistor
state is performed only if a change of battery presence is
detected when the supply is not present.

GPIO AND STATUS FUNCTIONS

All of the GPIO pins are open drain with N-MOSFET drivers
capable of sinking current suffi cient to drive an LED (see

). The pins are not capable of sourcing any current and

V

OL

instead enter a Hi-Z mode when the output is not low. An
external pull-up will be required to create any high output
logic state.

4110fa

25

LTC4110

OPERATION

The three I/O outputs, GPIO1, GPIO2 and GPIO3 are digital
I/O pins with two modes of operation.

1) General Purpose I/O

2) Status Reporting

A host can set the mode of each I/O pin with each I/O pin’s
setting independent of the others such that any combination
of status reporting or bit I/O can be implemented. Only a
UVLO or a SHDN event will change the GPIO_n_EN bits
back to default values. If you enable a GPIO pin to report
status output, it overrides the GPIO_n_OUT setting. In
addition, the LTC4110 supports a special power up mode
of status reporting on all 3 IO pins for standalone applica­tions where it is assumed “no host” exists. This power up
status mode is enabled if the SELA pin is set to 0.5 • V
voltage as developed from V

pin resistor divider. This

REF

REF

mode does not actually disable the SMBus in any way and
if a host does exist in this power up mode, the host can
reprogram the I/O settings at any time.

All GPIO pins operate as digital inputs at all times regard­less of the pin settings with pin state reported on the
GPIO_n_IN bits in the BBuStatus() register. However to
actually read digital input data from an external device, you
must disable the GPIO_n_EN bit. Otherwise the input will
simply refl ect the output state assuming external powered
pull-ups exist.

There are a total of 5 status signals possible. CHGb, C/xb,
BKUP-FLTb, CHG_FLTb, and CAL_COMPLETEb. Each of
these signals is asserted low on the output when they
are true. CHGb is an asserted low signal when either
CHG_STATE_0 or CHG_STATE_1 is set to one. C/xb is
asserted low signal when C/x state in the charge cycle is
reached. This status signal is only available if the TYPE pin
is set to SLA mode and replaces the CHGb status output.
BKUP_FLTb is asserted low when the BKUP_FLT bit is set
to one in the BBuStatus() register. BKUP_FLT is a sticky bit
that is designed to be cleared primarily through the setting
of the BUFLT_RST bit in the BBuControl() register. The value
of this bit does not inhibit charging or calibration functions.
CHG_FLTb is asserted low when the CHG_FLT bit is set to
one in the BBuStatus() register. CAL_COMPLETEb bit is
asserted low when the conditions of successful calibra­tion cycle are met. CAL_COMPLETEb status output can
be used as an interrupt to a host for the purpose of help
implementing a simple gas gauge function or capacity
verifi cation function with a standard battery. However, if the
LTC4110 is set up in no host mode, CAL_COMPLETEb as a
status signal is not considered usable since it is assumed
there is no host to enable calibration mode. Therefore the
CHG_FLTb signal is substituted for CAL_COMPLETEb as
the status output signal. Table 5 describes the specifi c
modes and status signal options of each GPIO pin.

Table 5a. GPIO1 Modes

HOST PROGRAMMED BIT SETTINGS GPIO_1 MODE DATA NOTE

GPIO_1_EN GPIO_1_OUT GPIO_1_CHG

0 0 0 Digital Input Input Data GPIO_1_IN

1 X 1 Status Output CHGb With Pull-Up

1 0 0 Digital Output 0 With Pull-Up

1 1 0 Digital Output 1 With Pull-Up

Table 5b. GPIO1 Power Up Mode (SELA = 0.5 • V

FORCED BIT SETTINGS TYPE = SLA GPIO_1 MODE DATA NOTE

GPIO_1_EN GPIO_1_OUT GPIO_1_CHG

1 X 1 0 Status Output CHGb With Pull-Up

1 X 1 1 Status Output C/xb With Pull-Up

REF

26

)

4110fa

OPERATION

Table 5c. GPIO2 Modes

HOST PROGRAMMED BIT SETTINGS GPIO_2 MODE DATA NOTE

GPIO_2_EN GPIO_2_OUT GPIO_2_BUFLT

0 0 0 Digital Input Input Data GPIO_2_IN

1 X 1 Status Output BKUP_FLTb With Pull-Up

1 0 0 Digital Output 0 With Pull-Up

1 1 0 Digital Output 1 With Pull-Up

LTC4110

Table 5d. GPIO2 Power Up Mode (SELA = 0.5 • V

FORCED BIT SETTINGS GPIO_2 MODE DATA NOTE

GPIO_2_EN GPIO_2_OUT GPIO_2_ BUFLT

1 X 1 Status Output BKUP_FLTb With Pull-Up

Table 5e. GPIO3 Modes

HOST PROGRAMMED BIT SETTINGS GPIO_3 MODE DATA NOTE

GPIO_3_EN GPIO_3_OUT GPIO_3_CAL

0 0 0 Digital Input Input Data GPIO_3_IN

1 X 1 Status Output CAL_COMPLETEb With Pull-Up

1 0 0 Digital Output 0 With Pull-Up

1 1 0 Digital Output 1 With Pull-Up

Table 5f. GPIO3 Power Up Mode (SELA = 0.5 • V

FORCED BIT SETTINGS GPIO_3 MODE DATA NOTE

GPIO_3_EN GPIO_3_OUT GPIO_3_ CAL

1 X 1 Status Output CHG_FLTb With Pull-Up

REF

REF

)

)

SMBUS INTERFACE

All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device. All internal LTC4110 registers may be updated
and accessed through the SMBus interface as required.

2

The SMBus protocol is a derivative of the I

C-BusTM. (For

a complete description of the bus protocol requirements,

2

reference “The I

®

, and “System Management Bus Specifi cation, Version

ips

C-Bus and How to Use It, V1.0” by Phil-

1.1,” from the SMBus organization). See Table 6: Register

Command Set Description and Table 7: Summary of Sup­ported SMBus Functions, for complete details.

All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condi­tion, or power-on reset will reset the SMBus interface to
an initial state at any time. The LTC4110 command set is
interpreted by the SMBus interface and passed onto the
charger controller block as control signals or updates to
internal registers. Smart battery charge commands are

4110fa

27

LTC4110

OPERATION

processed to allow compliance with smart battery charge
and discharge termination and protection control. How­ever, there is no actual value processing of the voltage or
current charge commands. IC will acknowledge all smart
battery write commands, but process only a subset of
them. Full SMBus error and reset handling is supported.
The SMBus remains functional during backup mode, but
not in SHDN mode.

The LTC4110 SMBus address can be changed when
standard batteries are used to facilitate redundant backup
systems. Connect SELA pin to GND for 12h, V
and V
TYPE pin the SELA pin must be connected to GND to select
address 12h. Note: Although there are only 7 address bits
for SMBus, the above addresses shown follow the smart
battery convention of including the Read/Write bit as part
of the address value. The Read/Write bit becomes the
LSB of the SMBus address with the Read/Write bit value
assumed to be a 0 value.

If multiple LTC4110s with smart batteries are to be used,
each LTC4110 must be SMBus isolated from all other
LTC4110s so the main bus or host bus can only see one
LTC4110 and its corresponding smart battery at a time.
Failure to do so will cause multiple LTC4110s and smart
batteries responding to a single host query resulting in
errors. There are multiple channel SMBus multiplexer ICs
such as the LTC4305 and LTC4306 to help implement the
required isolation. Furthermore, if a given SMBus is high
in SMBus device count or long in length, you may want to
consider using SMBus accelerators. The above ICs listed
support that option.

for 20h. When a smart battery is selected by the

REF

for 28h

DD

If the SMBus is not used or to force all GPIOs to status
mode upon power-up, connect SELA to a typically 0.5 •

voltage from V

V

REF

address then, if used, will be 12h.

Pull-ups are required on the SDA and SCL pin such that
when they are not being used, they are in a default high
state that means no bus activity. The pull-up voltage need
only be high enough to satisfy the logic high threshold.
Tying the pins low is a valid state on the SMBus that
means anything but the bus is free. This state will force
the LTC4110’s internal SMBus state machine to reset itself
because it thinks the SMBus is hung.

The LTC4110 does not support or respond to the following
SMBus V1.1 timing specifi cations:

a) T

TIMEOUT

LTC4110’s t

b) T

LOW:SEXT

c) T

LOW:MEXT

The above specifi cations have to do with detecting bus
hangs or SMBus devices that are taking too long to reply
using clock stretching and slowing down the SMBus
bandwidth. The LTC4110 is a slave only device that does
not do any clock stretching and works all the way up to
maximum 100kHz bus speed. It will not hang the bus.
The design will always reset its SMBus interface upon
receiving an SMBus Start Bit or a Stop Bit regardless of
the prior state of the bus.

(This is not to be confused with the

TIMEOUT

pin resistor divider. The SMBus

REF

specifi cation.)

28

4110fa

LTC4110

OPERATION

Table 6. Register Command Set Descriptions (XxxxXxxx() – Register Byte, XXXXXXXX – Status Bit)

LABEL DESCRIPTION

ChargerStatus() – Read Only. The SMBus host uses this command to read the LTC4110’s charge status bits.

+ V

AC_PRESENT Set to 1 when suffi cient input voltage (DCDIV > V

battery to main supply. Zero indicates backup mode engaged.

BATTERY_PRESENT BATTERY_PRESENT is set if a battery is present, otherwise it is cleared. The LTC4110 uses the SafetySignal to

determine battery presence. If the LTC4110 detects a RES_OR condition, the BATTERY_PRESENT bit is cleared
immediately. The LTC4110 will not set the BATTERY_PRESENT bit until it successfully samples the SafetySignal
twice and does not detect a RES_OR condition on either sampling. If AC is not present (DCDIV < V
below UVLO), this bit may not be set for up to one-half second after the battery is connected to the SafetySignal.
The ChargingCurrent() and ChargingVoltage() register values are immediately cleared whenever this bit is cleared.
Charging will never be allowed if this bit is cleared.

ALARM_INHIBITED ALARM_INHIBITED bit is set if a valid AlarmWarning() message has been received and charging is inhibited as a

result. This bit is cleared if POR_RESET is set, both ChargingVoltage() and ChargingCurrent() are rewritten to the
LTC4110, the power is removed (DCDIV < V
removed.

RES_UR Set to 1 when NTC pin is below 500Ω typical. This bit is never set when TYPE pin selects SLA battery..

RES_HOT The RES_HOT bit is set only when the SafetySignal resistance is less than 3kΩ (3.1k for SLA) typical, which

indicates a hot battery. The RES_HOT bit will be set whenever the RES_UR bit is set.

RES_COLD The RES_COLD bit is set only when the SafetySignal resistance value is greater than 30kΩ typical. The SafetySignal

indicates a cold battery. The RES_COLD bit will be set whenever the RES_OR bit is set. This bit is the same as
RES_OR for SLA.

RES_OR The RES_OR bit is set when the SafetySignal resistance value is above 100kΩ (114k for SLA) typical. The

SafetySiganl indicates an open circuit.

LEVEL:3/LEVEL:2 The LTC4110 always reports itself as a Level 2 Smart Battery Charger.

CHARGE_INHIBITED Indicates charge inhibited is enabled when set to a one. This is a duplicate of the CHARGE_INHIBIT bit in the

BBuStatus() register.

ChargingCurrent() – Write Only. The battery, system host or other master device sends the desired charging current to the LTC4110.

ChargingCurrent() LTC4110 only monitors for zero or non-zero values. A value of zero will stop the charger. A non-zero value here, and

for ChargingVoltage(), will restart the charger.

ChargingVoltage() – Write Only. The Battery, System Host or other master device sends the desired charging voltage to the LTC4110.

ChargingVoltage() LTC4110 only monitors for zero or non-zero values. A value of zero will stop the charger. A non-zero value here, and

for ChargingCurrent(), will restart the charger.

AlarmWarning() – Write Only. The Smart Battery, acting as a bus master device, sends the AlarmWarning() message to the LTC4110 to notify it that one or
more alarm conditions exist. Alarm indications are encoded as bit fi elds in the battery’s status register, which is then sent to the LTC4110 by this function.
Only the OVER_CHARGED_ALARM, TERMINATE_CHARGE_ALARM,RESERVED_ALARM, OVER_TEMP_ALARM and TERMINATE_DISCHARGE_ALARM
bits are supported by the LTC4110. The ALARM_INHIBITED bit in the ChargerStatus() register indicates whether a charging process or a calibration
process was halted by a write to this register.

OVER_CHARGED_ALARM Set to one indicates battery has been overcharged and stops charge. Setting this bit will only stop a charging

process (default = zero).

TERMINATE_CHARGE_ALARM Set to one indicates battery requesting charge termination. Setting this bit will only stop a charging process (default

= zero).

RESERVED_ALARM Set to one for reserved alarm condition. Setting this bit will stop both a calibration process and a charging process

(default = zero).

AC

or DCIN below UVLO), the SHDN pin is set high, or if a battery is

AC

and DCIN above UVLO) available and switches load from

ACH

or DCIN

AC

4110fa

29

LTC4110

OPERATION

LABEL DESCRIPTION

OVER_TEMP_ALARM Set to one indicates battery is temperature is out of range. Setting this bit will stop both a calibration process and a

TERMINATE_DISCHARGE_ALARM Set to one indicates battery requesting discharge termination. Smart battery only. Setting this bit will only stop a

BBuStatus() – Read Only. The SMBus host uses this command to read the LTC4110’s status bits.

CAL_ON Set to one indicates calibration in progress to discharge the battery.

CAL_COMPLETE Set to one indicates calibration process is complete. Can be used as a battery capacity indicator. Bit is cleared by

BKUP_ON Set to one verifi es backup mode is active

GPIO_1_IN Shows logic state of general purpose I/O Pin #1. This is always enabled.

GPIO_2_IN Shows logic state of general purpose I/O Pin #2. This is always enabled.

GPIO_3_IN Shows logic state of general purpose I/O Pin #3. This is always enabled.

CHG_FLT Set to one indicates battery charge fault.

BKUP_FLT Set to one indicates battery cell voltage < V

CAL_FLT Set to one indicates a calibration fault. Calibration terminated early.

CHG_STATE_0 Combined with CHG_STATE_1 indicates phase of charging. 00 = Off, 01 = precharge, 10 = bulk charge, 11 = top off

CHG_STATE_1 See CHG_STATE_0

CHARGE_INHIBITED Indicates charge inhibited is enabled when set to a one. This as a duplicate of CHARGE_INHIBIT bit in the

BBuControl() – Write Only. The SMBus host uses this command to control the LTC4110.

CAL_START Set to one starts a discharge based calibration of battery (default = self cleared to zero-off)

CAL_RESET Set to one clears the CAL_FLT as well as the CAL COMPLETE and CAL_ON status bits. If calibration is in progress, it

GPIO_1_EN Set to one enables GPIO1 pin as an output (default = set to one if programming SMBus not used by connecting SELA

GPIO_2_EN Set to one enables GPIO2 pin as an output (default = set to one if programming SMBus not used by connecting SELA

GPIO_3_EN Set to one enables GPIO3 pin as an output (default = set to one if programming SMBus not used by connecting SELA

GPIO_1_OUT Programmable logic bit whose state will be refl ected on the GPIO1 pin if the GPIO_1_CHG bit is cleared (default = set

GPIO_2_OUT Programmable logic bit whose state will be refl ected on the GPIO2 pin if the GPIO_2_BUFLT bit is cleared (default =

GPIO_3_OUT Programmable logic bit whose state will be refl ected on the GPIO3 pin if the GPIO_3_CALCOM bit is cleared (default

charging process (default = zero).

calibration process (default = zero).

CAL_RESET. This bit is available as a status signal output on the GPIO3 pin.

. This bit state is retained as long as suffi cient V
bit is available as a status signal output on the GPIO2 port. This bit remains until either the SHDN pin is cycled or
register bits POR_RESET or BUFLT_RST are set when DCOUT returns.

charge

ChargerStatus() register.

will also stop the calibration process (default = self cleared to zero-off)

pin to 0.5V

pin to 0.5V

pin to 0.5V

to zero/GPIO1 pulled low)

set to zero/GPIO2 pulled low).

= set to zero/GPIO3 pulled low)

, otherwise default = set to zero/GPIO1 high-Z )

REF

, otherwise default = set to zero/ GPIO2 high-Z)

REF

, otherwise default = set to zero/ GPIO3 high-Z)

REF

DIS

is applied. This

BAT

30

4110fa

LTC4110

OPERATION

LABEL DESCRIPTION

GPIO_1_CHG Set to one sends an inverted CHG_ON (internal register, set to 1 when either CHG_STATE_0 or CHG_STATE_1 is set

GPIO_2_BUFLT Set to one sends an inverted BKUP_FLT status signal out to the GPIO2 pin. If this bit is set, the value of BKUP_FLT

GPIO_3_CALCOM Set to one sends an inverted CAL_COMPLETE signal out to the GPIO3 pin. If this bit is set, the value of CAL_

RESET_TO_ZERO Set to one resets all faults and timers in charge and forces the ChargingCurrent() and ChargingVoltage() to zero

POR_RESET Resets LTC4110 to power-on default values. Setting the bit to a one will activate POR_RESET. POR_RESET performs

BUFLT_RST Resets the BKUP_FLT bit. The bit clears itself automatically after the command is executed (default = cleared).

CHARGE_INHIBIT Disables charging of battery. Set to one halts charge current while holding the charger state and pausing all battery

to 1) status signal out to the GPIO1 pin. If this bit is set, the value of CHG_ON overrides the value of the GPIO_1_
OUT bit state. Pin must be output enabled with GPIO_1_EN bit (default = set to zero/off)

overrides the value of the GPIO_2_OUT bit state. Pin must be output enabled with GPIO_2_EN bit (default = set to
zero/off)

COMPLETE overrides the value of the GPIO_3_OUT bit state. Pin must be output enabled with GPIO_3_EN bit
(default = set to zero/off)

values. Clears Alarm_Warning() register. Does not affect BBuControl() register. Bit clears to zero automatically after
the command is executed (default = cleared to zero-no reset)

a total chip wide reset like the SHDN pin function without the chip actually shutting down. This includes clearing any
bits in registers. The bit clears itself automatically after the command is executed (default = cleared/no reset)

charge timers without changing the ChargingCurrent() and ChargingVoltage() values. Charge may be enabled by
clearing this bit. This bit is automatically cleared when power is reapplied or when a battery is re-inserted (default =
cleared to zero-off)

4110fa

31

LTC4110

OPERATION

Table 7. Summary of Supported SMBus Functions

Function

ChargerStatus( )

Charging­Current(

)

Charging­Voltage( )

Alarm­Warning( )

Access

Read

Write

Write

SMBus

Address

7’b0001_

001

7’b0001_

001

7’b0001_

001

7’b0001_

001

Command

Code

8'h13 Status

8'h14 Value

8'h15 Value

8'h16 Control

Data
Type D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Return

Value

Permitted

Values

Permitted

Values

AC_PRESENT

1/0 1/0

BATTERY_PRESENT

POWER_FAIL

0

1/0 1/0 1/0 1/0 1/0

ALARM_INHIBITED

RES_UR

RES_HOT

RES_COLD

RES_OR

VOLTAGE_OR

CURRENT_OR

LEVEL:3/LEVEL:2

0001000

Note 1

Unsigned Integer Representing Current in mA

Note 2

Unsigned Integer Representing Voltage in mV

CURRENT_NOTREG

VOLTAGE_NOTRES

POLLING_ENABLED

CHARGE_INHIBITED

1/0

OVER_CHARGED_ALARM

TERMINATE_CHARGE_ALARM

RESERVED_ALARM

OVER_TEMP_ALARM

TERMINATE_DISCHARGE_ALARM

RESERVED

Write

BBuStatus( ) 7’b0001_

Read Return

BBuControl()
[Charger­Mode()]

Write

Note 1: IC only looks for a zero (off) or a non-zero (on) value. Actual charge current is set by the I
Note 2: IC only looks for a zero (off)or a non-zero (on) value. Actual charge voltage is set by the V

001

7’b0001_

001

8'h3D Status

8'h12 Control

Permitted

Values

Values

Permitted

Values

1/0 1/0 1/0 1/0 1/0

CAL__ON

CAL_COMPLETE

BKUP_ON

Reserved

1/0 1/0 1/0

CAL_START

CAL_RESET

1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

00

GPIO_1_EN

GPIO_2_EN

0 0000000000

Reserved

GPIO_1_IN

1/0 1/0 1/0

GPIO_3_EN

GPIO_1_OUT

CHG

CHG

REMAINING_CAPACITY_ALARM

REMAINING_TIME_ALRAM

INITIALIZED

GPIO_2_IN

GPIO_3_IN

Reserved

1

1/0 1/0 1/0 1/0 1/0

GPIO_2_OUT

GPIO_3_OUT

Reserved

0

1/0 1/0 1/0 1/0 1/0 1/0 1/0

pin.
pin.

DISCHARGING

FULLY_CHARGED

FULLY_DISCHARGED

CHG_FLT

BKUP_FLT

CAL_FLT

GPIO_1_CHG

GPIO_2_BUFLT

GPIO_3_CALCOM

ERROR

CHG_STATE_0

CHG_STATE_1

Reserved

0

1/0

RESET_TO_ZERO

POR_RESET

BUFLT_RST

4110fa

CHARGE_INHIBITED

CHARGE_INHIBIT

32

APPLICATIONS INFORMATION

LTC4110

The fi rst confi guration option to set for the LTC4110 is the
type and cell count of the battery you wish to use. Pins
TYPE and SELC are use to set this confi guration. Please
note NiMH and NiCd batteries are only supported in the
smart battery confi guration. The three state input pins
SELA, SELC and TYPE should NOT be changed while power
is applied to the IC unless in shutdown mode. Such action
will result in unpredictable behavior from the LTC4110.

based on the desired cap voltage and series cell count.
Other per cell voltages can be obtained by adjusting the

pin as required.

V

CHG

When the LTC4110 is confi gured to charge a super cap,
if TYPE pin is tied to 0.5V

, use the bulk charge current

REF

equation (see the Programming Charging/Calibration Cur­rent section for details) to set the charging current. If TYPE
pin is tied to GND, then the charging current will equal
to preconditioning charge current when the cap voltage

SUPERCAPS

Table 8 shows all of the options with the exception of
SuperCaps. SuperCaps are supported by using standard
Li-ion or SLA modes in combination with the adjusting the
charge voltage with the V

pin. As far as the LTC4110

CHG

is concerned, it is still working with a Li-ion or SLA bat­tery and will follow all the charge states as required for
that chemistry. Table 9 shows the required confi guration

Table 8. Battery Type and Number of Series Cell Selection for Batteries

STANDARD Li-Ion

SELC = GND 1241

SELC = 0.5V

SELC = V

SELC = V

Note: When smart battery is selected by the TYPE pin, SELA pin must be connected to GND to select address 12h.

REF

REF

DD

(TYPE = GND)

2362

3593

4 6 10 4

(TYPE = 0.5V

is below the bulk charge threshold (as listed in Table 9)
and bulk charge current when the voltage is above the
threshold. Simply tie the I

PCC

pin to I

pin if these two

CHG

currents need to be the same. If the capacitor is too small
(<10mF), the voltage might rise too fast to be regulated
by the loop. In that case, the capacitor will be charged to
over voltage pretection threshold (typically 107.5% of the
fl oat voltage. See V

SLA

)

REF

SMART NiMH/NiCd

(TYPE = V

BOV

)

REF

)

SMART Li-Ion

(TYPE = VDD)

Table 9. Battery Type and Number of Series Cell Selection for Super Caps

CAP VOLTAGE (V)

2.5 2 5 0.5V

2.5 3 7.5 0.5V

2.5 5 12.5 0.5V

2.5 6 15 0.5V

2.5 7 17.5 GND V

2.7 3 8.1 GND 0.5V

2.7 5 13.5 GND V

2.7 6 16.2 GND V

3 3 9 GND 0.5V

3 4 12 GND V

3 5 15 0.5V

3 6 18 GND V

SERIES CAP

COUNT

STACK CAP

VOLTAGE (V) TYPE SELC V

REF

REF

REF

REF

REF

GND 0.625V

0.5V

V

V

V

REF

REF

DD

DD

REF

REF

DD

REF

REF

DD

DD

0.625V

0.625V

0.625V

0.646V

0.375V

0.750V

0.375V

0.750V

0.333V

0.625V

0.750V

CHG

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

BULK CHARGE

THRESHOLD (V/CELL)

N/A

N/A

N/A

N/A

1.71

2

1.8

2

2

2.25

N/A

2

4110fa

33

LTC4110

APPLICATIONS INFORMATION

SOFT-START

The LTC4110 is soft-started with the 0.1µF capacitor on

pin. On start-up, the ITH pin voltage will rise quickly

the I

TH

to 0.1V, then ramp up at a rate set by the internal 24µA
pull-up current and the external capacitor. Battery charging
current starts ramping up when I
and full current is achieved with I

voltage reaches 0.7V

TH

at about 2V. With a

TH

0.1µF capacitor, time to reach full charge current is about
8ms and it is assumed that input voltage to the charger
will reach full value in less than 8ms. The capacitor can
be increased up to 1µF if longer input start-up times are
needed.

In any switching regulator, conventional timer-based soft­starting can be defeated if the input voltage rises much
slower than the timeout period. This happens because
the switching regulators in the battery charger and the
computer power supply are typically supplying a fi xed
amount of power to the load. If input voltage comes up
slowly compared to the soft-start time, the regulators will
try to deliver full power to the load when the input voltage
is still well below its fi nal value. If the adapter is current
limited, it cannot deliver full power at reduced output
voltages and the possibility exists for a quasi “latch” state
where the adapter output stays in a current limited state at
reduced output voltage. For instance, if maximum charger
plus computer load power is 30W, a 15V adapter might
be current limited at 2.5A. If adapter voltage is less than
(30W/2.5A = 12V) when full power is drawn, the adapter
voltage will be pulled down by the constant 30W load
until it reaches a lower stable state where the switching
regulators can no longer supply full load. This situation
can be prevented by utilizing the DCDIV resistor divider,
set higher than the minimum adapter voltage where full
power can be achieved.

CALIBRATION MODE BACK-DRIVE CURRENT
PROTECTION

A resistor between CLP and CLN programs the minimum
supply forward current, this feature prevent the LTC4110
from back-driving the supply in calibration mode and
pulling the voltage higher when the system load is low.
The resistor value is given by

I

=

I

BDT

FR MIN

()

R

CL

where

= back-drive current limit threshold, 10mV typical

I

BDT

I

FR(MIN)

= minimum forward current in calibration mode

An RC fi lter may be required to fi lter out system load noise
as shown in Figure 11.

BATTERY AND CHARGER CURRENT SENSE

The LTC4110 uses two sense resistors to monitor and
control all charge and calibration currents: R
R

SNS(FET)

R

SNS(BAT)

R

SNS(BAT)

.

is used to monitor the DC current going into

SNS(BAT)

and

the battery for charge, and the current going out of the
battery for calibration. Before any current programming
can be done, the value of R

SNS(BAT)

must be determined

fi rst. Highest accuracy is achieved when full-scale current,

is set to develop a 100mV drop across the resistor.

I

MAX

Although values greater than 100mV can be used to improve
accuracy, this requires larger sense resistors to handle
the extra heat and lower effi ciency. I

must be set to

MAX

34

LTC4110

BACK
DRIVE

–

CL1

10mV

+

+

Figure 11. Back-Drive Protection

CLP

CLN

4110 F11

V

IN

100nF

10mV

TO

+

5k

SYSTEM
LOAD

C

IN

4110fa

APPLICATIONS INFORMATION

LTC4110

the highest current fl ow between charge and calibration
modes, whichever is greater.

mV

=

100

I

MAX

R

SNS BAT

()

See Table 10 for example values.

R

SNS(BAT)

accuracy is intentionally made very high to permit
development of an accurate host software based capacity
measurements of standard batteries. Use resistors with
1% accuracy or better or use a 4-terminal Kelvin sensing
resistor. See the PCB Layout section for a reasonable no
cost Kelvin sensing layout that permits the use of less
expensive standard two terminal sense resistors. For more
electrical information relating to R

SNS(BAT)

itself, see the

Component Selection section.

As designed, any signifi cant AC ripple voltage seen by
CSP and CSN pins can lead to current sensing errors for
both current programming and capacity measurements.
To prevent the Flyback’s AC ripple voltage from interfering
with DC accuracy, R

SNS(BAT)

installed between the R

must have a RC fi lter network

SNS(BAT)

and CSP and CSN pins.

The CSP and CSN pins have an input bias current of ±10nA
typically. A very large R

CSP1

+ R

value will cause a

CSP2

large current mismatch error. The current fl owing into
the CSP and CSN pins equals V
100mV/(R

CSP1

+ R

), a very small R

CSP2

SNS

/(R

CSP1

CSP1

+ R

+ R

CSP2

CSP2

) =

value
will result in a large current. Typically a value between 3k
and 30k gives the best performance.

Recommended starting values for the fi lter is:

= R

R

CSP1

+ R

R

CSP1

= C

C

CSP

Figure 12 shows typical values for C

R

SNS(FET)

between 1K and 2K

CSN1

= R

CSP2

CSN

CSN1

= about 3 • C

+ R

CSN2

ITH

.

= about 3K

= 0.1µF

ITH

The LTC4110’s Flyback converter operates in current mode
with R

SNS(FET)

monitoring cycle-by-cycle transformer cur-

rent in both Charge and Calibration modes. The LTC4110’s

pin serves two functions. First is to regulate the

I

SENSE

primary current as required by the feedback loop. Second
is to monitor the secondary current and check for short
circuits. The traditional Flyback primary and secondary
currents look like the following:

∆I

0

0

Figure 13. Flyback Primary and Secondary Current

I

PRI

PRIMARY CURRENT

I

PRI

SECONDARY CURRENT

N

4110 F13

The waveforms in Figure 13 each assume a view of posi­tive current fl ow into the load. The value N represents the
ratio of the secondary to the primary with the primary
set to a value of 1. Unlike a traditional Flyback topology,
the LTC4110 Flyback is bi-directional, so the meaning of
“primary” is a function of the operating mode. In order

LTC4110

C

CSP

R

CSP2

+

CA

–

2k

R

CSN2

2k

Figure 12. CSP, CSN RC Filter

330n

C

CSN

330n

R

CSP1

1k

RCSN1

1k

R

SNS(BAT)

100mV

4110 F12

4110fa

35

LTC4110

APPLICATIONS INFORMATION

to monitor the primary current in both sides with a single
R

SNS(FET)

connected prior to R

resistor, both transformer windings must be

SNS(FET)

. Since the secondary phase
is always 180 degrees out of phase with the primary, the
following current waveform in Figure 14 is the result.

I

PRI

0

Figure 14. R

SNS(FET)

PRIMARY CURRENT

I

PRI

SECONDARY CURRENT

N

Current Waveform

4110 F14

In terms of current sensing, the primary current portion
of the above waveform is monitored for peak current (DC
+ AC) at any time in any mode. It does not monitor the
batteries’ DC current. The LTC4110 uses leading edge
blanking to mask out noise to make the application of this
part simple to use. The secondary portion of the above
waveform is monitored for negative peak current to sense
for short circuit.

The value of ripple current, ΔI, is a direct function of the
transformer inductance. See transformer section for more
information about transformer ripple current.

You must calculate the I

for both charge current mode

PRI

and calibration current mode. The equation for calculating
the I

I

PRI

for charge mode is as follows:

PRI

I

PRI(CHG)

I

CHG

=

E

2•f•L



V

BAT

•



V



DCIN

V

BAT•VDCIN

•V

( )

PRI

+N

BAT



+




+N•V

DCIN

for the Calibration mode is as follows:

I

PRI(CAL)=ICAL



•




N•V

V

BAT

DCIN

V

BAT•VDCIN

+1



+






2•f•(N2•L

PRI

)• V




DCIN

+

V

BAT

N

(1)

(2)






The value of E is the fl yback effi ciency. Use 80% (0.8) as
the value since the fl yback uses synchronous rectifi ca­tion. E is not used for the calibration equation because

in calibration mode input current is regulated, not the
output current.

The LTC4110’s I
voltage range for V

pin has a limited usable positive

SENSE

SNS(FET)

. The range must be between
30mV and 150mV peak in both charge and calibration
modes when operating at full current. The negative portion
of the waveform is also monitored but has a dynamic trip
level that tracks the actual primary current. The trip level
has a gain factor of –3. If the secondary current trips the
negative level, the fl yback goes into current limit.

These limits have the following implications:

• The ratio of peak current between I

PRI(CHG)

cannot be greater than 5-to-1 as seen by R

and I

PRI(CAL)

SNS(FET)

.

• The transformer turns ratio will approximately reduce

the maximum available DC current ratio between I

by a factor of 1/N. The additional variables

to I

CAL

CHG

being ripple current and effi ciency.

• You cannot use a transformer with a turns ratio

greater than 3.

• Because effi ciency is always less than 100%, you

never have to worry about peak secondary current
causing a false short circuit trip within the turns ratio
limit of 3 or less.

As a design starting point, use the lowest value between
I

PRI(CHG)

and I

PRI(CAL)

for good effi ciency and solve for R

R

SNS FET

=

()

With an initial value of R
V

SNS(FET)

I

PRI(CAL)

using the highest value between I

and see if the calculated value of V

V

SNS FET

I

PRI

for I

PRI

()

SNS(FET)

, let V

SNS(FET)

SNS(FET)

be set to 50mV

.

identifi ed, solve for

SNS(FET)

PRI(CHG)

falls

or

below the upper limits. If it is too high, you may have to
drop the value of R

SNS(FET).

If you cannot meet the V

SNS(FET)

upper or lower limits and/or ratio limits, you may have to
back off on one

of the I

CHG

and I

DC current parameters

CAL

to compensate.

Once within all the limits, optimize R

SNS(FET)

effi ciency by using very low value of R
a popular R
values of R

SNS(FET)

SNS(FET)

value. The tradeoff of using lower

is increased waveform jitter due to

for maximum

SNS(FET)

and/or fi nd

higher switching noise sensitivity issues.

4110fa

36

APPLICATIONS INFORMATION

LTC4110

PROGRAMMING CHARGE VOLTAGE

Depending on the battery chemistry chosen by the TYPE
pin, a charge termination voltage or a fl oat voltage will be
required. The difference between the two is time. A fl oat
voltage is applied to a battery forever. The V

pin is used

CHG

to set any of these voltages and the equations remain the
same. For this document, we will use the term fl oat voltage
generically. If nickel chemistry is chosen, the V

CHG

pin is
disabled placing the charger in constant current mode. If
you are using a smart battery, wake-up charge is subject
to the V

Connecting the V

pin setting when active.

CHG

pin to GND will set the default per

CHG

cell fl oat voltage (4.2V for Li-ion, 2.35V for SLA). If a dif­ferent fl oat voltage is needed, tie the V
between 0.25 V
on the V

pin. Unlike V

REF

and 0.75 V

BGR

REF

voltage of the same voltage as V
(±0.5%) tolerance than V



V

FLOAT

= 2•




V
V

CHG

BGR

REF

 1

using a resistor divider

BGR

, V

is an internal reference

BGR

but with a much tighter

REF

.



•0.6




pin to a voltage

CHG

where

ΔV

V

CHG

V

BGR

The resistor divider connected to V
(see the Programming Charge Time with TIMER and V

= Adjusted Float Voltage – Default Float Voltage

FLOAT

= V

Pin Voltage,

CHG

= 1.220V

pin will affect timer

REF

REF

Pins section for more details).

THERMISTOR FOR LEAD ACID BATTERIES

When the TYPE pin is programmed for Lead Acid, THA
pin will be force to V

, THB will be used to sense the

BGR

NTC resistance. The value of R1 is given by:

R1=R0 •

β−2•T0

β +2•T0

β = exponential temperature coeffi cient of resistance

The LTC4110 is designed to work best with a 5% 10k NTC
thermistor with a β near 3750, such as the Siemens/EPCOS
B57620C103J062. In this case, R1 = 7256Ω.

R1

+

THA

THB

R

NTC

V

BGR

+

TH_HI

–

HI_REF

REF

LO_REF

Figure 15. Lead Acid Thermistor

+

TH_LO

–

LOGIC

RES_OR

RES_HOT

4110 F15

LEAD ACID BATTERY TEMPERATURE COMPENSATION

To program the temperature compensation for SLA charg­ing, an external circuit is needed as shown in Figure 16.

The values are given by:

R1=R0 •

β−2•T0

β +2•T0

k1=

R0

R0 +R1

TCk1=–

TCV

k2 =

β •R1•R0

(R1+R0)

FLOAT

2

•T0

2

1.2 • TCk1

0.5+ΔV

k3 =

FLOAT

/ 1.2− k1• k2

1− k2

where:

TCV

= temperature coeffi cient of the fl oat voltage

FLOAT

(Range: –2mV/°C – –6mV/°C)

where:

R0 = thermistor resistance (Ω) at T0

T0 = thermistor reference temperature (°K)

ΔV

= fl oat voltage at 25°C – default fl oat voltage

FLOAT

2.35V (Range: –0.15V – 0.15V)

For example, if a 10k NTC with β = 3750 is used, desired

4110fa

37

LTC4110

APPLICATIONS INFORMATION

V

REF

(1 – k3) • R

+

k3 • R

–

R2

R2

k2 =

R2 + R3

Figure 16. Lead Acid Temperature Compensation

R3

+

–

VREF

VREF

V

CHG

THA

R1

THB

R

NTC

10k

R0

k1 =

R0 + R1

4110 F16

fl oat voltage = 2.5V at 25°C with a temperature coeffi cient of
–2mV/°C, then R1 = 7256, k1 = 0.580, TCk1 = –10.3m/°C,
ΔV

= 2.5 – 2.35 = 0.15V, k2 = 0.162, k3 = 0.634.

FLOAT

R

SNS(BAT)

= resistor between fl yback transformer and

battery

= R

R

CSP

R

= R

CSN

R

= resistor connected between I

ICHG

= resistor connected between I

R

IPCC

= resistor connected between I

R

ICAL

CSP1

CSN1

+ R

+ R

CSP2

CSN2

pin and GND

CHG

pin and GND

PCC

pin and GND.

CAL

If any programming resistor value on any of the three
pins exceeds 100k, see Flyback Compensation section
for more information.

Pins can be tied together to save components if any of
the currents have the same value. If two pins share a
common programming resistor greater than 100k, only
one compensation circuit is required.

If the TYPE pin is set for SLA/LEAD ACID, then the I
pin is not used. You can leave the I

pin open.

PCC

PCC

PROGRAMMING BACKUP MODE ENTRY THRESHOLD
AND CALIBRATION MODE BACK-DRIVE VOLTAGE
DETECTION THRESHOLD

PROGRAMMING CURRENT

Charge/calibration currents are programmed using the
following equations:

V

=

R

=

R

R

BGR

SNS BAT

()

V

BGR

SNS B

(

V

BGR

SNS BAT

()

I

CHG

I

PCC

I

CAL

AAT

R

CSP

•
R

ICHG

R

CSP

•
R

IPCC

)

R

CSN

•=

R

ICAL

where:

= bulk charge current

I

CHG

= preconditioning charge current

I

PCC

= calibration current

I

CAL

= 1.220V

V

BGR

A resistor divider connected to supply input sets both the
backup mode entry threshold and the calibration mode
back-drive voltage detection threshold.

V

BACKUP

V

BACKDRIVE

R2
R

1

V

=



=




BACKUP

V

BGR

R2

R

=

1






+1

V
V

 1






OVP

BGR

•V






BGR

•V

BACKUP

where:

V

BACKUP

= supply voltage when backup starts, it should

not be programmed to less than 4.5V

V

BACKDRIVE

= supply voltage when calibration is terminated,

it should not be programmed to more than 20V

= DCDIV pin back-drive detect threshold in calibration

V

OVP

mode, typically 1.5V (see V

OVP

)

4110fa

38

APPLICATIONS INFORMATION

LTC4110

R1 = resistor connected between DCDIV and GND

= resistor connected between supply input and

R2
DCDIV

= reference voltage 1.220V

V

BGR

For example, if supply input = 12V and backup starts when
it drops to 11V, then V

BACKUP

= 11V, V

BACKDRIVE

= 13.5V,

R2/R1 = 8.02, choose R1 = 10k, then R2 = 80.6k.

If a higher ratio than V
V

BACKDRIVE

and V

BACKUP

OVP/VBGR

= 1.23 is desired between

, a third resistor can be used as

shown in Figure 17.

SUPPLY

INPUT

OPTIONAL RESISTOR

TO INCREASE THE

1.23 TO 1 RATIO

R3

V

DC

Figure 17. Backup and Boost Detect Comparators

RRVV

2

BACKDRIVE BACKUP

= −

1023

V

BACKDRIVE

023

3

R

RVV

DC

=

1

BGR

023

VV–. •123

BACKDRIVE BACKUP

R2

DCDIV

R1

1.23 • V

–

V

.•

––. •

.•

•

.•

BGR

123

VV

V

BACKUP

V

DC

V

BACKD

RRIVE BACKUP

BACKDRIVE BACKUP

V

DDC

–

+

V

BGR

+

–

BGR

1

−

V

–

–. •

123

1−

CMP

CMP

BACKUP

BOOST

4110 F17

−

where:

= Any regulated DC voltage available in the system

V

DC

such as SMBus pull up, LED supply or LTC4110’s V

DD

voltage, must be higher than 1.7V. R3 = resistor connected
between V

and DCDIV.

DC

For example, if supply input = 12V and backup starts when
it drops to 8V, calibration terminates when it rises to 16V,
and V

= VDD = 4.75V, then R2/R1 = 21.87, R3/R1 = 3.88,

DC

choose R1 = 10k then R2 = 221k and R3 = 39.2k.

If the noise on supply input is a problem, a capacitor can
be connected between DCDIV and GND.

PROGRAMMING CALIBRATION/BACKUP CUT-OFF
THRESHOLD

The pins V

CAL

and V

are used to calculate custom

DIS

discharge cut-off voltages for their respective operating
modes. The equations shown below are generic for both.
There is no implied relationship between V

CAL

and V

DIS

for they are independent of each other.

The equations are most helpful if you pick the V

CUTOFF

voltage you want, within the range limits offered, and then
solve for V

calculated, determine the necessary voltage divider

V

DIS

CAL

or V

network from V

. With the voltage value of V

DIS

required to get the calculated voltage

REF

CAL

or

on these pins respectively. It is recommended that one
single series resistor divider network from V

to ground

REF

be used to obtain all of the pin voltages you need. It should
be noted that custom values of V

would also affect the

CHG

divider network complexity. See Programming Charge
Voltage section for more information.

Connect the V

CAL

or V

pin to GND will set the default

DIS

calibration/backup cut-off threshold (2.75V for Li-Ion,

1.93V for SLA, 0.95V for NiMH/NiCd). These threshold
voltages can be adjusted (±400mV for Li-Ion, ±300mV
for SLA, ±200mV for NiMH/NiCd) by tying the pin to ap­propriate voltage on the V

pin resistor divider according

REF

to the following equations:

VV

/

CAL DIS

= −

V

BGR

/

V

AAL DIS

C

=

V

BGR

VV

/

CAL DIS

= ••( / )2 NiMH NiCD

V

BGR

•. ( )42

V

•. ( )

235

Li Ion

SLA

V

CUTOFF

V

CUTOFF

V

CUTOFF

4110fa

39

LTC4110

APPLICATIONS INFORMATION

where

V

V

V

The resistor divider connected to V
See the Programming Charge Time with TIMER and V

= adjusted cutoff threshold voltage

CUTOFF

CAL/VDIS

=1.220V

BGR

= voltage on V

CAL

or V

pin

DIS

pin will affect timer.

REF

REF

Pins section for more details.

PROGRAMMING CHARGE TIME WITH TIMER AND

PINS

V

REF

Charge time limits for Li-Ion batteries can be programmed
by selection of capacitance on the TIMER pin, but is
dependent upon resistance on the V

pin. Typical pro-

REF

grammed bulk charge times range from 2 to 12 hours
and is set as follows:

C

TIMER

(F) =

As an example if R
time limit is fi ve hours then C

T(Hrs)

(944• R

= 113k and the desired bulk charge

VREF

VREF

(Ω))

TIMER

= 47nF. See F

TMR

which directly affects the 944 constant in the Electrical
Characteristics Table for the tolerance.

Avoid capacitors with high leakage currents. The V

REF

pin load resistor range is 49k to 125k or 10µA to 25µA of
load current. At 125k the maximum capacitance on V

REF

is limited to a maximum of 50pF to maintain suffi cient AC
stability for the internal amplifi er. At 49k the maximum is
125pF. The maximum capacitance is inversely proportional
to the resistance.

The voltage (V

) on the V

REF

pin can be used as a

REF

precision voltage for other uses with some limitations.
The total V

pin current must not exceed 25µA and the

REF

capacitance must be limited as discussed above. Load
current fl uctuations will modulate the programmed charge
time. In shutdown mode V

In some applications a divided down V
to program the SELA, SELC, TYPE, V

will drop to 0V.

REF

REF

CHG

voltage is needed

, V

and V

CAL

DIS

pins. This is easily implemented by use of a resistor divider
connected from V

to GND that sets the V

REF

pin current

REF

instead of a single resistor.

If the TYPE pin is set for SLA/LEAD ACID or any nickel
based smart battery, the TIMER pin is not used. You can
ground the TIMER pin. Furthermore, if there is no need
of any timer function and there is no need of any voltage
divider from V
the V

pin between 10µA and 25µA. It is recommended

REF

you place a 49.9k load resistor from V

to ground, you must still keep a load on

REF

to ground.

REF

CHARGING BATTERIES OVER 12 HOURS

In situations where required bulk charge time cycle will
exceed the 12 hour time limit imposed by the charge TIMER
pin, you have two options. You can have an SMBus host
clear the CHG_FLT bit and force start another charge cycle
or you can switch to a smart version of the same battery.
If you chose the former, reduce the TIMER pin time to
about 2/3 of the actual time required. This will result in
faster termination in the second cycle and with autorestart
cycles when V

is tripped. If you choose the smart bat-

AR

tery option, the smart battery itself safely controls charge
termination. Bulk charge can last as long as necessary
to charge the battery to 100%. No host is required to do
anything, as the battery will maintain its full charge state
using its SMBus charge commands.

PROGRAMMING AC PRESENT INDICATION DELAY
TIME WITH ACPDLY AND V

REF

PINS

When the main supply, DCIN, returns after a power failure
the ACPb pin is driven low to indicate presence of main
power. This transition can be delayed to allow time for the
system to stabilize before actions are taken by the system
based on this pin status. The high to low transition only
delay on the ACPb pin can be programmed by selection
of capacitance on the ACPDLY pin, but is dependent upon
resistance on the V

pin. Typical programmed delay times

REF

range from 10ms to 200ms and is set as follows:

T(s)

2•R

VREF

TIMER

(Ω)

VREF

= 113k and the desired delay time

= 470nF. See tAC in the Electrical

C

ACPDLY

(F) =

As an example if R
is 105ms then C
Characteristics Table for the tolerance.

40

4110fa

APPLICATIONS INFORMATION

LTC4110

Avoid capacitors with high leakage currents. See the
Programming Charge Time with TIMER and V
section for details concerning the V

pin. For minimum

REF

REF

Pins

delay open the ACPDLY pin.

BAT PIN CURRENT IN IDLE MODE

When LTC4110 is in IDLE mode (i.e., not in charge, calibra­tion or backup mode), there will be a typical 30µA current
pulled from the battery through the BAT pin, if this current
is of concern, a diode in series with a resistor can be con­nected between DCIN and battery to compensate it.

SHOW BATTERY FULL WITH ACPB AND CHGB

Tie the source of an N-MOSFET to ACPb, gate to CHGb and
drain in series with R to an LED to show battery full. In
that case if CHG or ACP status LED is not needed, replace
it with a short but keep the pull-up resistor.

+5V

This current ramp starts at zero right after the primary side
MOSFET (CHGFET in charge mode, DCHFET in calibration
mode) is turned on. The current rises linearly towards a
peak of V

= DCIN in calibration mode), shutting off once the

V

SEC

/400k (where V

SEC

primary side MOSFET is turned off. A series resistor (R
connecting the I
(R

SNS(FET)

) thus develops a ramping voltage drop. From

the perspective of the I

pin to the current sense resistor

SENSE

SENSE

= BAT in charge mode,

SEC

SL

pin, this ramping voltage

)

adds to the voltage across the sense resistor, effectively
reducing the current comparator threshold in proportion
to duty cycle. This stabilizes the control loop against
subharmonic oscillation. The amount of reduction in the
current comparator threshold (ΔV

) can be calculated

ISENSE

using the following equation:

V

ΔV

ISENSE

=DUTY CYCLE •

SEC

400k

•R

SL

To program m = m2,

kR

400••

SL

1

=

N

FLm

R

SNSFET

•

,

FULL ACP

Figure 18. Display Battery Full

CHG

CHGb

ACPb

4110 F18

FLYBACK COMPENSATION

The values given for the I

pin in the application schematics

TH

have been found to compensate both the voltage loop and
current loop quite well. However, if the resistor connected
to I

CHG

CAL

or I

is larger than 100k, a 37k resistor in

PCC

, I
series with a 100nF capacitor should also be connected
between that pin and GND to compensate the loop.

SLOPE COMPENSATION

The LTC4110 injects a ramping current through its I
pin into an external slope compensation resistor (R

SENSE

SL

).

where

N = transformer turns ratio N

R

SNS(FET)

= sense resistor connected between MOSFET

BAT/NDCIN

and GND

f = switching frequency

Lm = magnetizing inductance of the transformer

Designs not needing slope compensation may replace

with a short.

R

SL

CALCULATING IC POWER DISSIPATION

The power dissipation of the LTC4110 is dependent upon
the gate charge of the two MOSFETs (Q

and QG2). The

G1

gate charge is determined from the manufacturer’s data
sheet and is dependent upon both the gate voltage swing
and the drain voltage swing of the MOSFET. Use 5V for
the gate voltage swing and V

for the drain voltage

DCIN

swing.

P

D

= V

DCIN

• (f

(QG1 + QG2) + IQ)

OSC

4110fa

41

LTC4110

APPLICATIONS INFORMATION

Example:

V

DCIN

= 3mA

I

Q

P

D

= 12V, f

= 144mW

= 300kHz, QG1 = QG2 = 15nC,

OSC

SNUBBER DESIGN

The values given in the applications schematics have been
found to work quite well for this 12V-1A application. Care
should be taken in selecting other values for your applica­tion since effi ciency may be impacted by a poor choice.
For a detailed look at snubber design, Application Note
19 is very helpful.

COMPONENT SELECTION

Current Sense Resistors

The LTC4110 uses up to three sense resistors—one of
them optional. In general, current sense resistors should
have a low temperature coeffi cient and suffi cient power
dissipation capability to avoid self-heating. Tolerance
depends on system accuracy requirements.

R

SNS(FET):

highest value between I

The power rating of R

or I

CHG

SNS(FET)

CAL

is defi ned by the

and the transformer
turns ratio. Use one the following equations to calculate
I

RSNS(FET)

depending on which value, I

CHG

or I

CAL

which-

ever is higher.

I

R(SNSFETCHG)

• 1+

I

CHG

I

R(SNSFETCAL)

I

• 1+

CAL











=

V

N•V

=

V

N•V

BAT

DCIN

BAT

DCIN














E





N•E






N•V

2

•V

V

BAT

DCIN

2

•V

DCIN

BAT

+1





+1







Plug in the higher value of the above two results as
I

R(SNSFET)

P

R(SNSFET)

and solve for power:

= I

R(SNSFET)2

• R

SNS(FET)

RCL:

RCL power rating is a function of the maximum forward

current the system load draws. See Figure 11.

P

R(CL)

= I

MAX

2

• R

CL

Find a sense resistor who’s power rating is greater than
P

R(CL)

R

SNS(BAT):

highest current value between I

R

SNS(BAT)

power rating is a function of the

CHG

or I

with which

CAL

the battery will work. Plug in the higher of the two into
I

BAT(MAX)

P

R(SNSBAT)

and solve:

MAX

2

• R

= I

SNS(BAT)

Use a sense resistor with a power rating greater than
P

SNS(BAT)

FLYBACK MOSFET SELECTION

The LTC4110 uses two low side N-channel switching
MOSFETs in its fl yback converter. These MOSFETs have
dual roles. An any given time, only one MOSFET is the
primary switch while the other acts as a synchronous recti­fi er on the secondary to improve effi ciency. The individual
MOSFETs’ roles depend on whether the battery is being
charged or calibrated. Each MOSFET specifi cation must
account for both roles.

The MOSFET voltage ratings in a fl
with other factors beyond V

yback design must deal

. During switch “on” time, a

IN

current is established in the primary leakage inductance

) equal to peak primary current (I

(L

L

turns off, the energy stored in L

). When the switch

PRI

, (Energy = I

L

PRI

2

• L

L

/2)
causes the switch voltage to fl y up, starting from the input
voltage on up to the breakdown of the MOSFET if the volt­age is not clamped. Thus, the snubber design is critical
in dealing with this voltage spike and can infl uence the
MOSFET voltage selection value. From a MOSFET point
of view, the minimum voltage must be greater than the
snubber clamp voltage V

SNUB

. If V

itself is too low,

SNUB

zener clamp dissipation rises rapidly thus encouraging
higher MOSFET voltages. The maximum DC voltage that

the N-channel MOSFET

VV

CHG FET DCIN

=+

()

VVNV

CAL FET BAT DCIN()

=+•

s sees is:

V

BAT

N

4110fa

42

APPLICATIONS INFORMATION

LTC4110

The VDS ratings of the MOSFETs need to be higher than
these values.

The MOSFET current ratings for the primary side must be
higher than I

, which is I

PRI

PRI(CHG)

or I

PRI(CAL)

for charge
and Calibration mode respectively. See Equations 1 and 2.
MOSFET current ratings for the secondary side must be
higher than I

/N. Since both MOSFETs must perform

PRI

both roles, the minimum current rating of the MOSFETs
should be greater than the higher of these values.

MOSFET power dissipation is a function of the RMS cur­rent fl owing through the MOSFET.

Charge Mode:

I

()

PRI FETCHG

I

CHG

•

E

II

SEC FETCHG CHG

()

=

VVNV

()

•+•

BAT BAT DCIN

V

DCIN

VNV

+•

=•

BAT DCIN

NV

•

DCIN

Calibration Mode:

VNV

+•

II

PRI FETCAL CAL

()

=•

I

SEC FETCAL

()

IE

••

CAL

=

VVNV

•+•

BAT BAT DCIN

Where I
I

PRI(FETCAL)

PRI(FETCHG)

is the same FET as I

is the same FET as I

BAT DCIN

NV

•

DCIN

()

V

NN

DCI

SEC(FETCAL)

SEC(FETCHG)

.

and

Using the equation below, plug in the higher current from
above into I

to fi nd each FET’s power dissipation for

FET

the given mode.

2

P

The R

= I

FET

DS(ON)

vatively you can use the R

• R

FET

DS(ON)

value of the MOSFET depends on VGS. Conser-

value with a VGS rating of

DS(ON)

4.5V. If you are using a dual-MOSFET package, determine
whether charge mode or calibration mode results is the
highest overall power dissipation and use that as the rating
for the dual MOSFET.

The MOSFET should be specifi ed for fast or PWM switching.
The MOSFET that meets all the above specifi cations but
has the lowest Q

and/or QGD is often the best choice.

G

PowerPath MOSFET SELECTION

Important parameters for the selection of PowerPath
MOSFETS are the maximum drain-source voltage V
threshold voltage V

.

Q

GATE

, on-resistance R

GS(VT)

DS(ON)

The maximum allowable drain-source voltage, V

DS(MAX)

DS(MAX)

,

and

,
must be high enough to withstand the maximum drain­source voltage seen in the application.

The gates of these MOSFETs are driven by the INID (Input
Ideal Diode) and BATID (Battery Ideal Diode) pins. The
gate turn-on voltage, V

, is set by the smaller of the

GS

PowerPath supply voltage or the internal clamping volt­age V

. For the MOSFET driven from the INID pin its

GON

PowerPath supply voltage is the higher of the DCIN pin
or DCOUT pin voltage. For the MOSFETs driven from the
BATID pin, their PowerPath supply voltage is the higher
of the DCOUT pin or BAT pin voltage. Logic-level V

GS(VT)

MOSFET is commonly used, but if a low supply voltage
limits the gate voltage a sub-logic-level threshold MOSFET
should be considered.

As a general rule, select a MOSFET with a low enough
R
current load and an achievable V

to obtain the desired VDS while operating at full

DS(ON)

. The MOSFET normally

GS

operates in the linear region and acts like a voltage con­trolled resistor. If the MOSFET is grossly undersized then it
can enter the saturation region and a large V

may result.

DS

However, the drain-source diode of the MOSFET, if forward
biased will limit V

. A large VDS combined with the load

DS

current could result in excessively high MOSFET power
dissipation. Keep in mind that the LTC4110 will regulate
the forward voltage drop across the MOSFETs at 20mV
(V

FR

) if R

is low enough. The required R

DS(ON)

DS(ON)

can
be calculated by dividing 0.02V by the load current in amps.
Achieving forward regulation will minimize power loss and
heat dissipation, but it is not a necessity. If a forward volt­age drop of more than 20mV is acceptable then a smaller
MOSFET can be used, but must be sized compatible with the
higher power dissipation. Care should be taken to ensure

4110fa

43

LTC4110

APPLICATIONS INFORMATION

that the power dissipated is never allowed to rise above
the manufacturer’s recommended maximum level.

Switching transition time is another consideration. When
the LTC4110 senses a need to switch any PowerPath
MOSFETs on or off time delays are encountered. MOSFETs
with higher Q

will require more bulk capacitance on

GATE

DCOUT to hold up all the system’s power supply function
during the transition. The transition time of a MOSFET to
an on or off state is directly proportional to the MOSFET
gate charge. Switching times are given in the Electrical
Characteristics Table (see t

dDON

, t

dDOFF

).

TRANSFORMER

There are two ways to design a transformer.

1. Design it yourself.

2. Work with a transformer vendor to identify an off­the-shelf transformer.

Even if you choose to design it yourself, you still have to
fi nd a transformer manufacturer to make it for you.

We recommend contacting a transformer manufacturer
directly since they often have online tools that can help
you quickly fi nd and select the right transformer. There are
many off the shelf transformers that can be successfully be
used with the LTC4110. Table 10 shows some suggested
off the shelf transformers.

If you want to design a custom transformer optimized
for your design, Application Note 19 has an example of
how to design a Flyback transformer in the “Transformer”
section.

Regardless of which way you go, we offer the following
thoughts.

Turns ratio affects the duty factor of the power converter
which impacts current and voltage stress on the power
MOSFETs, input and output capacitor RMS currents and
transformer utilization (size vs power). Using a 50%
duty factor under nominal operating conditions usually
gives reasonable results. For a 50% duty factor, the turns
ratio is:

V

BAT

N

=

V

V

BAT

DCIN

is the nominal battery voltage. N should be calculated
for the design operating in charging mode and in calibration
mode. The fi nal turns ratio should be chosen so that it is
approximately equal to the average of the two calculated
values for N. In addition, choose a turns ratio which can
be made from the ratio of small integers. This allows
bifi lar windings to be used in the transformer, which can
reduce the leakage inductance and the need for aggressive
snubber design, thus improving effi ciency.

Avoid transformer saturation under all operating conditions
and combinations (usually the biggest problems occur at
high output currents and extreme duty cycles). Choose
the magnetizing inductance so that the current ripple is
about 20% of DC current.

Finally, in low voltage applications, select a transformer
with low winding resistance. This will improve effi ciency
at heavier loads.

Table 10. Recommended Components Values for 12V Input Supply Li-Ion Battery Backup System Manager

Cell

MAX

(I

, I

)

CAL

(A) R

CHG

3 1 100 50 24 BH 510-1019 TDK PCA14.5/6ER-U03S002

3 2 50 25 12 COILTRONICS VP4-0140-R

3 3 33 15 9 TDK PCA20EFD-U04S002

4 1 100 50 24 COILTRONICS VPH4-0140-R

4 2 50 25 12 COILTRONICS VPH4-0075-R

4 3 33 15 9 COILTRONICS VP5-0155-R

Note: 1:1 turns ratio for all the transformers listed in the table..

SNS(BAT)

(m)R

SNS(FET)

(m) TRANSFORMER

INDUCTANCE

(μH) TRANSFORMER VENDOR AND PART NUMBER

4110fa

44

APPLICATIONS INFORMATION

LTC4110

INPUT AND OUTPUT CAPACITORS

The LTC4110 uses a synchronous fl yback regulator to
provide high battery charging current. A chip ceramic
capacitor is recommended for both the input and output
capacitors because it provides low ESR and ESL and can
handle the high RMS ripple currents. However, some
Hi-Q capacitors may produce high transients due to self
resonance under some start-up conditions, such as con­necting the charger input to a hot power source. For more
information, refer to Application Note 88.

For charge mode, the ripple current can be calculated as
follows:

I

RMSDCINCAP

I

CHG BAT

=•

E

NV

•

V

DCIN

and

V

II

RMSBATCAP CHG

=•

BAT

NV

•

DCIN

For calibration mode, the ripple current can be calculated
as follows:

Similar techniques may also be applied to minimize EMI
from the input leads.

Diodes

Schottky diodes should be placed in parallel with the drain
and source of the Flyback MOSFETs. This prevents body
diode turn-on and improves effi ciency by eliminating loss
from reverse recovery in these diodes. It also reduces
conduction loss during the dead time of the MOSFETs.

PROTECTING SMBUS PINS

The SMBus inputs, SCL and SDA, are exposed to uncon­trolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to transients that can cause
damage after repeated exposure. Also, if the battery’s posi­tive terminal makes contact to the connector before the
negative terminal, the SMBus inputs can be forced below
ground with the full battery potential, causing a potential
for latch-up in any of the devices connected to the SMBus
inputs. Therefore, it is good design practice to protect the
SMBus inputs as shown in Figure 19.

NV

•

IIE

RMSDCINCAP CAL

=••

V

DCIN

BAT

and

V

II

RMSBATCAP CAL

=•

BAT

NV

•

DCIN

EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or induc­tors may be added to increase battery impedance at the
300kHz switching frequency. Switching ripple current splits
between the battery and the output capacitor depending
on the ESR of the output capacitor and the battery imped­ance. If the ESR of the output capacitor is 0.1Ω and the
battery impedance is raised to 2v with a bead or induc­tor, only 5% of the ripple current will fl ow in the battery.

V

DD

CONNECTOR

TO BATTERY

Figure 19. SMBus Protection

TO SYSTEM

4110 F19

START-UP DELAYS

When exiting shutdown mode, internal supplies must
ramp up and settle. 500µs-1ms should be adequate after
shutdown is exited or when power is quickly (<100µs)
fi rst applied to the IC. For slow power ramp-up (>1ms)
internal supplies will be in regulation after power input
reaches 4.5V. Until internal supplies settle, status outputs
may be invalid.

4110fa

45

LTC4110

APPLICATIONS INFORMATION

OPERATION WITH DUAL BACKUP SYSTEMS

If a dual backup system consisting of two LTC4110s
each with its own backup battery is needed and a SMBus
is used, each LTC4110 should be programmed by the
SELA pin to have different addresses. If smart batteries
with SMBus are used, a SMBus mux may be required to
selectively address each battery. This mux may also be
used to address the LTC4110. See SMBus Interface section
for more information.

BACKUP OPERATION WITH EXTERNAL BACKUP
SUPPLY REGULATOR

If a dedicated DC regulator with enable inputs is used in
place of an actual battery to supply backup power, the
PowerPath MOSFETs connected to the BATID pin may not
be required. It depends on the regulator’s ability to accept
being back driven by a voltage on the DCOUT pin coming
from some other power source such as DCIN. The ACPb
pin can control the regulator such that it is turned on when
DCIN goes away. However for fastest transient response,
keeping the regulator on may prove to work better. The
output voltage of the regulator should be less than DCOUT
under normal operating conditions so that DCIN is pro­viding the power to the load. The voltage provided by the
regulator must not be allowed to go below the lower limit
of the DCOUT pin or erratic operation may result.

BACKUP OPERATION WITH A DOWNSTREAM
REGULATOR

Since the backup voltage supplied to the load is not regu­lated, often some form of a regulator is needed between
the LTC4110 and the actual load. The characteristics of
this regulator should offer high effi ciency when running
from the battery in backup mode to maximize backup
time. Some regulators may need advance warning when
to enter into this mode, which can be accomplished by
using the LTC4110’s ACPb pin.

DCIN TO BATTERY TRANSITION CHATTER REMOVAL

The LTC4110 is designed to automatically switch the bat­tery to the output load when DCIN is lost. Under certain
conditions, a rapid loss of DCIN can cause the input and
battery ideal diode circuits to chatter. The result is the
transition time between the DCIN FET turning fully off
and the battery FET turning fully on can last in excess
of 200ms with each switching on and off multiple times.

This problem is likely to occur under the following
conditions:

1. Large system load causing the INID pin to be more

than 3V below DCIN.

2. The DCIN and battery voltages are approximately the

same.

3. The DCIN pin goes high impedance very rapidly (less

than 10µs)

Q1 and R1 shown in Figure 20 increase the effective hys­teresis of the DCDIV pin by using the ACPb pin to drive
Q1. The threshold of Q1 must be less than the V

SUPPLY

to assure the drain of Q1 pulls down to ground when
ACPb is high. R1 sets the amount of increase in negative
hysteresis you need relative to the values chosen for the
DCDIV resistor divider. A 100k is suggested as a starting
point. You will also need to place a capacitor C

ACPDLY

on

the ACPDLY pin. This capacitor in conjunction with resistor

should be set for a delay of 10ms, which is more

R

VREF

than suffi cient to eliminate all the chatter.

DCDIV

R1

100k

Q1

2N7002

Figure 20.

ACPb

4110 F20

46

4110fa

APPLICATIONS INFORMATION

LTC4110

PCB LAYOUT CONSIDERATIONS

For maximum effi ciency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical fi eld (EMI) radiation and high frequency resonant
problems, proper layout of the components connected to
the IC is essential.

Flyback Layout

Lowest EMI and maximum effi ciency are obtained when the
high frequency switching current loop area is minimized.
It is best to make direct connections, avoiding the use of
other circuit board copper planes, i.e. no vias, in making
the following connections for this prevents current based
noise injection into the copper planes below.

1. Input/output capacitors positive terminals need to
be placed as close as possible between the fl yback
transformer “top” or positive supply rail connections
and R

SNS(FET)

ground connection.

2. Place fl yback MOSFETs drain connections right next
to the fl yback transformers “bottom” connections.

3. Place the R

SNS(FET)

current sense resistor right next
to the N-MOSFET source connections completing
the connection back to the input/output capacitors’
negative terminals.

4. Place the snubber connections as close as possible
to the circuit after the above layout connections are
completed as required. Again, avoid using vias.

5. The layer below the fl yback layout should be ground.

Other Recommendations

6. Optionally use vias to connect power supply sources
positive and negative (ground) connections from
other copper layers to the fl yback layout. Place
multiple vias in a tight cluster such that they act as
one large via. Recommended 1 via for each 0.5A of
current

7. The current sense feedback traces must be routed
together as a single pair on the same layer at any
given time with smallest trace spacing possible.
Locate any fi lter component on these traces next to
the IC and not at the sense resistor location.

8. The control IC must be close to the switching FET’s
gate terminals. Keep the gate drive signals short for
a clean FET drive. This includes IC supply pins that
connect to the switching FET source pins. The IC can
be placed on the opposite side of the PCB relative to
fl yback layout above.

9. Figure 21 shows an inexpensive way to achieve
Kelvin like sensing using standard current sense
resistors.

DIRECTION OF CHARGING CURRENT

R

SNS(BAT)

4110 F21

TO CSP AND CSN

Figure 21. Kelvin Sensing of Battery Current

4110fa

47

LTC4110

TYPICAL APPLICATIONS

Battery Backup System Manager Controlling a Six-Series Cell

SLA Battery with Temperature Compensation

SUPPLY

INPUT

(12V)

8.66k

1.21k

+

–

+

–

R

CL

0.02
1W

0.1µF
LOW

ESR

DCIN

CLN

CLP

25.5k

V

DD

C

DCDIV

THA

THB

V

V

V

V

I

I

I

SELA

SELC

SDA

SCL

7.32k

24.3k

V

DD

36.5k

16.2k

V

DD

84.5k

2

I

TO

HOST

REF

CHG

CAL

DIS

CHG

CAL

PCC

INPUT

IDEAL DIODE

INID

LTC4110

Q2

DCOUT

BATID

CHGFET

DCHFET

I

ACPDLY

TIMER

GP101

GP102

GP103

NC

SENSE

CSP

CSN

BAT

I

V

ACPb

0.1µF
LOW
ESR

20µF

VERY

LOW ESR

R

SL

3.32k

1k2k

1k2k

TH

3.01k

33

0.5W
5%

Q1A

330nF

330nF

0.1µF

T1

1nF1nF

33

0.5W
5%

Q1B

R

SNS(FET)

0.05

0.5W

FLOAT VOLTAGE = 2.35V/CELL

AT 25°C TC = –2mV/°C

20µF
VERY
LOW ESR

R

SNS(BAT)

0.1

0.25W

+

+

+

+

+

DD

0.1µF
LOW
ESR

+

TO SYSTEM
LOAD

TO BACKUP
LOAD

Q3

BATTERY
IDEAL
DIODE

12V

10k
NTC
ß = 3750

NO TIMER
HIGH CURRENT BACKUP LOAD DESIGN

0.5A BACKDRIVE CURRENT CUTOFF (CALIBRATION)
1A CHARGE AND CALIBRATION CURRENT
ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE

Q1: Si7216DN
Q2: Si7445DP
Q3: Si7983DP
T1: BH510-1019

48

TYPE

GND SGND

SHDN

4110 TA04

4110fa

TYPICAL APPLICATIONS

Battery Backup System Manager Controlling a Nine-Series Cell NiMH Battery with

LTC4110

Calibration Managed by Host Processor

SUPPLY

INPUT

(12V)

8.66k

1.21k

49.9k

R

CL

0.02
1W

0.1µF
LOW

R

R

36.5k

187k

37.4k

ESR

THA

THB

1.13k

54.9k

0.1µF

I2C

HOST

TO SYSTEM

INPUT

IDEAL DIODE

Q2

DCIN

CLN

CLP

DCDIV

THA

THB

V

REF

V

CHG

V

CAL

V

DIS

I

CHG

I

CAL

I

PCC

SELA

SELC

TO

SDA

SCL

INID

LTC4110

DCOUT

NC

BATID

CHGFET

DCHFET

I

SENSE

CSP

CSN

BAT

I

ACPDLY

TIMER

V

DD

ACPb

GP101

GP102

GP103

TH

LOW ESR

R

SL

3.32k

0.1µF
LOW
ESR

20µF

VERY

3.01k

1k2k

1k2k

0.1µF
LOW
ESR

0.5W

Q1A

330nF

330nF

0.1µF

33

5%

T1

1nF1nF

33

0.5W
5%

Q1B

R

SNS(FET)

0.05

0.5W

R

SNS(BAT)

0.1

0.25W

20µF
VERY
LOW ESR

+

+

+

+

I2C

TO

HOST

+

+

+

+

+

LOAD

TO BACKUP
LOAD

Q3

BATTERY
IDEAL
DIODE

10.8V (9 CELL)

10k
NTC

TYPE

GND SGND

NO TIMER
HIGH CURRENT BACKUP LOAD DESIGN

0.5A BACKDRIVE CURRENT CUTOFF (CALIBRATION)
1A CHARGE AND CALIBRATION CURRENT

0.2A WAKE-UP/PRECONDITIONING CURRENT
HOST PROVIDES SMBus PULL-UP RESISTORS
ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE

Q1: Si7216DN
Q2: Si7445DN
Q3: Si7983DP
T1: BH510-1019

SHDN

4110 TA05

4110fa

49

LTC4110

TYPICAL APPLICATIONS

TO SYSTEM

LOAD

TO BACKUP

LOAD

Q6

BATTERY

IDEAL

DIODE

T2T1

10k

NTC

BATTERY 2 (12.6V)

+++

20µF

VERY

LOW ESR

SNS(BAT)

R

0.1

0.25W

1nF1nF

33

0.5W

SNS(FET)

R

0.05

0.5W

5%

Q2B

SMB2

10.8V

3 CELL

INPUT

IDEAL DIODE

SHDN

TYPE

GND SGND

4110 TA06

SMB1

SMB2

SMBUS

LTC4305

MULTIPLEXOR

HOST

C/SMBus

2

I

5%

33

0.5W

20µF

LOW

LOW

Q5

VERY

ESR

LOW ESR

NC

BATID

DCOUT

INID

DCIN

CLN

CLP

ESR

BATTERY

IDEAL

DIODE

1nF1nF

33

0.5W

5%

0.1µF

Q4

0.1µF

Q2A

CHGFET

DCDIV

20µF

Q1B

SL

SL

R

R

DCHFET

1.13k

THA

R

VERY

LOW ESR

SNS(FET)

R

3.32k

3.32k

THA

0.05

I

0.5W

SENSE

54.9k

THB

R

330nF

330nF

THB

0.1µF

330nF

0.1µF

330nF

1k2k

1k2k

1k2k

1k2k

3.01k

3.01k

CSP

V

SNS(BAT)

R

BAT

CSN

LTC4110

REF

CHGVCALVDIS

V

113k

10k

NTC

BATTERY 1 (12.6V)

+++

0.1

0.25W
SMB1

TH

I

TIMER

ACPDLY

CHGICALIPCC

I

187k

36.5k

10.8V

3 CELL

68nF

DD

V

37.4k

0.1µF

LOW

ESR

ACPb

GP101

GP102

GP103

SDA

SELC

SCL

SMB2

SELA

0.1µF

50

5%

33

0.5W

20µF

0.1µF

1.21k

LOW

LOW

0.1µF

Batteries with Calibration Managed by Host Processor and SMBus Multiplexer

CL

R

INPUT

IDEAL DIODE

1W

0.02

INPUT

SUPPLY

(12V)

Q3

8.66k

Dual Battery Backup System Managers Controlling a Two Three-Series Cell Li-Ion, Gas Gauge Smart

VERY

ESR

ESR

LOW ESR

NC

BATID

DCOUT

INID

DCIN

CLN

CLP

Q1A

CHGFET

DCDIV

SL

R

DCHFET

1.13k

THA

R

330nF

1k2k

3.32k

CSP

SENSE

I

REF

THB

THA

V

54.9k

THB

R

113k

0.1µF

330nF

1k2k

3.01k

BAT

CSN

LTC4110

CHGVCALVDIS

V

TH

I

TIMER

ACPDLY

CHGICALIPCC

I

187k

36.5k

68nF

DD

V

37.4k

0.1µF

LOW

ESR

ACPb

GP101

GP102

SDA

SELA

SELC

0.1µF
SMB1

GP103

SCL

SHDN

TYPE

GND SGND

7HR CHARGE TIME

HIGH CURRENT BACKUP LOAD DESIGN

0.5A BACKDRIVE CURRENT CUTOFF

1A CHARGE AND CALIBRATION CURRENT

0.2A WAKE-UP/PRECONDITIONING CURRENT

ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE

SEE LTC4305 DATA SHEET FOR PULL-UP INFORMATION

Q1, Q2: Si7216DN

Q3, Q4: Si7445DP

Q5, Q6: Si7983DP

T1, T2: BH510-1019

4110fa

PACKAGE DESCRIPTION

LTC4110

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701)

0.70 p 0.05

5.50 p 0.05

4.10 p 0.05

3.00 REF

5.00 p 0.10

PIN 1
TOP MARK
(SEE NOTE 6)

5.15 ± 0.05

3.15 ± 0.05

0.25 p 0.05

0.50 BSC

5.5 REF

6.10 p 0.05

7.50 p 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 p 0.05

0.00 – 0.05

PACKAGE
OUTLINE

3.00 REF

PIN 1 NOTCH
R = 0.30 TYP OR

0.35 s 45o CHAMFER

37

38

0.40 p0.10

1

2

7.00 p 0.10

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

5.50 REF

0.200 REF

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

0.25 p 0.05

0.50 BSC

5.15 ± 0.10

3.15 ± 0.10

R = 0.125
TYP

BOTTOM VIEW—EXPOSED PAD

R = 0.10
TYP

(UH) QFN REF C 1107

4110fa

51

LTC4110

TYPICAL APPLICATION

Battery Backup System Manager Controlling a Three-Series Cell Li-Ion, Gas

Gauge Smart Battery with Calibration Managed by Host Processor

SUPPLY

INPUT

(12V)

8.66k

1.21k

15ms ACPDLY
7HR TIMER
LOW CURRENT BACKUP DESIGN

2.8V CUTOFF VOLTAGE FOR V
1A CHARGE CURRENT

0.2A CALIBRATION AND PRECONDITIONING CURRENT

0.3A BACKDRIVE CURRENT CUTOFF
HOST PROVIDES SMBus PULL-UP RESISTORS
ALL RESISTORS ARE 1% UNLESS NOTED OTHERWISE

Q1: Si7216DN
Q2: Si7445DP
Q3: SiA911DJ
T1: BH510-1019

AND V

CAL

DIS

25.5k

51.1k

R

CL

0.033

0.5W

R

THA

R

THB

30.1k

187k

37.4k

HOST

1.13k

54.9k

0.1µF

2

I

TO

TO SYSTEM

(12.6V)

10.8V

3 CELL

LOAD

TO BACKUP
LOAD

Q3

BATTERY
IDEAL
DIODE

10k
NTC

T1

0.1µF

4110 TA02

22µF
VERY
LOW ESR

0.1µF
LOW ESR

1nF1nF

33

0.5W
5%

Q1B

R

SNS(FET)

0.05

0.5W

HOST

R

SNS(BAT)

0.1

0.25W

I2C
TO

22µF
VERY
LOW ESR

+

+

+

DCOUT

BATID

CHGFET

DCHFET

I

SENSE

CSP

CSN

BAT

ACPDLY

TIMER

V

ACPb

GP101

GP102

GP103

SHDN

0.1µF
LOW ESR

R

3.32k

SL

3.01k

100nF

Q1A

33

0.5W
5%

330nF

1k2k

1k2k

330nF

0.1µF

0.1µF
LOW
ESR

NC

I

TH

DD

INPUT

IDEAL DIODE

Q2

DCIN

CLN

CLP

DCDIV

THA

THB

V

V

V

V

I

I

I

SELA

SELC

SDA

C

SCL

TYPE

INID

REF

CHG

CAL

LTC4110

DIS

CHG

CAL

PCC

GND SGND

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC4414 36V, Low Loss PowerPath Controller for Large PFETs Drives Large Q

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ThinSot is a Trademark of Linear Technology Corporation.

Linear Technology Corporation

52

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

SMBus Rev 1.1 Compliant

Current and Voltage, Input Current Limiting Maximizes Charge Current

Simplifi ed Load Sharing, 3V ≤ VIN ≤ 28V, (3V ≤ VIN ≤ 36V for HV) ThinSOT
Package

PFETs, Very Low Loss Replacement for Power Supply ORing

G

Diodes, 3.5V to 36V AC/DC Adapter Voltage Range, MSOP-8 Package

Operation to 36V, Programmable Autonomous Switching

LT 0708 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2008

4110fa