100% Compliant (Rev. 1.1) SMBus Support Allows
for Operation with or without Host
■
Up to 4A Charging Current Capability
■
High Efficiency Synchronous Buck Charger
■
V
Optimized 3V to 5.5V
BAT
■
SMBus Accelerator Improves SMBus Timing
■
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
■
0.5V Dropout Voltage; Maximum Duty Cycle > 98%
■
AC Adapter Current Limit Maximizes Charge Rate
■
±0.8% Voltage Accuracy; ±4% Current Accuracy
■
10-Bit DAC for Charge Current Programming
■
11-Bit DAC for Charger Voltage Programming
■
User-Selectable Overvoltage and Overcurrent Limits
■
High Noise Immunity SafetySignal Sensor
■
Available in a 24-Pin SSOP Package
U
APPLICATIOS
■
Portable Instruments and Computers
■
Data Storage Systems and Battery Backup Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including 6650174, 5723970.
LTC4101
Smart Battery
Charger Controller
U
DESCRIPTIO
The LTC®4101 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construction of an SBS compliant system. The LTC4101 implements a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for temperature, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
Charging current and voltage are restricted to chemistryspecific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Additionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging
current. When supplying system load current, charging
current is automatically reduced to prevent adapter
overload.
TYPICAL APPLICATIO
DCIN
9V to 12V, 2A
3V
TO 5.5V
CHGEN
ACP
1.13k
54.9k
SMBALERT#
SMBCLK
SMBDAT
U
1.21k
LTC4101
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
V
GND
0.1µF
SET
I
TH
5
4
24
23
1
3
2
21
22
18
19
12
6.04k
0.12µF
SafetySignal
10k
6.04k
17
11
6
10
7
9
8
15
16
13
14
20
0.068µF
V
DD
DCDIV
CHGEN
ACP
SMBALERT
SCL
SDA
THB
THA
I
LIM
V
LIM
I
DC
Figure 1. 1A Smart Battery Charger
0.1µF
5k
0.0015µF
0.05Ω
5µF
24µH
0.03µF
0.1µF
0.1Ω 1%
100Ω
V
BAT
< 5.5V
> 5.5V
5µF
PART
LTC4101
LTC4100
SMART BATTERY
SMBCLK
SMBDAT
SYSTEM LOAD
4101 F01a
4101f
1
LTC4101
WW
W
U
ABSOLUTE AXIU RATIGS
(Note 1)
Voltage from VDD to GND ................................ 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA, SCL
and SMBALERT to GND .............................. 7V/–0.3V
Voltage from DCIN, CLP, CLN to GND ........... 32V/–0.3V
Voltage from CLP to CLN...................................... ±0.3V
CSP, BAT to GND.............................................. 28V/–5V
Operating Ambient Temperature Range (Note 4)
........................................................... – 40°C to 85°C
Junction Temperature Range............... – 40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
UUW
PACKAGE/ORDER IFORATIO
TOP VIEW
1
TGATE
2
PGND
3
BGATE
4
INFET
5
DCIN
6
CHGEN
SMBALERT
7
8
SDA
9
SCL
10
ACP
11
DCDIV
12
GND
24-LEAD PLASTIC SSOP
T
= 125°C, θJA = 90°C/W
JMAX
G PACKAGE
ORDER PART NUMBER
LTC4101EG
CLP
24
CLN
23
BAT
22
CSP
21
I
20
DC
I
19
TH
V
18
SET
V
17
DD
THA
16
THB
15
V
14
LIM
I
13
LIM
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
I
DCIN
DCIN Operating Range
DCIN Operating CurrentCharging, Sum of Currents on35mA
●
628V
DCIN, CLP and CLN
V
I
V
TOL
TOL
DD
Charge Voltage Accuracy(Note 2)–1.11.1%
●
–1.31.3%
Charge Current Accuracy (Note 3)V
VDD Operating Voltage0V ≤ V
I
CSP
DAC
– V
Target = 102.3mV–26%
BAT
= 0xFFFF
≤ 28V
DCIN
●
–37%
●
35.5V
Shutdown
Battery Leakage CurrentDCIN = 0V, V
UVLOUndervoltage Lockout ThresholdDCIN Rising, V
VDD Power-FailPart Held in Reset Until this VDD Present
DCIN Current in ShutdownV
= 0V23mA
CHGEN
CLP
BAT
= V
= 0V
CLN
= V
CSP
= V
BAT
●
●
4.24.75.5V
●
1535µA
3V
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin11.66µA
CMSLCA1/I1 Input Common Mode Low
CMSHCA1/I1 Input Common Mode HighV
DCIN
≤ 28V
●
0V
●
V
-0.2V
CLN
4101f
2
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Current Comparators I
I
TREV
REV
Reverse Current Threshold (V
CSP-VBAT
)–30mV
Current Sense Amplifier, CA2
Transconductance1mmho
Source CurrentMeasured at ITH, V
Sink CurrentMeasured at ITH, V
= 1.4V–40µA
ITH
= 1.4V40µA
ITH
Current Limit Amplifier
Transconductance1.5mmho
V
I
CLP
CLN
Current Limit Threshold
●
93100107mV
CLN Input Bias Current50nA
Voltage Error Amplifier, EA
Transconductance1mmho
Sink CurrentMeasured at I
OVSDOvervoltage Shutdown Threshold as a Percent
= 1.4V36µA
TH, VITH
●
102107110%
of Programmed Charger Voltage
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (V
DCIN-VCLP
Forward Regulation Voltage (V
Reverse Voltage Turn-Off Voltage (V
INFET “ON” Clamping Voltage (V
INFET “OFF” Clamping Voltage (V
)DCIN Voltage Ramping Up
from V
CLP
DCIN-VCLP
)
DCIN-VCLP
DCIN-VINFET
DCIN-VINFET
)
)I
)I
= 1µA
INFET
= –25µA0.25V
INFET
-0.05V
●
00.170.25V
●
●
–60–25mV
●
55.86.5V
2550mV
Oscillator
f
f
DC
OSC
MIN
MAX
Regulator Switching Frequency255300345kHz
Regulator Switching Frequency in Drop OutDuty Cycle ≥ 98%2025kHz
Regulator Maximum Duty CycleV
CSP
= V
BAT
9899%
Gate Drivers (TGATE, BGATE)
V
High (V
TGATE
V
BGATE
V
TGATE
V
BGATE
CLP-VTGATE
HighC
Low (V
CLP-VTGATE
LowI
)I
)C
= –1mA50mV
TGATE
= 3000pF4.55.610V
LOAD
= 3000pF4.55.610V
LOAD
= 1mA50mV
BGATE
TGATE Transition Time
TGTRTGATE Rise TimeC
TGTFTGATE Fall TimeC
= 3000pF, 10% to 90%50110ns
LOAD
= 3000pF, 10% to 90%50100ns
LOAD
BGATE Transition Time
BGTRBGATE Rise TimeC
BGTFBGATE Fall TimeC
V
at Shutdown (V
TGATE
V
at ShutdownI
BGATE
CLN-VTGATE
)I
= 3000pF, 10% to 90%4090ns
LOAD
= 3000pF, 10% to 90%4080ns
LOAD
= –1µA100mV
TGATE
= 1µA100mV
TGATE
4101f
3
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
AC Present Comparator
V
ACP
DCDIV ThresholdV
Rising from 1V to 1.4V
DCDIV
●
1.141.201.26V
DCDIV Hysteresis25mV
DCDIV Input Bias CurrentV
ACP V
OH
ACP V
OL
DCDIV to ACP DelayV
= 1.2V–11µA
DCDIV
I
= –2mA2V
ACP
I
= 1mA0.5V
ACP
= 1.3V10µs
DCDIV
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR)R
SafetySignal Trip (RES_IDEAL/RES_COLD) R
SafetySignal Trip (RES_HOT/RES_IDEAL)R
SafetySignal Trip (RES_UR/RES_HOT)R
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
R
= 54.9Ω ±1%
THB
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
●
95100105kΩ
●
28.53031.5kΩ
●
2.8533.15kΩ
●
425500575Ω
Time Between SafetySignal MeasurementsDCDIV = 1.3V32ms
DCDIV = 1V250ms
DACs
Charging Current ResolutionGuaranteed Monotonic Above I
Charging Current GranularityR
Wake-Up Charging Current (I
)All Values of R
WAKE-UP
Charging Current LimitR
= 01mA
ILIM
= 10k ±1%2mA
R
ILIM
= 33k ±1%4mA
R
ILIM
R
= Open (or Short to VDD)4mA
ILIM
All Values of R
ILIM =
ILIM
VLIM
0 (0-1A)97.3107.3mV
/1610Bits
MAX
80 (Note 5)mA
CSP – BATCharging Current = 0x03FF (0x0400 Note 7)
R
10k ±1% (0-2A)97.3107.3mV
ILIM =
Charging Current = 0x07FE (0x0800 Note 7)
R
33k ±1% (0-3A)72.382.3mV
ILIM =
Charging Current = 0x0BFC (0x0C00 Note 7)
R
0pen (or Short to VDD) (0-4A)
ILIM =
●
97.3107.3mV
Charging Current = 0x0FFC (0x1000 Note 7)
Charging Voltage ResolutionGuaranteed Monotonic (2.9V ≤ V
5.6V)11Bits
BAT ≤
Charging Voltage Granularity16mV
Charging Voltage LimitR
= 04.2064.2404.274V
VLIM
Charging Voltage = 0x1090 (Note 7)
R
= 10k ±1%4.2704.3044.338V
VLIM
Charging Voltage = 0x10D0 (Note 7)
R
= 33k ±1%4.3974.4324.467V
VLIM
Charging Voltage = 0x1150 (Note 7)
R
= 100k ±1%4.4764.5124.548V
VLIM
Charging Voltage = 0x11A0 (Note 7)
R
= 0pen (or Short to VDD)5.4605.5045.548V
VLIM
Charging Voltage = 0x1580 (Note 7)
4101f
4
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Logic Levels
V
V
V
I
IL
I
IH
V
I
LEAK
V
V
V
IL
IH
OL
OL
OL
IL
IH
SCL/SDA Input Low VoltageVDD = 3V and VDD = 5.5V
SCL/SDA Input High VoltageVDD = 3V and VDD = 5.5V
SDA Output Low VoltageI
SCL/SDA Input CurrentV
SCL/SDA Input CurrentV
SMBALERT Output Low VoltageI
SMBALERT Output Pull-Up CurrentV
SDA/SCL/SMBALERT Power Down Leakage V
PULL-UP
, V
SDA
, V
SDA
PULL-UP
SMBALERT
, V
SDA
= 350µA
= V
SCL
= V
SCL
= 500µA
= V
, V
SCL
IL
IH
OL
SMBALERT
= 5.5V, VDD = OV
CHGEN Output Low VoltageIOL = 100µA
CHGEN Output Pull-Up CurrentV
CHGEN
= V
OL
CHGEN Input Low Voltage
CHGEN Input High VoltageVDD = 3V
= 5.5V3.9V
V
DD
●
●
2.1V
●
0.8V
0.4V
–11µA
–11µA
●
0.4V
–17.5–10–3.5µA
●
–22µA
●
0.5V
–17.5–10–3.5µA
●
●
2.5V
0.9V
Power-On Reset DurationVDD Ramp from 0V to >3V in <5µs100µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
t
HIGH
t
LOW
t
R
t
F
t
SU:STA
t
HD:STA
t
HD:DAT
SCL Serial Clock High PeriodI
SCL Serial Clock Low PeriodI
SDA/SCL Rise TimeC
SDA/SCL Fall TimeC
= 350µA, C
PULL-UP
V
= 3V and VDD = 5.5V
DD
= 350µA, C
PULL-UP
V
= 3V and VDD = 5.5V
DD
= 250pF, RPU = 9.31k, VDD = 3V
LOAD
= 5.5V
and V
DD
= 250pF, RPU = 9.31k, VDD = 3V
LOAD
= 5.5V
and V
DD
LOAD
LOAD
Start Condition Setup TimeVDD = 3V and VDD = 5.5V
Start Condition Hold TimeVDD = 3V and VDD = 5.5V
SDA to SCL Falling-Edge Hold Time,VDD = 3V and VDD = 5.5V
= 250pF, RPU = 9.31k,
= 250pF, RPU = 9.31k,
●
4µs
●
4.715000µs
●
●
●
4.7µs
●
4µs
●
300ns
1000ns
300ns
Slave Clocking in Data
t
TIMEOUT
Time Between Receiving ValidVDD = 3V and VDD = 5.5V
●
140175210sec
ChargingCurrent() and
ChargingVoltage() Commands
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4101E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: C
is defined as the sum of capacitance on THA, THB and
TH
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
4101f
5
LTC4101
UW
TYPICAL PERFOR A CE CHARACTERISTICS
INFET Response Time to
Reverse CurrentOutput Voltage vs Output CurrentPWM Frequency vs Duty Cycle
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
OUTPUT VOLTAGE ERROR (%)
V
= 20V
DCIN
= 4.176V
V
PROG
–4.5
–5.0
= 4V
I
PROG
0 0.5 1.02.03.04.01.52.53.54.5
OUTPUT CURRENT (A)
= 0
V
gs
V
= 0V
s
Id (REVERSE) OF
PFET (5A/DIV)
I
= 0A
d
TEST PERFORMED ON DEMOBOARD
= 15V
V
IN
DC
CHARGER = ON
= <10mA
I
CHARGE
Vgs OF PFET (2V/DIV)
Vs OF PFET (5V/DIV)
1.25µs/DIV
V
= 4.2V
CHARGE
INFET = 1/2 Si4925DY
4101 G01
TA = 25°C unless otherwise noted.
350
300
250
200
150
PROGRAMMED CURRENT = 10%
DCIN = 9V
DCIN = 12V
0
0 0.1 0.20.40.60.90.80.30.50.71.0
DCIN = 24V
DUTY CYCLE (V
4101 G02
100
PWM FREQUENCY (kHz)
50
OUT/VIN
)
4101 G03
Disconnect/Reconnect Battery
(Load Dump)
3A STEP
DISCONNECT
= 4.2V
FLOAT
1A STEP
V
FLOAT
1V/(DIV)
LOAD
STATE
LOAD CURRENT = 1A, 2A, 3A
DCIN = 12V
V
SMBus Accelerator Operation
VDD = 5V
C
BUS
5V
LTC4101
0V
1A STEP
3A STEP
RECONNECT
= 200pF
R
PULLUP
1µs/DIV
4101 G04
= 15k
Battery Leakage Current vs
Battery Voltage
40
VDCIN = 0V
35
30
25
20
15
10
BATTERY LEAKAGE CURRENT (µA)
5
0
051015202530
4101 G09
BATTERY VOLTAGE (V)
Efficiency at V
100
96
92
88
84
80
POWER EFFICIENCY (%)
76
72
4101 G05
Low Current Operation
0.6
VDD = 5V
= 4V
V
BAT
0.5
0.4
(A)
0.3
CHARGE
I
0.2
0.1
= 20V
V
DCIN
= 4.208V
V
PROG
NO LOW
CURRENT
MODE
0
0.10
0.05
0
= 4.208V
PROG
VIN = 8V
VIN = 20V
0.50.01.51.02.02.53.53.0
I
PROGRAMMED
CURRENT
LOW
CURRENT
MODE
(A)
PROG
I
OUT
(A)
0.400.15 0.20 0.25 0.30 0.35
4101 G10
4101 G07
4101f
6
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC4101
TA = 25°C unless otherwise noted.
Charging Current Error
200
VDD = 5V
100
0
–100
OUTPUT CURRENT ERROR (mA)
–200
0
U
1
CHARGING CURRENT (A)
UU
V
= 20V
DCIN
V
= 9V
DCIN
2
43
4101 G11
PI FU CTIO S
TGATE (Pin 1): Drives the Top External P-MOSFET of the
Battery Charger Buck Converter.
PGND (Pin 2): High Current Ground Return for BGATE
Driver.
BGATE (Pin 3): Drives the Bottom External N-MOSFET of
the Battery Charger Buck Converter.
INFET (Pin 4): Drives the Gate of the External Input
P-MOSFET.
DCIN (Pin 5): External DC Power Source Input. Bypass to
ground with a 0.1µF capacitor.
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger
Function. This pin is connected as a wired AND bus.
The following events will cause the POWER_FAIL bit in
the ChargerStatus register to become set:
1. An external device pulling the CHGEN signal to within
0.9V to GND;
2. The AC adapter voltage is not above the battery
voltage.
Transfer Function of Charger
50
VDD = 5V
= 0.120A
I
BAT
V
= 9V
0
–50
–100
OUTPUT VOLTAGE ERROR (V)
–150
0
CHARGING VOLTAGE (V)
V
DCIN
V
DCIN
= 20V
= 28V
DCIN
453126
4101 G12
any action on its part is required. This signal can be
connected to the optional SMBALERT line of the SMBus.
Open drain with weak current source pull-up to V
DD
(with
Schottky to allow it to be pulled to 5V externally).
SDA (Pin 8): SMBus Data Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
SCL (Pin 9): SMBus Clock Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
ACP (Pin 10): This Output Indicates the Value of the DCDIV
Comparator. It can be used to indicate whether AC is
present or not.
DCDIV (Pin 11): Supply Divider Input. This is a high
impedance comparator input with a 1.2V threshold (rising
edge) and hysteresis.
GND (Pin 12): Ground for Digital and Analog Circuitry.
I
(Pin 13): An external resistor is connected between
LIM
this pin and GND. The value of the external resistor
programs the range and resolution of the programmed
charger current.
SMBALERT (Pin 7): Active Low Interrupt Output to Host
(referred to as the SMBALERT signal in the SMBus Revision 1.1 specification). Signals host that there has been a
change of status in the charger registers and that the host
should read the LTC4101 status registers to determine if
V
(Pin 14): An external resistor is connected between
LIM
this pin and GND. The value of the external resistor
programs the range and resolution of the charging
voltage.
4101f
7
LTC4101
U
UU
PI FU CTIO S
THB (Pin 15): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
54.9k needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
V
(Pin 17): Power Supply Input for the LTC4101 Digital
DD
Circuitry. Bypass this pin with 0.1µF. Typically between
3.3V and 5V
V
(Pin 18): Tap Point of the Programmable Resistor
SET
Divider, which Provides Battery Voltage Feedback to the
Charger.
DC
.
ITH (Pin 19): Control Signal of the Inner Loop of the
Current Mode PWM. Higher I
charging current in normal operation. A 0.0015µF capacitor to GND filters out PWM ripple. Typical full-scale output
current is 40µA. Nominal voltage range for this pin is 0V
to 3V.
I
(Pin 20): Bypass to GND with a 0.068µF Capacitor.
DC
CSP (Pin 21): Current Amplifier CA1 Input. This pin and
the BAT pin measure the voltage across the sense resistor,
R
quired for both peak and average current mode operation.
BAT (Pin 22): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A bypass capacitor of at least 10µF is required.
CLN (Pin 23): Negative Input to the Input Current Limiting
Circuit Block. If no current limit function is desired, connect this pin to CLP. The threshold is set at 100mV below
the voltage at the CLP pin. When used to limit supply
current, a filter is needed to filter out the switching noise.
, to provide the instantaneous current signals re-
SENSE
corresponds to higher
TH
CLP (Pin 24): Positive Input to the Input Current Limiting
Circuit Block. This pin also serves as a power supply for
the IC.
8
4101f
BLOCK DIAGRA
LTC4101
W
V
BAT
SYSTEM
LOAD
L1
CSP
D1
R1
R
CL
Q1
V
IN
TO HOST AND BATTERY
1.13k
54.9k
R4
100Ω
C5, 0.1µF
C9
C1, 0.1µF
10k
0.03µF
Q2
Q3
C4
V
GND
20µF
TGATE
BGATE
PGND
CLN
CLP
DCIN
INFET
CHGEN
SMBALERT
SDA
SCL
THA
THB
SET
V
20µF
R
ILIM
BAT
C7
0.0015µF
V
IN
–
+
+
–
–
+
10-BIT
I
DAC
3k
11.67µA
3k
9k
17mV
1.19V
1.2V
CA1
BUFFERED
÷ 5
I
CMP
I
REV
gm = 1m
–
+
–
+
I
TH
CA2
Ω
LIMIT
DECODER
18
11-BIT
V
10µA
t
PWM
LOGIC
DAC
1.28V
ON
1.19V
100mV
V
DD
SMBus
INTERFACE
AND CONTROL
THERMISTER
INTERFACE
–
EA
+
Q
+
CL1
–
0V
gm = 1m
S
R
gm = 1.5m
Ω
Ω
CLP
12
1
3
2
23
24
5
4
6
7
8
9
16
15
CLP
DCIN
OSCILLATOR
WATCHDOG
DETECT
5.8V
22
R
21
20
19
10
11
17
13
14
BAT
SENSE
CSP
CSP
I
DC
I
TH
C6, 0.12µF
ACP
DCDIV
R11
V
TO SMBUS
DD
POWER SUPPLY
I
LIM
V
LIM
R
VLIM
C8
0.068µF
R5, 6.04k
R10
Figure 2.
4101f
9
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