100% Compliant (Rev. 1.1) SMBus Support Allows
for Operation with or without Host
■
Up to 4A Charging Current Capability
■
High Efficiency Synchronous Buck Charger
■
V
Optimized 3V to 5.5V
BAT
■
SMBus Accelerator Improves SMBus Timing
■
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
■
0.5V Dropout Voltage; Maximum Duty Cycle > 98%
■
AC Adapter Current Limit Maximizes Charge Rate
■
±0.8% Voltage Accuracy; ±4% Current Accuracy
■
10-Bit DAC for Charge Current Programming
■
11-Bit DAC for Charger Voltage Programming
■
User-Selectable Overvoltage and Overcurrent Limits
■
High Noise Immunity SafetySignal Sensor
■
Available in a 24-Pin SSOP Package
U
APPLICATIOS
■
Portable Instruments and Computers
■
Data Storage Systems and Battery Backup Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including 6650174, 5723970.
LTC4101
Smart Battery
Charger Controller
U
DESCRIPTIO
The LTC®4101 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construction of an SBS compliant system. The LTC4101 implements a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for temperature, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
Charging current and voltage are restricted to chemistryspecific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Additionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging
current. When supplying system load current, charging
current is automatically reduced to prevent adapter
overload.
TYPICAL APPLICATIO
DCIN
9V to 12V, 2A
3V
TO 5.5V
CHGEN
ACP
1.13k
54.9k
SMBALERT#
SMBCLK
SMBDAT
U
1.21k
LTC4101
DCIN
INFET
CLP
CLN
TGATE
BGATE
PGND
CSP
BAT
V
GND
0.1µF
SET
I
TH
5
4
24
23
1
3
2
21
22
18
19
12
6.04k
0.12µF
SafetySignal
10k
6.04k
17
11
6
10
7
9
8
15
16
13
14
20
0.068µF
V
DD
DCDIV
CHGEN
ACP
SMBALERT
SCL
SDA
THB
THA
I
LIM
V
LIM
I
DC
Figure 1. 1A Smart Battery Charger
0.1µF
5k
0.0015µF
0.05Ω
5µF
24µH
0.03µF
0.1µF
0.1Ω 1%
100Ω
V
BAT
< 5.5V
> 5.5V
5µF
PART
LTC4101
LTC4100
SMART BATTERY
SMBCLK
SMBDAT
SYSTEM LOAD
4101 F01a
4101f
1
LTC4101
WW
W
U
ABSOLUTE AXIU RATIGS
(Note 1)
Voltage from VDD to GND ................................ 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA, SCL
and SMBALERT to GND .............................. 7V/–0.3V
Voltage from DCIN, CLP, CLN to GND ........... 32V/–0.3V
Voltage from CLP to CLN...................................... ±0.3V
CSP, BAT to GND.............................................. 28V/–5V
Operating Ambient Temperature Range (Note 4)
........................................................... – 40°C to 85°C
Junction Temperature Range............... – 40°C to 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
UUW
PACKAGE/ORDER IFORATIO
TOP VIEW
1
TGATE
2
PGND
3
BGATE
4
INFET
5
DCIN
6
CHGEN
SMBALERT
7
8
SDA
9
SCL
10
ACP
11
DCDIV
12
GND
24-LEAD PLASTIC SSOP
T
= 125°C, θJA = 90°C/W
JMAX
G PACKAGE
ORDER PART NUMBER
LTC4101EG
CLP
24
CLN
23
BAT
22
CSP
21
I
20
DC
I
19
TH
V
18
SET
V
17
DD
THA
16
THB
15
V
14
LIM
I
13
LIM
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
I
DCIN
DCIN Operating Range
DCIN Operating CurrentCharging, Sum of Currents on35mA
●
628V
DCIN, CLP and CLN
V
I
V
TOL
TOL
DD
Charge Voltage Accuracy(Note 2)–1.11.1%
●
–1.31.3%
Charge Current Accuracy (Note 3)V
VDD Operating Voltage0V ≤ V
I
CSP
DAC
– V
Target = 102.3mV–26%
BAT
= 0xFFFF
≤ 28V
DCIN
●
–37%
●
35.5V
Shutdown
Battery Leakage CurrentDCIN = 0V, V
UVLOUndervoltage Lockout ThresholdDCIN Rising, V
VDD Power-FailPart Held in Reset Until this VDD Present
DCIN Current in ShutdownV
= 0V23mA
CHGEN
CLP
BAT
= V
= 0V
CLN
= V
CSP
= V
BAT
●
●
4.24.75.5V
●
1535µA
3V
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin11.66µA
CMSLCA1/I1 Input Common Mode Low
CMSHCA1/I1 Input Common Mode HighV
DCIN
≤ 28V
●
0V
●
V
-0.2V
CLN
4101f
2
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Current Comparators I
I
TREV
REV
Reverse Current Threshold (V
CSP-VBAT
)–30mV
Current Sense Amplifier, CA2
Transconductance1mmho
Source CurrentMeasured at ITH, V
Sink CurrentMeasured at ITH, V
= 1.4V–40µA
ITH
= 1.4V40µA
ITH
Current Limit Amplifier
Transconductance1.5mmho
V
I
CLP
CLN
Current Limit Threshold
●
93100107mV
CLN Input Bias Current50nA
Voltage Error Amplifier, EA
Transconductance1mmho
Sink CurrentMeasured at I
OVSDOvervoltage Shutdown Threshold as a Percent
= 1.4V36µA
TH, VITH
●
102107110%
of Programmed Charger Voltage
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (V
DCIN-VCLP
Forward Regulation Voltage (V
Reverse Voltage Turn-Off Voltage (V
INFET “ON” Clamping Voltage (V
INFET “OFF” Clamping Voltage (V
)DCIN Voltage Ramping Up
from V
CLP
DCIN-VCLP
)
DCIN-VCLP
DCIN-VINFET
DCIN-VINFET
)
)I
)I
= 1µA
INFET
= –25µA0.25V
INFET
-0.05V
●
00.170.25V
●
●
–60–25mV
●
55.86.5V
2550mV
Oscillator
f
f
DC
OSC
MIN
MAX
Regulator Switching Frequency255300345kHz
Regulator Switching Frequency in Drop OutDuty Cycle ≥ 98%2025kHz
Regulator Maximum Duty CycleV
CSP
= V
BAT
9899%
Gate Drivers (TGATE, BGATE)
V
High (V
TGATE
V
BGATE
V
TGATE
V
BGATE
CLP-VTGATE
HighC
Low (V
CLP-VTGATE
LowI
)I
)C
= –1mA50mV
TGATE
= 3000pF4.55.610V
LOAD
= 3000pF4.55.610V
LOAD
= 1mA50mV
BGATE
TGATE Transition Time
TGTRTGATE Rise TimeC
TGTFTGATE Fall TimeC
= 3000pF, 10% to 90%50110ns
LOAD
= 3000pF, 10% to 90%50100ns
LOAD
BGATE Transition Time
BGTRBGATE Rise TimeC
BGTFBGATE Fall TimeC
V
at Shutdown (V
TGATE
V
at ShutdownI
BGATE
CLN-VTGATE
)I
= 3000pF, 10% to 90%4090ns
LOAD
= 3000pF, 10% to 90%4080ns
LOAD
= –1µA100mV
TGATE
= 1µA100mV
TGATE
4101f
3
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
AC Present Comparator
V
ACP
DCDIV ThresholdV
Rising from 1V to 1.4V
DCDIV
●
1.141.201.26V
DCDIV Hysteresis25mV
DCDIV Input Bias CurrentV
ACP V
OH
ACP V
OL
DCDIV to ACP DelayV
= 1.2V–11µA
DCDIV
I
= –2mA2V
ACP
I
= 1mA0.5V
ACP
= 1.3V10µs
DCDIV
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR)R
SafetySignal Trip (RES_IDEAL/RES_COLD) R
SafetySignal Trip (RES_HOT/RES_IDEAL)R
SafetySignal Trip (RES_UR/RES_HOT)R
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
= 54.9Ω ±1%
R
THB
= 1130Ω±1%, C
THA
R
= 54.9Ω ±1%
THB
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
= 1nF (Note 6)
TH
●
95100105kΩ
●
28.53031.5kΩ
●
2.8533.15kΩ
●
425500575Ω
Time Between SafetySignal MeasurementsDCDIV = 1.3V32ms
DCDIV = 1V250ms
DACs
Charging Current ResolutionGuaranteed Monotonic Above I
Charging Current GranularityR
Wake-Up Charging Current (I
)All Values of R
WAKE-UP
Charging Current LimitR
= 01mA
ILIM
= 10k ±1%2mA
R
ILIM
= 33k ±1%4mA
R
ILIM
R
= Open (or Short to VDD)4mA
ILIM
All Values of R
ILIM =
ILIM
VLIM
0 (0-1A)97.3107.3mV
/1610Bits
MAX
80 (Note 5)mA
CSP – BATCharging Current = 0x03FF (0x0400 Note 7)
R
10k ±1% (0-2A)97.3107.3mV
ILIM =
Charging Current = 0x07FE (0x0800 Note 7)
R
33k ±1% (0-3A)72.382.3mV
ILIM =
Charging Current = 0x0BFC (0x0C00 Note 7)
R
0pen (or Short to VDD) (0-4A)
ILIM =
●
97.3107.3mV
Charging Current = 0x0FFC (0x1000 Note 7)
Charging Voltage ResolutionGuaranteed Monotonic (2.9V ≤ V
5.6V)11Bits
BAT ≤
Charging Voltage Granularity16mV
Charging Voltage LimitR
= 04.2064.2404.274V
VLIM
Charging Voltage = 0x1090 (Note 7)
R
= 10k ±1%4.2704.3044.338V
VLIM
Charging Voltage = 0x10D0 (Note 7)
R
= 33k ±1%4.3974.4324.467V
VLIM
Charging Voltage = 0x1150 (Note 7)
R
= 100k ±1%4.4764.5124.548V
VLIM
Charging Voltage = 0x11A0 (Note 7)
R
= 0pen (or Short to VDD)5.4605.5045.548V
VLIM
Charging Voltage = 0x1580 (Note 7)
4101f
4
LTC4101
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. V
A
= 20V, VDD = 3.3V, V
DCIN
= 4V unless otherwise noted. (Note 4)
BAT
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Logic Levels
V
V
V
I
IL
I
IH
V
I
LEAK
V
V
V
IL
IH
OL
OL
OL
IL
IH
SCL/SDA Input Low VoltageVDD = 3V and VDD = 5.5V
SCL/SDA Input High VoltageVDD = 3V and VDD = 5.5V
SDA Output Low VoltageI
SCL/SDA Input CurrentV
SCL/SDA Input CurrentV
SMBALERT Output Low VoltageI
SMBALERT Output Pull-Up CurrentV
SDA/SCL/SMBALERT Power Down Leakage V
PULL-UP
, V
SDA
, V
SDA
PULL-UP
SMBALERT
, V
SDA
= 350µA
= V
SCL
= V
SCL
= 500µA
= V
, V
SCL
IL
IH
OL
SMBALERT
= 5.5V, VDD = OV
CHGEN Output Low VoltageIOL = 100µA
CHGEN Output Pull-Up CurrentV
CHGEN
= V
OL
CHGEN Input Low Voltage
CHGEN Input High VoltageVDD = 3V
= 5.5V3.9V
V
DD
●
●
2.1V
●
0.8V
0.4V
–11µA
–11µA
●
0.4V
–17.5–10–3.5µA
●
–22µA
●
0.5V
–17.5–10–3.5µA
●
●
2.5V
0.9V
Power-On Reset DurationVDD Ramp from 0V to >3V in <5µs100µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
t
HIGH
t
LOW
t
R
t
F
t
SU:STA
t
HD:STA
t
HD:DAT
SCL Serial Clock High PeriodI
SCL Serial Clock Low PeriodI
SDA/SCL Rise TimeC
SDA/SCL Fall TimeC
= 350µA, C
PULL-UP
V
= 3V and VDD = 5.5V
DD
= 350µA, C
PULL-UP
V
= 3V and VDD = 5.5V
DD
= 250pF, RPU = 9.31k, VDD = 3V
LOAD
= 5.5V
and V
DD
= 250pF, RPU = 9.31k, VDD = 3V
LOAD
= 5.5V
and V
DD
LOAD
LOAD
Start Condition Setup TimeVDD = 3V and VDD = 5.5V
Start Condition Hold TimeVDD = 3V and VDD = 5.5V
SDA to SCL Falling-Edge Hold Time,VDD = 3V and VDD = 5.5V
= 250pF, RPU = 9.31k,
= 250pF, RPU = 9.31k,
●
4µs
●
4.715000µs
●
●
●
4.7µs
●
4µs
●
300ns
1000ns
300ns
Slave Clocking in Data
t
TIMEOUT
Time Between Receiving ValidVDD = 3V and VDD = 5.5V
●
140175210sec
ChargingCurrent() and
ChargingVoltage() Commands
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4101E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: C
is defined as the sum of capacitance on THA, THB and
TH
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
4101f
5
LTC4101
UW
TYPICAL PERFOR A CE CHARACTERISTICS
INFET Response Time to
Reverse CurrentOutput Voltage vs Output CurrentPWM Frequency vs Duty Cycle
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
OUTPUT VOLTAGE ERROR (%)
V
= 20V
DCIN
= 4.176V
V
PROG
–4.5
–5.0
= 4V
I
PROG
0 0.5 1.02.03.04.01.52.53.54.5
OUTPUT CURRENT (A)
= 0
V
gs
V
= 0V
s
Id (REVERSE) OF
PFET (5A/DIV)
I
= 0A
d
TEST PERFORMED ON DEMOBOARD
= 15V
V
IN
DC
CHARGER = ON
= <10mA
I
CHARGE
Vgs OF PFET (2V/DIV)
Vs OF PFET (5V/DIV)
1.25µs/DIV
V
= 4.2V
CHARGE
INFET = 1/2 Si4925DY
4101 G01
TA = 25°C unless otherwise noted.
350
300
250
200
150
PROGRAMMED CURRENT = 10%
DCIN = 9V
DCIN = 12V
0
0 0.1 0.20.40.60.90.80.30.50.71.0
DCIN = 24V
DUTY CYCLE (V
4101 G02
100
PWM FREQUENCY (kHz)
50
OUT/VIN
)
4101 G03
Disconnect/Reconnect Battery
(Load Dump)
3A STEP
DISCONNECT
= 4.2V
FLOAT
1A STEP
V
FLOAT
1V/(DIV)
LOAD
STATE
LOAD CURRENT = 1A, 2A, 3A
DCIN = 12V
V
SMBus Accelerator Operation
VDD = 5V
C
BUS
5V
LTC4101
0V
1A STEP
3A STEP
RECONNECT
= 200pF
R
PULLUP
1µs/DIV
4101 G04
= 15k
Battery Leakage Current vs
Battery Voltage
40
VDCIN = 0V
35
30
25
20
15
10
BATTERY LEAKAGE CURRENT (µA)
5
0
051015202530
4101 G09
BATTERY VOLTAGE (V)
Efficiency at V
100
96
92
88
84
80
POWER EFFICIENCY (%)
76
72
4101 G05
Low Current Operation
0.6
VDD = 5V
= 4V
V
BAT
0.5
0.4
(A)
0.3
CHARGE
I
0.2
0.1
= 20V
V
DCIN
= 4.208V
V
PROG
NO LOW
CURRENT
MODE
0
0.10
0.05
0
= 4.208V
PROG
VIN = 8V
VIN = 20V
0.50.01.51.02.02.53.53.0
I
PROGRAMMED
CURRENT
LOW
CURRENT
MODE
(A)
PROG
I
OUT
(A)
0.400.15 0.20 0.25 0.30 0.35
4101 G10
4101 G07
4101f
6
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC4101
TA = 25°C unless otherwise noted.
Charging Current Error
200
VDD = 5V
100
0
–100
OUTPUT CURRENT ERROR (mA)
–200
0
U
1
CHARGING CURRENT (A)
UU
V
= 20V
DCIN
V
= 9V
DCIN
2
43
4101 G11
PI FU CTIO S
TGATE (Pin 1): Drives the Top External P-MOSFET of the
Battery Charger Buck Converter.
PGND (Pin 2): High Current Ground Return for BGATE
Driver.
BGATE (Pin 3): Drives the Bottom External N-MOSFET of
the Battery Charger Buck Converter.
INFET (Pin 4): Drives the Gate of the External Input
P-MOSFET.
DCIN (Pin 5): External DC Power Source Input. Bypass to
ground with a 0.1µF capacitor.
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger
Function. This pin is connected as a wired AND bus.
The following events will cause the POWER_FAIL bit in
the ChargerStatus register to become set:
1. An external device pulling the CHGEN signal to within
0.9V to GND;
2. The AC adapter voltage is not above the battery
voltage.
Transfer Function of Charger
50
VDD = 5V
= 0.120A
I
BAT
V
= 9V
0
–50
–100
OUTPUT VOLTAGE ERROR (V)
–150
0
CHARGING VOLTAGE (V)
V
DCIN
V
DCIN
= 20V
= 28V
DCIN
453126
4101 G12
any action on its part is required. This signal can be
connected to the optional SMBALERT line of the SMBus.
Open drain with weak current source pull-up to V
DD
(with
Schottky to allow it to be pulled to 5V externally).
SDA (Pin 8): SMBus Data Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
SCL (Pin 9): SMBus Clock Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
ACP (Pin 10): This Output Indicates the Value of the DCDIV
Comparator. It can be used to indicate whether AC is
present or not.
DCDIV (Pin 11): Supply Divider Input. This is a high
impedance comparator input with a 1.2V threshold (rising
edge) and hysteresis.
GND (Pin 12): Ground for Digital and Analog Circuitry.
I
(Pin 13): An external resistor is connected between
LIM
this pin and GND. The value of the external resistor
programs the range and resolution of the programmed
charger current.
SMBALERT (Pin 7): Active Low Interrupt Output to Host
(referred to as the SMBALERT signal in the SMBus Revision 1.1 specification). Signals host that there has been a
change of status in the charger registers and that the host
should read the LTC4101 status registers to determine if
V
(Pin 14): An external resistor is connected between
LIM
this pin and GND. The value of the external resistor
programs the range and resolution of the charging
voltage.
4101f
7
LTC4101
U
UU
PI FU CTIO S
THB (Pin 15): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
54.9k needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
V
(Pin 17): Power Supply Input for the LTC4101 Digital
DD
Circuitry. Bypass this pin with 0.1µF. Typically between
3.3V and 5V
V
(Pin 18): Tap Point of the Programmable Resistor
SET
Divider, which Provides Battery Voltage Feedback to the
Charger.
DC
.
ITH (Pin 19): Control Signal of the Inner Loop of the
Current Mode PWM. Higher I
charging current in normal operation. A 0.0015µF capacitor to GND filters out PWM ripple. Typical full-scale output
current is 40µA. Nominal voltage range for this pin is 0V
to 3V.
I
(Pin 20): Bypass to GND with a 0.068µF Capacitor.
DC
CSP (Pin 21): Current Amplifier CA1 Input. This pin and
the BAT pin measure the voltage across the sense resistor,
R
quired for both peak and average current mode operation.
BAT (Pin 22): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A bypass capacitor of at least 10µF is required.
CLN (Pin 23): Negative Input to the Input Current Limiting
Circuit Block. If no current limit function is desired, connect this pin to CLP. The threshold is set at 100mV below
the voltage at the CLP pin. When used to limit supply
current, a filter is needed to filter out the switching noise.
, to provide the instantaneous current signals re-
SENSE
corresponds to higher
TH
CLP (Pin 24): Positive Input to the Input Current Limiting
Circuit Block. This pin also serves as a power supply for
the IC.
8
4101f
BLOCK DIAGRA
LTC4101
W
V
BAT
SYSTEM
LOAD
L1
CSP
D1
R1
R
CL
Q1
V
IN
TO HOST AND BATTERY
1.13k
54.9k
R4
100Ω
C5, 0.1µF
C9
C1, 0.1µF
10k
0.03µF
Q2
Q3
C4
V
GND
20µF
TGATE
BGATE
PGND
CLN
CLP
DCIN
INFET
CHGEN
SMBALERT
SDA
SCL
THA
THB
SET
V
20µF
R
ILIM
BAT
C7
0.0015µF
V
IN
–
+
+
–
–
+
10-BIT
I
DAC
3k
11.67µA
3k
9k
17mV
1.19V
1.2V
CA1
BUFFERED
÷ 5
I
CMP
I
REV
gm = 1m
–
+
–
+
I
TH
CA2
Ω
LIMIT
DECODER
18
11-BIT
V
10µA
t
PWM
LOGIC
DAC
1.28V
ON
1.19V
100mV
V
DD
SMBus
INTERFACE
AND CONTROL
THERMISTER
INTERFACE
–
EA
+
Q
+
CL1
–
0V
gm = 1m
S
R
gm = 1.5m
Ω
Ω
CLP
12
1
3
2
23
24
5
4
6
7
8
9
16
15
CLP
DCIN
OSCILLATOR
WATCHDOG
DETECT
5.8V
22
R
21
20
19
10
11
17
13
14
BAT
SENSE
CSP
CSP
I
DC
I
TH
C6, 0.12µF
ACP
DCDIV
R11
V
TO SMBUS
DD
POWER SUPPLY
I
LIM
V
LIM
R
VLIM
C8
0.068µF
R5, 6.04k
R10
Figure 2.
4101f
9
LTC4101
TEST CIRCUIT
+
–
+
21221819
CSP
4101 TC01
BAT
V
SET
1.19V
LT1055
EA
–
V
BAT
DAC
LTC4101
I
TH
+
–
0.7V
U
OPERATIO
Overview (Refer to Block Diagram)
The LTC4101 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger current, an 11-bit DAC to control charger voltage, a SafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled
if DCDIV is low, or the SafetySignal is decoded as
RES_HOT. If a battery is inserted and AC power is connected, the battery will be charged with an 80mA “wakeup” current. The wake-up current is discontinued after
t
TIMEOUT
RES_C0LD, and the battery or host doesn’t transmit
charging commands.
The SMBus interface and control block receives
ChargingCurrent() and ChargingVoltage() commands via
the SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a t
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence.
ChargingCurrent() and ChargingVoltage() values are compared against limits programmed by the limit decoder
if the SafetySignal is decoded as RES_UR or
TIMEOUT
interval, the
VV
–
V
TOL
BATVDAC
=
V
VDAC
FOR VVx
VDAC
DCINV
=
CLN CLPV
==
33).
VV
=
DD
•
100
=
.(
4 1760 10050
21
20
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The charger controller will assert SMBALERT whenever
a status change is detected, namely: AC_PRESENT,
BATTERY_PRESENT, ALARM_INHIBITED, or V
DD
power-fail. The host may query the charger, via the SMBus,
to obtain ChargerStatus() information. SMBALERT will be
deasserted upon a successful read of ChargerStatus() or
a successful Alert Response Address (ARA) request.
Battery Charger Controller
The LTC4101 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator I
resets the SR latch. While
CMP
the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current
comparator I
, or the beginning of the next cycle.
REV
The oscillator uses the equation,
VV
(–)
t
OFF
DCINBAT
=
Vf
(•)
DCINOSC
4101f
10
OPERATIO
LTC4101
U
to set the bottom MOSFET on time. The result is quasiconstant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
OFF
TGATE
ON
ON
BGATE
OFF
INDUCTOR
CURRENT
The peak inductor current, at which I
t
OFF
Figure 3.
TRIP POINT SET
VOLTAGE
BY I
TH
resets the SR
CMP
4101 F01
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the I
ITH for the desired voltage across R
DAC
at the I
SENSE
pin and adjusts
DC
.
The voltage at BAT is divided down by an internal resistor
divider set by the V
and is used by error amp EA to
DAC
decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the I
TH
voltage to reduce charging current.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the I
voltage exceeds a threshold that assures initial
TH
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
SMBus Interface
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device. All internal LTC4101 registers may be updated and accessed through the SMBus interface, and
charger controller as required. The SMBus protocol is a
derivative of the I
to Use It, V1.0”
2
CTM bus (Reference
“I2C-Bus and How
by Philips, and “System Management Bus
Specification,” Version 1.1, from the SBS Implementers
Forum, for a complete description of the bus protocol
requirements.)
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condition,
or power-on reset via the V
power-fail, will reset the
DD
SMBus interface to an initial state at any time.
The LTC4101 command set is interpreted by the SMBus
interface and passed onto the charger controller block as
control signals or updates to internal registers.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on the
TGATE pin. If TGATE stops switching for more than 40µs,
the watchdog activates and turns off the top MOSFET for
about 400ns. The watchdog engages to prevent very low
frequency operation in dropout – a potential source of audible
noise when using ceramic input and output capacitors.
Description of Supported Battery Charger Functions
The functions are described as follows (see Table 1 also):
FunctionName() 'hnn (command code)
Description: A brief description of the function.
Purpose: The purpose of the function, and an example
where appropriate.
• SMBus Protocol: Refer to Section 5 of the Smart
Battery Charger specification for more details.
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
4101f
11
LTC4101
OPERATIO
U
Input, Output or Input/Output: A description of the data
supplied to or returned by the function.
ChargerSpecInfo() ('h11)
Description: The SMBus Host uses this command to read
the LTC4101’s extended status bits.
Purpose: Allows the System Host to determine the specification revision the charger supports as well as other
extended status information.
• SMBus Protocol: Read Word.
Output: The CHARGER_SPEC indicates that the LTC4101
supports Version 1.1 of the Smart Battery Charger Specification. The SELECTOR_SUPPORT indicates that the
LTC4101 does not support the optional Smart Battery
Selector Commands.
ChargerMode() ('h12)
Description: The SMBus Host uses this command to set
the various charger modes. The default values are set to
allow a Smart Battery and the LTC4101 to work in concert
without requiring an SMBus Host.
Purpose: Allows the SMBus Host to configure the charger
and change the default modes. This is a write only function, but the value of the “mode” bit, INHIBIT_CHARGE
may be determined using the ChargerStatus() function.
• SMBus Protocol: Write Word.
Input: The INHIBIT_CHARGE bit allows charging to be
inhibited without changing the ChargingCurrent() and
ChargingVoltage() values. The charging may be resumed
by clearing this bit. This bit is automatically cleared when
power is reapplied or when a battery is reinserted.
The ENABLE_POLLING bit is not supported by the LTC4101.
Values written to this bit are ignored.
ChargerStatus() ('h13)
Description: The SMBus Host uses this command to read
the LTC4101’s status bits.
Purpose: Allows the SMBus Host to determine the status
and level of the LTC4101.
• SMBus Protocol: Read Word.
Output: The CHARGE_INHIBITED bit reflects the status of
the LTC4101 set by the INHIBIT_CHARGE bit in the
ChargerMode() function.
The POLLING_ENABLED, VOLTAGE_NOTREG, and
CURRENT_NOTREG are not supported by the LTC4101.
The LTC4101 always reports itself as a Level 2 Smart
Battery Charger.
CURRENT_OR bit is set only when ChargingCurrent() is
set to a value outside the current regulation range of the
LTC4101. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingCurrent() to determine the current capability of
the LTC4101. When ChargingCurrent() is set to the programmatic maximum current + 1, the CURRENT_OR bit
will be set.
VOLTAGE_OR bit is set only when ChargingVoltage() is
set to a value outside the voltage regulation range of the
LTC4101. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingVoltage() to determine the voltage capability of
the LTC4101. When ChargingVoltage() is set to the
programmatic maximum voltage, the VOLTAGE_OR bit
will be set.
The RES_OR bit is set only when the SafetySignal resistance value is greater than 95kΩ. This indicates that the
SafetySignal is to be considered as an open circuit.
The POR_RESET bit sets the LTC4101 to its power-on
default condition.
The RESET_TO_ZERO bit sets the ChargingCurrent()and
ChargingVoltage() values to zero. This function ALWAYS
clears the ChargingVoltage() and ChargingCurrent() values to zero even if the INHIBIT_CHARGE bit is set.
12
The RES_COLD bit is set only when the SafetySignal
resistance value is greater than 28.5kΩ. The SafetySignal
indicates a cold battery. The RES_COLD bit will be set
whenever the RES_OR bit is set.
The RES_HOT bit is set only when the SafetySignal
resistance is less than 3150Ω, which indicates a hot
battery. The RES_HOT bit will be set whenever the
RES_UR bit is set.
The RES_UR bit is set only when the SafetySignal resistance value is less than 575Ω.
ALARM_INHIBITED bit is set if a valid AlarmWarning()
message has been received and charging is inhibited as a
result. This bit is cleared if both ChargingVoltage() and
ChargingCurrent() are rewritten to the LTC4101, power is
removed (DCDIV < V
), or if a battery is removed. The
ACP
setting of the ALARM_INHIBITED will activate the LTC4101
SMBALERT pull-down.
POWER_FAIL bit is set if the LTC4101 does not have
sufficient DCIN voltage to charge the battery or if an
external device is pulling the CHGEN input signal low.
Charging is disabled whenever this bit is set. The setting
of this bit does not clear the values in the ChargingVoltage()
and ChargingCurrent() function values, nor does it necessarily affect the charging modes of the LTC4101.
BATTERY_PRESENT is set if a battery is present otherwise
it is cleared. The LTC4101 uses the SafetySignal
in order to determine battery presence. If the LTC4101
detects a RES_OR condition, the BATTERY_PRESENT bit
is cleared immediately. The LTC4101 will not set the
BATTERY_PRESENT bit until it successfully samples the
SafetySignal twice and does not detect a RES_OR condition on either sampling. If AC is not present (e.g. DCDIV <
V
), this bit may not be set for up to one-half second
ACP
after the battery is connected to the SafetySignal. The
ChargingCurrent() and ChargingVoltage() function values
are immediately cleared whenever this bit is cleared.
Charging will never be allowed if this bit is cleared. A
change in BATTERY_PRESENT will activate the LTC4101
SMBALERT pull-down.
AC_PRESENT is set if the voltage on DCDIV is greater than
. This does not necessarily indicate that the voltage on
V
ACP
DCIN is sufficient to charge the battery. A change in
AC_PRESENT will activate the LTC4101 SMBALERT pulldown.
ChargingCurrent() ('h14)
Description: The Battery, System Host or other master de-
vice sends the desired charging current (mA) to the LTC4101.
Purpose: The LTC4101 uses R
I
, and the value of the ChargingCurrent() function to
DAC
, the granularity of the
ILIM
determine its charging current supplied to the battery. The
charging current will never exceed the maximum current
permitted by R
truncated to the granularity of the I
. The ChargingCurrent() value will be
ILIM
. The charging
DAC
current will also be reduced if the battery voltage exceeds
the programmed charging voltage.
• SMBus Protocol: Write Word.
Input: The CHARGING_CURRENT is an unsigned 16 bit
integer specifying the requested charging current in mA.
The following table defines the maximum permissible
value of CHARGING_CURRENT that will not set the
CURRENT_OR in the ChargerStatus() function for a given
value of the R
R
ILIM
Short to GND 0x0000 through 0x03FF 0mA through 1023mA
10kΩ±1% 0x0000 through 0x07FF0mA through 2047mA
33kΩ±1% 0x0000 through 0x0BFF 0mA through 3071mA
Open (or short to VDD) 0x0000 through 0x0FFF0mA through 4095mA
ILIM
:
ChargingCurrent()Current
ChargingVoltage() ('h15)
Description: The Battery, SMBus Host or other master
device sends the desired charging voltage (mV) to the
LTC4101.
Purpose: The LTC4101 uses R
V
, and the value of the ChargingVoltage() function to
DAC
, the granularity of the
VLIM
determine its charging voltage supplied to the battery. The
charging voltage will never be forced beyond the voltage
permitted by R
truncated to the granularity of the V
. The ChargingVoltage() value will be
VLIM
. The charging
DAC
voltage will also be reduced if the battery current exceeds
the programmed charging current.
14
• SMBus Protocol: Write Word.
Input: The CHARGING_VOLTAGE is an unsigned 16-bit
integer specifying the requested charging voltage in mV.
The LTC4101 considers any value from 0x0001 through
0x044F the same as writing 0x0000. The following
4101f
OPERATIO
LTC4101
U
table defines the maximum permissible value of
CHARGING_VOLTAGE that will not set the VOLTAGE_OR
in the ChargerStatus() function for a given value of R
R
VLIM
Short to GND0x1090 (4240mV)
10kΩ ± 1%0x10D0 (4304mV)
33kΩ ± 1%0x1150 (4432mV)
100kΩ± 1%0x11A0 (4512mV)
Open (or short to VDD)0x1580 (5504mV)
Maximum ChargingVoltage()
VLIM
:
AlarmWarning() ('h16)
Description: The Smart Battery, acting as a bus master
device, sends the AlarmWarning() message to the LTC4101
to notify it that one or more alarm conditions exist. Alarm
indications are encoded as bit fields in the Battery’s Status
register, which is then sent to the LTC4101 by this
function.
Purpose: The LTC4101 will use the information sent by
this function to properly charge the battery. The LTC4101
will only respond to certain alarm bits. Writing to this
function does not necessarily cause an alarm condition
that inhibits battery charging.
disabling the LOWI current mode of the I
DAC
.
• SMBus Protocol: Write Word.
Input: The NO_LOWI is the only bit recognized by this
function. The default value of NO_LOWI is zero. The
LTC4101 LOWI current mode provides a more accurate
average charge current when the charge current is less
than 1/16 of the full scale I
is set, a less accurate I
value. When the NO_LOWI
DAC
algorithm is used to generate
DAC
the charging current, but because the charger is not
pulsed on and off, it may be preferred.
• SMBus Protocol: Read Word.
Output: The NO_LOWI indicates the I
mode of opera-
DAC
tion. If clear, then the LOWI current mode will be used
when the charging current is less than 1/16 of the fullscale I
DAC
value.
The LTC Version Identification will always be 0x4040 for
the LTC4101.
Alert Response Address (ARA)
Description: The SMBus system host uses the Alert
Response Address to quickly identify the generator of an
SMBALERT# event.
• SMBus Protocol: Write Word.
Input: Only the OVER_CHARGED_ALARM, TERMINATE
_CHARGE_ALARM, reserved (0x2000), and OVER
_TEMP_ALARM bits are supported by the LTC4101.
Writing a one to any of these specified bits will inhibit
the charging by the LTC4101 and will set the
ALARM_INHIBITED bit in the ChargerStatus() function. The
TERMINATE_DISCHARGE_ALARM, REMAINING_
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the
ERROR bits are ignored by the LTC4101.
LTC0() ('h3C)
Description: The SMBus Host uses this command to
determine the version number of the LTC4101 and set
extended operation modes not defined by the Smart
Battery Charger Specification.
Purpose: This function allows the SMBus Host to
determine if the battery charger is an LTC4101. Identifying the manufacturer and version of the Smart Battery
Charger permits software to perform tasks specific to
a given charger. The LTC4101 also provides a means of
Purpose: The LTC4101 will respond to an ARA if the
SMBALERT signal is actively pulling down the SMBALERT#
bus. The LTC4101 will follow the prioritization reporting as
defined in the System Management Bus Specification,
Version 1.1, from the SBS Implementers Forum.
• SMBus Protocol: A 7-bit Addressable Device Re-
sponds to an ARA.
Output: The Device Address will be sent to the SMBus
system host. The LTC4101 Device address is 0x12
(or 0x09 if just looking at the 7-bit address field).
The following events will cause the LTC4101 to pull-down
the SMBALERT# bus through the SMBALERT pin:
• Change of AC_PRESENT in the ChargerStatus()
function.
• Change of BATTERY_PRESENT in the ChargerStatus()
function.
• Setting ALARM_INHIBITED in the ChargerStatus()
function.
• Internal power-on reset condition.
4101f
15
LTC4101
OPERATIO
U
SMBus Accelerator Pull-Ups
Both SCL and SDA have SMBus accelerator circuits which
reduce the rise time on systems with significant capacitance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
1mA to 10mA pull-up to V
< VDD – 0.8V (external pull-up resistors are still required
to supply DC current). This action allows the bus to meet
SMBus rise time requirements with as much as 250pF on
each SMBus signal. The improved rise time will benefit all
of the devices which use the SMBus, especially those
devices that use the I
pull-up circuits only pull to V
that are not compliant to the SMBus specifications may
still have rise time compliance problems if the SMBus pullup resistors are terminated with voltages higher than VDD.
The Control Block
The LTC4101 charger operations are handled by the
control block. This block is capable of charging the selected battery autonomously or under SMBus Host control. The control block can request communications with
the system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present,
to poll the LTC4101.
The control block receives SMBus slave commands from
the SMBus interface block.
The control block allows the LTC4101 to meet the following Smart Battery-controlled (Level 2) charger
requirements:
1. Implements the Smart Battery’s critical warning messages over the SMBus.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output parameters accordingly.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcasting
the charging commands to the LTC4101 over the SMBus.
2
C logic levels. Note that the dynamic
when VIN > 0.8V until V
DD
, so some SMBus devices
DD
IN
Wake-up Charging Mode
The following conditions must be met in order to allow
wake-up charging of the battery:
1. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
ACP
ACP
)
.
2. AC must be present. This is qualified by DCDIV > V
Wake-up charging initiates when a newly inserted battery
does not send ChargingCurrent() and ChargingVoltage()
functions to the LTC4101.
The following conditions will terminate the Wake-up Charging Mode.
1. A T
TIMEOUT
RES_COLD or RES_UR.
2. The SafetySignal is registering RES_OR.
3. The successful writing of the ChargingCurrent() AND
ChargingVoltage() function. The LTC4101 will proceed
to the controlled charging mode after these two functions are written.
4. The SafetySignal is registering RES_HOT.
5. The AC power is no longer present. (DCDIV < V
6.The ALARM_INHIBITED becomes set in the
ChargerStatus() function.
7. The INHIBIT_CHARGE is set in the ChargerMode()
function.
8. The CHGEN pin is pulled low by an external device. The
LTC4101 will resume wake-up charging, if the CHGEN
pin is released by the external device. Toggling the
CHGEN pin will not reset the T
9. There is insufficient DCIN voltage to charge the battery.
The LTC4101 will resume wake-up charging when there
is sufficient DCIN voltage to charge the battery. This
condition will not reset the T
period is reached when the SafetySignal is
TIMEOUT
TIMEOUT
timer.
timer.
4. The LTC4101 will still respond to Smart Battery critical
warning messages without host intervention.
16
4101f
OPERATIO
LTC4101
U
Controlled Charging Algorithm Overview
The following conditions must be met in order to allow
controlled charging to start on the LTC4101:
1. The ChargingVoltage() AND ChargingCurrent() function must be written to non-zero values.
2. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
3. AC must be present. This is qualified by DCDIV > V
ACP
.
The following conditions will stop the Controlled Charging
Algorithm and will cause the Battery Charger Controller to
stop charging:
1. The ChargingCurrent() AND ChargingVoltage() functions have not been written for T
TIMEOUT
.
2. The SafetySignal is registering RES_OR.
3. The SafetySignal is registering RES_HOT.
4. The AC power is no longer present. (DCDIV < V
ACP
)
5. ALARM_INHIBITED is set in the ChargerStatus()
function.
6. INHIBIT_CHARGE is set in the ChargerMode() function.
Clearing INHIBIT_CHARGE will cause the LTC4101 to
resume charging using the previous ChargingVoltage()
AND ChargingCurrent() function values.
7. RESET_TO_ZERO is set in the ChargerMode() function.
8. CHGEN pin is pulled low by an external device. The
LTC4101 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function values, if the CHGEN pin is released by the external device.
9. Insufficient DCIN voltage to charge the battery. The
LTC4101 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function values, when there is sufficient DCIN voltage to charge the
battery.
10. Writing a zero value to ChargingVoltage() function.
11. Writing a zero value to ChargingCurrent() function.
The SafetySignal Decoder Block
This block measures the resistance of the SafetySignal
and features high noise immunity at critical trip points. The
low power standby mode supports only battery presence
SMB charger reporting requirements when AC is not
present. The SafetySignal decoder is shown in Figure 4.
The value of R
is 1.13k and R
THA
is 54.9k.
THB
SafetySignal sensing is accomplished by a state machine
that reconfigures the switches of Figure 4 using THA_SELB
and THB_SELB, a selectable reference generator, and two
comparators. This circuit has two modes of operation
based upon whether AC is present.
V
DD
V
DD
THA_SELB
THB_SELB
MUX
REF
SafetySignal
CONTROL
LATCH
HI_REF
LO_REF
RES_OR
RES_COLD
RES_H0T
RES_UR
+
TH_HI
–
+
TH_LO
–
4101 F04
4101f
R
THA
1.13k
16
THA
R
THB
54.9k
15
R
SafetySignal
THB
Figure 4. SafetySignal Decoder Block
C
SS
17
LTC4101
OPERATIO
U
When AC is present, the LTC4101 samples the value of the
SafetySignal and updates the ChargerStatus register approximately every 32ms. The state machine successively
samples the SafetySignal value starting with the RES_OR
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally
the RES_HOT ≥ RES_UR threshold. Once the SafetySignal
range is determined, the lower value thresholds are not
sampled. The SafetySignal decoder block uses the previously determined SafetySignal value to provide the appropriate adjustment in threshold to add hysteresis. The R
THB
resistor value is used to measure the RES_OR ≥ RES_COLD
and RES_COLD ≥ RES_IDEAL thresholds by connecting
the THB pin to V
the THA pin. The R
and measuring the voltage resultant on
DD
resistor value is used to measure
THA
the RES_IDEAL ≥ RES_HOT and RES_HOT ≥ RES_UR
thresholds by connecting the THA pin to V
and measur-
DD
ing the voltage resultant on the THB pin.
The SafetySignal decoder block uses a voltage divider
network between VDD and GND to determine SafetySignal
range thresholds. Since the THA and THB inputs are
sequentially connected to V
, this provides VDD noise
DD
immunity during SafetySignal measurement.
When AC power is not available the SafetySignal block
supports the following low power operating features:
1. The SafetySignal is sampled every 250ms or less,
instead of 32ms.
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms.
The SafetySignal impedance is interpreted according to
Table 4.
Note: The underrange detection scheme is a very important feature of the
LTC4101. The R
well above the 0.047 • V
pull-up. A system using a 10k pull-up would not be able to resolve the
important underrange to hot transition point with a modest 100mV of
ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.
THA/RSafetySignal
The required values for R
divider trip point of 0.333 • VDD (1V) is
(140mV) threshold of a system using a 10k
DD
THA
and R
are shown in
THB
Table 5.
Table 5. SafetySignal External Resistor Values
EXTERNAL RESISTORVALUE (Ω)
R
THA
R
THB
1130 ±1%
54.9k ±1%
CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
immunity from transients in the application. C
cannot
SS
exceed 1nF if the LTC4101 is to properly sense the value
of R
SafetySignal
.
18
4101f
OPERATIO
LTC4101
U
The I
Decoder Block
LIM
The value of an external resistor connected from this pin
to GND determines one of four current limits that are used
for maximum charging current value. These limits provide
a measure of safety with a hardware restriction on charging current which cannot be overridden by software.
Table 6. I
EXTERNALCONTROLLED
RESISTORCHARGING
(R
ILIM
Short to GNDV
10k ±1%0.17V
33k ±1%0.42V
Open (>250k,0.66V
or Short to V
Trip Points and Ranges
LIM
)I
VOLTAGECURRENT RANGE GRANULARITY
LIM
< 0.09V
ILIM
< 0.34V
VDD
VDD
< V
VDD
< V
DD
ILIM
ILIM
< 0.59V
< V
VDD
ILIM
DD
)
0 < I < 1023mA1mA
0 < I < 2046mA2mA
0 < I < 3068mA4mA
0 < I < 4092mA4mA
The V
Decoder Block
LIM
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are
applied to the charger output value. These limits provide
a measure of safety with a hardware restriction on charging voltage which cannot be overridden by software.
Table 7. V
EXTERNALCONTROLLED
RESISTOR CHARGING VOLTAGE
(R
VLIM
Short toV
GND< 4240mV
10k ±1%0.17V
33k ±1%0.42V
100k ±1%0.66V
Open or0.91V
Tied to V
Trip Points and Ranges (See Figure 5)
LIM
)V
DD
VOLTAGE(V
LIM
< 0.09V
VLIM
< 0.34V
< 0.59V
< 0.84V
VDD
VCCP
VDD
VDD
< V
VDD
< V
VDD
< V
VDD
< V
VCCP
VLIM
VLIM
VLIM
VLIM
OUT
2900mV < V
2900mV < V
< 4304mV
2900mV < V
< 4432mV
2900mV < V
< 4512mV
2900mV < V
< 5504mV
) RANGEGRANULARITY
OUT
OUT
OUT
OUT
OUT
16mV
16mV
16mV
16mV
16mV
V
DD
12.5k
33k
V
LIM
14
R
VLIM
25k
25k
25k
12.5k
Figure 5. Simplified V
+
–
+
–
+
–
+
–
Circuit Concept (I
LIM
AC_PRESENT
ENCODER
LIM
4
V
LIM
is Similar)
[3:0]
4101 F05
4101f
19
LTC4101
OPERATIO
U
The Voltage DAC Block
Note that the charger output voltage is offset by V
Therefore, the value of V
is subtracted from the SMBus
REF
REF
.
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 1.104V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage() value is above the limit set by the V
LIM
pin, then the charger output voltage is set to the value
determined by the V
resistor and the VOLTAGE_OR bit
LIM
is set. These limits are demonstrated in Figure 6.
6
R
= 33k
VLIM
5
4
(V)
BAT
3
2
CHARGER V
1
0
0
PROGRAMMED VALUE (V)
NOTE: THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.104V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
Figure 6. Transfer Function of Charger
453126
4101 F06
I
PROG
(FROM CA1 AMP)
I
DC
20
R
SET
Figure 7. Current DAC Operation
V
REF
MODULATOR
–
+
∆-∑
CHARGING_CURRENT
VALUE
19
4101 F07
I
TH
When a value less than 1/16th of the maximum current
allowed by I
is applied to the current DAC input, the
LIM
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is I
/8. The delta-sigma output gates this
MAX
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/bit,
so that the charger has time to settle to the I
MAX
/8 value.
The resulting average charging current is equal to that
requested by the ChargingCurrent() value.
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, independent of the I
setting.
LIM
Input FET
The Current DAC Block
The current DAC is a delta-sigma modulator which controls the effective value of an external resistor, R
SET
, used
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the ChargingCurrent() value,
received via the SMBus, to a variable resistance equal to:
1.25R
/[ChargingCurrent()/I
SET
LIM[x]
] = R
IDC
Therefore, programmed current is equal to:
CHARGE
= (102.3mV/R
I
for ChargingCurrent() < I
) (ChargingCurrent()/I
SENSE
.
LIM[x]
LIM[x]
),
20
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than V
130mV higher than V
to activate the charger. The
CLP
, it must go at least
CLP
CHGEN pin is forced low unless this condition is met. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
4101f
OPERATIO
LTC4101
U
the input FET is turned off slowly. If the voltage between
DCIN and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
The AC Present Block (AC_PRESENT)
The DCDIV pin is used to determine AC presence. If the
DCDIV voltage is above the DCDIV comparator threshold
(V
), then the ACP output pin will be switched to VDD and
ACP
the AC_PRESENT bit in the ChargerStatus() function will
be set. If the DCDIV voltage is below the DCDIV comparator threshold minus the DCDIV comparator hysteresis,
then the ACP output pin is switched to GND and the
AC_PRESENT bit in the ChargerStatus() function is cleared.
The ACP output pin is designed to drive 2mA continuously.
Adapter Limiting
An important feature of the LTC4101 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across R
, connected
CL
between the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/R
. A lowpass
CL
filter formed by 4.99k and 0.1µF is required to eliminate
switching noise. If the current limit is not used, CLP should
be connected to CLP, but leave CLN connected to power.
Setting Input Current Limit
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
input current limit tolerance and use that current to determine the resistor value.
R
= 100mV/I
CL
I
= Adapter Min Current –
LIM
LIM
(Adapter Min Current • 7%)
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Figure 9).
AVERAGE CHARGER CURRENT
I
/8
LIMIT
0
Figure 8. Charging Current Waveform in Low Current Mode
~40ms
LTC4101
+
100mV
24
23
4
–
CL1
+
*RCL =
100mV
ADAPTER CURRENT LIMIT
Figure 9. Adapter Current Limiting
CLP
CLN
INFET
C9
0.1µF
R1
4.99k
RCL*
TO LOAD
4101 F09
4101 F08
V
IN
4101f
21
LTC4101
WUUU
APPLICATIO S I FOR ATIO
Charge Termination Issues
Batteries with constant current charging and voltagebased charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
Setting Output Current Limit (Refer to Figure 1)
The LTC4101 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Table 9. Recommended Resistor Values
I
(A)R
MAX
1.0230.1000.250
2.0460.050.2510k
3.0680.0250.533k
4.0920.0250.5Open
SENSE
(Ω) 1%R
SENSE
(W)R
ILIM
(Ω) 1%
Warning
DO NOT CHANGE THE VALUE OF R
TION. The value must remain fixed and track the R
DURING OPERA-
ILIM
SENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentially damage the battery or overload the wall adapter
if no input current limiting is provided.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆I
with higher frequency and increases with higher V
* Rounded to nearest 5% standard step value. Many non standard values are popular.
CL
RCLPowerRCL Power
4101f
22
LTC4101
U
WUU
APPLICATIOS IFORATIO
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(I
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET is
on. Lower inductor values (higher ∆IL) will cause this to
occur at higher load currents, which can cause a dip in
efficiency in the upper range of low current operation.
Choose and inductor who’s inductance value is equal to
or greater than the value shown. Values assume:
1.–32% RSS result from –20% inductance tolerance
and a –25% inductance loss at I
MAX
2.Inductor ripple current ratio of 0.51 of I
SENSE
is at 4.2V
OUT
.
R
3. V
Charger Switching Power MOSFET
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BV
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
, total gate capacitance QG, reverse
DS(ON)
). Remember the
MAX
(A)
.
across
OUT
DSS
transfer capacitance C
, input voltage and maximum
RSS
output current. The charger is operating in continuous
mode so the duty cycles for the top and bottom MOSFETs
are given by:
Main Switch Duty Cycle = V
Synchronous Switch Duty Cycle = (VIN – V
OUT/VIN
OUT
)/VIN.
The MOSFET power dissipations at maximum output
current are given by:
OUT
)/VIN(I
)2(1 + δ∆T)R
)(C
MAX
)(f
RSS
)2(1 + δ∆T)R
MAX
DS(ON)
)
OSC
DS(ON)
DS(ON)
and
PMAIN = V
OUT/VIN(IMAX
+ k(VIN)2(I
PSYNC = (V
IN
– V
Where δ∆T is the temperature dependency of R
k is a constant inversely related to the gate drive current.
2
Both MOSFETs have I
R losses while the PMAIN equation
includes an additional term for transition losses, which are
highest at high input voltages. For V
< 20V the high
IN
current efficiency generally improves with larger MOSFETs, while for V
increase to the point that the use of a higher R
with lower C
RSS
> 20V the transition losses rapidly
IN
device
DS(ON)
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage or during a short circuit when the duty cycle in this
switch in nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized R
DS(ON)
vs
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs. C
∆V
is usually specified in the MOSFET characteristics.
DS
RSS
= QGD/
The constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation
equation.
If the charger is to operate in low dropout mode or with a
high duty cycle less than 50%, then the bottomside
N-Channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
Both of the LTC4101 MOSFET drivers are optimized to take
advantage of MOSFETs Q
values of less than 22nC and a
G
TD-off delay specification of around 60ns or less. Larger
FETs may work, but you must qualify them and monitor
LTC4101 temperature rise.
4101f
23
LTC4101
WUUU
APPLICATIO S I FOR ATIO
Using excessively large MOSFETs relative to the I
MAX
charge current they are working with will actually reduce
efficiency at lighter current levels with very limited gain at
high currents. A good place to start looking for a suitable
MOSFET in a datasheet is to look for a part with an ID rating
a little over 2 times the I
charge current rating. For the
MAX
LTC4101, the P-channel FET can typically be scaled down
a bit to take advantage of the lower duty cycle limits.
However make sure you never exceed the PD rating of the
device.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4101 is dependent upon
the gate charge of the top and bottom MOSFETs (Q2 & Q3
respectively) The gate charge (QG) is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and V
DCIN
for
the drain voltage swing.
= V
P
D
Example: V
DCIN
• (f
DCIN
QG
Q3
I
= 1mA.
DD
(QGQ2 + QGQ3) + I
OSC
= 12V, f
= 15nC, I
= 345kHz, QGQ2 = 25nC,
OSC
DCIN
) + VDD • I
DCIN
= 5mA, VDD = 5.5V,
DD
Soft-Start and Undervoltage Lockout
The LTC4101 is soft-started by the 0.12µF capacitor on the
pin. On start-up, ITH pin voltage will rise quickly to 0.5V,
I
TH
then ramp up at a rate set by the internal 30µA pull-up
current and the external capacitor. Battery charging
current starts ramping up when I
and full current is achieved with I
voltage reaches 0.8V
TH
at 2V. With a 0.12µF
TH
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
In any switching regulator, conventional timer-based
soft-starting can be defeated if the input voltage rises
much slower than the time out period. This happens
because the switching regulators in the battery charger
and the computer power supply are typically supplying a
fixed amount of power to the load. If input voltage comes
up slowly compared to the soft-start time, the regulators
will try to deliver full power to the load when the input
voltage is still well below its final value. If the adapter is
current limited, it cannot deliver full power at reduced
output voltages and the possibility exists for a quasi
“latch” state where the adapter output stays in a current
limited state at reduced output voltage. For instance, if
maximum charger plus computer load power is 30W, a
15V adapter might be current limited at 2.5A. If adapter
voltage is less than (30W/2.5A = 12V) when full power is
drawn, the adapter voltage will be pulled down by the
constant 30W load until it reaches a lower stable state
where the switching regulators can no longer supply full
load. This situation can be prevented by utilizing the
DCDIV resistor divider, set higher than the minimum
adapter voltage where full power can be achieved.
= 231mW
P
D
24
4101f
WUUU
⎛
⎞
APPLICATIO S I FOR ATIO
LTC4101
Input and Output Capacitors
In the 4A Lithium Battery Charger (Typical Application on
back page), the input capacitor (C2) is assumed to absorb
all input switching ripple current in the converter, so it
must have adequate ripple current rating. Worst-case
RMS ripple current will be equal to one half of output
charging current. Actual capacitance value is not critical.
Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package,
but
caution must be used when tantalum capacitors are used
for input or output bypass
. High input surge currents can
be created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid
tantalum capacitors have a known failure mechanism
when subjected to very high turn-on surge currents. Only
Kemet T495 series of “Surge Robust” low ESR tantalums
are rated for high surge conditions such as battery to
ground.
The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
The highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least 20µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OSCON capacitors
from Sanyo.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
V
0291
.()–
I
=
RMS
For example, V
f = 300kHz, I
RMS
V
BAT
Lf
()()
= 12V, V
DCIN
= 0.26A.
1
BAT
⎜
⎝
⎟
⎠
V
DCIN
= 4.2V, L1 = 10µH, and
BAT
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the300kHz
switching frequency. Switching ripple current splits between the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance. If the ESR of C3
is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
Protecting SMBus Inputs
The SMBus inputs, SCL and SDA, are exposed to uncontrolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to transients which can cause
damage after repeated exposure. Also, if the battery’s
positive terminal makes contact to the connector before
the negative terminal, the SMBus inputs can be forced
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 10.
V
DD
CONNECTOR
TO BATTERY
Figure 10. Recommended SMBus Transient Protection
TO SYSTEM
4101 F13
4101f
25
LTC4101
WUUU
APPLICATIO S I FOR ATIO
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
Interfacing with a Selector
The LTC4101 is designed to be used with a true analog
multiplexer for the SafetySignal sensing path. Some selector ICs from various manufacturers may not implement
this. Consult LTC applications department for more
information.
Electronic Loads
The LTC4101 is designed to work with a real battery.
Electronic loads will create instability within the LTC4101
preventing accurate programming currents and voltages.
Consult LTC applications department for more
information.
V
IN
26
SWITCH NODE
HIGH
FREQUENCY
C2
CIRCULATING
PATH
Figure 11. High Speed Switching Path
L1
D1
V
BAT
C4
BAT
4101 F15
Figure 12. Kelvin Sensing of Charging Current
DIRECTION OF CHARGING CURRENT
R
SENSE
TO CSP AND BAT
4101 F14
4101f
PACKAGE DESCRIPTIO
LTC4101
U
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
1.25 ±0.12
7.8 – 8.2
0.42 ±0.030.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
5.00 – 5.60**
(.197 – .221)
0.09 – 0.25
(.0035 – .010)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
0.55 – 0.95
(.022 – .037)
MILLIMETERS
(INCHES)
5.3 – 5.7
0° – 8°
7.90 – 8.50*
(.311 – .335)
212218 17 16 15 14
19202324
12345678 9 10 11 12
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
13
(.291 – .323)
2.0
(.079)
MAX
0.05
(.002)
MIN
G24 SSOP 0204
7.40 – 8.20
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4101f
27
LTC4101
TYPICAL APPLICATIO
U
LTC4101 Li-Ion Battery Charger I
DCIN
R10
424 23
6.04k
1%
5
DCIN
11
DCDIV
R5
6.04k
1%
19
I
20
I
12
GND
17
V
14
V
13
I
10
ACP
6
CHGEN
7
SMBALERT
8
SDA
9
SCL
Q1
INFET
TH
DC
LIM
3V TO 5.5V
SDA
SCL
9V TO 12V
DCIN
FROM WALL
ADAPTER
R11
1.21k
1%
10k10k
D4
D5
C1
0.1µF
C6, 0.12µF
10V, X7R
C7, 0.0015µF
10V, X7R
C8, 0.068µF
10V, X7R
0.1µF
10V
D2
D3
DD
LIM
0.033Ω
0.5W
0.1µF
LTC4101
LIM
R
CL
1%
C9
10V
TGATE
BGATE
PGND
V
= 4A/V
R1
4.9k
CLNCLP
CSP
BAT
SET
THA
THB
= 4.240V, Adapter Rating = 2.7A
LIM
1
Q2
3
Q3
2
21
22
18
16
15
0.5W, 1%
C4
0.03µF
25V
C5
R
0.1µF
1.13k
10V
R
54.9k
D1: MBRM140T3
D2-D5: SMALL SIGNAL SCHOTTKY
Q1: 1/2 Si790IEDN
Q2: FDS6685
Q3: Si7804DN
0.025Ω
100Ω
THA
1%
THB
1%
SYSTEM
LOAD
C2, C3
10µF × 2
L1
6µH
4A
C4,C5
10µF × 2
10V
16V
DCIN
100k
10k
SafetySignal
SMART
BATTERY
Q4
1/2 Si790IEDN
4101 TA02
SDA
SCL
D1
R
SNS
R4
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