LINEAR TECHNOLOGY LTC4006 Technical data

FEATURES

■

Complete Charger Controller for 2-, 3- or 4-Cell
Lithium-Ion Batteries

■

High Conversion Efficiency: Up to 96%

■

Output Currents Exceeding 4A

■

±0.8% Accurate Preset Voltages: 8.4V, 12.6V, 16.8V

■

Built-In Charge Termination with Automatic Restart

■

AC Adapter Current Limiting Maximizes Charge Rate*

■

Automatic Conditioning of Deeply Discharged
Batteries

■

Thermistor Input for Temperature Qualified Charging

■

Wide Input Voltage Range: 6V to 28V

■

0.5V Dropout Voltage; Maximum Duty Cycle: 98%

■

Programmable Charge Current: ±4% Accuracy

■

Indicator Outputs for Charging, C/10 Current
Detection and AC Adapter Present

■

Charging Current Monitor Output

■

16-Pin Narrow SSOP Package

U

APPLICATIO S

■

Notebook Computers

■

Portable Instruments

■

Battery-Backup Systems

■

Standalone Li-Ion Chargers

LTC4006

4A, High Efficiency,

Standalone Li-Ion

Battery Charger

U

DESCRIPTIO

The LTC®4006 is a complete constant-current/constant­voltage charger controller for 2-, 3- or 4-cell lithium bat­teries in a small package using few external components.
The PWM controller is a synchronous, quasi-constant fre­quency, constant off-time architecture that will not gener­ate audible noise even when using ceramic capacitors.

The LTC4006 is available in 8.4V, 12.6V and 16.8V versions
with ±0.8% voltage accuracy. Charging current is program-
mable with a single sense resistor to ±4% typical accuracy.
Charging current can be monitored as a representative
voltage at the I
resistor, sets the total charge time or is reset to 25% of total
charge time after C/10 charging current is reached. Charg­ing automatically resumes when the cell voltage falls below

3.9V/cell.

Fully discharged cells are automatically trickle charged at
10% of the programmed current until the cell voltage ex­ceeds 2.5V/cell. Charging terminates if the low-battery
condition persists for more than 25% of the total charge
time.

The LTC4006 includes a thermistor sensor input that
suspends charging if an unsafe temperature condition is
detected and automatically resumes charging when the
battery temperature returns to within safe limits.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5723970.

pin. A timer, programmed by an external

MON

TYPICAL APPLICATIO

DCIN

0V TO 28V

3A

V

LOGIC

CHG

ACP

CHARGING

CURRENT MONITOR

THERMISTOR

10k

NTC

0.47µF

U

32.4k

0.0047µF

309k

TIMING

RESISTOR

(~2 HOURS)

100k

0.1µF

0.12µF

4A Li-Ion Battery Charger

INPUT SWITCH

T

LTC4006

INFET

CLP

CLN

TGATE

BGATE

PGND

CSP

BAT

DCIN

CHG

ACP/SHDN

I

MON

NTC

R

I

TH

6k

GND

5k

15nF

0.033Ω

20µF
10µH

TO SYSTEM LOAD

0.025Ω

4006 TA01

BATTERY

20µF

4006fa

1

LTC4006

WW

W

ABSOLUTE MAXIMUM RATINGS

U

U

W

PACKAGE/ORDER INFORMATION

U

(Note 1)

Voltage from DCIN, CLP, CLN, TGATE, INFET,

ACP/SHDN, CHG to GND ....................... +32V to –0.3V

Voltage from CLP to CLN..................................... ±0.3V

CSP, BAT to GND................................... +28V to –0.3V

to GND ................................................. +7V to –0.3V

R

T

NTC ........................................................ +10V to –0.3V

Operating Ambient Temperature Range

(Note 4) ............................................. –40°C to 85°C

DCIN

CHG

ACP/SHDN

GND

NTC

I

I

MON

Operating Junction Temperature ......... –40°C to 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

ELECTRICAL CHARACTERISTICS

temperature range (Note 4), otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DCIN Operating Range 628V

I

DCIN

V

TOL

I

TOL

T

TOL

Shutdown

UVLO Undervoltage Lockout Threshold DCIN Rising, V

Current Sense Amplifier, CA1

CMSL CA1/I1 Input Common Mode Low
CMSH CA1/I1 Input Common Mode High

DCIN Operating Current Sum of Current from CLP, CLN, DCIN 3 5 mA

Voltage Accuracy (Note 2)

Current Accuracy (Note 3) V

Termination Timer Accuracy RRT = 270k

Battery Leakage Current DCIN = 0V 20 35 µA

Shutdown Threshold at ACP/SHDN
DCIN Current in Shutdown V

Input Bias Current Into BAT Pin 11.67 µA

The ● denotes specifications which apply over the full operating

= 25°C. V

A

LTC4006-6 8.333 8.4 8.467 V
LTC4006-6
LTC4006-2 12.499 12.6 12.700 V
LTC4006-2
LTC4006-4 16.665 16.8 16.935 V
LTC4006-4

– V

CSP

= 11.5V (LTC4006-2)

V

BAT

V

= 7.6V (LTC4006-6)

BAT

= 12V (LTC4006-4)

V

BAT

V

< 6V, V

BAT

6V ≤ V

BAT

– V

V

CSP

DCIN = 0V
DCIN = 20V, V

= 0V, Sum of Current from CLP, 2 3 mA

SHDN

CLN, DCIN

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Target = 100mV – 4 4 %

BAT

– V

CSP

≤ V

LOBAT

Target = 10mV

BAT

SHDN

BAT

T

= 20V, V

DCIN

Target = 10mV –60 60 %

BAT

,–4040%

= 0V, V

= 0V

TOP VIEW

1

2

3

4

R

T

5

6

7

TH

8

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θJA = 110°C/W

JMAX

= 12V unless otherwise noted.

BAT

= 12V

BAT

ORDER PART

INFET

16

BGATE

15

PGND

14

TGATE

13

CLN

12

CLP

11

BAT

10

CSP

9

NUMBER

LTC4006EGN-2
LTC4006EGN-4
LTC4006EGN-6

GN PART MARKING

40062
40064
40066

●

8.316 8.4 8.484 V

●

12.474 12.6 12.726 V

●

16.632 16.8 16.968 V

●

–5 5 %

●

–15 15 %

●

●

–10 0 10 µA

●

4.2 4.7 5.5 V

●

1 2.5 V

●

0V

●

25 45 µA

V

– 0.2 V

CLN

4006fa

2

LTC4006

ELECTRICAL CHARACTERISTICS

temperature range (Note 4), otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. V

A

DCIN

= 20V, V

= 12V unless otherwise noted.

BAT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Current Comparators I

I

TMAX

I

TREV

Maximum Current Sense Threshold (V

Reverse Current Threshold (V

CMP

and I

REV

CSP

– V

)V

CSP

BAT

– V

)–30mV

BAT

ITH

= 2.5V

●

140 165 200 mV

Current Sense Amplifier, CA2

Transconductance 1 mmho

Source Current Measured at ITH, V

Sink Current Measured at ITH, V

= 1.4V – 40 µA

ITH

= 1.4V 40 µA

ITH

Current Limit Amplifier

Transconductance 1.5 mmho

V

I

CLP

CLP

Current Limit Threshold

●

93 100 107 mV

CLP Input Bias Current 100 nA

Voltage Error Amplifier, EA

Transconductance 1 mmho

Sink Current Measured at ITH, V

OVSD Overvoltage Shutdown Threshold as a Percent

= 1.4V 36 µA

ITH

●

102 107 110 %

of Programmed Charger Voltage

Input P-Channel FET Driver (INFET)

DCIN Detection Threshold (V

Forward Regulation Voltage (V

Reverse Voltage Turn-Off Voltage (V

INFET “On” Clamping Voltage (V

INFET “Off” Clamping Voltage (V

DCIN

DCIN

– V

) DCIN Voltage Ramping Up

DCIN

DCIN

– V

DCIN

CLN

– V

– V

CLN

)

– V

INFET

INFET

from V

CLN

) DCIN Voltage Ramping Down

CLN

)I

)I

= 1µA

INFET

= –25µA 0.25 V

INFET

– 0.1V

●

0 0.17 0.25 V

●

●

–60 –25 mV

●

5 5.8 6.5 V

25 50 mV

Thermistor

NTCVR Reference Voltage During Sample Time 4.5 V

High Threshold V

NTC

Rising

●

NTCVR NTCVR NTCVR V

• 0.48 • 0.5 • 0.52

Low Threshold V

NTC

Falling

●

NTCVR NTCVR NTCVR V

• 0.115 • 0.125 • 0.135

Thermistor Disable Current V

≤ 10V 10 µA

NTC

Indicator Outputs (ACP/SHDN, CHG)

C10TOL C/10 Indicator Accuracy Voltage Falling at PROG

LBTOL LOBAT Threshold Accuracy LTC4006-6

LTC4006-2
LTC4006-4

RESTART Threshold Accuracy LTC4006-6

LTC4006-2
LTC4006-4

V

OL

V

OH

I

PO

Low Logic Level of ACP/SHDN, CHG IOL = 100µA

High Logic Level of ACP/SHDN IOH = –1µA

Pull-Up Current on ACP/SHDN V = 0V –10 µA

IC10 C/10 Indicator Sink Current from CHG VOH = 3V

I

OFF

Off State Leakage Current of CHG VOH = 3V –1 1 µA

●

0.375 0.400 0.425 V

●

4.70 4.93 5.14 V

●

7.27 7.5 7.71 V

●

9.70 10 10.28 V

●

7.5 7.8 7.96 V

●

11.35 11.7 11.94 V

●

15.15 15.6 15.92 V

●

●

2.7 V

●

15 25 38 µA

0.5 V

Timer Defeat Threshold at CHG 1 V

4006fa

3

LTC4006

ELECTRICAL CHARACTERISTICS

temperature range (Note 4), otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. V

A

DCIN

= 20V, V

= 12V unless otherwise noted.

BAT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Oscillator

f

f

DC

OSC

MIN

MAX

Regulator Switching Frequency 255 300 345 kHz
Regulator Switching Frequency in Drop Out Duty Cycle ≥ 98% 20 25 kHz

Regulator Maximum Duty Cycle V

CSP

= V

BAT

98 99 %

Gate Drivers (TGATE, BGATE)

V

High (V

TGATE

V

High C

BGATE

V

Low (V

TGATE

V

Low I

BGATE

CLN

CLN

– V

– V

)I

TGATE

)C

TGATE

= –1mA 50 mV

TGATE

= 3000pF 4.5 5.6 10 V

LOAD

= 3000pF 4.5 5.6 10 V

LOAD

= 1mA 50 mV

BGATE

TGATE Transition Time
TGTR TGATE Rise Time C
TGTF TGATE Fall Time C

= 3000pF, 10% to 90% 50 110 ns

LOAD

= 3000pF, 10% to 90% 50 100 ns

LOAD

BGATE Transition Time
BGTR BGATE Rise Time C
BGTF BGATE Fall Time C

V

at Shutdown (V

TGATE

V

at Shutdown I

BGATE

CLN

– V

)I

TGATE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: See Test Circuit

= 3000pF, 10% to 90% 40 90 ns

LOAD

= 3000pF, 10% to 90% 40 80 ns

LOAD

= –1µA, DCIN = 0V, CLN = 12V 100 mV

TGATE

= 1µA, DCIN = 0V, CLN = 12V 100 mV

BGATE

Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4006E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

INFET Response Time to
Reverse Current

= 0

V

gs

= 0V

V

s

Id (REVERSE) OF
PFET (5A/DIV)

I

= 0A

d

TEST PERFORMED ON DEMOBOARD

= 15VDC

V

IN

CHARGER = ON

= <10mA

I

CHARGE

Vgs OF PFET (2V/DIV)

Vs OF PFET (5V/DIV)

1.25µs/DIV

LTC4006-2
INFET = 1/2 Si4925DY

4006 G01

V

vs I

OUT

OUT

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

OUTPUT VOLTAGE ERROR (%)

DCIN = 20V

–4.5

–5.0

= 12.6V

V

BAT

0 0.5 1.0 2.0 3.0 4.01.5 2.5 3.5 4.5

OUTPUT CURRENT (A)

4006 G02

PWM Frequency vs Duty Cycle

350

300

250

200

150

100

PWM FREQUENCY (kHz)

50

PROGRAMMED CURRENT = 10%

DCIN = 15V
DCIN = 20V

0

0 0.1 0.2 0.4 0.6 0.90.80.3 0.5 0.7 1.0

DCIN = 24V

DUTY CYCLE (V

OUT/VIN

)

4006 G03

4006fa

4

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC4006

Disconnect/Reconnect Battery
(Load Dump)

3A STEP

V

FLOAT

1V/(DIV)

LOAD

STATE

LOAD CURRENT = 1A, 2A, 3A
DCIN = 20V
LTC4006-2

1A STEP

DISCONNECT

Efficiency at 19VDC V

100

LTC4006-4

95

90

1A STEP

3A STEP

RECONNECT

LTC4006-2

Battery Leakage Current vs
Battery Voltage

40

VDCIN = 0V

35

30

25

20

15

10

BATTERY LEAKAGE CURRENT (µA)

5

0

0 5 10 15 20 25 30

4006 G04

BATTERY VOLTAGE (V)

4006 G05

LTC4006-2 Efficiency with

IN

15VDC V

100

95

90

IN

85

EFFICIENCY (%)

80

75

U

1.000.50 1.50 2.00 2.50 3.00
CHARGING CURRENT (A)

4006 G07

UU

PI FU CTIO S

DCIN (Pin 1): External DC Power Source Input. Bypass
this pin with at least 0.01µF. See Applications Information
section.

CHG (Pin 2): Open-Drain Charge Status Output. When the
battery is being charged, the CHG pin is pulled low by an
internal N-channel MOSFET. When the charge current
drops below 10% of programmed current, the N-channel
MOSFET turns off and a 25µA current source is connected
from the CHG pin to GND. When the timer runs out or the
input supply is removed, the current source will be discon-

85

EFFICIENCY (%)

80

75

1.000.50 1.50 2.00 2.50 3.00
CHARGING CURRENT (A)

4006 G08

nected and the CHG pin is forced into a high impedance
state. A pull-up resistor is required. The timer function is
defeated by forcing this pin below 1V (or connecting it to
GND).

ACP/SHDN (Pin 3): Open-Drain Output used to indicate if
the AC adapter voltage is adequate for charging. Active
high digital output. Internal 10µA pull-up to 3.5V. The
charger can also be inhibited by pulling this pin below 1V.
Reset the charger by pulsing the pin low for a minimum of

0.1µs.

4006fa

5

LTC4006

U

UU

PI FU CTIO S

(Pin 4): Timer Resistor. The timer period is set by

R

T

placing a resistor, R

The timer period is t

If this resistor is not present, the charger will not start.

GND (Pin 5): Ground for low power circuitry.

NTC (Pin 6): A thermistor network is connected from NTC

to GND. This pin determines if the battery temperature is
safe for charging. The charger and timer are suspended if
the thermistor indicates a temperature that is unsafe for
charging. The thermistor function may be disabled with a
300k to 500k resistor from DCIN to NTC.

I

(Pin 7): Control Signal of the Inner Loop of the Current

TH

Mode PWM. Higher I
charging currrent in normal operation. A 6.04k resistor, in
series with a capacitor of at least 0.1µF to GND, provides
loop compensation. Typical full-scale output current is
40µA. Nominal voltage range for this pin is 0V to 3V.

I

(Pin 8): Current Monitoring Output. The voltage at

MON

this pin provides a linear indication of charging current.
Peak current is equivalent to 1.19V. Zero current is ap­proximately 0.309V. A capacitor from I
required to filter higher frequency components. If V

2.5V/cell, then V(I
depleted battery. Any current sourced or sinked from this
pin directly affects the charging current accuracy. If this
pin is to be monitored, a high impedance input buffer
should be used.

, to GND.

RT

= (1hour • RRT/154k)

TIMER

voltage corresponds to higher

TH

to ground is

MON

) = 1.19V when conditioning a

MON

BAT

<

CSP (Pin 9): Current Amplifier CA1 Input. This pin and the
BAT pin measure the voltage across the sense resistor,
R

, to provide the instantaneous current signals re-

SENSE

quired for both peak and average current mode operation.

BAT (Pin 10): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A precision
internal resistor divider sets the final float potential on this
pin. The resistor divider is disconnected during shutdown.

CLP (Pin 11): Positive Input to the Supply Current Limiting
Amplifier, CL1. The threshold is set at 100mV above the
voltage at the CLN pin. When used to limit supply current,
a filter is needed to filter out the switching noise. If no
current limit function is desired, connect this pin to CLN.

CLN (Pin 12): Negative Reference for the Input Current
Limit Amplifier, CL1. This pin also serves as the power
supply for the IC. A 10µF to 22µF bypass capacitor should
be connected as close as possible to this pin.

TGATE (Pin 13): Drives the top external P-channel MOSFET
of the battery charger buck converter.

PGND (Pin 14): High Current Ground Return for the BGATE
Driver.

BGATE (Pin 15): Drives the bottom external N-channel
MOSFET of the battery charger buck converter.

INFET (Pin 16): Drives the Gate of the External Input PFET.

TEST CIRCUIT

6

35mV

+

–

LTC4006

I

7

4006 TC

TH

0.6V

4006fa

11.67µA

+

–

3k

BAT

10

V

+

REF

EA

–

CSP

9

LT1055

BLOCK DIAGRA

V

IN

DCIN

0.1µF

Q3

5.1k

R

15nF

CL

INFET

ACP/SHDN

GND

CLP

CLN

20µF

1

16

3

5

11

12

–

100mV

+

W

5.8V

CL1

OSCILLATOR

WATCH DOG

DETECT t

DCIN

OFF

g

= 1.5m

m

1.19V

Ω

708mV

1.28V

1.105V

LTC4006

25µA

CLN

RESTART

LOBAT

TIMER/CONTROLLER

35mV

I

CL

T

BAD

C/10

OSCILLATOR

THERMISTOR

397mV

–

11.67µA

+

+

EA

Ω

= 1m

g

m

CA1

3k

–

3k

+

–

9k

Ω

g

= 1m

m

OV

÷ 5

BUFFERED I

CA2

–

1.19V

+

TH

2

4

6

10

9

7

CHG

R

T

NTC

BAT

CSP

I

TH

6.04k

0.12µF

100k

R

32.4k

0.47µF

R

SENSE

V

LOGIC

RT

10k
NTC

20µF

TGATE

BGATE

PGND

13

15

14

PWM

LOGIC

Q1

Q2

L1

Q

CHARGE

I

REV

S

R

I

CMP

+

+

–

–

–

17mV

+

R

26.44k

R

52.87k

IMON1

IMON2

I

MON

8

4.7nF

4006 BD

4006fa

7

LTC4006

OPERATIO

U

Overview

The LTC4006 is a synchronous current mode PWM step­down (buck) switcher battery charger controller. The charge
current is programmed by the sense resistor (R

SENSE

)
between the CSP and BAT pins. The final float voltage is
internally programmed to 8.4V (LTC4006-6), 12.6V
(LTC4006-2) or 16.8V (LTC4006-4) with better than ±0.8%
accuracy. Charging begins when the potential at the DCIN
pin rises above the voltage at CLN (and the UVLO voltage)
and the ACP/SHDN pin is allowed to go high; the CHG pin
is set low. At the beginning of the charge cycle, if the cell
voltage is below 2.5V, the charger will trickle charge the
battery with 10% of the maximum programmed current.
If the cell voltage stays below 2.5V for 25% of the total
charge time, the charge sequence will be terminated im­mediately and the CHG pin will be set to a high impedance.

An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended. If the thermistor value returns to
an acceptable value, charging resumes. An external resis­tor on the R

pin sets the total charge time. The timer can

T

be defeated by forcing the CHG pin to a low voltage.

As the battery approaches the final float voltage, the charge
current will begin to decrease. When the current drops to
10% of the programmed charge current, an internal C/10
comparator will indicate this condition by sinking 25µA at the
CHG pin. The charge timer is also reset to 25% of the total
charge time. If this condition is caused by an input current
limit condition, described below, then the C/10 comparator
will be inhibited. When a time-out occurs, charging is termi­nated immediately and the CHG pin changes to a high
impedance. The charger will automatically restart if the cell
voltage is less than 3.9V. To restart the charge cycle manu­ally, simply remove the input voltage and reapply it, or force
the ACP/SHDN pin low momentarily. When the input voltage
is not present, the charger goes into a sleep mode, dropping
battery current drain to 15µA. This greatly reduces the current
drain on the battery and increases the standby time. The
charger can be inhibited at any time by forcing the ACP/SHDN
pin to a low voltage.

Input FET

The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the

ACP/SHDN pin. It controls the gate of the input FET to keep
a low forward voltage drop when charging and also
prevents reverse current flow through the input FET.

If the input voltage is less than V
170mV higher than V

to activate the charger. When this

CLN

, it must go at least

CLN

occurs the ACP/SHDN pin is released and pulled up with
an internal load to indicate that the adapter is present. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLN is ever less than – 25mV, then the input FET
is turned off in less than 10µs to prevent significant
reverse current from flowing in the input FET. In this
condition, the ACP/SHDN pin is driven low and the charger
is disabled.

Battery Charger Controller

The LTC4006 charger controller uses a constant off-time,
current mode step-down architecture. During normal opera­tion, the top MOSFET is turned on each cycle when the
oscillator sets the SR latch and turned off when the main
current comparator I

resets the SR latch. While the top

CMP

MOSFET is off, the bottom MOSFET is turned on until either
the inductor current trips the current comparator I

REV

or the

beginning of the next cycle. The oscillator uses the equation:

VV

–

t

OFF

DCIN BAT

=

Vf

•

DCIN OSC

to set the bottom MOSFET on time. This activity is dia­grammed in Figure 1.

The peak inductor current, at which I

resets the SR latch,

CMP

is controlled by the voltage on ITH. ITH is in turn controlled by
several loops, depending upon the situation at hand. The
average current control loop converts the voltage between
CSP and BAT to a representative current. Error amp CA2

OFF

TGATE

ON

BGATE

INDUCTOR

CURRENT

ON

OFF

t

OFF

TRIP POINT SET BY ITH VOLTAGE

Figure 1

4006 F01

4006fa

8

LTC4006

U

OPERATIO

Table 1. Truth Table for LTC4006 Operation

MODE DCIN BAT VOLTAGE BAT CURRENT ACP/SHDN TIMER STATE CHG*

Shut Down by Low Adapter Voltage <BAT >UVLO Leakage LOW Reset HIGH
Conditioning a Depleted Battery >BAT <2.5V/Cell 10% Programmed HIGH Running LOW

Current

Normal Charging >BAT >2.5V/Cell Programmed HIGH Running LOW

Input Current Limited Charging >BAT >2.5V/Cell Programmed HIGH Running LOW

Charger Paused Due to Thermistor Out of Range >BAT X OFF HIGH Paused LOW or 25µA

Shut Down by ACP/SHDN Pin >BAT X OFF Forced LOW Reset HIGH
Terminated by Low-Battery Fault (Note 1) >BAT <2.5V/Cell OFF HIGH >T/4 Stopped HIGH

Top-Off Charging. C/10 is Latched >BAT V

Timer is Reset by C/10 Comparator (Latched), >BAT V
then Terminates After 1/4 T Comparator Trip. (Waiting

Terminated by Expired Timer >BAT V

Timer Defeated. (Low-Battery Conditioning Still X X X X X Forced LOW
Functional)

Shut Down by Undervoltage Lockout >BAT <UVL OFF HIGH Reset HIGH**

Timer Defeated Until V

*Open Drain. High when used with pull-up resistor.
**Most probable condition, X = Don’t care

> 3.9V/Cell >BAT 2.5V ≤ V

BAT

and <UVL

FLOAT

FLOAT

** OFF HIGH >T Stopped HIGH

FLOAT

≤3.9V Programmed HIGH Running LOW

BAT

(V/Cell) Current

Note 1: If a depleted battery is inserted while the charger is in this state,
the charger must be reset to initiate charging.

Current

Current

(Faulted)

(Faulted)

OFF HIGH <T/4 After C/10 25µA

Comparator Trip.

Running

OFF HIGH >T/4 After C/10 HIGH

Stopped for Restart)

(Waiting

for Restart)

compares this current against the desired current programmed
by R

IMON

V

R

IMON

REF

at the I

VV Ak

=

pin and adjusts ITH until:

MON

–.•11 67 3

CSP BAT

+µΩ

k

Ω

3

therefore,

I

CHARGE

⎛

V

REF

=µ

⎜
⎝

R

–. •11 67

IMON SENSE

⎞

A

⎟
⎠

Ω

3

k

R

The voltage at BAT is divided down by an internal resistor
divider and is used by error amp EA to decrease ITH if the
divider voltage is above the 1.19V reference. When the
charging current begins to decrease, the voltage at I
will decrease in direct proportion. The voltage at I

MON

MON

is

then given by:

R

VI R Ak

=+µΩ

IMON CHARGE SENSE

()

•.••11 67 3

IMON

k

Ω

3

The accuracy of V

V

is plotted in Figure 2.

IMON

will range from 0% to I

IMON

TOL

.

The amplifier CL1 monitors and limits the input current to
a preset level (100mV/R
decrease the I

voltage, thereby reducing charging cur-

TH

). At input current limit, CL1 will

CL

rent. When this condition is detected, the C/10 indicator will

(V)

IMON

V

1.2

1.0

0.8

0.6

0.4

0.2

0

0

0.309V

20 40 60 80 100

I

(% OF MAXIMUM CURRENT)

CHARGE

Figure 2. V

IMON

1.19V

vs I

4006 F02

CHARGE

4006fa

9

LTC4006

MASTER

SHUTDOWN

1

2

ANY

SHUTDOWN

4

CONDITION

11

13

3, 18, 19,
20, 21, 22

3, 8,

9, 10

5,
6,

7

CHARGE

12, 14, 15, 16, 17

4006 F15

U

OPERATIO

Table 2. Truth Table for LTC4006 Operation (Supplemental)

NUMBER STATE STATE MODE DCIN VOLTAGE LATCH LATCH CURRENT ACP/SHDN STATE CHG*

Note 1: If a depleted battery is inserted while the charger is in this state,

the charger must be reset to initiate charging.

Note 2: See section on “Adapter Limiting”.
Note 3: The information contained in this table is supplemental to the

LTC4006 data sheet and has not been production qualified.
Note 4: Blank fields indicate no change, not considered, or other states

impact value.
*Open Drain. High when used with pull-up resistor.
** Most probable condition.

FROM TO BAT PRESENT C/10 NEXT C/10 MAX BAT TIMER

1 Any MSD Shut Down by Low Adapter Voltage <BAT 0 OFF LOW Reset HIGH

2 MSD SD Charge Shutdown >BAT 0 OFF HIGH Reset HIGH

3 SD, SD Shut Down by Undervoltage Lockout >BAT OFF HIGH Reset HIGH**

CONDITION, and

CHARGE <UVL

4 SD CONDITION Start Conditioning a Depleted Battery >BAT <2.5V/Cell 10% Programmed HIGH LOW

5 CONDITION CONDITION Input Current Limited Condition Charging >BAT <2.5V/Cell <10% Programmed HIGH Running LOW

6 CONDITION CONDITION Conditioning a Depleted Battery >BAT <2.5V/Cell 10% Programmed HIGH Running LOW

7 CONDITION CONDITION Timer Defeated. (Low-Battery Conditioning Still >BAT <2.5V/Cell 10% Programmed HIGH Ignored Forced LOW

8 CONDITION SD Charger Paused Due to Thermistor Out of Range >BAT <2.5V/Cell OFF HIGH Paused LOW

9 CONDITION SD Timeout in CONDITION Mode >BAT <2.5V/Cell OFF HIGH >T/4 HIGH

10 CONDITION SD Shut Down by ACP/SHDN Pin >BAT <2.5V/Cell 0 OFF Forced LOW Reset HIGH

11 CONDITION CHARGE Start Normal Charging >BAT >2.5V/Cell Programmed HIGH Running

12 CHARGE CHARGE Timer Defeated. (Low-Battery Conditioning Still >BAT >2.5V/Cell Programmed HIGH Ignored Forced LOW

13 SD CHARGE Restart >BAT 2.5V ≤ V

14 CHARGE CHARGE Top-Off Charging >BAT >3.9V/Cell 0 Programmed HIGH Running LOW

15 CHARGE CHARGE C/10 Latch is SET when Battery Current is Less >BAT >2.5V/Cell 1 Programmed HIGH Reset 25µA

16 CHARGE CHARGE Top-Off Charging >BAT >3.9V/Cell 1 Programmed HIGH Running 25µA

17 CHARGE CHARGE Input Current Limited Charging >BAT >2.5V/Cell <Programmed HIGH

18 CHARGE SD Charger Paused Due to Thermistor Out of Range >BAT >2.5V/Cell OFF HIGH Paused LOW or 25µA

19 CHARGE SD Shut Down by ACP/SHDN Pin >BAT >2.5V/Cell 0 OFF Forced LOW Reset HIGH

20 CHARGE SD Terminated by Low-Battery Fault (Note 1) >BAT <2.5V/Cell 0 OFF HIGH >T/4 then Reset HIGH

21 CHARGE SD Terminates After 1/4 T >BAT V

22 CHARGE SD Terminates After T >BAT V

Functional) Current

Functional) Current

≤ 3.9V 0 Programmed HIGH Reset

BAT

(V/Cell) Current

Than 10% of Programmed Current Current

FLOAT

** 0 OFF HIGH >T/4 then Reset HIGH

FLOAT

1 OFF HIGH >T/4 then Reset HIGH

Current

Current (Note 2)

Current

Current

Current

Current

Current (Note 2)

LTC4006: State Diagram (Supplemental)

(Faulted)

(Faulted)

(Faulted)

(Faulted)

10

4006fa

OPERATIO

LTC4006

U

be inhibited if it is not already active. If the charging current
decreases below 10% to 15% of programmed current,
while engaged in input current limiting, BGATE will be
forced low to prevent the charger from discharging the
battery. Audible noise can occur in this mode of operation.

An overvoltage comparator guards against voltage tran­sient overshoots (>7% of programmed value). In this
case, both MOSFETs are turned off until the overvoltage
condition is cleared. This feature is useful for batteries
which “load dump” themselves by opening their protec­tion switch to perform functions such as calibration or
pulse mode charging.

As the voltage at BAT increases to near the input voltage
at DCIN, the converter will attempt to turn on the top
MOSFET continuously (“dropout’’). A watchdog timer
detects this condition and forces the top MOSFET to turn
off for about 300ns at 40µs intervals. This is done to
prevent audible noise when using ceramic capacitors at
the input and output.

Charger Startup

When the charger is enabled, it will not begin switching
until the I

voltage exceeds a threshold that assures initial

TH

current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation but is typically less than 100µs.

Thermistor Detection

The thermistor detection circuit is shown in Figure 3. It requires
an external resistor and capacitor in order to function properly.

The thermistor detector performs a sample-and-hold func­tion. An internal clock, whose frequency is determined by
the timing resistor connected to R

, keeps switch S1

T

closed to sample the thermistor:

t

SAMPLE

for R

= 127.5 • 20 • RRT • 17.5pF = 13.8ms,

= 309k

RT

The external RC network is driven to approximately 4.5V
and settles to a final value across the thermistor of:

.•

VR

TH

TH

+459

V

()

RTH FINAL

=

RR

R

10k

NTC

LTC4006

R9

32.4k

NTC

TH

C7

0.47µF

6

S1

DCQ

Figure 3

–

~4.5V

+

+

–

–

+

60k

45k

15k

4006 F03

CLK

T

BAD

This voltage is stored by C7. Then the switch is opened for a
short period of time to read the voltage across the thermistor.

= 10 • R

t

HOLD

for R

RT

When the t

= 309k

HOLD

• 17.5pF = 54µs,

RT

interval ends the result of the thermistor
testing is stored in the D flip-flop (DFF). If the voltage at
NTC is within the limits provided by the resistor divider
feeding the comparators, then the NOR gate output will be
low and the DFF will set T

to zero and charging will

BAD

continue. If the voltage at NTC is outside of the resistor
divider limits, then the DFF will set T

to one, the charger

BAD

will be shut down, and the timer will be suspended until
T

returns to zero (see Figure 4).

BAD

CLK

(NOT TO

SCALE)

VOLTAGE ACROSS THERMISTOR

V

NTC

Figure 4

t

SAMPLE

t

HOLD

COMPARATOR HIGH LIMIT

COMPARATOR LOW LIMIT

4006 F04

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11

LTC4006

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APPLICATIO S I FOR ATIO

Charger Current Programming

The basic formula for charging current is:

mV

I

CHARGE MAX

()

Table 3. Recommended R

I

(A) R

MAX

1.0 0.100 0.25

2.0 0.050 0.25

3.0 0.033 0.5

4.0 0.025 0.5

=

100
R

SENSE

Resistor Values

SENSE

(Ω) 1% R

SENSE

SENSE

(W)

Setting the Timer Resistor

The charger termination timer is designed for a range of 1
hour to 3 hours with a ±15% uncertainty. The timer is
programmed by the resistor R

using the following

RT

equation:

t

TIMER

= 10 • 2

27

• R

• 17.5pF (Refer to Figure 5)

RT

(seconds)

It is important to keep the parasitic capacitance on the R

T

pin to a minimum. The trace connecting RT to RRT should
be as short as possible.

Alternatively, a normally closed switch can be used to
detect when the battery is present (see Figure 8).

200

180

160

140

120

100

(MINUTES)

80

TIMER

t

60

40

20

0

100

150 250

LTC4006

200

Figure 5. t

CHG

2

300

RRT (kΩ)

3.3V

200k

350

TIMER

33k

Figure 6. Microprocessor Interface

400

vs R

RT

OUT
IN

450

V

µP

500

4006 F05

DD

4006 F06

CHG Status Output Pin

When the charge cycle starts, the CHG pin is pulled down
to ground by an internal N-channel MOSFET that can drive
more than 100µA. When the charge current drops to 10%
of the full-scale current (C/10), the N-channel MOSFET is
turned off and a weak 25µA current source to ground is
connected to the CHG pin. After a time out occurs, the pin
will go into a high impedance state. By using two different
value pull-up resistors, a microprocessor can detect three
states from this pin (charging, C/10 and stop charging).
See Figure 6.

Battery Detection

It is generally not good practice to connect a battery while
the charger is running. The timer is in an unknown state
and the charger could provide a large surge current into
the battery for a brief time. The circuit shown in Figure 7
keeps the charger shut down and the timer reset while a
battery is not connected.

ADAPTER

POWER

SWITCH CLOSED IF

BATTERY CONNECTED

ADAPTER

POWER

SWITCH OPEN WHEN

BATTERY CONNECTED

470k

Figure 7

Figure 8

DCIN

1

ACP/SHDN

3

DCIN

1

ACP/SHDN

3

LTC4006

LTC4006

4006 F07

4006 F08

4006fa

12

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APPLICATIO S I FOR ATIO

LTC4006

Soft-Start

The LTC4006 is soft started by the 0.12µF capacitor on the
I

pin. On start-up, ITH pin voltage will rise quickly to 0.5V,

TH

then ramp up at a rate set by the internal 40µA pull-up
current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with I

at 2V. With a 0.12µF

TH

capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.

Input and Output Capacitors

The input capacitor (C2) is assumed to absorb all input
switching ripple current in the converter, so it must have
adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging current.
Actual capacitance value is not critical. Solid tantalum low
ESR capacitors have high ripple current rating in a rela­tively small surface mount package,

but caution must be
used when tantalum capacitors are used for input or
output bypass

. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capaci­tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.

I

RMS

V

BAT

Lf

()()

⎛
⎜

⎝

1

029 1

.–

()

=

V

V

DCIN

BAT

⎞
⎟

⎠

For example:

= 19V, V

V

DCIN

f = 300kHz, I

= 12.6V, L1 = 10µH, and

BAT

= 0.41A.

RMS

EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the 300kHz
switching frequency. Switching ripple current splits be­tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance.
If the ESR of C3

is 0.2Ω and the battery impedance is

raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.

Inductor Selection

Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener­ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆I
with higher frequency and increases with higher V

I

∆ =

L OUT

1

fL

()( )

⎛

V

1–

⎜
⎝

V

OUT

V

IN

⎞
⎟

⎠

decreases

L

.

IN

The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to Appli­cation Note 88 for more information.

Highest possible voltage rating on the capacitor will mini­mize problems. Consult with the manufacturer before use.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. Other
alternative capacitors include OS-CON capacitors from
Sanyo.

The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:

Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(I
∆I

exceed 0.6(I

L

) due to limits imposed by I

MAX

CA1. Remember the maximum ∆I

). In no case should

MAX

REV

occurs at the maxi-

L

and

mum input voltage. In practice 10µH is the lowest value
recommended for use.

Lower charger currents generally call for larger inductor
values. Use Table 4 as a guide for selecting the correct
inductor value for your application.

4006fa

13

LTC4006

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APPLICATIO S I FOR ATIO

Table 4

MAXIMUM INPUT MINIMUM INDUCTOR

AVERAGE CURRENT (A) VOLTAGE (V) VALUE (µH)

1 ≤20 40 ±20%

1 > 20 56 ± 20%
2 ≤20 20 ±20%

2 > 20 30 ± 20%
3 ≤20 15 ±20%

3 > 20 20 ± 20%
4 ≤20 10 ±20%

4 > 20 15 ± 20%

Charger Switching Power MOSFET
and Diode Selection

Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn­chronous) switch.

The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BV

DSS

specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R
transfer capacitance C

, total gate capacitance QG, reverse

DS(ON)

, input voltage and maximum

RSS

output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:

Main Switch Duty Cycle = V

Synchronous Switch Duty Cycle = (VIN – V

OUT/VIN

OUT

)/VIN.

The MOSFET power dissipations at maximum output
current are given by:

PMAIN = V

OUT/VIN

+ k(V

PSYNC = (VIN – V

Where δ is the temperature dependency of R

2

(I

)(1 + δ∆T)R

MAX

2

)(I

)(C

IN

MAX

OUT

)/VIN(I

RSS

2

MAX

DS(ON)

)(f

)

OSC

)(1 + δ∆T)R

DS(ON)

DS(ON)

and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I

2

R losses while the PMAIN equation

includes an additional term for transition losses, which are

highest at high input voltages. For V

< 20V the high

IN

current efficiency generally improves with larger MOSFETs,
while for V
to the point that the use of a higher R
lower C

> 20V the transition losses rapidly increase

IN

device with

DS(ON)

actually provides higher efficiency. The syn-

RSS

chronous MOSFET losses are greatest at high input volt­age or during a short circuit when the duty cycle in this
switch is nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized R

DS(ON)

vs

temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs. C
specified in the MOSFET characteristics; if not, then C
can be calculated using C

= QGD/∆VDS. The constant

RSS

is usually

RSS

RSS

k = 2 can be used to estimate the contributions of the two
terms in the main switch dissipation equation.

If the charger is to operate in low dropout mode or with a
high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.

The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.

The diode may be omitted if the efficiency loss can be
tolerated.

Calculating IC Power Dissipation

The power dissipation of the LTC4006 is dependent upon
the gate charge of the top and bottom MOSFETs (Q

respectively). The gate charge is determined from the

Q

G2

G1

and

manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and V

DCIN

for

the drain voltage swing.

PD = V

DCIN

• (f

(QG1 + QG2) + I

OSC

DCIN

)

14

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APPLICATIO S I FOR ATIO

LTC4006

Example:

V

DCIN

= 19V, f

= 345kHz, QG1 = QG2 = 15nC.

OSC

PD = 292mW

= 5mA

I

DCIN

Adapter Limiting

An important feature of the LTC4006 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod­uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.

This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed-loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across R

LTC4006

=

*R

CL

ADAPTER CURRENT LIMIT

100mV

–

CL1

+

100mV

Figure 9. Adapter Current Limiting

CLP

+

11

12

CLN

15nF

+

C

IN

5k

RCL*

TO SYSTEM
LOAD

CL

AC ADAPTER

, connected

INPUT

V

IN

4006 F09

between the CLP and DCIN pins. When this voltage ex­ceeds 100mV, the amplifier will override programmed
charging current to limit adapter current to 100mV/R

CL

. A

lowpass filter formed by 5kΩ and 15nF is required to
eliminate switching noise. If the current limit is not used,
CLP should be connected to CLN.

Setting Input Current Limit

To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
input current limit tolerance and use that current to deter­mine the resistor value.

R

= 100mV/I

CL

I

= Adapter Min Current –

LIM

LIM

(Adapter Min Current • 7%)

As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Figure 9).

Designing the Thermistor Network

There are several networks that will yield the desired
function of voltage vs temperature needed for proper
operation of the thermistor. The simplest of these is the
voltage divider shown in Figure 10. Unfortunately, since
the HIGH/LOW comparator thresholds are fixed internally,
there is only one thermistor type that can be used in this
network; the thermistor must have a HIGH/LOW resis­tance ratio of 1:7. If this happy circumstance is true for

Table 5. Common RCL Resistor Values

ADAPTER –7% ADAPTER RCL VALUE* R

RATING (A) RATING (A) (Ω) 1% LIMIT (A) DISSIPATION (W) RATING (W)

1.5 1.40 0.068 1.47 0.15 0.25

1.8 1.67 0.062 1.61 0.16 0.25

2.0 1.86 0.051 1.96 0.20 0.25

2.3 2.14 0.047 2.13 0.21 0.25

2.5 2.33 0.043 2.33 0.23 0.50

2.7 2.51 0.039 2.56 0.26 0.50

3.0 2.79 0.036 2.79 0.28 0.50

3.3 3.07 0.033 3.07 0.31 0.50

3.6 3.35 0.030 3.35 0.33 0.50

4.0 3.72 0.027 3.72 0.37 0.50

* Rounded to nearest 5% standard step value. Many non-standard values are popular.

CL

RCL POWER RCL POWER

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APPLICATIO S I FOR ATIO

LTC4006

NTC

Figure 10. Voltage Divider Thermistor Network Figure 11. General Thermistor Network

you, then simply set R9 = R

6

R9

TH(LOW)

C7 R

4006 F10

TH

If you are using a thermistor that doesn’t have a 1:7 HIGH/
LOW ratio, or you wish to set the HIGH/LOW limits to
different temperatures, then the more generic network in
Figure 11 should work.

Once the thermistor, R

, has been selected and the

TH

thermistor value is known at the temperature limits, then
resistors R9 and R9A are given by:

For NTC thermistors:

R9 = 6 R

R9A = 6 R
where R

TH(LOW)

TH(LOW)

TH(LOW)

• R

TH(HIGH)

• R

TH(HIGH)

> 7 • R

/(R

/(R

TH(HIGH)

TH(LOW)

TH(LOW)

– R

TH(HIGH)

– 7 • R

)

TH(HIGH)

)

For PTC thermistors:

R9 = 6 R

R9A = 6 R
where R

TH(HIGH)

TH(LOW)

TH(LOW)

• R

• R

> 7R

TH(HIGH)

TH(HIGH)

TH(LOW)

/(R

TH(HIGH)

/(R

TH(HIGH)

– R

TH(LOW)

– 7 • R

)

TH(LOW)

)

Example #1: 10kΩ NTC with custom limits

TLOW = 0°C, THIGH = 50°C
RTH = 10k at 25°C,
R

TH(LOW)

R

TH(HIGH)

= 32.582k at 0°C

= 3.635k at 50°C

R9 = 24.55k → 24.3k (nearest 1% value)
R9A = 99.6k → 100k (nearest 1% value)

Example #2: 100kΩ NTC

LTC4006

NTC

R9

6

C7 R9A R

TH

4006 F11

RTH= 22k at 25°C,
R

TH(LOW)

R

TH(HIGH)

= 6.53k at 0°C

= 61.4k at 50°C

R9 = 43.9k → 44.2k (nearest 1% value)
R9A = 154k

Sizing the Thermistor Hold Capacitor

During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of C7
is given by:

C7 = t

= 10 • R

/(R9/7 • –ln(1 – 8 • 15mV/4.5V))

HOLD

• 17.5pF/(R9/7 • –ln(1 – 8 • 15mV/4.5V)

RT

Example:

R9 = 24.3k

= 309k (~2 hour timer)

R

RT

C7 = 0.57µF → 0.56µF (nearest value)

Disabling the Thermistor Function

If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
be sized to provide at least 10µA with the minimum voltage
applied to DCIN and 10V at NTC. Do not exceed 30µA into
NTC. Generally, a 301k resistor will work for DCIN less
than 15V. A 499k resistor is recommended for DCIN
between 15V and 24V.

TLOW = 5°C, THIGH = 50°C

= 100k at 25°C,

R

TH

R

TH(LOW)

R

TH(HIGH)

= 272.05k at 5°C

= 33.195k at 50°C

R9 = 226.9k → 226k (nearest 1% value)
R9A = 1.365M → 1.37M (nearest 1% value)

Example #3: 22kΩ PTC

TLOW = 0°C, THIGH = 50°C

16

Optional Simple Battery Discharge Path Circuit

It is NOT recommended that one permit battery current to
flow backwards through R
TGATE MOSFET internal diode to reach V
MOSFET is off when VIN < V

, inductor and out the

SENSE

. The TGATE

OUT

. Figure 12 shows an op-

BAT

tional high efficiency discharge path for the battery such that
V

power comes from lossless “diode or” of VIN and V

OUT

Normally when VIN > V

, P-channel MOSFET Q1B VGS =

BAT

BAT

4006fa

.

WUUU

4006 F13

V

BAT

L1

V

IN

HIGH

FREQUENCY

CIRCULATING

PATH

BAT

SWITCH NODE

C2

C3

D1

APPLICATIO S I FOR ATIO

LTC4006

TGATE

100k

INDUCTOR R

ZENER

18V

SENSE

4006 F12

Q1B

V

OUT

V

BAT

V

IN

Q1A

Figure 12. Optional Simple High
Efficiency Battery Discharge Path

0V keeping Q1B in the off state while P-channel MOSFET
Q1A is on. If V

were to suddenly go away, Q1B internal

IN

diode will provide a passive but instant discharge path for
battery current to reach V

and hold up the load. Q1B

OUT

internal diode has the same current rating as the FET itself,
but has a very high V
quickly build up in Q1B if left alone. However as V
falls below V

BAT

of about a volt such that heat will

f

’s voltage

IN

by Q1B’s VGS threshold, Q1B will then turn
on shorting out its internal diode removing both the heat
and voltage losses created by the diode. When V

falls to

IN

zero volts, Q1B gate will be driven to the same voltage as

providing the lowest possible RDSON value. A zener

V

BAT

diode along with a 100k resistor in series with the Q1B gate
protects the gate from any hazardous voltage spikes that
can exceed Q1B maximum permissible VGS voltage. The
zener voltage rating must be less than Q1B V
age but greater than V

BAT

.

GS(MAX)

volt-

Since Q1A and Q1B are always at opposite states and share
the same load, it is often advantagous to combine both FETs
into a single package and save PCB space. The P

rate of

D

the FET that is on is enhanced when the other FET is off. The
choice of a combined Q1 should take into account the high­est load current conditions of both paths and choose
whichever is greater as the driving force behind the MOSFET

selection. If the V

supply is going to collapse very slowly

IN

such that Q1B is not turned on quickly enough for the given
load and stay within its P

limits, you should install a suit-

D

able Schottky diode in parallel with Q1B.

PCB Layout Considerations

For maximum efficiency, the switch node rise and fall times
should be minimized. To prevent magnetic and electrical
field radiation and high frequency resonant problems,
proper layout of the components connected to the IC is
essential. (See Figure 13.) Here is a PCB layout priority list
for proper layout. Layout the PCB using this specific order.

1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.

2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con­nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.

3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.

Figure 13. High Speed Switching Path

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17

LTC4006

WUUU

APPLICATIO S I FOR ATIO

4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.

5. Place output capacitors next to the sense resistor
output and ground.

6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.

General Rules

7. Connection of switching ground to system ground or
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.

8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to
any other ground. Avoid using the system ground
plane. CAD trick: make analog ground a separate
ground net and use a 0Ω resistor to tie analog ground
to system ground.

9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.

10. If possible, place all the parts listed above on the same
PCB layer.

11. Copper fills or pours are good for all power connec­tions except as noted above in Rule 3. You can also use
copper planes on multiple layers in parallel too—this
helps with thermal management and lower trace in­ductance improving EMI performance further.

12. For best current programming accuracy provide a
Kelvin connection from R

to CSP and BAT. See

SENSE

Figure 13 as an example.

It is important to keep the parasitic capacitance on the RT,
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.

DIRECTION OF CHARGING CURRENT

R

SNS

4006 F14

CSP

Figure 14. Kelvin Sensing of Charging Current

BAT

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18

PACKAGE DESCRIPTION

LTC4006

U

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045

±

.005

.254 MIN

±

.0015

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

INCHES

(MILLIMETERS)

.150 – .165

.0250 BSC.0165

.015 ± .004

(0.38

0° – 8° TYP

± 0.10)

.189 – .196*

(4.801 – 4.978)

16

15

.229 – .244

(5.817 – 6.198)

12

×

45

°

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

12 11 10

14

13

4

3

5

9

678

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.150 – .157**

(3.810 – 3.988)

.004 – .0098

GN16 (SSOP) 0204

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4006fa

19

LTC4006

TYPICAL APPLICATIO

U

2A Li-Ion Battery Charger

Q3

INPUT SWITCH

16

11

12

13

15

14

9

10

R1

5k

C4
15nF

R

CL

0.04Ω

Q1

Q2

TO SYSTEM LOAD

C2
20µF

22µH 2A

D1

L1

D1: MBRM140T3
Q1, Q2: Si7501DN
Q3: Si5435B

R

SENSE

0.05Ω

4006 TA02

C3
20µF

BATTERY

CURRENT MONITOR

THERMISTOR

10k

NTC

DCIN

0V TO 20V

2.5A

V

LOGIC

CHG

ACP

CHARGING

0.0047µF

C7

0.47µF

C5

R9 32.4k

309k

TIMING

RESISTOR

(~2 HOURS)

C1

0.1µF

R3
100k

R

T

6.04k
C6

0.12µF

1

DCIN

2

CHG

3

ACP/SHDN

8

I

MON

6

NTC

4

R

T

7

I

R4

TH

5

GND

LTC4006

INFET

CLP

CLN

TGATE

BGATE

PGND

CSP

BAT

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SENSE

NIMH and NiCd Batteries

, Power Good Output, 3.5V ≤ VIN ≤ 36V

OUT

3hr Charge Termination, I

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, Uses Smallest Components for

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20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

4006fa

LT 0506 REV A • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2003