LINEAR TECHNOLOGY LTC3876 Technical data

Dual DC/DC Controller for DDR Power with Differential V
Sensing and ±50mA V

Reference

TT

DDQ

Design Note 503

Ding Li

Introduction

The LTC®3876 is a complete DDR power solution,
compatible with DDR1, DDR2, DDR3 and DDR4 lower
voltage standards. The IC includes V
DC controllers and a precision linear V

and VTT DC/

DDQ

reference.

TT

A differential output sense amplifi er and precision
internal reference combine to offer an accurate V
supply. The V

controller tracks the precision VTTR

TT

linear reference with less than 20mV total error. The
precision VTTR reference maintains 1.2% regulation
accuracy, tracking one-half V

over temperature for

DDQ

a ±50mA reference load.

The LTC3876 features controlled on-time, valley cur­rent mode control, allowing it to accept a wide 4.5V to
38V input range, while supporting V

1.0V to 2.5V, and V

and VTTR outputs from 0.5V to

TT

outputs from

DDQ

1.25V. Its phase-loc ked loop (PLL) can be synchr onized
to an external clock between 200kHz and 2MHz. It also
features voltage-tracking soft-start, PGOOD and fault
protection.

High Effi ciency, 4.5V to 14V Input, Dual Output
DDR Power Supply

Figure 1 shows a DDR3 power supply that operates
from a 4.5V to 14V input. Figure 2 shows effi ciency
curves for discon tinuous and forced continuous modes
of operation.

DDQ

Load-Release Transient Detection

As output voltages drop, a major challenge for switch­ing regulators is to limit the overshoot in V
a load-release transient. The LTC3876 uses the DTR
pin to monitor the fi rst derivative of the ITH voltage to
detect load release transients. Figure 3 shows how this
pin is used for transient detection.

The two R
INTV

CC

resistors establish a voltage divider from

ITH

to SGND, and bias the DC voltage on the DTR
pin (at steady-state load or ITH voltage) slightly above
half of INTV

L, LT, LTC, LTM, Linear Technology, the Linear logo and OPTI-LOOP are registered
trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners.

. For a given C

CC

, this divider does not

ITH1

OUT

during

V

IN

4.5V TO
14V

C

IN1

180μF

w2

1.5V,
20A

VDDQ

C

OUT1

100μF

06/12/503

0.1μF

15k

MT1

3.57k

L1, 0.47μH

C

OUT2

330μF
w2

30.1k

20k

MB1

Figure 1. 1.5V V

0.1μF

V

IN

LTC3876

–

SENSE1

+

SENSE1

BOOST1

TG1

SW1

DB1

DRV

CC1

INTV

CC

4.7μF

1μF

BG1

PGND

V

OUTSENSE1

V

100k

15k

DDQ

OUTSENSE1

PGOOD

PGOOD

0.1μF
TRACK/SS1

1000pF

ITH1

100k

RT

SGND

/20A 0.75V VTT/10A DDR3 Power Supply

SENSE2

SENSE2

+

VTTRV CC

–

BOOST2

TG2

SW2

DRV

BG2

VTTSNS

VTTR

ITH2

RUN

–

+

DB2

CC2

1000pF

0.1μF

15k

MT2

MB2

1μF

2.2μF

0.1μF

15k

3.57k

L2, 0.47μH VTT

C

OUT4

330μF

VTTR
±50mA

dn503 F01

0.75V
±10A

C

OUT3

100μF

95

90

85

80

75

70

EFFICIENCY (%)

65

60

55

48

014

6101612 20

218

OUTPUT CURRENT (A)

VIN = 12V, DCM

= 12V, CCM

V

IN

= 5V, DCM

V

IN

= 5V, CCM

V

IN

dn503 F02

Figure 2. Effi ciency of Circuit
in Figure 1 (V

= 400kHz, L = 470nH)

f

SW

DDQ

= 1.5V,

ITH DTR

1/2 INTV

CC

INTV

V

CC

+

LOAD

RELEASE

DETECTION

TO LOGIC
CONTROL

–

LOAD

CURRENT

10A/DIV

V

OUT

100mV/DIV

SW

5V/DIV

= 12V, VDDQ = 1.5V,

IN

= 0A TO 15A

I

O

INTV

CC

C

R

ITH1

ITH2

R

ITH1

C

ITH2

dn503 F03

Figure 3. Functional Diagram of DTR Connection for
Load Transient Detection

change compensation performance as long as R

equals R

R

ITH2

ventional single-resistor OPTI-LOOP

that would normally be used in con-

ITH

®

compensation.

ITH1

The divider sets the RC time constant needed for the
DTR duration. The DTR sensitivity can be adjusted by
the DC bias voltage difference between DTR and half
INTV

. This difference could be set as low as 100mV,

CC

as long as the ITH ripple voltage with DC load current
does not trigger the DTR. If the load transient is fast
enough that the DTR volt age drops below half of INT V

CC

a load release event is detected. The bottom gate (BG)
is turned off, so that the inductor current fl ows through
the body diode in the bottom MOSFET.

Note that the DTR feature causes additional losses on
the bottom MOSFET, due to its body diode conduction.
The bottom FET temperature may be higher with a load
of frequent and large load steps—an important design
consideration. Test results show a 20°C increase when
a continuous 100%-to-50% load step pulse chain with
50% duty cycle and 100kHz frequency is applied to
the output.

VTT Reference (VTTR)

The linear VTT reference, VTTR, is specifi cally designed
for large DDR memory systems by providing superior
accuracy and load regulation for up to ±50mA output
load. VT TR is the buffered output of the V

differential

TT

reference resistor divider. VTTR is a high output linear
reference, which tracks the V

differential reference

TT

resistor divider and equals half of the remote-sense

voltage.

V

DDQ

Connect V TTR directly to the DDR memor y VREF input.
Both input and output supply decoupling are important
to performance and accuracy. A 2.2μF output capaci-

Data Sheet Download

www.linear.com

V

OVS

= 127.5mV

dn503 F04a

a. LTC3876 DTR Disabled

V

V

OVS

= 12V, VDDQ = 1.5V,

IN

= 0A TO 15A

I

O

= 115mV

dn503 F04b

LOAD

CURRENT

10A/DIV

V

OUT

100mV/DIV

/

SW

5V/DIV

b. LTC3876 DTR Enabled

Figure 4. Load Release Comparison

tor is recommended for most typical applications. It is
suggested to use no less than 1μF and no more than
47μF on the VTTR output. The VTTR power comes

,

from the V TTRVCC pin. The t ypical recommended input
VTTRVCC RC decoupling fi lter is 2.2μF and 1Ω. When
VDDQSNS is tied to INTVCC, the VTTR linear reference
output is 3-stated and V TTR becomes a reference input
pin, with voltage from another LTC3876 in a multiphase
application.

VTT Supply

The VTT supply reference is connected internally to
the output of the VTTR V

reference output. The VTT

TT

supply opera tes in forced con tinuous mode and tracks

in start-up and in normal operation regardless of

V

DDQ

the MODE/ PLLIN settings. In star t-up, the V
enabled coincident with the V

suppl y in for ced continuous mode allows accur ate

V

TT

supply. Operating the

DDQ

supply is

TT

tracking in start-up and under all operating conditions.

Conclusion

The LTC3876 is a complete high effi ciency and high
accuracy solut ion for DDR memory power supplie s. The
unique controlled on-time architecture allows extremely
low step-down r atios while maintaining a fast, constant
switching frequency. The wide input voltage range of

4.5V–38V and pr ogrammable, synchronizable sw itching
frequency from 200kHz to 2MHz gives designers the
fl exibility needed to optimize their systems.

For applications help,

call [phone], Ext. 3598

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone]

●

FAX: [phone] ● www.linear.com

dn503f LT/AP 0612 196K • PRINTED IN THE USA

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