LINEAR TECHNOLOGY LTC3862 Technical data

LTC3862

Multi-Phase Current Mode

Step-Up DC/DC Controller

FEATURES

n

Wide VIN Range: 4V to 36V Operation

n

2-Phase Operation Reduces Input and Output

Capacitance

n

Fixed Frequency, Peak Current Mode Control

n

5V Gate Drive for Logic-Level MOSFETs

n

Adjustable Slope Compensation Gain

n

Adjustable Max Duty Cycle (Up to 96%)

n

Adjustable Leading Edge Blanking

n

±1% Internal Voltage Reference

n

Programmable Operating Frequency with One

External Resistor (75kHz to 500kHz)

n

Phase-Lockable Fixed Frequency 50kHz to 650kHz

n

SYNC Input and CLKOUT for 2-, 3-, 4-, 6- or

12-Phase Operation (PHASEMODE Programmable)

n

Internal 5V LDO Regulator

n

24-Lead Narrow SSOP Package

n

5mm × 5mm QFN with 0.65mm Lead Pitch and

24-Lead Thermally Enhanced TSSOP Packages

APPLICATIONS

n

Automotive, Telecom and Industrial Power Supplies

DESCRIPTION

The LTC®3862 is a two phase constant frequency, current
mode boost and SEPIC controller that drives N-channel
power MOSFETs. Two phase operation reduces system
fi ltering capacitance and inductance requirements. The 5V
gate drive is optimized for most automotive and industrial
grade power MOSFETs.

Adjustable slope compensation gain allows the user to fi ne­tune the current loop gain, improving noise immunity.

The operating frequency can be set with an external resistor
over a 75kHz to 500kHz range and can be synchronized
to an external clock using the internal PLL. Multi-phase
operation is possible using the SYNC input, the CLKOUT
output and the PHASEMODE control pin allowing 2-, 3-,
4-, 6- or 12-phase operation.

Other features include an internal 5V LDO with undervoltage
lockout protection for the gate drivers, a precision RUN
pin threshold with programmable hysteresis, soft-start
and programmable leading edge blanking and maximum
duty cycle

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 6144194, 6498466, 6611131.

TYPICAL APPLICATION

84.5k

RUN

INTV

CC

BLANK
FREQ
SYNC
PLLFLTR

SS

3V8

FB

ITH

V

IN

LTC3862

PHASEMODE
SGND

475k 12.4k

68.1k

4.7µF

10nF

10nF

24.9k

66.5k

10k

10nF

1nF

100pF

GATE1

SENSE1

SENSE1

GATE2

SENSE2

SENSE2

PGND

CLKOUT

SLOPE

D

MAX

V

IN

5V TO 36V

19.4µH 19.4µH

+

220µF

0.006

–

+

–

50V

0.006

22µF
50V

3862 TA01

V

OUT

48V
5A (MAX)

Effi ciency vs Output Current

98

V

= 48V

OUT

96

94

92

90

88

EFFICIENCY (%)

86

84

82

80

100

VIN = 12V

VIN = 24V

VIN = 5V

1000 10000

LOAD CURRENT (mA)

3862 TA01b

3862fa

1

LTC3862

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Input Supply Voltage (VIN) ......................... –0.3V to 40V

INTV
INTV

Voltage ............................................ –0.3V to 6V

CC

LDO RMS Output Current .........................50mA

CC

RUN Voltage ................................................ –0.3V to 8V

SYNC Voltage ............................................... –0.3V to 6V

SLOPE, PHASEMODE, D

MAX

,

BLANK Voltage ........................................... –0.3V to 3V8

+

SENSE1
SENSE2

, SENSE1–, SENSE2+,

–

Voltage ....................................... –0.3V to 3V8

SS, PLLFLTR Voltage ................................. –0.3V to 3V8

PIN CONFIGURATION

TOP VIEW

1

D

MAX

2

SLOPE

3

BLANK

PHASEMODE

CLKOUT

PLLFLTR

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

4

5

FREQ

6

SS

7

ITH

8

FB

9

SGND

10

11

SYNC

12

FE PACKAGE

24-LEAD PLASTIC TSSOP

T

= 150°C, θJA = 38°C/W

JMAX

25

24

23

22

21

20

19

18

17

16

15

14

13

3V8

SENSE1

SENSE1

RUN

V

IN

INTV

CC

GATE1

PGND

GATE2

NC

SENSE2

SENSE2

+

–

–

+

D

MAX

SLOPE

BLANK

PHASEMODE

FREQ

SS

ITH

FB

SGND

CLKOUT

SYNC

PLLFLTR

24-LEAD NARROW PLASTIC SSOP

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

GN PACKAGE

T

= 150°C, θJA = 85°C/W

JMAX

ITH Voltage ............................................... –0.3V to 2.7V

FB Voltage .................................................. –0.3V to 3V8

FREQ Voltage ............................................ –0.3V to 1.5V

Operating Junction Temperature Range (Notes 3, 4)

LTC3862E ............................................. –40°C to 85°C

LTC3862I............................................ –40°C to 125°C

LTC3862H .......................................... –40°C to 150°C

Storage Temperature Range ................... –65°C to 150°C

Refl ow Peak Body Temperature ........................... 260°C

TOP VIEW

3V8

24

23

22

21

20

19

18

17

16

15

14

13

SENSE1

SENSE1

RUN

V

IN

INTV

CC

GATE1

PGND

GATE2

NC

SENSE2

SENSE2

+

–

PHASEMODE

FREQ

SS

ITH

FB

–

+

EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB

SLOPE

DMAX

3V8

SENSE1+SENSE1–RUN

24 23 22 21 20 19

1

2

3

4

5

6

24-LEAD (5mm s 5mm) PLASTIC QFN

T

JMAX

25

7 8 9

SGND

10 11 12

SYNC

CLKOUT

PLLFLTR

UH PACKAGE

= 150°C, θJA = 34°C/W

+

SENSE2

18BLANK

17

16

15

14

13

–

SENSE2

V

IN

INTV

GATE1

PGND

GATE2

NC

CC

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3862EFE#PBF LTC3862EFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 85°C
LTC3862IFE#PBF LTC3862IFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 125°C
LTC3862HFE#PBF LTC3862HFE#TRPBF 3862FE 24-Lead Plastic TSSOP –40°C to 150°C
LTC3862EGN#PBF LTC3862EGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 85°C
LTC3862IGN#PBF LTC3862IGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 125°C
LTC3862HGN#PBF LTC3862HGN#TRPBF LTC3862GN 24-Lead Plastic SSOP –40°C to 150°C
LTC3862EUH#PBF LTC3862EUH#TRPBF 3862
LTC3862IUH#PBF LTC3862IUH#TRPBF 3862
LTC3862HUH#PBF LTC3862HUH#TRPBF 3862

24-Lead (5mm × 5mm) Plastic QFN
24-Lead (5mm × 5mm) Plastic QFN
24-Lead (5mm × 5mm) Plastic QFN

–40°C to 85°C
–40°C to 125°C
–40°C to 150°C

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.

For more information on lead free part marking, go to:
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

http://www.linear.com/leadfree/

3862fa

2

LTC3862

ELECTRICAL CHARACTERISTICS

(Notes 2, 3) The l denotes the specifi cations which apply over the full
operating junction temperature range, otherwise specifi cations are at T
otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Input and INTV

V

IN

I

VIN

INTV

CC

dV

INTVCC(LINE)

dV

INTVCC(LOAD)

V

UVLO

3V8 LDO Regulator Output Voltage 3.8 V

Switcher Control Loop

V

FB

dV

/dV

FB

IN

dV

/dV

FB

ITH

g

m

f

0dB

V

ITH

I

ITH

I

FB

V

ITH(PSKIP)

I

SENSE(ON)

V

SENSE(MAX)

RUN/Soft-Start

I

RUN

V

RUN

V

RUNHYS

I

SS

R

SS

Oscillator

f

OSC

V

FREQ

f

SYNC

V

SYNC

Linear Regulator

CC

VIN Supply Voltage Range 4 36 V

VIN Supply Current
Normal Mode, No Switching
Shutdown

(Note 5)
V

= 0V

RUN

LDO Regulator Output Voltage 4.8 5.0 5.2 V

Line Regulation 6V < VIN < 36V 0.002 0.02 %/V

Load Regulation Load = 0mA to 20mA –2 %

INTVCC UVLO Voltage Rising INTV

Falling INTV

Reference Voltage V

= 0.8V (Note 6) E-Grade (Note 3)

ITH

I-Grade and H-Grade (Note 3)

Feedback Voltage VIN Line Regulation VIN = 4V to 36V (Note 6) ±0.002 0.01 %/V

Feedback Voltage Load Regulation V

Transconductance Amplifi er Gain V

Error Amplifi er Unity-Gain Crossover

= 0.5V to 1.2V (Note 6) 0.01 0.1 %

ITH

= 0.8V (Note 6), ITH Pin Load = ±5µA 660 µMho

ITH

(Note 7) 1.8 MHz

Frequency

Error Amplifi er Maximum Output Voltage

VFB = 1V, No Load 2.7 V

(Internally Clamped)

Error Amplifi er Minimum Output Voltage V

= 1.5V, No Load 50 mV

FB

Error Amplifi er Output Source Current –30 µA

Error Amplifi er Output Sink Current 30 µA

Error Amplifi er Input Bias Currents (Note 6) –50 –200 nA

Pulse Skip Mode Operation ITH Pin Voltage Rising ITH Voltage (Note 6)

Hysteresis

SENSE Pin Current 0.01 2 µA

Maximum Current Sense Input Threshold V

= Float, Low Duty Cycle

SLOPE

(Note 3)

RUN Source Current V

V

RUN
RUN

= 0V
= 1.5V

High Level RUN Channel Enable Threshold 1.22 V

RUN Threshold Hysteresis 80 mV

SS Pull-Up Current VSS = 0V –5 µA

SS Pull-Down Resistance V

Oscillator Frequency R

= 0V 10 k

RUN

= 45.6k

FREQ

R

= 45.6k

FREQ

Oscillator Frequency Range

Nominal FREQ Pin Voltage R

SYNC Minimum Input Frequency V

SYNC Maximum Input Frequency V

= 45.6k 1.223 V

FREQ

= External Clock

SYNC

= External Clock

SYNC

SYNC Input Threshold Rising Threshold 1.5 V

= 25°C. VIN = 12V, RUN = 2V and SS = open, unless

A

CC
CC

l
l

l

1.210

l

1.199

1.8
30

3.3

2.9

1.223

1.223

0.275
25

65

l

60

75
75

–0.5

–5

280

l

260

l

75 500 kHz

l

l

650 kHz

300
300

3.0
80

1.235

1.248

85
90

320
340

50 kHz

mA

µA

mV

mV
mV

µA
µA

kHz
kHz

V
V

V
V

V

3862fa

3

LTC3862

ELECTRICAL CHARACTERISTICS

(Notes 2, 3) The l denotes the specifi cations which apply over the full
operating junction temperature range, otherwise specifi cations are at T
otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

PLLFLTR

CH1-CH2 Channel 1 to Channel 2 Phase Relationship V

CH1-CLKOUT Channel 1 to CLKOUT Phase Relationship V

D

MAX

t

ON(MIN)1

t

ON(MIN)2

t

ON(MIN)3

Gate Driver

R

DS(ON)

Overvoltage

V

FB(OV)

Phase Detector Sourcing Output Current f

Phase Detector Sinking Output Current f

Maximum Duty Cycle V

Minimum On-Time V

Minimum On-Time V

Minimum On-Time V

Driver Pull-Up R

Driver Pull-Down R

DS(ON)

DS(ON)

VFB, Overvoltage Lockout Threshold V

> f

SYNC

OSC

< f

SYNC

OSC

PHASEMODE

V

PHASEMODE

V

PHASEMODE

PHASEMODE

V

PHASEMODE

V

PHASEMODE

= 0V

DMAX

V

= Float

DMAX

V

= 3V8

DMAX

= 0V (Note 8) 180 ns

BLANK

= Float (Note 8) 260 ns

BLANK

= 3V8 (Note 8) 340 ns

BLANK

– V

FB(OV)

= 25°C. VIN = 12V, RUN = 2V and SS = open, unless

A

–15 µA

15 µA

= 0V
= Float
= 3V8

= 0V
= Float
= 3V8

180
180
120

90
60

240

96
84
75

2.1 

0.7 

in Percent 8 10 12 %

FB(NOM)

Deg
Deg
Deg

Deg
Deg
Deg

%
%
%

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specifi ed.

Note 3: The LTC3862E is guaranted to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3862I is guaranteed
over the full –40°C to 125°C operating junction temperature range and
the LTC3862H is guaranteed over the full –40°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C.

Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Continuous
operation above the specifi ed maximum operating junction temperature
may impair device reliability.

Note 5: Supply current in normal operation is dominated by the current
needed to charge the external MOSFET gates. This current will vary with
supply voltage and the external MOSFETs used.

Note 6: The IC is tested in a feedback loop that adjusts V

to achieve a

FB

specifi ed error amplifi er output voltage.

Note 7: Guaranteed by design, not subject to test.
Note 8: The minimum on-time condition is specifi ed for an inductor peak-

to-peak ripple current = 30% (see Minimum On-Time Considerations in the
Applications Information section).

4

3862fa

TYPICAL PERFORMANCE CHARACTERISTICS

Effi ciency and Power Loss vs
Input Voltage

96

95

94

93

EFFICIENCY (%)

92

91

90

0

I

LOAD

5A/DIV

1A TO 5A

5A/DIV

5A/DIV

V

OUT

500mV/DIV

Effi ciency vs Output Current

100

V

= 48V

OUT

95

90

85

80

75

70

EFFICIENCY (%)

65

VIN = 12V

60

55

50

10

VIN = 35V

VIN = 24V

100 1000 10000

LOAD CURRENT (mA)

3862 G01

Load Step Inductor Current at Light Load

SW1

50V/DIV

I

L1

I

L2

3862 G03

V

IN
OUT

= 24V

= 48V

500µs/DIVV

SW2

50V/DIV

2A/DIV

2A/DIV

I

L1

I

L2

V
I

LOAD

= 12V

IN
OUT

= 48V

= 100mA

1µs/DIVV

EFFICIENCY

POWER LOSS

V

= 48V

OUT

= 1A

I

OUT

10 20 30 40

INPUT VOLTAGE (V)

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

3862 G04

QUIESCENT CURRENT (mA)

0.50

0.25

LTC3862

4000

3500

POWER LOSS (mW)

3000

2500

2000

1500

3862 G02

Quiescent Current vs Input
Voltage

0

4

12 16 20

8

INPUT VOLTAGE (V)

24 28 32 36

3862 G05

Quiescent Current vs Temperature

1.90

1.85

1.80

1.75

1.70

1.65

1.60

QUIESCENT CURRENT (mA)

1.55

1.50
–50

–25

0

50

25

TEMPERATURE (°C)

75

100

125

3862 G06

150

Shutdown Quiescent Current vs
Input Voltage

45

40

35

30

25

20

15

SHUTDOWN CURRENT (µA)

10

5

0

8

4

12

20

16

INPUT VOLTAGE (V)

24

Shutdown Quiescent Current vs
Temperature

50

VIN = 12V

40

30

20

SHUTDOWN CURRENT (µA)

10

32

3862 G07

36

28

0

–50

–25 0

50

25 75 150

TEMPERATURE (°C)

100 125

3862 G08

3862fa

5

LTC3862

TYPICAL PERFORMANCE CHARACTERISTICS

INTVCC Line Regulation INTVCC Load Regulation INTVCC vs Temperature

5.25

5.00

VOLTAGE (V)

CC

INTV

4.75
51015 25

0

INPUT VOLTAGE (V)

5.00

4.95

4.90

VOLTAGE (V)

CC

INTV

4.85

20

3962 G09

4.80
10

0

INTVCC LOAD CURRENT (mA)

30

40

20

50

3862 G10

5.00

4.99

4.98

4.97

4.96

4.95

VOLTAGE (V)

4.94

CC

4.93

INTV

4.92

4.91

4.90
–50

–25 25

0

50

TEMPERATURE (°C)

125

100

75

150

3862 G11

INTVCC LDO Dropout vs Load
Current, Temperature

1600

1400

1200

1000

800

600

400

DROPOUT VOLTAGE (mV)

200

0

10 20 40

0

INTVCC LOAD (mA)

Feedback Voltage Line
Regulation

1.226

1.225

1.224

1.223

FB VOLTAGE (V)

1.222

1.221

1.220
4

12 20

816

INPUT VOLTAGE (V)

125°C

30

24

150°C

28

85°C

25°C

–40°C

3862 G12

32

3862 G15

INTVCC UVLO Threshold vs
Temperature

3.6

3.5

3.4

3.3

3.2

3.1

VOLTAGE (V)

3.0

CC

2.9

INTV

2.8

2.7

50

2.6
–50

–25 25

Current Sense Threshold vs
ITH Voltage

80

70

60

50

40

30

20

CURRENT SENSE THRESHOLD (mV)

10

36

0

0 0.4 0.8 1.2 1.6 2.0 2.4

0

50

TEMPERATURE (°C)

ITH VOLTAGE (V)

Feedback Voltage vs Temperature

1.235

1.233

1.231

1.229

1.227

1.225

1.223

1.221

FB VOLTAGE (V)

1.219

1.217

1.215

1.213

1.211

125

100

75

150

3862 G13

–50

02550

–25

TEMPERATURE (°C)

75 100 125 150

3862 G14

Current Sense Threshold vs
Temperature

80

79

78

77

76

75

74

73

72

CURRENT SENSE THRESHOLD (mV)

71

3862 G16

70

–50

–25 25

0

TEMPERATURE (°C)

50

75

100

125

150

3862 G17

6

3862fa

TYPICAL PERFORMANCE CHARACTERISTICS

Maximum Current Sense
Threshold vs Duty Cycle

80

RUN Threshold vs Temperature RUN Threshold vs Input Voltage

1.30

LTC3862

1.5

75

70

65

60

55

MAXIMUM CURRENT SENSE THRESHOLD (mV)

50

20 40 60 80

DUTY CYCLE (%)

SLOPE = 0.625

SLOPE = 1

SLOPE = 1.66

RUN (Off) Source Current vs
Temperature

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

RUN PIN CURRENT (µA)

–0.8

–0.9

–1.0

–50

–25 25

0

50

TEMPERATURE (°C)

100

75

3862 G18

125

3862 G21vv

100100 30507090

150

1.25

1.20

RUN PIN VOLTAGE (V)

1.15

1.10
–50

–25 0 25 50

TEMPERATURE (°C)

RUN (On) Source Current vs
Temperature

0

–1

–2

–3

–4

–5

RUN PIN CURRENT (µA)

–6

–7

–8

–25

–50

0

50

25

TEMPERATURE (°C)

ON

OFF

75

75

100 125 150

3862 G09

125

150

1344 G06

100

1.4

1.3

1.2

RUN PIN VOLTAGE (V)

1.1

1.0
0

510

15 25 40

INPUT VOLTAGE (V)

RUN Source Current vs
Input Voltage

0

–1

–2

–3

–4

–5

RUN PIN CURRENT (µA)

–6

–7

48

12 16 203224 36

INPUT VOLTAGE (V)

ON

OFF

20

30 35

3862 G20

28

3862 G23

Soft-Start Current vs Temperature

–5.0

–5.1

–5.2

–5.3

–5.4

SOFT-START CURRENT (µA)

–5.5

–5.6

–50

050

–25 25

TEMPERATURE (°C)

75

100

125

3862 G24

150

Soft-Start Current vs
Soft-Start Voltage

0

–1

–2

–3

–4

SOFT-START CURRENT (µA)

–5

–6

0

12

0.5 1.5
SOFT-START VOLTAGE (V)

2.5

Oscillator Frequency vs
Temperature

307

306

305

304

303

302

301

FREQUENCY (kHz)

300

299

3

3.5

4

3862 G25

298

–50

–25

0

50

25

TEMPERATURE (°C)

75

100

125

150

3862 G26

3862fa

7

LTC3862

TYPICAL PERFORMANCE CHARACTERISTICS

Oscillator Frequency vs

R

Input Voltage

320

315

310

305

300

295

FREQUENCY (kHz)

290

285

280

436

0

16

8

12

INPUT VOLTAGE (V)

1000

(k)

100

FREQ

R

20

32

24

28

3862 G27

10

vs Frequency

FREQ

200 1000

100

0

400

500

300

FREQUENCY (kHz)

Frequency vs PLLFLTR Voltage

1400

1200

1000

800

600

FREQUENCY (kHz)

400

200

800700600

900

3862 G28

0

0.5 1 1.5 2.5

0

PLLFLTR VOLTAGE (V)

2

3862 G29

Frequency Voltage vs
Temperature

1.235

1.233

1.231

1.229

1.227

1.225

1.223

1.221

1.219

FREQ VOLTAGE (V)

1.217

1.215

1.213

1.211
–50

–25

0

50

25

TEMPERATURE (°C)

75

100

125

150

3862 G30

Gate Turn-On Waveform Driving
Renesas HAT2266

GATE

1V/DIV

Minimum On-Time vs
Temperature

400

350

300

250

200

MINIMUM ON-TIME (ns)

150

100

–50

050

–25 25

TEMPERATURE (°C)

BLANK = 3V8

BLANK = FLOAT

BLANK = SGND

75

Minimum On-Time vs
Input Voltage

400

350

300

250

200

MINIMUM ON-TIME (ns)

150

100

125

150

3862 G31

100

4

Gate Turn-Off Waveform Driving
Renesas HAT2266

GATE

1V/DIV

BLANK = 3V8

BLANK = FLOAT

BLANK = SGND

12 20

816

INPUT VOLTAGE (V)

28

24

32

36

3862 G32

8

= 12V

IN
OUT = 48V

V

OUT = 1A

I
MOSFET RENESAS HAT2266

20ns/DIVV

3862 G33

= 12V

IN
OUT = 48V

V

OUT = 1A

I
MOSFET RENESAS HAT2266

20ns/DIVV

3862 G34

3862fa

PIN FUNCTIONS

LTC3862

3V8: Output of the Internal 3.8V LDO from INTVCC. Supply
pin for the low voltage analog and digital circuits. A low
ESR 1nF ceramic bypass capacitor should be connected
between 3V8 and SGND, as close as possible to the IC.

BLANK: Blanking Time. Floating this pin provides a nominal
minimum on-time of 260ns. Connecting this pin to 3V8
provides a minimum on-time of 340ns, while connecting
it to SGND provides a minimum on-time of 180ns.

CLKOUT: Digital Output Used for Daisy-Chaining Multiple
LTC3862 ICs in Multi-Phase Systems. The PHASEMODE
pin voltage controls the relationship between CH1 and
CH2 as well as between CH1 and CLKOUT.

: Maximum Duty Cycle.This pin programs the maxi-

D

MAX

mum duty cycle. Floating this pin provides 84% duty cycle.
Connecting this pin to 3V8 provides 75% duty cycle, while
connecting it to SGND provides 96% duty cycle.

FB: Error Amplifi er Input. The FB pin should be connected
through a resistive divider network to V
output voltage.

FREQ: A resistor from FREQ to SGND sets the operating
frequency.

GATE1, GATE2: Gate Drive Output. The LTC3862 provides
a 5V gate drive referenced to PGND to drive a logic-level
threshold MOSFET.

INTV

(LDO). A low ESR 4.7µF (X5R or better) ceramic bypass
capacitor should be connected between INTV
as close as possible to the IC.

: Output of the Internal 5V Low Dropout Regulator

CC

to set the

OUT

and PGND,

CC

ITH: Error Amplifi er Output. The current comparator trip
threshold increases with the ITH control voltage. The ITH
pin is also used for compensating the control loop of the
converter.

PGND: Power Ground. Connect this pin close to the
sources of the power MOSFETs. PGND should also be
connected to the negative terminals of V
bypass capacitors. PGND is electrically isolated from the
SGND pin. The Exposed Pad of the FE and QFN packages
is connected to PGND.

PHASEMODE: The PHASEMODE pin voltage programs
the phase relationship between CH1 and CH2 rising gate
signals, as well as the phase relationship between CH1
gate signal and CLKOUT. Floating this pin or connecting
it to either 3V8, or SGND changes the phase relationship
between CH1, CH2 and CLKOUT.

PLLFLTR: PLL Lowpass Filter Input. When synchroniz­ing to an external clock, this pin serves as the lowpass
fi lter input for the PLL. A series resistor and capacitor
connected from PLLFLTR to SGND compensate the PLL
feedback loop.

RUN: Run Control Input. A voltage above 1.22V on the pin
turns on the IC. Forcing the pin below 1.22V causes the
IC to shut down. There is a 0.5µA pull-up current for this
pin. Once the RUN pin raises above 1.22V, an additional

4.5µA pull-up current is added to the pin for program­mable hysteresis.

and INTVCC

IN

3862fa

9

LTC3862

PIN FUNCTIONS

SENSE1+, SENSE2+: Positive Inputs to the Current
Comparators. The ITH pin voltage programs the current
comparator offset in order to set the peak current trip
threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.

–

SENSE1

parators. This pin is normally connected to the bottom of
the sense resistor.

SGND: Signal Ground. All feedback and soft-start con­nections should return to SGND. For optimum load
regulation, the SGND pin should be kelvin connected to
the PCB location between the negative terminals of the
output capacitors.

SLOPE: This pin programs the gain of the internal slope
compensation. Floating this pin provides a normalized
slope compensation gain of 1.00. Connecting this pin
to 3V8 increases the normalized slope compensation by

, SENSE2–: Negative Inputs to the Current Com-

66%, and connecting it to SGND decreases the normalized
slope compensation by 37.5%. See Applications Informa­tion for more details.

SS: Soft-Start Input. For soft-start operation, connecting
a capacitor from this pin to SGND will clamp the output of
the error amp. An internal 5µA current source will charge
the capacitor and set the rate of increase of the peak switch
current of the converter.

SYNC: PLL Synchronization Input. Applying an external
clock between 50kHz and 650kHz will cause the operating
frequency to synchronize to the clock. SYNC is pulled down
by a 50k internal resistor. The rising edge of the SYNC
input waveform will align with the rising edge of GATE1
in closed-loop operation.

: Main Supply Input. A low ESR ceramic capacitor

V

IN

should be connected between this pin and SGND.

10

3862fa

FUNCTIONAL DIAGRAM

CLKOUT

SYNC

PLLFLTR

R

P

C

P

D

MAX

PHASEMODE

FREQ

R

FREQ

SLOPE

BLANK

SS

SLOPE

COMPENSATION

BLANK

LOGIC

3V8

5µA

BLOGIC

DETECT

PSKIP

SYNC

VCO

OV

UV

ITRIP

LTC3862

V

IN

C

5V

LDO

UVLO

LOOP

S

R1 Q

R2

UV

OT

OVER
TEMP

SD

BLOGIC

CLK1

CLK2

D

MAX

OT

PWM LATCH

+

R

ICMP

–

3.8V
LDO

BIAS

LOGIC

INTV

3V8

GATE

PGND

SENSE

SENSE

IN

CC

C

VCC

C

3V8

+

–

V

IN

L

D

+

M

C

OUT

R

S

V

OUT

C

SS

ITH

R

C

C

C

PSKIP

0.275V

PSKIP

–

OT
UV
SD

+

+

1.223V

V TO I

RUN

–

1.22V

SD

+

OV

OV

EA

–

–

+

1.345V

4.5µA

DUPLICATE FOR
SECOND CHANNEL

V

FB

SGND

0.5µA
RUN

R2

R1

3862 FD

3862fa

11

LTC3862

OPERATION

The Control Loop

The LTC3862 uses a constant frequency, peak current
mode step-up architecture with its two channels operat­ing 180 degrees out of phase. During normal operation,
each external MOSFET is turned on when the clock for
that channel sets the PWM latch, and is turned off when
the main current comparator, ICMP, resets the latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifi er, EA. The error amplifi er
compares the output feedback signal at the V

pin to the

FB

internal 1.223V reference and generates an error signal
at the ITH pin. When the load current increases it causes
a slight decrease in V

relative to the reference voltage,

FB

which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the MOSFET is turned off, the inductor current fl ows
through the boost diode into the output capacitor and load,
until the beginning of the next clock cycle.

Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry

The LTC3862 contains two cascaded PMOS output stage
low dropout voltage regulators (LDOs), one for the gate

drive supply (INTV

) and one for the low voltage analog

CC

and digital control circuitry (3V8). A block diagram of this
power supply arrangement is shown in Figure 1.

The Gate Driver Supply LDO (INTV

The 5V output (INTV

and supplies power to the power MOSFET gate driv-

V

IN

ers. The INTV

pin should be bypassed to PGND with a

CC

) of the fi rst LDO is powered from

CC

CC

)

minimum of 4.7F of ceramic capacitance (X5R or better),
placed as close as possible to the IC pins. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a Q

greater than 50nC is used, then it is

G

recommended that the bypass capacitance be increased
to a minimum of 10F.

An undervoltage lockout (UVLO) circuit senses the INTV

CC

regulator output in order to protect the power MOSFETs
from operating with inadequate gate drive. For the LTC3862
the rising UVLO threshold is typically 3.3V and the hyster­esis is typically 400mV. The LTC3862 was optimized for
logic-level power MOSFETs and applications where the
output voltage is less than 50V to 60V. For applications
requiring standard threshold power MOSFETs, please refer
to the LTC3862-1 data sheet.

LTC3862

1.223V

–

+

R2 R1

Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power

SGND

1.223V

R4

NOTE: PLACE C

VCC

–

+

R3

AND C

P-CH

INTV

CC

P-CH

SGND

CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS

3V8

3V8

ANALOG

CIRCUITS

LOGIC

INTV

V

GATE

PGND

3V8

SGND

IN

C

IN

CC

C

VCC

C

3V8

3862 F01

3862fa

12