LINEAR TECHNOLOGY LTC3830, LTC3830-1 Technical data

FEATURES

LTC3830/LTC3830-1

High Power Step-Down

Synchronous DC/DC Controllers

for Low Voltage Operation

U

DESCRIPTIO

■

High Power Switching Regulator Controller
for 3.3V-5V to 1.xV-3.xV Step-Down Applications

■

No Current Sense Resistor Required

■

Low Input Supply Voltage Range: 3V to 8V

■

Maximum Duty Cycle >91% Over Temperature

■

All N-Channel External MOSFETs

■

Excellent Output Regulation: ±1% Over Line, Load
and Temperature Variations

■

High Efficiency: Over 95% Possible

■

Adjustable or Fixed 3.3V Output (16-Pin Version)

■

Programmable Fixed Frequency Operation: 100kHz to
500kHz

■

External Clock Synchronization

■

Soft-Start (16-Pin Version and LTC3830-1)

■

Low Shutdown Current: <10µA

■

Overtemperature Protection

■

Available in S8, S16 and SSOP-16 Packages

U

APPLICATIO S

■

CPU Power Supplies

■

Multiple Logic Supply Generator

■

Distributed Power Applications

■

High Efficiency Power Conversion

The LTC®3830/LTC3830-1 are high power, high effi­ciency switching regulator controllers optimized for

3.3V-5V to 1.xV-3.xV step-down applications. A preci­sion internal reference and feedback system provide
±1% output regulation over temperature, load current
and line voltage variations. The LTC3830/LTC3830-1 use
a synchronous switching architecture with N-channel
MOSFETs. Additionally, the chip senses output current
through the drain-source resistance of the upper
N-channel FET, providing an adjustable current limit
without a current sense resistor.

The LTC3830/LTC3830-1 operate with an input supply
voltage as low as 3V and with a maximum duty cycle of
>91% over temperature. They include a fixed frequency
PWM oscillator for low output ripple operation. The 200kHz
free-running clock frequency can be externally adjusted or
synchronized with an external signal from 100kHz to 500kHz.
In shutdown mode, the LTC3830 supply current drops to
<10µA. The LTC3830-1 differs from the LTC3830 S8 ver-
sion by replacing shutdown with a soft-start function.

For a similar, pin compatible DC/DC converter with an
output voltage as low as 0.6V, please refer to the LTC3832.

, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO

4.7µF

0.1µF

15k

12.7k 1%

0.01µF

SS

COMP

GND

FB

5.36k 1%

3.3nF

LTC3830-1

PV

CC2

G1

PV

CC1

G2

L: SUMIDA CDEP105-3R2MC-88
C

Figure 1. High Efficiency 3V-6V to 1.8V Power Converter

5.1Ω

MBR0520T1

: PANASONIC EEFUEOD271R

OUT

U

V

IN

3V TO 6V

0.1µF

+

M1
Si7806DN

M2
Si7806DN

220µF
10V

L

3.2µH

B320A

Efficiency and Power Loss vs Load Current

4.0

3.5

3.0

2.5

1.8V
9A

+

C

OUT

270µF
2V

3830 F01

2.0

1.5

POWER LOSS (W)

1.0

0.5

0

0

LOAD CURRENT (A)

VIN = 3.3V
V

OUT

100

90

80

EFFICIENCY (%)

70

60

50

40

30

= 1.8V

20

87654321910

3830 TA02

3830fa

1

LTC3830/LTC3830-1

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Supply Voltage

VCC....................................................................... 9V

PV

................................................................ 14V

CC1,2

Input Voltage

IFB, I

............................................... –0.3V to 14V

MAX

SENSE+, SENSE–, FB,

SHDN, FREQSET ....................... –0.3V to V

UU

W

+ 0.3V

CC

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LTC3830ES8

S8

PART MARKING

3830

ORDER PART

NUMBER

LTC3830-1ES8

S8

PART MARKING

38301

G1

1

PV

2

CC1

GND

3

FB

4

8-LEAD PLASTIC SO

T

= 125°C, θJA = 130°C/ W

JMAX

G1

1

PV

2

CC1

GND

3

FB

4

8-LEAD PLASTIC SO

T

= 125°C, θJA = 130°C/ W

JMAX

TOP VIEW

S8 PACKAGE

TOP VIEW

S8 PACKAGE

8

G2

V

/PV

7

CC

CC2

COMP

6

SHDN

5

8

G2

/PV

V

7

CC

CC2

COMP

6

SS

5

Junction Temperature (Note 11)........................... 125°C

Operating Temperature Range (Note 9) .. – 40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

ORDER PART

NUMBER

TOP VIEW

1

G1

2

PV

CC1

3

PGND

4

GND

–

SENSE

SENSE

16-LEAD PLASTIC SSOP

5

6

FB

+

7

8

SHDN

GN PACKAGE

T

= 125°C, θJA = 130°C/ W (GN)

JMAX

= 125°C, θJA = 100°C/ W (S)

T

JMAX

G2

16

PV

15

CC2

V

14

CC

I

13

FB

I

12

MAX

FREQSET

11

COMP

10

SS

9

S PACKAGE

16-LEAD PLASTIC SO

LTC3830EGN
LTC3830ES

GN PART

MARKING

3830

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. VCC, PV

The ● denotes specifications that apply over the full operating temperature

, PV

CC1

= 5V, unless otherwise noted. (Note 2)

CC2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

PV

V

V

V

∆V

CC

CC

UVLO

FB

OUT

OUT

Supply Voltage ● 358 V

PV

, PV

CC1

Voltage (Note 7) ● 3 13.2 V

CC2

Undervoltage Lockout Voltage 2.4 2.9 V

Feedback Voltage V

Output Voltage V

Output Load Regulation I
Output Line Regulation V

= 1.25V 1.255 1.265 1.275 V

COMP

= 1.25V 3.250 3.3 3.350 V

COMP

= 0A to 10A (Note 6) 2 mV

OUT

= 4.75V to 5.25V 0.1 mV

CC

● 1.252 1.265 1.278 V

● 3.235 3.3 3.365 V

3830fa

2

LTC3830/LTC3830-1

ELECTRICAL CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. VCC, PV

The ● denotes specifications that apply over the full operating temperature

, PV

CC1

= 5V, unless otherwise noted. (Note 2)

CC2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

VCC

I

PVCC

f

OSC

V

SAWL

V

SAWH

V

COMPMAX

∆f

/∆I

OSC

FREQSET

A

V

g

m

I

COMP

I

MAX

V

IH

V

IL

I

IN

I

SS

I

SSIL

R

SENSE

R

SENSEFB

tr, t

f

t

NOV

DC

MAX

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.

Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3830 operating frequency, operating voltage and the external FETs
used.

Note 4: The open-loop DC gain and transconductance from the SENSE
and SENSE– pins to COMP pin will be (AV)(1.265/3.3) and (gm)(1.265/3.3)
respectively.

Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.

Note 6: Guaranteed by design, not subject to test.
Note 7: PV

at 95% maximum duty cycle and for the current limit protection circuit to

Supply Current Figure 2, V

V

= 0V ● 110 µA

SHDN

PVCC Supply Current Figure 2, V

= 0V ● 0.1 10 µA

V

SHDN

= V

SHDN

SHDN

CC

= VCC (Note 3) ● 14 20 mA

● 0.7 1.6 mA

Internal Oscillator Frequency FREQSET Floating ● 160 200 250 kHz

V

at Minimum Duty Cycle 1.2 V

COMP

V

at Maximum Duty Cycle 2.2 V

COMP

Maximum V

COMP

VFB = 0V, PV

= 8V 2.85 V

CC1

Frequency Adjustment 10 kHz/µA

Error Amplifier Open-Loop DC Gain Measured from FB to COMP, ● 46 55 dB

Error Amplifier Transconductance Measured from FB to COMP, ● 520 650 780 µmho

+

SENSE

and SENSE– Floating, (Note 4)

+

and SENSE– Floating, (Note 4)

SENSE

Error Amplifier Output Sink/Source Current 100 µA

I

Sink Current V

MAX

I

Sink Current Tempco V

MAX

= V

IMAX

CC

(Note 10)

= VCC (Note 6) 3300 ppm/°C

IMAX

91215 µA

● 41220 µA

SHDN Input High Voltage ● 2.4 V

SHDN Input Low Voltage ● 0.8 V

SHDN Input Current V

Soft-Start Source Current VSS = 0V, V

Maximum Soft-Start Sink Current V
In Current Limit V

= V

SHDN

CC

= 0V, V

IMAX

= VCC, V

IMAX

= VCC (Note 8), PV

SS

IFB

● 0.1 1 µA

IFB

= V

CC

● –8 –12 –16 µA

= 0V, 1.6 mA

= 8V

CC1

SENSE Input Resistance 29.2 kΩ

SENSE to FB Resistance 18 kΩ

Driver Rise/Fall Time Figure 3, PV

Driver Nonoverlap Time Figure 3, PV

Maximum G1 Duty Cycle Figure 3, VFB = 0V (Note 5), PV

CC1

CC1

= PV

= 5V (Note 5) ● 80 250 ns

CC2

= PV

= 5V (Note 5) ● 25 120 250 ns

CC2

= 8V ● 91 95 %

CC1

Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.

Note 9: The LTC3830E/LTC3830-1E are guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.

Note 10: The minimum and maximum limits for I

over temperature

MAX

includes the intentional temperature coefficient of 3300ppm/°C. This

+

induced temperature coefficient counteracts the typical temperature
coefficient of the external power MOSFET on-resistance. This results in a
relatively flat current limit over temperature for the application.

Note 11: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.

must be higher than VCC by at least 2.5V for G1 to operate

CC1

Continuous operation above the specified maximum operating temperature
may impair device reliability.

be active.

3830fa

3

LTC3830/LTC3830-1

TEMPERATURE (˚C)

–50

ERROR AMPLIFIER TRANSCONDUCTANCE (µmho)

700

750

800

25 75

3830 G05

650

600

–25 0

50 100 125

550

500

TEMPERATURE (°C)

–50

40

ERROR AMPLIFIER OPEN-LOOP GAIN (dB)

45

50

55

60

–25 0 25 50

2830 G07

75 100 125

EXTERNAL SYNC FREQUENCY (kHz)

100

0.5

V

SAWH

– V

SAWL

(V)

0.6

0.8

0.9

1.0

1.5

1.2

200

300

3830 G10

0.7

1.3

1.4

1.1

400

500

TA = 25°C

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

3.34
TA = 25°C

REFER TO FIGURE 12

3.33

3.32

3.31

(V)

3.30

OUT

V

3.29

3.28

3.27

3.26

–10 –5 5

–15

0

OUTPUT CURRENT (A)

10 15

3830 G02

Line Regulation

1.275
TA = 25°C

1.273

1.271

1.269

1.267

(V)

1.265

FB

V

1.263

1.261

1.259

1.257

1.255

3

4

5

SUPPLY VOLTAGE (V)

6

7

3830 G03

Error Amplifier Transconductance
vs Temperature

10

8

6

4

∆V

2

FB

(mV)

0

–2

–4

–6

–8

–10

8

Output Voltage Temperature Drift

3.34
REFER TO FIGURE 12

OUTPUT = NO LOAD

3.33

3.32

3.31

(V)

3.30

OUT

V

3.29

3.28

3.27

3.26

–25 0 50

–50

TEMPERATURE (°C)

Oscillator Frequency
vs Temperature

250

FREQSET FLOATING

240

230

220

210

200

190

180

OSCILLATOR FREQUENCY (kHz)

170

160

–50

–25

4

0

TEMPERATURE (°C)

25

25 125

75 100 125

50

75 100

3830 G04

3831 G08

∆V

OUT

(mV)

200

180

160

140

120

100

80

60

40

ERROR AMPLIFIER SINK/SOURCE CURRENT (µA)

–50

40

30

20

10

0

–10

–20

–30

–40

Oscillator Frequency
vs FREQSET Input Current

600

500

400

300

200

OSCILLATOR FREQUENCY (kHz)

100

0

–40

Error Amplifier Sink/Source
Current vs Temperature

–25 0 50

–30

FREQSET INPUT CURRENT (µA)

25

TEMPERATURE (°C)

–20 –10 0

75 100 125

TA = 25°C

10 20

3830 G09

3830 G06

Error Amplifier Open-Loop Gain
vs Temperature

Oscillator (V

SAWH

– V

SAWL

)

vs External Sync Frequency

3830fa

UW

OUTPUT CURRENT (A)

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3830 G13

2 4 6 8 10 12 14

OUTPUT VOLTAGE (V)

TA = 25°C
REFER TO FIGURE 12
R

IMAX

= 5k

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3830/LTC3830-1

Maximum G1 Duty Cycle
vs Temperature

100

VFB = 0V
REFER TO FIGURE 3

99

98

97

96

95

94

93

MAXIMUM G1 DUTY CYCLE (%)

92

91

–50

0

–25

TEMPERATURE (°C)

25 125

50

Output Current Limit Threshold
vs Temperature

16

14

12

10

8

6

4

OUTPUT CURRENT LIMIT (A)

REFER TO FIGURE 12 AND NOTE 10 OF

2

THE ELECTRICAL CHARACTERISTICS

= 5k

R

IMAX

0

–50

0

–25

TEMPERATURE (°C)

50

25

75 100

75

100

3830 G11

3830 G14

125

I

Sink Current

MAX

vs Temperature Output Overcurrent Protection

20

18

16

14

12

10

SINK CURRENT (µA)

MAX

8

I

6

4

–25 0 50

–50

25

TEMPERATURE (°C)

Soft-Start Source Current
vs Temperature

–8

–9

–10

–11

–12

–13

–14

–15

SOFT-START SOURCE CURRENT (µA)

–16

–25 0 50

–50

25

TEMPERATURE (°C)

75 100 125

3830 G12

75 100 125

3830 G15

Soft-Start Sink Current
vs (V

– V

IFB

2.00
TA = 25°C

1.75

1.50

1.25

1.00

0.75

0.50

SOFT-START SINK CURRENT (mA)

0.25

0

–125 –100 –50

–150

IMAX

V

IFB

– V

)

–75

IMAX

(mV)

–25

0

3830 G16

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0
–50

UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)

Undervoltage Lockout Threshold
Voltage vs Temperature

50

25

0

–25

TEMPERATURE (°C)

75

100

3830 G17

125

VCC Operating Supply Current
vs Temperature

1.6
FREQSET FLOATING

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

OPERATING SUPPLY CURRENT (mA)

CC

0.5

V

0.4

–50

0

–25

TEMPERATURE (°C)

50

25

PVCC Supply Current
vs Oscillator Frequency

90

TA = 25°C

80

70

60

50

G1 AND G2

40

WITH 1000pF,

PV

30

SUPPLY CURRENT (mA)

CC

20

PV

10

100

125

3830 G18

75

0

0

G1 AND G2 LOADED

WITH 6800pF,

= 12V

PV

CC1,2

G1 AND G2

LOADED

= 5V

CC1,2

100 300

200

OSCILLATOR FREQUENCY (kHz)

LOADED

WITH 6800pF,

PV

CC1,2

400

= 5V

500

3830 G19

3830fa

5

LTC3830/LTC3830-1

UW

TYPICAL PERFOR A CE CHARACTERISTICS

PVCC Supply Current
vs Gate Capacitance

50

TA = 25°C

40

PV

CC1,2

30

20

SUPPLY CURRENT (mA)

CC

10

PV

0

123

0

GATE CAPACITANCE AT G1 AND G2 (nF)

PV

45

CC1,2

U

PI FU CTIO S

= 12V

= 5V

67 9

8

10

3830 G20

UU

(16-Lead LTC3830/8-Lead LTC3830/LTC3830-1)

G1 Rise/Fall Time
vs Gate Capacitance Transient Response

200

TA = 25°C

180

160

140

120

100

80

60

G1 RISE/FALL TIME (ns)

40

20

0

0

tf AT PV

t

AT PV

r

CC1,2

21

GATE CAPACITANCE AT G1 AND G2 (nF)

G1 (Pin 1/Pin 1/Pin 1): Top Gate Driver Output. Connect
this pin to the gate of the upper N-channel MOSFET, Q1.
This output swings from PGND to PV

. It remains low if

CC1

G2 is high or during shutdown mode.

V

OUT

50mV/DIV

= 5V

CC1,2

= 5V

AT PV

t

r

43

5

tf AT PV

67 9

CC1,2

CC1,2

= 12V

= 12V

8

10

3830 G21

I

LOAD

2AV/DIV

50µs/DIV

3830 G22.tif

resistor divider to set the output voltage, float SENSE+ and
SENSE– and connect the external resistor divider to FB.
The internal resistor divider is not included in the LTC3830-1
and the 8-lead LTC3830.

PV

(Pin 2/Pin 2/Pin 2): Power Supply Input for G1.

CC1

Connect this pin to a potential of at least VIN + V

GS(ON)(Q1)

.
This potential can be generated using an external supply or
charge pump.

PGND (Pin 3/Pin 3/Pin 3): Power Ground. Both drivers
return to this pin. Connect this pin to a low impedance
ground in close proximity to the source of Q2. Refer to the
Layout Consideration section for more details on PCB
layout techniques. The LTC3830-1 and the 8-lead LTC3830
have PGND and GND tied together internally at Pin 3.

GND (Pin 4/Pin 3/Pin 3): Signal Ground. All low power
internal circuitry returns to this pin. To minimize regula­tion errors due to ground currents, connect GND to PGND
right at the LTC3830.

SENSE–, FB, SENSE+ (Pins 5, 6, 7/Pin 4/Pin 4): These
three pins connect to the internal resistor divider and input
of the error amplifier. To use the internal divider to set the
output voltage to 3.3V, connect SENSE+ to the positive
terminal of the output capacitor and SENSE– to the nega­tive terminal. FB should be left floating. To use an external

SHDN (Pin 8/Pin 5/NA): Shutdown. A TTL compatible low
level at SHDN for longer than 100µs puts the LTC3830 into
shutdown mode. In shutdown, G1 and G2 go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also doubles
as an external clock input to synchronize the internal
oscillator with an external clock. The shutdown function is
disabled in the LTC3830-1.

SS (Pin 9/NA/Pin 5): Soft-Start. Connect this pin to an
external capacitor, CSS, to implement a soft-start function.
If the LTC3830 goes into current limit, CSS is discharged
to reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level. The soft-start function is disabled in
the 8-lead LTC3830.

COMP (Pin 10/Pin 6/Pin 6): External Compensation. This
pin internally connects to the output of the error amplifier
and input of the PWM comparator. Use a RC + C network
at this pin to compensate the feedback loop to provide
optimum transient response.

3830fa

6

LTC3830/LTC3830-1

U

UU

PI FU CTIO S

FREQSET (Pin 11/NA/NA): Frequency Set. Use this pin to
adjust the free-running frequency of the internal oscillator.
With the pin floating, the oscillator runs at about 200kHz.
A resistor from FREQSET to ground speeds up the oscil­lator; a resistor to V

(Pin 12/NA/NA): Current Limit Threshold Set. I

I

MAX

sets the threshold for the internal current limit compara­tor. If I

drops below I

FB

into current limit. I
GND. Connect this pin to the main V
of Q1, through an external resistor to set the current limit
threshold. Connect a 0.1µF decoupling capacitor across
this resistor to filter switching noise.

IFB (Pin 13/NA/NA): Current Limit Sense. Connect this pin
to the switching node at the source of Q1 and the drain of
Q2 through a 1k resistor. The 1k resistor is required to
prevent voltage transients from damaging IFB.This pin is
used for sensing the voltage drop across the upper
N-channel MOSFET, Q1.

slows it down.

CC

with G1 on, the LTC3830 goes

MAX

has an internal 12µA pull-down to

MAX

supply at the drain

IN

MAX

(Pin 14/Pin 7/Pin 7): Power Supply Input. All low

V

CC

power internal circuits draw their supply from this pin.
Connect this pin to a clean power supply, separate from
the main VIN supply at the drain of Q1. This pin requires a

4.7µF bypass capacitor. The LTC3830-1 and the 8-lead
LTC3830 have V

and PV

CC

tied together at Pin 7 and

CC2

require a 10µF bypass capacitor to GND.

PV

(Pin 15/Pin 7/Pin 7): Power Supply Input for G2.

CC2

Connect this pin to the main high power supply.

G2 (Pin 16/Pin 8/Pin 8): Bottom Gate Driver Output.
Connect this pin to the gate of the lower N-channel
MOSFET, Q2. This output swings from PGND to PV

CC2

. It
remains low when G1 is high or during shutdown mode.
To prevent output undershoot during a soft-start cycle, G2
is held low until G1 first goes high. (FFBG in Block
Diagram.)

BLOCK DIAGRA

SHDN

FREQSET

COMP

SS

QC

W

12µA

100ms DELAY

INTERNAL

OSCILLATOR

QSS

+

V

REF

2.2V

1.2V

LOGIC AND

THERMAL SHUTDOWN

–

PWM

+

–

V

–

CC

+

DISABLE
ILIM

POWER DOWN

–

– 3% V

REF

I

FB

I

MAX

12µA

+

V

–

DISDR

PV

CC1

3830 BD

G1

PV

CC2

G2

PGND

FB

SENSE

SENSE

+

–

3830fa

Q

S

Q

R

FFBG

SQ

ENABLE
G2

RPOR

MAXMINERR

–

+ 3%

+

18k

11.2k

V

REF

V

– 3%

REF

+ 3%

V

REF

BG

+

REF

PV

CC1

+ 2.5V

V

CC1

7

LTC3830/LTC3830-1

COMP

FB

V

COMP

V

FB

G1

G2

I

FBVCCPVCC1

5V

PV

CC2

6800pF

0.1µF

10µF

6800pF

G1 RISE/FALL

G2 RISE/FALL

3830 F03

I

MAX

GND PGND

LTC3830

+

TEST CIRCUITS

PV

V

SHDNVCC

CC

NC
NC
NC
NC

SHDN V
FB
SS
FREQSET
COMP
I

MAX

CC

LTC3830

GND PGND SENSE

PV

CC2PVCC1

–

I

FB

SENSE

G1

G2

+

3830 F02

6800pF

6800pF

Figure 2 Figure 3

WUUU

APPLICATIO S I FOR ATIO

OVERVIEW

The LTC3830 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) de­signed for use in high power, low voltage step-down
(buck) converters. It includes an onboard PWM generator,
a precision reference trimmed to ±0.8%, two high power
MOSFET gate drivers and all necessary feedback and
control circuitry to form a complete switching regulator
circuit. The PWM loop nominally runs at 200kHz.

The 16-lead versions of the LTC3830 include a current
limit sensing circuit that uses the topside external N-channel
power MOSFET as a current sensing element, eliminating
the need for an external sense resistor.

Also included in the 16-lead version and the LTC3830-1
is an internal soft-start feature that requires only a single
external capacitor to operate. In addition, 16-lead parts
feature an adjustable oscillator that can free run or
synchronize to external signal with frequencies from
100kHz to 500kHz, allowing added flexibility in external
component selection. The 8-lead version does not in­clude current limit, internal soft-start and frequency
adjustability. The LTC3830-1 does not include current
limit, frequency adjustability, external synchronization
and the shutdown function.

THEORY OF OPERATION

Primary Feedback Loop

The LTC3830/LTC3830-1 sense the output voltage of the
circuit at the output capacitor and feeds this voltage back
to the internal transconductance error amplifier, ERR,
through a resistor divider network. The error amplifier
compares the resistor-divided output voltage to the inter­nal 1.265V reference and outputs an error signal to the
PWM comparator. This error signal is compared with a
fixed frequency ramp waveform, from the internal oscil­lator, to generate a pulse width modulated signal. This
PWM signal drives the external MOSFETs through the G1
and G2 pins. The resulting chopped waveform is filtered by
LO and C

which closes the loop. Loop compensation is

OUT

achieved with an external compensation network at the
COMP pin, the output node of the error amplifier.

MIN, MAX Feedback Loops

Two additional comparators in the feedback loop provide
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MIN
compares the feedback signal to a voltage 40mV below the
internal reference. If the signal is below the comparator
threshold, the MIN comparator overrides the error ampli­fier and forces the loop to maximum duty cycle, >91%.

3830fa

8