LINEAR TECHNOLOGY LTC3783 Technical data

FEATURES

V

PWMIN

5V/DIV

I

L

2.5A/DIV

I

LED

0.5A/DIV

V

OUT

0.2V/DIV

AC COUPLED

1µs/DIV

3783 TA01b

LTC3783

PWM LED Driver and Boost,

Flyback and SEPIC Controller

U

DESCRIPTIO

■

True Color PWMTM Delivers Constant Color with
3000:1 Dimming Ratio

■

Fully Integrated Load FET Driver for PWM Dimming
Control of High Power LEDs

■

100:1 Dimming from Analog Inputs

■

Wide FB Voltage Range: 0V to 1.23V

■

Constant Current or Constant Voltage Regulation

■

Low Shutdown Current: IQ = 20µA

■

1% 1.23V Internal Voltage Reference

■

2% RUN Pin Threshold with 100mV Hysteresis

■

Programmable Operating Frequency (20kHz to
1MHz) with One External Resistor

■

Synchronizable to an External Clock Up to 1.3f

■

Internal 7V Low Dropout Voltage Regulator

■

Programmable Output Overvoltage Protection

■

Programmable Soft-Start

■

Can be Used in a No R

■

16-Lead DFN and TSSOP Packages

SENSE

TM

Mode for VDS < 36V

OSC

U

APPLICATIO S

■

High Voltage LED Arrays

■

Telecom Power Supplies

■

42V Automotive Systems

■

24V Industrial Controls

■

IP Phone Power Supplies

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
True Color PWM and No R
All other trademarks are the property of their respective owners.

are trademarks of Linear Technology Corporation.

SENSE

The LTC®3783 is a current mode LED driver and boost,
flyback and SEPIC controller that drives both an N-channel
power MOSFET and an N-channel load PWM switch.
When using an external load switch, the PWMIN input not
only drives PWMOUT, but also enables controller GATE
switching and error amplifier operation, allowing the con­troller to store load current information while PWMIN is
low. This feature (patent pending) provides extremely fast,
true PWM load switching with no transient overvoltage or
undervoltage issues; LED dimming ratios of 3000:1 can be
achieved digitally, avoiding the color shift normally asso­ciated with LED current dimming. The FBP pin allows
analog dimming of load current, further increasing the
effective dimming ratio by 100:1 over PWM alone.

In applications where output load current must be re­turned to V

, optional constant current/constant voltage

IN

regulation controls either output (or input) current or
output voltage and provides a limit for the other. I

LIM

provides a 10:1 analog dimming ratio.

For low- to medium-power applications, No R

SENSE

mode
can utilize the power MOSFET’s on-resistance to eliminate
the current-sense resistor, thereby maximizing efficiency.

The IC’s operating frequency can be set with an external
resistor over a 20kHz to 1MHz range and can be synchro­nized to an external clock using the SYNC pin.

The LTC3783 is available in the 16-lead DFN and TSSOP
packages.

TYPICAL APPLICATIO

350mA PWM LED Boost Application

V

IN

6V TO 16V

OF LEDs)

(< TOTAL V

F

0.1µF

10µF

10k 6k

1M

RUN
PWMIN
I

TH

SS

105k

V

REF

FBP
FBN
FREQ
SYNC

M1, M2: SILICONIX Si4470EY

LTC3783

PWMOUT

OV/FB

GATE

SENSE

INTV

GND

V

IN

I

LIM

CC

U

10µF

2.2µH

×2

ZETEX ZLLS1000

237k

M1

4.7µF

0.05Ω

12.4k 0.3Ω

*LUMILEDS LHXL-BW02

LED*
STRING

M2

3783 TA01a

C

10µF

GND

V

OUT

<25V

OUT

Typical Waveforms

3783fa

1

LTC3783

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

VIN, SENSE, FBP, FBN Voltages ................ – 0.3V to 42V

INTV
INTV

Voltage ........................................... –0.3V to 9V

CC

Output Current ........................................ 75mA

CC

GATE Output Current ................................ 50mA (RMS)

PWMOUT Output Current ......................... 25mA (RMS)

Ouput Current................................................ 1mA

V

REF

GATE, PWMOUT Voltages ..... –0.3V to (V

, I

I

TH

, SS Voltages .............................. – 0.3V to 2.7V

LIM

INTVCC

+ 0.3V)

RUN, SYNC, PWMIN Voltages .................... – 0.3V to 7V

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

FBN

1

FBP

2

I

3

LIM

V

4

REF

FREQ

SYNC

PWMIN

PWMOUT

16-LEAD (5mm × 4mm) PLASTIC DFN

T

JMAX

EXPOSED PAD (PIN 17) IS GND

MUST BE SOLDERED TO PCB

17

5

6

7

8

DHD PACKAGE

= 125°C, θJA = 43°C/ W

16

RUN

15

I

TH

OV/FB

14

SS

13

SENSE

12

V

11

IN

INTV

10

CC

GATE

9

ORDER PART

NUMBER

LTC3783EDHD

DHD PART MARKING

3783

FREQ, V

, OV/FB Voltages .....................– 0.3V to 1.5V

REF

Operating Temperature Range

(Note 2) .................................................. – 40°C to 85°C

Junction Temperature (Note 3)............ – 40°C to 125°C

Storage Temperature Range

DFN Package ................................... –65°C to 125°C

TSSOP Package ............................... – 65°C to 150°C

Lead Temperature (Soldering, 10sec)

TSSOP Package ............................................... 300°C

TOP VIEW

1

FBN

2

FBP

3

I

LIM

4

V

REF

5

FREQ

6

SYNC

7

PWMIN

PWMOUT

8

FE PACKAGE

16-LEAD PLASTIC TSSOP

T

= 125°C, θJA = 38°C/ W

JMAX

EXPOSED PAD (PIN 17) IS GND

MUST BE SOLDERED TO PCB

RUN

16

I

15

TH

OV/FB

14

SS

13

17

SENSE

12

V

11

IN

INTV

10

CC

GATE

9

ORDER PART

NUMBER

LTC3783EFE

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V

= 12V, V

IN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop/Whole System

V

IN

I

Q

+

V

RUN

–

V

RUN

V

RUN(HYST)

= 1.5V, V

RUN

SYNC

= 0V, V

FBP

= V

, RT = 20k, unless otherwise specified.

REF

Input Voltage Range 336V
Input Voltage Supply Current (Note 4)

Continuous Mode V
Shutdown Mode V

= 1.5V, V

OV/FB

= 0V 20 µA

RUN

= 0.75V 1.5 mA

ITH

Rising RUN Input Threshold Voltage 1.348 V
Falling RUN Input Threshold Voltage 1.223 1.248 1.273 V
RUN Pin Input Threshold Hysteresis 100 mV

3783fa

2

LTC3783

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
V

= 12V, V

IN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

RUN

V

SENSE(MAX)

I

SENSE(ON)

I

SENSE(OFF)

I

SS

Voltage/Temperature Reference

V

REF

I

REF

∆V

/∆VINReference Voltage Line Regulation 3V ≤ VIN ≤ 36V 0.002 0.02 %/V

REF

∆V

/∆I

REF

T

MAX

T

HYST

Error Amplifier

I

OV/FB

∆V

OV/FB(OV)

V

OV/FB(FB)

I

, I

FBP

FBN

V

– V

FBP

FBN

g

m

A

VOL

Oscillator

f

OSC

D

MAX

f

SYNC/fOSC

t

SYNC(MIN)

t

SYNC(MAX)

V

IH(SYNC)

V

HYST(SYNC)

R

SYNC

t

ON(MIN)

= 1.5V, V

RUN

SYNC

= 0V, V

FBP

= V

, RT = 20k, unless otherwise specified.

REF

RUN Pin Input Current 5nA
Maximum Current Sense Threshold 125 150 180 mV
SENSE Pin Current (GATE High) V
SENSE Pin Current (GATE Low) V

= 0V 70 µA

SENSE

= 36V 0.2 µA

SENSE

Soft-Start Pin Output Current VSS = 0V –50 µA

Reference Voltage 1.218 1.230 1.242 V

●

1.212 1.248 V

Max Reference Pin Output Current 0.5 mA

Reference Voltage Load Regulation 0mA ≤ I

REF

≤ 0.5mA 0.2 1.0 %/mA

REF

Overtemperature SD Threshold 165 °C
Rising

Overtemperature Hysteresis 25 °C

OV/FB Pin Input Current 18 60 nA
OV/FB Overvoltage Lockout Threshold V
OV/FB Pin Regulation Voltage 2.5V < V
Error Amplifier Input Current 0V ≤ V

2.5V < V

Error Amplifier Offset Voltage 0V ≤ V
(Note 5) 2.5V < V

2.5V < V

Error Amplifier Transconductance V

2.5V < V

OV/FB(OV)

FBP

FBP

≤ V

FBP

– V

OV/FB(NOM)

< 36V 1.212 1.230 1.248 V

FBP

≤ V

REF

< 36V 50 µA

FBP

≤ V

REF

≤ 36V (V

FBP

≤ 36V (V

FBP

REF

< 36V 14 mmho

FBP

in %, V

FBP

≤ V

REF

7%

–0.4 µA

–3 3 mV

= V

ILIM
ILIM

) 100 mV

REF

= 0.123V) 10 mV

1.7 mmho

Error Amplifier Open-Loop Gain 500 V/V

Oscillator Frequency R

= 20kΩ 250 300 350 kHz

FREQ

Oscillator Frequency Range 20 1000 kHz
Maximum Duty Cycle 85 90 97 %
Recommended Max SYNC Freq Ratio f
SYNC Minimum Input Pulse Width V
SYNC Maximum Input Pulse Width V

= 300kHz (Note 6) 1.25 1.3

OSC

= 0V to 5V 25 ns

SYNC

= 0V to 5V 0.8/f

SYNC

OSC

ns
SYNC Input Voltage High Level 1.2 V
SYNC Input Voltage Hysteresis 0.5 V
SYNC Input Pull-Down Resistance 100 kΩ
Minimum On-time With Sense Resistor, 10mV Overdrive 170 ns

No R

Mode 300 ns

SENSE

3783fa

3

LTC3783

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TJ = 25°C.

= 12V, V

V

IN

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Low Dropout Regulator

V

INTVCC

UVLO INTVCC Undervoltage Lockout Rising INTV

∆V

INTVCC

∆V

IN

∆V

LDO(LOAD)

V

DROPOUT

I

INTVCC(SD)

GATE/PWMOUT Drivers

t

r(GATE)

t

f(GATE)

I

PK(GATE,RISE)

I

PK(GATE,FALL)

V

PWMIN

R

PWMIN

t

r(PWMOUT)

t

f(PWMOUT)

I

PK(PWMOUT,RISE)

I

PK(PWMOUT,FALL)

= 1.5V, V

RUN

INTVCC Regulator Output Voltage V

Thresholds Falling INTV

SYNC

= 0V, V

FBP

= V

, RT = 20k, unless otherwise specified.

REF

= 1.5V

OV/FB

CC
CC

●

6.5 7 7.5 V

2.3 2.5 V

1.8 2.1 V

Hysteresis 0.2 V

INTVCC Line Regulation 12V ≤ VIN ≤ 36V 2 6 mV/V

INTVCC Load Regulation 0 ≤ I
INTVCC Dropout Voltage VIN = 7V, I
Bootstrap Mode INTVCC Supply V

Current in Shutdown V

SENSE
SENSE

≤ 10mA –1 –0.1 %

INTVCC

= 10mA 300 500 mV

INTVCC

= 0V 25 µA
= 7V 15 µA

GATE Driver Output Rise Time CL = 3300pF (Note 7) 15 ns
GATE Driver Output Fall Time CL = 3300pF (Note 7) 8 ns
GATE Driver Peak Current Sourcing V
GATE Driver Peak Current Sinking V

= 0V 0.5 A

GATE

= 7V 1 A

GATE

PWMIN Pin Input Threshold Voltages Rising PWMIN 1.6 V

Falling PWMIN 0.8 V
Hysteresis 0.8 V

PWMIN Input Pull-Up Resistance 100 kΩ
PWMOUT Driver Output Rise Time CL = 3300pF (Note 7) 30 ns
PWMOUT Driver Output Fall Time CL = 3300pF (Note 7) 16 ns
PWMOUT Driver Peak Current Sourcing V
PWMOUT Driver Peak Current Sinking V

= 0V 0.25 A

PWMOUT

= 7V 0.50 A

PWMOUT

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: The LTC3783E is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the – 40°C to
85°C operating temperature range are assured by design, characterization
and correlation with statistical process controls.

Note 3: T
dissipation P

is calculated from the ambient temperature TA and power

J

according to the following formula:

D

T

= TA + (PD • 43°C/W) for the DFN

J

T

= TA + (PD • 38°C/W) for the TSSOP

J

Note 4: The dynamic input supply current is higher due to power MOSFET

• f

gate charging (Q
Note 5: The LTC3783 is tested in a feedback loop which servos V

= V

V

FBP

(0.3V ≤ V

with the ITH pin forced to the midpoint of its voltage range

VREF

≤ 1.2V; midpoint = 0.75V).

ITH

). See Operation section.

G

OSC

FBN

to

Note 6: In a synchronized application, the internal slope compensation is
increased by 25%. Synchronizing to a significantly higher ratio will reduce
the effective amount of slope compensation, which could result in sub­harmonic oscillation for duty cycles greater than 50%

Note 7: Rise and fall times are measured at 10% and 90% levels.

3783fa

4

UW

I

REF

(mA)

0

V

REF

(V)

1.231

1.233

1.235

4

3783 G03

1.229

1.227

1.225
1

2

3

5

VIN = 12V

VIN = 2.5V

TYPICAL PERFOR A CE CHARACTERISTICS

V

1.25

vs Temperature V

REF

1.235

Line Regulation V

REF

LTC3783

TA = 25°C unless otherwise specified

Load Regulation

REF

1.20

1.15

(V)

REF

V

1.10

1.05

1.00

1.6

1.4

1.2

1.0

0.8

(mA)

Q

I

0.6

0.4

0.2

0

–50

I

–75

0 50 100

TEMPERATURE (°C)

3783 G01

vs Temperature (PWMIN Low) Dynamic IQ vs Frequency

Q

–25 25 125

TEMPERATURE (°C)

75

3783 G04

150

175

1.233

1.231

(V)

REF

V

1.229

1.227

1.225
0

10

IQ vs VIN (PWMIN Low)

2.0

1.9

1.8

1.7

1.6

1.5

(mA)

Q

I

1.4

1.3

1.2

1.1

0

0

10 30

VIN (V)

20

VIN (V)

20

30

40

3783 G02

30

CL = 3300pF

= 1.3mA + QG • f

I

Q(TOT)

25

20

(mA)

Q

15

10

DYNAMIC I

5

0

50

40

3783 G05

0

0.5 1
FREQUENCY (MHz)

1.5

3783 G06

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

RUN THRESHOLDS (V)

0.8

0.7

0.6

RUN Thresholds vs V

RUN HIGH

RUN LOW

0

10

20

VIN (V)

IN

RUN Thresholds vs Temperature RT vs Frequency

1.40

1.38

1.36

1.34

1.32

1.30

1.28

RUN THRESHOLDS (V)

1.26

1.24

30

40

3783 G07

1.22
–50

0

RUN HIGH

RUN LOW

50

TEMPERATURE (°C)

100

150

3783 G08

1000

100

(kΩ)

T

R

10

1

1 100 1000 10000

10

FREQUENCY (kHz)

3783 G09

3783fa

5

LTC3783

UW

TYPICAL PERFOR A CE CHARACTERISTICS

TA = 25°C unless otherwise specified

Frequency vs Temperature Maximum V

350

340

330

320

310

300

290

FREQUENCY (kHz)

280

270

260

250

–50

INTV

CC

7.00

6.95

6.90

6.85

(V)

CC

6.80

INTV

6.75

6.70

6.55

6.50

0.02 0.04 0.06 0.08

0

0

50

TEMPERATURE (°C)

100

150

3783 G10

Load Regulation INTVCC Line Regulation

0.10 0.12 0.14 0.16

I

(mA)

INTVCC

3783 G13

(V)

SENSE

V

7.05

7.00

6.95

6.90

6.85

(V)

CC

6.80

INTV

6.75

6.70

6.65

6.60

6.55

160

158

156

154

152

150

148

146

144

142

140

–50

0

SENSE

0

TEMPERATURE (°C)

10

20

VIN (V)

vs Temperature

50

100

30

40

3783 G11

3783 G14

150

50

I

vs Temperature

SENSE

75

74

73

72

71

(µA)

70

SENSE

69

I

68

67

66

65

–50

INTV

CC

Over Temperature

(V)

CC

INTV

7.0

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

–50°C, –25°C, 0°C

0

0

50

TEMPERATURE (°C)

Load Regulation

25°C

75°C

100°C

125°C

150°C

50

I

INTVCC

100

(mA)

100

150

3783 G12

50°C

150

3783 G15

INTV
vs Temperature

7.20

7.15

7.10

(V)

CC

7.05

INTV

7.00

6.95

6.90
5

6

Line Regulation

CC

25°C

1510 20 25 3530 40

VIN (V)

150°C

–50°C

3783 G16

Soft-Start Current

I

SS

vs Temperature

50.0

49.8

49.6

49.4

49.2

49.0

48.8

48.6

48.4

SOFT-START CURRENT (µA)

48.2

48.0

47.8
–50

0

50

TEMPERATURE (°C)

100

3783 G17

150

Gate Rise/Fall Time
vs Capacitance

80

70

60

50

40

TIME (ns)

30

20

10

0

0

GATE TR

5

GATE TF

10

CAPACITANCE (nF)

15

20

3783 G18

3783fa

LTC3783

U

UU

PI FU CTIO S

FBN (Pin 1): Error Amplifier Inverting Input/Negative
Current Sense Pin. In voltage mode (V
pin senses feedback voltage from either the external
resistor divider across V

for output voltage regula-

OUT

tion, or the grounded sense resistor under the load for
output current regulation. In constant current/constant
voltage mode (V

> 2.5V), connect this pin to the

FBP

negative side of the current-regulating resistor. Nominal
voltage for this pin in regulation is either V
100mV) for V

= 1.23V, depending on operational

ILIM

mode (voltage or constant current/constant voltage) set
by the voltage at V

FBP

.

FBP (Pin 2): Error Amplifier Noninverting Input/Positive
Current Sense Pin. This pin voltage determines the control
loop’s feedback mode (voltage or constant current/con­stant voltage), the threshold of which is approximately 2V.
In voltage mode (V

FBP

≤ V

), this pin represents the

REF

desired voltage which the regulated loop will cause FBN to
follow. In constant current/constant voltage mode (V

2.5V), connect this pin to the positive side of the load
current-sensing resistor. The acceptable input ranges for
this pin are 0V to 1.23V (voltage mode) and 2.5V to 36V
(constant current/constant voltage mode).

(Pin 3): Current Limit Pin. Sets current sense resistor

I

LIM

offset voltage (V
regulation (i.e., when V
100mV when V
with V

. Nominal voltage range for this pin is 0.1V to

ILIM

– V

FBP

= 1.23V and decreases proportionally

ILIM

) in constant current mode

FBN

> 2.5V). Offset voltage is

FBP

1.23V.

V

(Pin 4): Reference Voltage Pin. Provides a buffered

REF

version of the internal bandgap voltage, which can be
connected to FBP either directly or with attenuation.
Nominal voltage for this pin is 1.23V. This pin should never
be bypassed by a capacitor to GND. Instead, a 10k resistor
to GND should be used to lower pin impedance in noisy
systems.

FREQ (Pin 5): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nomi­nal voltage at the FREQ pin is 0.615V.

SYNC (Pin 6): This input allows for synchronizing the
operating frequency to an external clock and has an
internal 100k pull-down resistor.

FBP

≤ V

FBP

VREF

or (V

), this

FBP

>

FBP

–

PWMIN (Pin 7): PWM Gate Driver Input. Internal 100k
pull-up resistor. While PWMIN is low, PWMOUT is low,
GATE stops switching and the external I
disconnected, saving the I

TH

state.

network is

TH

PWMOUT (Pin 8): PWM Gate Driver Output. Used for
constant current dimming (LED load) or for output discon­nect (step-up power supply).

GATE (Pin 9): Main Gate Driver Output for the Boost
Converter.

INTVCC (Pin 10): Internal 7V Regulator Output. The main
and PWM gate drivers and control circuits are powered
from this voltage. Decouple this pin locally to the IC
ground with a minimum of 4.7µF low ESR ceramic
capacitor.

VIN (Pin 11): Main Supply Pin. Must be closely decoupled
to ground.

SENSE (Pin 12): Current Sense Input for the Control
Loop. Connect this pin to the drain of the main power
MOSFET for V

sensing and highest efficiency for V

DS

SENSE

≤ 36V. Alternatively, the SENSE pin may be connected to
a resistor in the source of the main power MOSFET.
Internal leading-edge blanking is provided for both sens­ing methods.

SS (Pin 13): Soft-Start Pin. Provides a 50µA pull-up
current, enabled and reset by RUN, which charges an
optional external capacitor. This voltage ramp translates
into a corresponding current limit ramp through the main
MOSFET.

OV/FB (Pin 14): Overvoltage Pin/Voltage Feedback Pin. In
voltage mode (V

FBP

≤ V

), this input, connected to V

REF

OUT

through a resistor network, sets the output voltage at
which GATE switching is disabled in order to prevent an
overvoltage situation. Nominal threshold voltage for the
OV pin is 1.32V (V
current/voltage mode (V

+ 7%) with 20mV hysteresis. In

REF

> 2.5V), this pin senses V

FBP

OUT

through a resistor divider and brings the loop into voltage
regulation such that pin voltage approaches V

= 1.23V,

REF

provided the loop is not regulating the load current (e.g.,
[V

FBP

– V

] < 100mV for I

FBN

= 1.23V).

LIM

3783fa

7

LTC3783

U

UU

PI FU CTIO S

ITH (Pin 15): Error Amplifier Output/Compensation Pin. The
current comparator input threshold increases with this
control voltage, which is the output of the g

type error

m

amplifier. Nominal voltage range for this pin is 0V to 1.40V.

RUN (Pin 16): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro­gramming the start-up threshold for the converter. The

W

BLOCK DIAGRA

SLOPE

COMP

FREQ

5

SYNC

6

OSCV-TO-I

falling RUN pin threshold is nominally 1.248V and the
comparator has 100mV hysteresis for noise immunity.
When the RUN pin is grounded, the IC is shut down and the
V

supply current is kept to a low value (20µA typ).

IN

Exposed Pad (Pin 17): Ground Pin. Solder to PCB ground
for electrical contact and rated thermal performance.

V

REF

GND

GATE

4

17

9

CLK

BIAS

S

Q0.615V

R

SS_RESET

V

REF

LOGIC

3

2

1

14

13

15

7

10

I

LIM

FBP

FBN

OV/FB

SS

I

TH

PWMIN

INTV

1.9V

CC

IVMODE

–
+

EA

A

–
–

+

V

REF

OV/FB

1

S

+

OV

V

–

REF

0.2V

TEMP

SENSOR

(165°C)

+

OT

SLEEP

ITRIP

+

SENSE

12

–

–

+

0

–

LDO

V

REF

2.23V

50µA

IMAX

V-TO-I

EN

+

UV

–

BIAS AND
START-UP

+
–

PWMOUT

+
–

0.15V

V

REF

RUN

V

8

16

IN

11

8

3738 BD

3783fa

OPERATIO

LTC3783

U

Main Control Loop

The LTC3783 is a constant frequency, current mode
controller for PWM LED as well as DC/DC boost, SEPIC
and flyback converter applications. In constant current
LED applications, the LTC3783 provides an especially
wide PWM dimming range due to its unique switching
scheme, which allows PWM pulse widths as short as
several converter switching periods.

For voltage feedback circuit operation (defined by V

FBP

≤

1.23V), please refer to the Block Diagram of the IC and the
Typical Application on the first page of this data sheet. In
normal operation with PWMIN high, the power MOSFET is
turned on (GATE goes high) when the oscillator sets the
PWM latch, and is turned off when the ITRIP current
comparator resets the latch. Based on the error voltage
represented by (V
signal at the I

TH

FBP

– V

), the error amplifier output

FBN

pin sets the ITRIP current comparator
input threshold. When the load current increases, a fall in
the FBN voltage relative to the reference voltage at FBP
causes the ITH pin to rise, causing the ITRIP current com­parator to trip at a higher peak inductor current value. The
average inductor current will therefore rise until it equals
the load current, thereby maintaining output regulation.

When PWMIN goes low, PWMOUT goes low, the I

TH

switch opens and GATE switching is disabled. Lowering
PWMOUT and disabling GATE causes the output capacitor

to hold the output voltage constant in the absence of

C

OUT

load current. Opening the I
load current value on the I
when PWMIN goes high again, both I

switch stores the correct

TH

capacitor C

TH

. As a result,

ITH

and V

TH

OUT

are

instantly at the appropriate levels.

In voltage feedback operation, an overvoltage compara­tor, OV, senses when the OV/FB pin exceeds the reference
voltage by 7% and provides a reset pulse to the main RS
latch. Because this RS latch is reset-dominant, the power
MOSFET is actively held off for the duration of an output
overvoltage condition.

For constant current/constant voltage regulation opera­tion (defined by V

> 2.5V), please refer to the Block

FBP

Diagram of the IC and Figure 11. Loop operation is similar
to the voltage feedback, except FBP and FBN now sense
the voltage across sense resistor RL in series with the load.
The I
differential set voltage, from 10mV to 100mV, for I
values of 0.123V to 1.23V. That is, with V
loop will regulate such that V
values of I

pin now represents the error from the desired

TH

= 1.23V, the

ILIM

– V

FBP

attenuate the difference proportionally.

LIM

= 100mV; lower

FBN

LIM

PWMIN is still functional as above, but will only work
properly if load current can be disconnected by the
PWMOUT signal.

In constant current/constant voltage operation, the OV/FB
pin becomes a voltage feedback pin, which causes the
loop to regulate such that V

= 1.23V, provided the

OV/FB

above current-sense voltage is not reached. In this way,
the loop regulates either voltage or current, whichever
parameter hits its preset limit first.

The nominal operating frequency of the LTC3783 is pro­grammed using a resistor from the FREQ pin to ground
and can be controlled over a 20kHz to 1MHz range. In
addition, the internal oscillator can be synchronized to an
external clock applied to the SYNC pin and can be locked
to a frequency between 100% and 130% of its nominal
value. When the SYNC pin is left open, it is pulled low by
an internal 100k resistor. With no load, or an extremely
light one, the controller will skip pulses in order to main­tain regulation and prevent excessive output ripple.

The RUN pin controls whether the IC is enabled or is in a
low current shutdown state. A micropower 1.248V refer­ence and RUN comparator allow the user to program the
supply voltage at which the IC turns on and off (the RUN
comparator has 100mV of hysteresis for noise immunity).
With the RUN pin below 1.248V, the chip is off and the
input supply current is typically only 20µA.

3783fa

9

LTC3783

OPERATIO

U

The SS pin provides a soft-start current to charge an
external capacitor. Enabled by RUN, the soft-start current
is 50µA, which creates a positive voltage ramp on V
which the internal I
currents on start-up. Once V

is limited, avoiding high peak

TH

reaches 1.23V, the full I

SS

SS

to

TH

range is established.

The LTC3783 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the
SENSE pin to a conventional shunt resistor in the source
of the power MOSFET, as shown in the Typical Application
on the first page of this data sheet. Sensing the voltage
across the power MOSFET maximizes converter efficiency
and minimizes the component count, but limits the output
voltage to the maximum rating for this pin (36V). By
connecting the SENSE pin to a resistor in the source of the
power MOSFET, the user is able to program output volt­ages significantly greater than 36V, limited only by other
components’ breakdown voltages.

Externally Synchronized Operation

When an external clock signal drives the SYNC pin at a rate
faster than the chip’s internal oscillator, the oscillator will
synchronize to it. When the oscillator’s internal logic
circuitry detects a synchronizing signal on the SYNC pin,
the internal oscillator ramp is terminated early and the
slope compensation is increased by approximately 25%.
As a result, in applications requiring synchronization, it is
recommended that the nominal operating frequency of the
IC be programmed to be about 80% of the external clock
frequency. Attempting to synchronize to too high an
external frequency (above 1.3f

) can result in inad-

OSC

equate slope compensation and possible subharmonic
oscillation (or jitter).

The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 1. The MOSFET turn-on will synchronize to the
rising edge of the external clock signal.

MODE/

SYNC

GATE

I

L

Figure 1. MODE/SYNC Clock Input and Switching Waveforms
for Synchronized Operation

t

MIN

= 25ns

D = 40%

0.8T

T T = 1/f

2V TO 7V

O

3783 F01

MOSFET and diode switching losses. However, lower
frequency operation requires more inductance for a given
amount of load current.

The LTC3783 uses a constant frequency architecture that
can be programmed over a 20kHz to 1MHz range with a
single external resistor from the FREQ pin to ground, as
shown in the application on the first page of this data
sheet. The nominal voltage on the FREQ pin is 0.615V, and
the current that flows out of the FREQ pin is used to charge
and discharge an internal oscillator capacitor. The oscil­lator frequency is trimmed to 300kHz with R
graph for selecting the value of R

for a given operating

T

= 20k. A

T

frequency is shown in Figure 2.

1000

100

(kΩ)

T

R

10

Programming the Operating Frequency

The choice of operating frequency and inductor value is a
tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing

10

1

1 100 1000 10000

Figure 2. Timing Resistor (R

10

FREQUENCY (kHz)

3783 G09

) Value

T

3783fa

OPERATIO

LTC3783

U

INTVCC Regulator Bypassing and Operation

An internal, P-channel low dropout voltage regulator pro­duces the 7V supply which powers the gate drivers and
logic circuitry within the LTC3783 as shown in Figure 3.
The INTV

regulator can supply up to 50mA and must be

CC

bypassed to ground immediately adjacent to the IC pins
with a minimum of 4.7µF low ESR or ceramic capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate driver.

For input voltages that don’t exceed 8V (the absolute
maximum rating for INTVCC is 9V), the internal low drop­out regulator in the LTC3783 is redundant and the INTV
pin can be shorted directly to the VIN pin. With the INTV

CC
CC

pin shorted to VIN, however, the divider that programs the
regulated INTV

voltage will draw 15µA from the input

CC

supply, even in shutdown mode. For applications that
require the lowest shutdown mode input supply current,
do not connect the INTVCC pin to VIN. Regardless of
whether the INTV

pin is shorted to VIN or not, it is always

CC

necessary to have the driver circuitry bypassed with a

4.7µF low ESR ceramic capacitor to ground immediately
adjacent to the INTVCC and GND pins.

In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
As a result, high input voltage applications in which a large
power MOSFET is being driven at high frequencies can
cause the LTC3783 to exceed its maximum junction tem­perature rating. The junction temperature can be esti­mated using the following equations:

= IQ + f • Q

I

Q(TOT)

G

PIC = VIN • (IQ + f • QG)

= TA + PIC • θ

T

J

The total quiescent current I
supply current (I

JA

consists of the static

Q(TOT)

) and the current required to charge and

Q

discharge the gate of the power MOSFET. The 16-lead FE
package has a thermal resistance of θ
DHD package has an θ

= 43°C/W

JA

As an example, consider a power supply with V
and V

= 25V at I

OUT

= 1A. The switching frequency is

OUT

= 38°C/W and the

JA

= 12V

IN

300kHz, and the maximum ambient temperature is 70°C.
The power MOSFET chosen is the Si7884DP, which has a
maximum R

of 10mΩ (at room temperature) and a

DS(ON)

V

IN

1.230V

R2 R1

–

DRIVER

P-CH

7V

INTV

GATE

GND

CC

C

VCC

4.7µF
X5R

PLACE AS CLOSE AS

3783 F03

POSSIBLE TO DEVICE PINS

+

LOGIC

Figure 3. Bypassing the LDO Regulator and Gate Driver Supply

INPUT
SUPPLY
6V TO 36V

C

IN

6V-RATED

M1

POWER
MOSFET

GND

3783fa

11

LTC3783

OPERATIO

U

maximum total gate charge of 35nC (the temperature
coefficient of the gate charge is low).

= 1.2mA + 35nC • 300kHz = 12mA

I

Q(TOT)

P

= 12V • 12mA = 144mW

IC

T

= 70°C + 110°C/W • 144mW = 86°C

J

This demonstrates how significant the gate charge current
can be when compared to the static quiescent current in
the IC.

To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in a continuous mode at high VIN. A tradeoff
between the operating frequency and the size of the power
MOSFET may need to be made in order to maintain a
reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with the
power MOSFET manufacturers for the latest low Q
R

devices. Power MOSFET manufacturing tech-

DS(ON)

, low

G

nologies are continually improving, with newer and better­performing devices being introduced almost monthly.

Output Voltage Programming

In constant voltage mode, in order to regulate the output
voltage, the output voltage is set by a resistor divider
according to the following formula:

R

VV

=+

OUT FBP

where 0 ≤ V

⎛

•1

⎜

⎝

≤ 1.23V. The external resistor divider is

FBP

2

⎞
⎟

⎠

R

1

connected to the output as shown in Figure 4, allowing
remote voltage sensing. The resistors R1 and R2 are
typically chosen so that the error caused by the 500nA
input bias current flowing out of the FBN pin during
normal operation is less than 1%, which translates to a
maximum R1 value of about 25k at V

= 1.23V. For

FBP

lower FBP voltages, R1 must be reduced accordingly to
maintain accuracy, e.g., R1 < 2k for 1% accuracy when
V

= 100mV. More accuracy can be achieved with lower

FBP

resistances, at the expense of increased dissipation and
decreased light load efficiency.

A similar analysis applies to the V

resistive divider, if

FBP

one is used:

R

VV

=

FBP REF

3

•
RR

+

34

where R3 is subject to a similar 500nA bias current.

V

IN

LTC3783

RUN
PWMIN
I

TH

R4

R3

Figure 4. LTC3783 Boost Application

SS
V

REF

FBP
FBN
FREQ
SYNC

V

OV/FB

PWMOUT

I

LIM

GATE

SENSE

INTV

GND

IN

CC

3V TO 36V

R2

R1

3783 F04

V

OUT

GND

Programming Turn-On and Turn-Off Thresholds
with the RUN Pin

The LTC3783 contains an independent, micropower volt­age reference and comparator detection circuit that re­mains active even when the device is shut down, as shown
in Figure 5. This allows users to accurately program an
input voltage at which the converter will turn on and off.
The falling threshold on the RUN pin is equal to the internal
reference voltage of 1.248V. The comparator has 100mV
of hysteresis to increase noise immunity.

The turn-on and turn-off input voltage thresholds are
programed using a resistor divider according to the fol­lowing formulas:

2

R

VV

IN OFF

()

VV

IN ON

()

1 248 1

.•

=+

1 348 1

=+

.•

⎛
⎜

⎝

⎛
⎜

⎝

⎞
⎟

⎠

1

R

2

R

⎞
⎟

⎠

1

R

The resistor R1 is typically chosen to be less than 1M.

12

3783fa

OPERATIO

EXTERNAL

LOGIC CONTROL

U

V

+

R2

INPUT

SUPPLY

OPTIONAL

FILTER

CAPACITOR

R1

–

Figure 5a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

RUN

RUN

6V

1.248V

COMPARATOR

+

–

3483 F05b

IN

RUN

GND

6V

1.248V

µPOWER

REFERENCE

+

–

INPUT

SUPPLY

RUN

COMPARATOR

+

R2

1M

–

BIAS AND

START-UP

CONTROL

3783 F05a

V

IN

RUN

GND

6V

1.248V

LTC3783

COMPARATOR

+

–

3483 F05c

RUN

Figure 5b. On/Off Control Using External Logic

For applications where the RUN pin is only to be used as
a logic input, the user should be aware of the 7V Absolute
Maximum Rating for this pin! The RUN pin can be con­nected to the input voltage through an external 1M resis­tor, as shown in Figure 5c, for “always on” operation.

Soft-Start Capacitor Selection

For proper soft-start operation, the LTC3783 should have
a sufficiently large soft-start capacitor, CSS, attached to
the SS pin. The minimum soft-start capacitor size can be
estimated on the basis of output voltage, capacitor size
and load current. In addition, PWM operation reduces the
effective SS capacitor value by the dimming ratio.

C

SS MIN

>

()

• dimmin • • • •

g ratio A C V R

µ250

OUT OUT DS ON SENSE

mV V

•.

150 1 2

()/

Figure 5c. External Pull-Up Resistor on
RUN Pin for “Always On” Operation

assuming 50% ripple current, where R
sents either the R
R

, whichever is used on the SENSE pin. Dimming

SENSE

ratio is described by 1/D

of the switching MOSFET or

DS(ON)

as shown in Figure 6.

PWM

DS(ON)/SENSE

repre-

Application Circuits

A basic LTC3783 PWM-dimming LED application is shown
on the first page of this data sheet.

Operating Frequency and PWM Dimming Ratio

The minimum operating frequency, f

, required for

OSC

proper operation of a PWM dimming application depends
on the minimum PWM frequency, f
1/D

, and N, the number of f

PWM

Nf

•

f

OSC

PWM

>

D

PWM

OSC

, the dimming ratio

PWM

cycles per PWM cycle:

3783fa

13

LTC3783

OPERATIO

U

Figure 6 illustrates these various quantities in relation to
one another.

Typically, in order to avoid visible flicker, f

should be

PWM

greater than 120Hz. Assuming inductor and capacitor
sizing which is close to discontinuous operation, 2 f

OSC

cycles are sufficient for proper PWM operation. Thus,
within the 1MHz rated maximum f
1/D

PWMIN

GATE

= 3000 is possible.

PWM

D

PWM/fPWM

# = N

1/f

OSC

Figure 6. PWM Dimming Parameters

1/f

PWM

, a dimming ratio of

OSC

3783 F06

Boost Converter: Duty Cycle Considerations

For a boost converter operating in a continuous conduc­tion mode (CCM), the duty cycle of the main switch is:

output current needs to be reflected back to the input in
order to dimension the power MOSFET properly. Based on
the fact that, ideally, the output power is equal to the input
power, the maximum average input current is:

I

()

I

()

IN MAX

OUT MAX

D

–=1

MAX

The peak input current is:

I

χ

⎛

⎞

OUT MAX

I

IN PEAK

=+

()

⎜

⎝

1

⎟

⎠

21

The maximum duty cycle, D
minimum V

IN

.

Boost Converter: Ripple Current ∆I

•

()

D

–

MAX

MAX

, should be calculated at

and the ‘χ’ Factor

L

The constant ‘χ’ in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 30% ripple
current is chosen, then χ = 0.3, and the peak current is
15% greater than the average.

VVV

++–

OUT D IN

D

=

VV

OUT D

where VD is the forward voltage of the boost diode. For
converters where the input voltage is close to the output
voltage, the duty cycle is low, and for converters that
develop a high output voltage from a low input voltage, the
duty cycle is high. The maximum output voltage for a
boost converter operating in CCM is:

V

()

V

OUT MAX

IN MIN

D

––=1

MAX

V

D()

The maximum duty cycle capability of the LTC3783 is
typically 90%. This allows the user to obtain high output
voltages from low input supply voltages.

Boost Converter: The Peak and Average Input Currents

The control circuit in the LTC3783 is measuring the input
current (either by using the R

of the power MOSFET

DS(ON)

or by using a sense resistor in the MOSFET source), so the

For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50% in order to avoid subharmonic oscillation. For the
LTC3783, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
used, the resulting current ramp (∆I

) will be small relative

L

to the internal ramp compensation (at duty cycles above
50%), and the converter operation will approach voltage
mode (ramp compensation reduces the gain of the current
loop). If too small an inductor is used, but the converter is
still operating in CCM (near critical conduction mode), the
internal ramp compensation may be inadequate to prevent
subharmonic oscillation. To ensure good current mode
gain and to avoid subharmonic oscillation, it is recom­mended that the ripple current in the inductor fall in the
range of 20% to 40% of the maximum average current. For
example, if the maximum average input current is 1A,
choose a ∆I

between 0.2A and 0.4A, and correspondingly

L

a value ‘χ’ between 0.2 and 0.4.

14

3783fa

OPERATIO

LTC3783

U

Boost Converter: Inductor Selection

Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:

L

=

where

∆ =

I

V

⎛

IN MIN

⎜

∆

⎝

:

L

⎞

()

⎟

•

If

⎠

L

•χ

I

OUT

(

D)–1

MAX

•

D

MMAX

MAX

Remember that most boost converters are not short­circuit protected. Under a shorted output condition, the
inductor current is limited only by the input supply capa­bility. For applications requiring a step-up converter that is
short-circuit protected, please refer to the applications
section covering SEPIC converters.

The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:

I

L SAT

()

⎛

>+

⎜

⎝

1

21

⎞

•

⎟

⎠

OUT MAX

()

D

–

MAX

I

χ

The saturation current rating for the inductor should be
checked at the minimum input voltage (which results in the
highest inductor current) and maximum output current.

Boost Converter: Operating in Discontinuous Mode

Discontinuous mode operation occurs when the load
current is low enough to allow the inductor current to run
out during the off-time of the switch, as shown in Figure 7.
Once the inductor current is near zero, the switch and
diode capacitances resonate with the inductance to form
damped ringing at 1MHz to 10MHz. If the off-time is long
enough, the drain voltage will settle to the input voltage.

Depending on the input voltage and the residual energy in
the inductor, this ringing can cause the drain of the power
MOSFET to go below ground where it is clamped by the
body diode. This ringing is not harmful to the IC and it has

OUTPUT

VOLTAGE

200mV/DIV

INDUCTOR

CURRENT

1A/DIV

MOSFET

DRAIN

VOLTAGE

20V/DIV

1µs/DIV

Figure 7. Discontinuous Mode Waveforms

3783 F07

not been shown to contribute significantly to EMI. Any
attempt to damp it with a snubber will degrade the
efficiency.

Boost Converter: Power MOSFET Selection

The power MOSFET can serve two purposes in the LTC3783:
it represents the main switching element in the power
path, and its R

can represent the current sensing

DS(ON)

element for the control loop. Important parameters for the
power MOSFET include the drain-to-source breakdown
voltage BV
resistance R
gate-to-source and gate-to-drain charges Q
respectively, the maximum drain current I
MOSFET’s thermal resistances θ

The gate drive voltage is set by the 7V INTV

, the threshold voltage V

DSS

versus gate-to-source voltage, the

DS(ON)

JC

GS(TH)

and θJA.

, the on-

and QGD,

GS

D(MAX)

low drop

CC

and the

regulator. Consequently, 6V rated MOSFETs are required
in most high voltage LTC3783 applications. If low input
voltage operation is expected (e.g., supplying power from
a lithium-ion battery or a 3.3V logic supply), then sublogic­level threshold MOSFETs should be used. Pay close atten­tion to the BV

specifications for the MOSFETs relative

DSS

to the maximum actual switch voltage in the application.
Many logic-level devices are limited to 30V or less, and the
switch node can ring during the turn-off of the MOSFET
due to layout parasitics. Check the switching waveforms
of the MOSFET directly across the drain and source
terminals using the actual PC board layout for excessive
ringing.

3783fa

15

LTC3783

OPERATIO

U

During the switch on-time, the IMAX comparator limits the
absolute maximum voltage drop across the power
MOSFET to a nominal 150mV, regardless of duty cycle.
The peak inductor current is therefore limited to
150mV/R
load current, duty cycle, and the R

. The relationship between the maximum

DS(ON)

of the power

DS(ON)

MOSFET is:

D

–

1

RmV

DS ON

()

<

150

•

χ

⎛

+

1

⎜

⎝

2

MAX

⎞

I

••

⎟

OUT MAX T

⎠

()

ρ

The ρT term accounts for the temperature coefficient of the
R
ure 8 illustrates the variation of normalized R

of the MOSFET, which is typically 0.4%/°C. Fig-

DS(ON)

DS(ON)

over

temperature for a typical power MOSFET.

Another method of choosing which power MOSFET to use
is to check what the maximum output current is for a given
R

, since MOSFET on-resistances are available in

DS(ON)

discrete values.

the maximum current drawn from the input supply, and
also to avoid triggering the 150mV IMAX comparator, as
this condition can result in excessive noise.

Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures

In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be
known. This power dissipation is a function of the duty
cycle, the load current, and the junction temperature itself
(due to the positive temperature coefficient of its R

DS(ON)

).
As a result, some iterative calculation is normally required
to determine a reasonably accurate value. Since the con­troller is using the MOSFET as both a switching and a
sensing element, care should be taken to ensure that the
converter is capable of delivering the required load current
over all operating conditions (line voltage and tempera­ture), and for the worst-case specifications for V
and the R

of the MOSFET listed in the manufacturer’s

DS(ON)

SENSE(MAX)

data sheet.

D

–

1

ImV

OMAX

=

()

150

•

⎛

+

1

⎜

⎝

It is worth noting that the 1 - D
I

O(MAX)

and R

can cause boost converters with a

DS(ON)

MAX

χ

⎞

R

••

DS ON T

⎟

⎠

2

()

relationship between

MAX

ρ

wide input range to experience a dramatic range of maxi­mum input and output currents. This should be taken into
consideration in applications where it is important to limit

2.0

1.5

1.0

0.5

NORMALIZED ON RESISTANCE

T

ρ

0

–50

Figure 8. Normalized R

0

JUNCTION TEMPERATURE (°C)

50

DS(ON)

100

vs Temperature

150

3783 F08

The power dissipated by the MOSFET in a boost converter
is:

MAX

2

⎞

RD

•••

DS ON MAX T

I

⎛

OUT MAX

⎜

1

⎝

()

⎞

()

⎟

D

⎠

MAX

⎟
⎠

185

.

ρ

+

Cf

RSS

P

FET

I

⎛

OUT MAX

=

()

⎜

D

–

1

⎝

kV

••–••

OUT

The first term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses. The constant k = 1.7 is an empirical factor inversely
related to the gate drive current and has the dimension of
1/current.

From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:

= TA + P

T

J

FET

• θ

JA

The θJA to be used in this equation normally includes the

θ

for the device plus the thermal resistance from the

JC

case to the ambient temperature (θCA). This value of TJ can
then be compared to the original, assumed value used in
the iterative calculation process.

3783fa

16

U

OPERATIO

Boost Converter: Output Diode Selection

LTC3783

To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desired. The
output diode in a boost converter conducts current during
the switch off-time. The peak reverse voltage that the
diode must withstand is equal to the regulator output
voltage. The average forward current in normal operation
is equal to the output current, and the peak current is equal
to the peak inductor current.

I

χ

⎛

⎞

OUT MAX

II

D PEAK L PEAK

()()

==+

1

⎜

⎝

⎟

⎠

21

•

()

D

–

MA

XX

The power dissipated by the diode is:

P

D

= I

OUT(MAX)

• V

D

and the diode junction temperature is:

T

= TA + PD • θ

J

JA

The θJA to be used in this equation normally includes the

for the device plus the thermal resistance from the

θ

JC

board to the ambient temperature in the enclosure.

Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased
dissipation.

V

OUT

(AC)

∆V

COUT

∆V

ESR

RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)

Figure 9. Output Ripple Voltage

3783 F09

ESR step and the charging/discharging ∆V. This percent­age ripple will change, depending on the requirements of
the application, and the equations provided below can
easily be modified.

For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:

V

ESR

where

I

IN PEAK

<=0011.•

COUT

:

⎛

()

⎜

⎝

++

OUT

I

IN PEAK

()

I

χ

⎞

OUT MAX

⎟

⎠

21•–

()

D

MAX

For the bulk C component, which also contributes 1% to
the total ripple:

Boost Converter: Output Capacitor Selection

Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct compo­nent for a given output ripple voltage. The effects of these
three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform are illustrated in Figure 9 for a
typical boost converter.

The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the

I

()

>

OUT MAX

.• •001

Vf

OUT

C

OUT

For many designs it is possible to choose a single capaci­tor type that satisfies both the ESR and bulk C require­ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR setup, while an electrolytic capacitor
can be used to supply the required bulk C.

Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board

3783fa

17

LTC3783

L

V

If

D

V

AMHz

µH

IN MIN

L

MAX

== =

()

•

•
.•

•.

∆

12

06 1

053 11

OPERATIO

U

Layout section for more information on component place­ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.

The output capacitor in a boost regulator experiences high
RMS ripple currents. The RMS output capacitor ripple
current is:

II

RMS COUT OUT MAX



() ()

•

OUT IN MIN

V

IN MIN

()

()

VV

–

Note that the ripple current ratings from capacitor manu­facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.

Boost Converter: Input Capacitor Selection

Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to the
input of the converter, and solid tantalum capacitors can
fail catastrophically under these conditions. Be sure to
specify surge-tested capacitors!

Boost Converter Design Example

The design example given here will be for the circuit shown
in Figure 1. The input voltage is 12V, and the output voltage
is 25V at a maximum load current of 0.7A (1A peak).

1. The duty cycle is:

VVV

OUT D IN

D

=

+

–.–

VV

+

OUT D

+

25 0 4 12

=

+

25 0 4

=

%

53

.

2. The operating frequency is chosen to be 1MHz to
maximize the PWM dimming range. From Figure 2, the
resistor from the FREQ pin to ground is 6k.

3. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is also
the minimum saturation current) is:

The input capacitor of a boost converter is less critical than
the output capacitor, due to the fact that the inductor is in
series with the input, and hence, the input current wave­form is continuous (see Figure 10). The input voltage
source impedance determines the size of the input capaci­tor, which is typically in the range of 10µF to 100µF. A low
ESR capacitor is recommended, although it is not as
critical as for the output capacitor.

The RMS input capacitor ripple current for a boost con­verter is:

V

IN MIN

I

RMS CIN

.•

I

L

Figure 10. Inductor and Input Currents

()

Lf

•

D

• 03

MAX()

I

IN

I

IN PEAK

()

⎛

=+

⎜

⎝

I

⎞

OUT MAX

•

⎟

⎠

21

D

–

()

MAX

The inductor ripple current is:

I

OUT MAX

∆ =

IL

()

D

−

1

MAX

=

04

And so the inductor value is:

4. R

R

SENSE

SENSE

should be:

.•

V

05

SENSE MAX

==

I

IN PEAK

()

()

.•

=1

12

1053

.

07

.

−

1053

.•

0 5 150

.

1

8842A

.

0χ

–.

=

06

mV

77

18

.= A

Aχ •.•

.

m= Ω

18

3783fa

OPERATIO

LTC3783

U

5. The diode for this design must handle a maximum DC
output current of 0.7A and be rated for a minimum reverse
voltage of V

, or 25V. A 1A, 40V diode from Zetex was

OUT

chosen for its specifications, especially low leakage at
higher temperatures, which is important for maintaining
dimming range.

6. Voltage and value permitting, the output capacitor
usually consists of some combination of low ESR ceram­ics. Based on a maximum output ripple voltage of 1%, or
250mV, the bulk C needs to be greater than:

I

OUT MAX

C

>=

OUT

()

.• •..• •001

Vf

OUT

07

A

001 25 1

VMHz

==µ3F

The RMS ripple current rating for this capacitor needs to
exceed:

II

RMS COUT OUT MAX

() ()

007

=

=

25 12

–.AVV

12

•

V

OUT IN MIN

07.•

A=

V

IN MIN

()

()

VV

–

Based on value and ripple current, and taking physical size
into account, a surface mount ceramic capacitor is a good
choice. A 4.7µF TDK C5750X7R1H475M will satisfy all
requirements in a compact package.

7. The soft-start capacitor should be:

C

SS MIN

•dimmin • • • •

>

()

•••.••

2 3000 50 4 7 25

>

gratio A C V R

µµ

150 1 2

µ250

OUT OUT DS

mV V

150 1 2

AFV

mV V

•.

•.
442

m

Ω

8

=µ

(

OON SENSE

)/

F

8. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design and lab setup, 20µF was found to
be satisfactory.

PC Board Layout Checklist

1. In order to minimize switching noise and improve
output load regulation, the GND pad of the LTC3783
should be connected directly to 1) the negative terminal of

the INTV

decoupling capacitor, 2) the negative terminal

CC

of the output decoupling capacitors, 3) the bottom termi­nals of the sense resistors or the source of the power
MOSFET, 4) the negative terminal of the input capacitor,
and 5) at least one via to the ground plane immediately
under the exposed pad. The ground trace on the top layer
of the PC board should be as wide and short as possible
to minimize series resistance and inductance.

2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and use
the input capacitor to avoid excess input ripple for high
output current power supplies. If the ground plane is to be
used for high DC currents, choose a path away from the
small-signal components.

3. Place the C
INTV

and GND pins on the IC package. This capacitor

CC

capacitor immediately adjacent to the

VCC

carries high di/dt MOSFET gate-drive currents. A low ESR
and ESL 4.7µF ceramic capacitor works well here.

4. The high di/dt loop from the bottom terminal of the
output capacitor, through the power MOSFET, through the
boost diode and back through the output capacitors should
be kept as tight as possible to reduce inductive ringing.
Excess inductance can cause increased stress on the
power MOSFET and increase HF noise on the output. If low
ESR ceramic capacitors are used on the output to reduce
output noise, place these capacitors close to the boost
diode in order to keep the series inductance to a minimum.

5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device ter­minals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware of
inductive ringing which can exceed the maximum speci­fied voltage rating of the MOSFET. If this ringing cannot be
avoided and exceeds the maximum rating of the device,
either choose a higher voltage device or specify an ava­lanche-rated power MOSFET.

6. Place the small-signal components away from high
frequency switching nodes. All of the small-signal compo­nents should be placed on one side of the IC and all of the
power components should be placed on the other. This
also allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents flow

3783fa

19

LTC3783

OPERATIO

U

out of the IC ground pad in one direction (to bottom plate
of the INTV

decoupling capacitor) and small-signal

CC

currents flow in the other direction.

7. If a sense resistor is used in the source of the power
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC3783 contains an internal leading-edge blanking time
of approximately 160ns, which should be adequate for
most applications.

8. For optimum load regulation and true remote sensing,
the top of the output resistor should connect indepen­dently to the top of the output capacitor (Kelvin connec­tion), staying away from any high dV/dt traces. Place the
divider resistors near the LTC3783 in order to keep the
high impedance FBN node short.

9. For applications with multiple switching power convert­ers connected to the same input supply, make sure that the
input filter capacitor for the LTC3783 is not shared with
any other converters. AC input current from another
converter could cause substantial input voltage ripple, and
this could interfere with the operation of the LTC3783. A
few inches of PC trace or wire (L ~ 100nH) between the C

IN

of the LTC3783 and the actual source VIN should be
sufficient to prevent current-sharing problems.

Returning the Load to V

: A Single Inductor

IN

Buck-Boost Application

As shown in Figure 11, due to its available high side
current sensing mode, the LTC3783 is also well-suited to
a boost converter in which the load current is returned to

, hence providing a load voltage (V

V

IN

be greater or less than the input voltage V

– VIN) which can

OUT

. This configu-

IN

ration allows for complete overlap of input and output
voltages, with the disadvantages that only the load cur­rent, and not the load voltage, can be tightly regulated. The
switch must be rated for a V

DS(MAX)

equal to VIN + V

LOAD

.

The design of this circuit resembles that of the boost
converter above, and the procedure is much the same,
except V

is now (VIN + V

OUT

), and the duty cycles and

LOAD

voltages must be adjusted accordingly.

Similar to the boost converter, which can be dimmed via
the digital PWMIN input or the analog FBP pin, the buck­boost can be dimmed via the PWMIN pin or the analog
I

pin, which adjusts the offset voltage to which the

LIM

loop will drive (V

FBP

– V

). In the case of the buck-

FBN

boost, however, the dimming ratio cannot be as high as
in the boost converter, since there is no load switch to
preserve the V

level while PWMIN is low.

OUT

V

IN

9V TO 26V

R

L

0.28Ω

LED STRING 1-4 EA
LUMILEDS LHXL-BW02
EACH LED IS 3V TO 4.2V
AT 350mA

V

OUT

10µF, 50V
C5750X7R1H106M
CERAMIC

GND

3783 F11

5V AT 0Hz TO 10Hz

PWM

1µF

4.7µF

100k

20k

1M

LTC3783

RUN
PWMIN
I

TH

SS
V

REF

FBP
FBN
FREQ
SYNC

V

OV/FB

PWMOUT

I

LIM

GATE

SENSE

INTV

GND

10µF, 50V
×2
UMK432C106MM

IN

0V TO

1.23V

CC

4.7µF

10µH
SUMIDA
CDRH8D28-100

PMEG6010

40.2k

FAIRCHILD
FDN5630

0.05Ω

1k

Figure 11. Single Inductor Buck-Boost Application with Analog Dimming and Low Frequency PWM Dimming

3783fa

20

OPERATIO

LTC3783

U

Using the LTC3783 for Buck Applications

As shown in Figure 12, high side current sensing also
allows the LTC3783 to control a functional buck con­verter when load voltage is always sufficiently less than

V

IN

6V TO 36V

LTC3783

RUN
PWMIN
I

TH

SS
V

REF

FBP
FBN
FREQ
SYNC

Figure 12. LED Buck Application

. In this scheme the input voltage to the inductor is

V

IN

lowered by the load voltage. The boost converter now
sees a V

IN

boosting from (V

V

IN

OV/FB

PWMOUT

I

LIM

GATE
SENSE
INTV

CC

GND

’ = VIN – V

IN

3783 F12

, meaning the controller is now

LOAD

– V

LED STRING

GND

LOAD

) to VIN.

3783fa

21

LTC3783

PACKAGE DESCRIPTIO

4.50 ±0.05

3.10 ±0.05

2.44 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

U

DHD Package

16-Lead Plastic DFN (5mm × 4mm)

(Reference LTC DWG # 05-08-1707)

0.70 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

4.34 ±0.05
(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

5.00 ±0.10
(2 SIDES)

R = 0.20

TYP

4.00 ±0.10
(2 SIDES)

0.75 ±0.05

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

2.44 ± 0.10
(2 SIDES)

0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD

R = 0.115

4.34 ±0.10
(2 SIDES)

TYP

0.25 ± 0.05

0.50 BSC

169

18

0.40 ± 0.10

PIN 1
NOTCH

(DHD16) DFN 0504

22

3783fa

PACKAGE DESCRIPTIO

(.141)

3.58

U

FE Package

16-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation BC

4.90 – 5.10*
(.193 – .201)

3.58

(.141)

16 1514 13 12 11

LTC3783

10 9

6.60 ±0.10

4.50 ±0.10

RECOMMENDED SOLDER PAD LAYOUT

0.09 – 0.20

(.0035 – .0079)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

0.65 BSC

4.30 – 4.50*
(.169 – .177)

0.50 – 0.75

(.020 – .030)

MILLIMETERS

(INCHES)

(.116)

0.45 ±0.05

2.94

1.05 ±0.10

1345678

2

0.25
REF

0° – 8°

0.65

(.0256)

BSC

0.195 – 0.30

(.0077 – .0118)

TYP

4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE

2.94

(.116)

1.10

(.0433)

MAX

0.05 – 0.15

(.002 – .006)

FE16 (BC) TSSOP 0204

6.40

(.252)

BSC

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3783fa

23

LTC3783

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PART NUMBER DESCRIPTION COMMENTS

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LTC3780 High Power Buck-Boost Controller 4-Switch, 4V ≤ VIN ≤ 36V, 0.8V ≤ V
LTC3782 2-Phase Boost Controller High Power, 6V ≤ VIN ≤ 40V, 150kHz to 500kHz

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LTC4002 Standalone 2A Li-Ion Battery Charger 1- and 2-Cell, 4.7V ≤ VIN ≤ 22V, 3 Hour Timer

, 2.5V ≤ VIN ≤ 36V, 92% Duty Cycle

SENSE

≤ 10V, 4V ≤ VIN ≤ 36V

OUT

OUT

≤ 30V

24

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

3783fa

LT 0406 REV A • PRINTED IN THE USA

© LINEAR TECHNOLOGY CORPORATION 2005