LTC3736
FEATURES
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
■
Tracking Function
■
Wide VIN Range: 2.75V to 9.8V
■
Constant Frequency Current Mode Operation
■
0.6V ±1.5% Voltage Reference
■
Low Dropout Operation: 100% Duty Cycle
■
True PLL for Frequency Locking or Adjustment
■
Selectable Burst Mode®/Forced Continuous Operation
■
Auxiliary Winding Regulation
■
Internal Soft-Start Circuitry
■
Power Good Output Voltage Monitor
■
Output Overvoltage Protection
■
Micropower Shutdown: IQ = 9µA
■
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages
U
APPLICATIO S
■
One or Two Lithium-Ion Powered Devices
■
Notebook and Palmtop Computers, PDAs
■
Portable Instruments
■
Distributed DC Power Systems
Dual 2-Phase, No R
SENSE
,
Synchronous Controller
with Output Tracking
U
DESCRIPTIO
The LTC®3736 is a 2-phase dual synchronous step-down
switching regulator controller with tracking that drives
external complementary power MOSFETs using few external components. The constant frequency current mode
architecture with MOSFET VDS sensing eliminates the
need for sense resistors and improves efficiency. Power
loss and noise due to the ESR of the input capacitance are
minimized by operating the two controllers out of phase.
Burst Mode operation provides high efficiency at light loads.
100% duty cycle capability provides low dropout operation,
extending operating time in battery-powered systems.
The switching frequency can be programmed up to 750kHz,
allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3736
switching frequency can be externally synchronized from
250kHz to 850kHz. Burst Mode operation is inhibited during synchronization or when the SYNC/FCB pin is pulled low
in order to reduce noise and RF interference. Automatic softstart is internally controlled.
The LTC3736 is available in the tiny thermally enhanced
(4mm × 4mm) QFN package or 24-lead SSOP narrow
package.
TM
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
is a registered trademark of Linear Technology Corporation. No R
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258,
6304066, 6611131, 6498466.
is a trademark of
SENSE
TYPICAL APPLICATIO
High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
SENSE1
2.2µH
47µF
187k
220pF
59k
V
OUT1
2.5V
TG1 TG2
SW1 SW2
BG1 BG2
PGND PGND
V
FB1
I
TH1
15k
V
IN
+
SENSE2
LTC3736
SGND
U
Efficiency vs Load Current
V
IN
2.75V TO 9.8V
10µF
220pF
×2
2.2µH
59k
118k
47µF
3736 TA01a
V
1.8V
OUT2
+
V
FB2
I
TH2
15k
100
95
VIN = 3.3V
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
1 100 1000 10000
VIN = 4.2V
VIN = 5V
10
LOAD CURRENT (mA)
FIGURE 16 CIRCUIT
= 2.5V
V
OUT
3736 TA01b
3736fa
1
LTC3736
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
PLLLPF, RUN/SS, SYNC/FCB,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages ................. – 0.3V to (V
V
, V
, I
, I
FB1
FB2
TH1
SW1, SW2 Voltages ............ – 2V to V
Voltages .................. – 0.3V to 2.4V
TH2
+ 1V or 10V Max
IN
+ 0.3V)
IN
PGOOD ..................................................... – 0.3V to 10V
UU
W
PACKAGE/ORDER I FOR ATIO
TOP VIEW
FB1
V
IPRG1
SW1
24 23 22 21 20 19
I
1
TH1
IPRG2
2
PLLLPF
3
SGND
4
V
5
IN
TRACK
6
24-LEAD (4mm × 4mm) PLASTIC QFN
T
JMAX
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
25
7 8 9
V
10 11 12
FB2
TH2
I
PGOOD
UF PACKAGE
= 125°C, θJA = 37°C/W
SENSE1+PGND
+
SW2
SENSE2
BG1
18
17
16
15
14
13
PGND
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
ORDER PART
NUMBER
LTC3736EUF
UF PART MARKING
3736
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. – 65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
(LTC3736EGN) ..................................................... 300°C
ORDER PART
NUMBER
LTC3736EGN
1
SW1
2
IPRG1
3
V
FB1
4
I
TH1
5
IPRG2
6
PLLLPF
7
SGND
8
V
IN
9
TRACK
10
V
FB2
11
I
TH2
12
PGOOD
24-LEAD PLASTIC SSOP
T
JMAX
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
GN PACKAGE
= 125°C, θJA = 130°C/ W
SENSE1
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
+
+
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
Input DC Supply Current (Note 4)
Sleep Mode 300 425 µA
Shutdown RUN/SS = 0V 9 20 µA
UVLO V
= UVLO Threshold –200mV 3 10 µA
IN
Undervoltage Lockout Threshold VIN Falling ● 1.95 2.25 2.55 V
Rising ● 2.15 2.45 2.75 V
V
IN
Shutdown Threshold at RUN/SS 0.45 0.65 0.85 V
Start-Up Current Source RUN/SS = 0V 0.4 0.7 1 µA
Regulated Feedback Voltage 0°C to 85°C (Note 5) 0.591 0.6 0.609 V
–40°C to 85°C
● 0.588 0.6 0.612 V
Output Voltage Line Regulation 2.75V < VIN < 9.8V (Note 5) 0.05 0.2 mV/V
3736fa
2
LTC3736
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Load Regulation ITH = 0.9V (Note 5) 0.12 0.5 %
ITH = 1.7V –0.12 –0.5 %
V
Input Current (Note 5) 10 50 nA
FB1,2
TRACK Input Current TRACK = 0.6V 10 50 nA
Overvoltage Protect Threshold Measured at V
Overvoltage Protect Hysteresis 20 mV
Auxiliary Feedback Threshold SYNC/FCB Ramping Positive 0.525 0.6 0.675 V
Top Gate (TG) Drive 1, 2 Rise Time CL = 3000pF 40 ns
Top Gate (TG) Drive 1, 2 Fall Time CL = 3000pF 40 ns
Bottom Gate (BG) Drive 1, 2 Rise Time CL = 3000pF 50 ns
Bottom Gate (BG) Drive 1, 2 Fall Time CL = 3000pF 40 ns
Maximum Current Sense Voltage (∆V
(SENSE+ – SW) IPRG = 0V ● 70 85 100 mV
Soft-Start Time Time for V
Oscillator and Phase-Locked Loop
Oscillator Frequency Unsynchronized (SYNC/FCB Not Clocked)
Phase-Locked Loop Lock Range SYNC/FCB Clocked
Phase Detector Output Current
Sinking f
Sourcing f
PGOOD Output
PGOOD Voltage Low I
PGOOD Trip Level VFB with Respect to Set Output Voltage
SENSE(MAX)
) IPRG = Floating ● 110 125 140 mV
IPRG = V
PLLLPF = Floating ● 480 550 600 kHz
PLLLPF = 0V
PLLLPF = V
Minimum Synchronizable Frequency ● 200 250 kHz
Maximum Synchronizable Frequency
> f
OSC
< f
OSC
PGOOD
VFB < 0.6V, Ramping Positive –13 –10.0 –7 %
V
FB
VFB > 0.6V, Ramping Negative 7 10.0 13 %
V
FB
FB
IN
to Ramp from 0.05V to 0.55V 0.667 0.833 1 ms
FB1
IN
SYNC/FCB
SYNC/FCB
Sinking 1mA 125 mV
< 0.6V, Ramping Negative –16 –13.3 –10 %
> 0.6V, Ramping Positive 10 13.3 16 %
0.66 0.68 0.7 V
● 185 204 223 mV
● 260 300 340 kHz
● 650 750 825 kHz
● 850 1150 kHz
–4 µA
4 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3736E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
Note 3: T
dissipation P
is calculated from the ambient temperature TA and power
J
according to the following formula:
D
TJ = TA + (PD • θJA°C/W)
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3736 is tested in a feedback loop that servos ITH to a
specified voltage and measures the resultant V
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
voltage.
FB
3736fa
3
LTC3736
INPUT VOLTAGE (V)
2
–5
NORMALIZED FREQUENCY SHIFT (%)
–4
–2
–1
0
5
2
4
6
7
3736 G08
–3
3
4
1
35
8
9
10
UW
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Efficiency and Power Loss
vs Load Current
100
FIGURE 15 CIRCUIT
95
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
1 100 1000 10000
VIN = 5V
SYNC/FCB = V
10
IN
LOAD CURRENT (mA)
V
OUT
V
OUT
V
OUT
V
OUT
Load Step (Pulse Skipping Mode)
V
OUT
AC-COUPLED
100mV/DIV
I
L
2A/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = 550kHz EXTERNAL CLOCK
FIGURE 17 CIRCUIT
= 3.3V
= 2.5V
= 1.8V
= 1.2V
3736 G01
100µs/DIV
10
AC-COUPLED
100mV/DIV
1
POWER LOSS (W)
0.1
0.01
0.001
Load Step (Burst Mode Operation)
V
OUT
I
L
2A/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = V
FIGURE 17 CIRCUIT
3736 G04
100µs/DIV
IN
SYNC/FCB = V
SKIPPING MODE
SYNC/FCB = 550kHz
Burst Mode
OPERATION
CONTINUOUS
SYNC/FCB = 0V
Load Step
(Forced Continuous Mode)
V
OUT
AC-COUPLED
100mV/DIV
I
L
2A/DIV
3736 G02
Inductor Current at Light Load
IN
FORCED
MODE
PULSE
= 3.3V
V
IN
= 1.8V
V
OUT
= 200mA
I
LOAD
FIGURE 17 CIRCUIT
4µs/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = 0V
FIGURE 17 CIRCUIT
100µs/DIV
3736 G05
I
L
1A/DIV
3736 G03
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
VIN = 5V
R
LOAD1
FIGURE 15 CIRCUIT
4
= R
LOAD2
200µs/DIV
= 1Ω
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
V
OUT1
2.5V
V
OUT2
1.8V
500mV/
DIV
3736 G06
VIN = 5V
= R
R
LOAD1
FIGURE 15 CIRCUIT
LOAD2
40ms/DIV
= 1Ω
3736 G07
V
OUT1
2.5V
V
OUT2
1.8V
500mV/
DIV
Oscillator Frequency
vs Input Voltage
3736fa
TEMPERATURE (°C)
–60
115
MAXIMUM CURRENT SENSE THRESHOLD (mV)
120
125
130
135
–40 –20 0 20
3736 G14
40 60 80 100
I
PRG
= FLOAT
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC3736
TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
Pin Voltage
vs I
TH
100
80
60
40
20
CURRENT LIMIT (%)
0
–20
Burst Mode OPERATION
(I
TH
Burst Mode OPERATION
(I
TH
FORCED CONTINUOUS
MODE
PULSE SKIPPING
MODE
0.5
RISING)
FALLING)
1 1.5
ITH VOLTAGE (V)
Shutdown (RUN) Threshold
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
RUN/SS VOLTAGE (V)
0.2
0.1
0
–60
–40 0
–20
20
TEMPERATURE (°C)
40
Regulated Feedback Voltage
Efficiency vs Load Current
3736 G09
2
100
95
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
Burst Mode
OPERATION
(SYNC/FCB = V
1 100 1000 10000
)
IN
PULSE SKIPPING
MODE
(SYNC/FCB = 550kHz)
FIGURE 15 CIRCUIT
V
V
10
LOAD CURRENT (mA)
FORCED
CONTINUOUS
(SYNC/FCB = 0V)
= 5V
IN
= 2.5V
OUT
3736 G10
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
RUN/SS PULL-UP CURRENT (µA)
80
60
100
3736 G12
0.4
–60
–20 20
–40 0
TEMPERATURE (°C)
60
40
80
100
3736 G13
vs Temperature
0.609
0.607
0.605
0.603
0.601
0.599
0.597
FEEDBACK VOLTAGE (V)
0.595
0.593
0.591
–60
–40
–20
20
0
TEMPERATURE (°C)
40
Maximum Current Sense Threshold
vs Temperature
80
3736 G11
100
60
Oscillator Frequency
vs Temperature
10
8
6
4
2
0
–2
–4
–6
NROMALIZED FREQUENCY (%)
–8
–10
–60
–40 0
–20
TEMPERATURE (°C)
Undervoltage Lockout Threshold
vs Temperature
2.50
2.45
2.40
2.35
2.30
) VOLTAGE (V)
IN
2.25
INPUT (V
2.20
2.15
80
20
60
40
100
3736 G15
2.10
–60
–40
VIN RISING
VIN FALLING
–20
20
0
TEMPERATURE (°C)
40
60
80
3736 G16
100
3736fa
5
LTC3736
UW
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Shutdown Quiescent Current
vs Input Voltage
20
RUN/SS = 0V
18
16
14
12
10
8
6
SHUTDOWN CURRENT (µA)
4
2
0
2
U
PI FU CTIO S
I
TH1/ITH2
(Pins 1, 8/ Pins 4, 11): Current Threshold and
35
4
6
INPUT VOLTAGE (V)
7
UU
(UF/GN Package)
9
8
10
3736 G17
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Controller. Allows the start-up of V
to “track” that of V
OUT2
OUT1
according to a ratio established by a resistor divider on
V
connected to the TRACK pin. For one-to-one track-
OUT1
ing of V
OUT1
and V
during start-up, a resistor divider
OUT2
RUN/SS Start-Up Current
vs Input Voltage
0.9
RUN/SS = 0V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
RUN/SS PIN PULL-UP CURRENT (µA)
0.1
0
3
2
4
with values equal to those connected to V
should be used to connect to TRACK from V
6
5
INPUT VOLTAGE (V)
7
9
3736 G18
10
from V
FB2
OUT1
OUT2
.
8
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
FB1
, V
FB2
) is not
within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power
Ground. These pins serve as the ground connection for the
gate drivers and the negative input to the reverse current
comparators. The Exposed Pad (UF package) must be
soldered to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
TG1/ TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive
Output. These pins drive the gates of the external P-channel
MOSFETs. These pins have an output swing from PGND to
SENSE+.
SYNC/FCB (Pin 18/Pin 21): This pin performs three
functions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, and 3)
Burst Mode operation or forced continuous mode select.
3736fa
6
LTC3736
U
PI FU CTIO S
UU
(UF/GN Package)
For auxiliary winding applications, connect to a resistor
divider from the auxiliary output. To synchronize with an
external clock using the PLL, apply a CMOS compatible
clock with a frequency between 250kHz and 850kHz. To
select Burst Mode operation at light loads, tie this pin to V
IN
.
Grounding this pin selects forced continuous operation,
which allows the inductor current to reverse. When
synchronized to an external clock, pulse-skipping operation
is enabled at light loads.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external Nchannel MOSFETs. These pins have an output swing from
PGND to SENSE
+
.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the external P-channel MOSFET.
SW1/ SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the external P-channel MOSFETs, the drain of the external N-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These pins
select the maximum allowed voltage drop between the
+
SENSE
and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to V
, GND or float to select 204mV, 85mV or 125mV
IN
respectively.
V
FB1/VFB2
(Pins 24, 7/Pins 3, 10): Feedback Pins. Receives
the remotely sensed feedback voltage for its controller from
an external resistor divider across the output.
U
U
W
FU CTIO AL DIAGRA
V
UNDERVOLTAGE
LOCKOUT
0.7µA
RUN/SS
SYNC/FCB
PLLLPF
IPRG1
IPRG2
0.6V
BURST DEFEAT/
SYNC DETECT
VOLTAGE
CONTROLLED
OSCILLATOR
–
FCB
+
VOLTAGE
MAXIMUM
CONTROLLED
SENSE VOLTAGE
OSCILLATOR
SELECT
(Common Circuitry)
R
SHDN
CLK1
CLK2
FCB
C
VIN
t
= 1ms
SEC
BURSTDIS
DETECTOR
IPROG1
IPROG2
0.6V
V
PHASE
IN
VOLTAGE
REFERENCE
EXTSS
VIN
V
IN
(TO CONTROLLER 1, 2)
REF
0.54V
+
–
SLOPE
COMP
V
V
INTSS
SLOPE1
SLOPE2
–
FB1
+
+
FB2
–
UV1
UV2
OV1
SHDN
OV2
PGOOD
3736 FD
3736fa
7
LTC3736
U
U
W
FU CTIO AL DIAGRA
CLK1
–
ICMP
+
IPROG1
BURSTDIS
0.3V
(Controller 1)
RS1
Q
S
R
OV1
SC1
FCB
SLOPE1
SW1
SENSE1
+
SWITCHING
LOGIC
BLANKING
CIRCUIT
SLEEP1
+
–
AND
IREV1
ANTISHOOT
THROUGH
SHDN
EAMP
PGND
SENSE1
–
+
+
SENSE1
TG1
SW1
BG1
PGND
+
0.6V
V
IN
C
IN
MP1
MN1
L1
C
OUT1
EXTSS
V
FB1
R1B
R1A
V
OUT1
SLEEP1
OV1
BURSTDIS
0.15V
INTSS
I
0.12V
V
FB1
TH1
R
ITH1
C
ITH1
–
+
SC1
+
SCP
–
V
+
FB1
IREV1
0.68V
–
RICMPOVP
IPROG1 FCB
–
+
PGND
SW1
3736 CONT1
8
3736fa
LTC3736
U
U
W
FU CTIO AL DIAGRA
CLK2
–
ICMP
+
BURSTDIS
0.3V
(Controller 2)
RS2
S
Q
R
OV2
SC2
FCB
SLOPE2
SW2
SENSE2
+
SWITCHING
LOGIC
BLANKING
CIRCUIT
SLEEP2
+
–
–
AND
IREV2
ANTISHOOT
THROUGH
SHDN
EAMP
PGND
SENSE2
–
+
0.6V
+
SENSE2
TG2
SW2
BG2
PGND
V
IN
+
MP2
MN2
V
FB2
TRACK
I
TH2
L2
C
OUT2
V
OUT1
R
R
TRACKB
TRACKA
R2B
R2A
V
OUT2
SLEEP2
OV2
BURSTDIS
OVP
R
+
SC2
0.15V
V
+
FB2
IREV2
0.68V
–
SCP
TRACK
IPROG2 FCB
+
–
–
+
0.12V
V
FB2
PGND
SW2
3736 CONT2
ITH2
C
ITH2
3736fa
9
LTC3736
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC3736 uses a constant frequency, current mode
architecture with the two controllers operating 180 degrees out of phase. During normal operation, the top
external P-channel power MOSFET is turned on when the
clock for that channel sets the RS latch, and turned off
when the current comparator (I
peak inductor current at which I
) resets the latch. The
CMP
resets the RS latch is
CMP
determined by the voltage on the ITH pin, which is driven
by the output of the error amplifier (EAMP). The V
FB
pin
receives the output voltage feedback signal from an external resistor divider. This feedback signal is compared to
the internal 0.6V reference voltage by the EAMP. When the
load current increases, it causes a slight decrease in V
relative to the 0.6V reference, which in turn causes the I
FB
TH
voltage to increase until the average inductor current
matches the new load current. While the top P-channel
MOSFET is off, the bottom N-channel MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the current reversal comparator, I
RCMP
, or the
beginning of the next cycle.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736 is shut down by pulling the RUN/SS pin low.
In shutdown, all controller functions are disabled and the
chip draws only 9µA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736’s two controllers are enabled.
The start-up of V
is controlled by the LTC3736’s
OUT1
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V
to the internal
FB1
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates the V
The start-up of V
proportionally linearly from 0V to 0.6V.
FB1
is controlled by the voltage on the
OUT2
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736 regulates
the V
reference. Typically, a resistor divider on V
nected to the TRACK pin to allow the start-up of V
“track” that of V
voltage to the TRACK pin instead of the 0.6V
FB2
is con-
OUT1
OUT2
. For one-to-one tracking during start-
OUT1
to
up, the resistor divider would have the same values as the
divider on V
that is connected to V
OUT2
FB2
.
Light Load Operation (Burst Mode or Continuous
Conduction) (SYNC/FCB Pin)
The LTC3736 can be enabled to enter high efficiency Burst
Mode operation or forced continuous conduction mode at
low load currents. To select Burst Mode operation, tie the
SYNC/FCB pin to a DC voltage above 0.6V (e.g., VIN). To
select forced continuous operation, tie the SYNC/FCB to a
DC voltage below 0.6V (e.g., SGND). This 0.6V threshold
between Burst Mode operation and forced continuous mode
can be used in secondary winding regulation as described
in the Auxiliary Winding Control Using SYNC/FCB Pin discussion in the Applications Information section.
When a controller is in Burst Mode operation, the peak
current in the inductor is set to approximate one-fourth of
the maximum sense voltage even though the voltage on
the ITH pin indicates a lower value. If the average inductor
current is lower than the load current, the EAMP will
decrease the voltage on the ITH pin. When the ITH voltage
drops below 0.85V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3736 draws.
The load current is supplied by the output capacitor. As
the output voltage decreases, the EAMP increases the I
TH
voltage. When the ITH voltage reaches 0.925V, the SLEEP
signal goes low and the controller resumes normal
operation by turning on the external P-channel MOSFET
on the next cycle of the internal oscillator.
10
3736fa
OPERATIO
LTC3736
U
(Refer to Functional Diagram)
When a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. Hence, the
controller operates discontinuously. The reverse current
comparator (RICMP) senses the drain-to-source voltage
of the bottom external N-channel MOSFET. This MOSFET
is turned off just before the inductor current reaches zero,
preventing it from reversing and going negative.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by the
voltage on the ITH pin. The P-channel MOSFET is turned on
every cycle (constant frequency) regardless of the ITH pin
voltage. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous mode
has the advantages of lower output ripple and less interference with audio circuitry.
When the SYNC/FCB pin is clocked by an external clock
source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop), the LTC3736 operates
in PWM pulse skipping mode at light loads. In this mode,
the current comparator I
may remain tripped for
CMP
several cycles and force the external P-channel MOSFET to
stay off for the same number of cycles. The inductor
current is not allowed to reverse, though (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. However, it provides low current efficiency
higher than forced continuous mode, but not nearly as
high as Burst Mode operation. During start-up or a shortcircuit condition (V
FB1
or V
≤ 0.54V), the LTC3736
FB2
operates in pulse skipping mode (no current reversal
allowed), regardless of the state of the SYNC/FCB pin.
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
The short-circuit threshold on V
is based on the smaller
FB2
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows V
easily. Note that if V
to start up and track V
OUT2
is truly short-circuited
OUT1
OUT1
more
(V
V
= V
OUT1
to 0V if a resistor divider on V
OUT2
= 0V), then the LTC3736 will try to regulate
FB1
is connected to
OUT1
the TRACK pin.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
pin has risen 13.33%
FB
above the reference voltage of 0.6V, the external P-channel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection and Phase-Locked Loop
(PLLLPF and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage.
The switching frequency of the LTC3736’s controllers can
be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external clock
source, the PLLLPF can be floated, tied to VIN or tied to
SGND to select 550kHz, 750kHz or 300kHz respectively.
A phase-locked loop (PLL) is available on the LTC3736 to
synchronize the internal oscillator to an external clock
source that connected to the SYNC/FCB pin. In this case,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3736
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of controller 1’s external P-channel
MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external P-channel
MOSFET is 180 degrees out of phase with the rising edge
of the external clock source.
The typical capture range of the LTC3736’s phase-locked
loop is from approximately 200kHz to 1MHz, and is
guaranteed over temperature to be between 250kHz and
850kHz. In other words, the LTC3736’s PLL is guaranteed
to lock to an external clock source whose frequency is
between 250kHz and 850kHz.
3736fa
11
LTC3736
OPERATIO
U
(Refer to Functional Diagram)
Dropout Operation
When the input supply voltage (V
) decreases towards
IN
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I
pin. Further reduction in the
TH
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3736. When the input supply voltage (VIN) drops
below 2.3V, the external P- and N-channel MOSFETs and
all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes.
peak sense voltage by a scale factor given by the curve in
Figure 1.
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
V
∆
SENSE MAX
I
=
PK
110
100
90
80
70
(%)
60
MAX
50
40
SF = I/I
30
20
10
R
0
DS ON
()
10
()
30
40
200
DUTY CYCLE (%)
70
80
90
50
60
100
3736 F01
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE+ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
∆ =
V
SENSE MAX
()
AV V
–.07
()
ITH
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to V
IN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of V
is typically about 1.98V, so the
ITH
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
Figure 1. Maximum Peak Current vs Duty Cycle
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736 is shut down or in undervoltage lockout.
2-Phase Operation
Why the need for 2-phase operation? Until recently, constant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
12
3736fa
OPERATIO
LTC3736
U
(Refer to Functional Diagram)
With 2-phase operation, the two controllers of the LTC3736
are operated 180 degrees out of phase. This effectively
interleaves the current pulses coming from the topside
MOSFET switches, greatly reducing the time where they
overlap and add together. The result is a significant
reduction in the total RMS current, which in turn allows the
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
Figure 2 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3736
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
operation would reduce the RMS input capacitor current
from 1.79A
RMS
to 0.91A
. While this is an impressive
RMS
reduction by itself, remember that power losses are proportional to I
2
, meaning that actual power wasted is
RMS
reduced by a factor of 3.86.
SW1 (V)
SW2 (V)
I
L1
I
L2
I
IN
Single Phase
Dual Controller
2-Phase
Dual Controller
3736 F02
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and protection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 3 depicts how the RMS input
current varies for single phase and 2-phase dual controllers with 2.5V and 1.8V outputs over a wide input voltage
range.
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
most applications is that 2-phase operation will reduce the
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
INPUT CAPACITOR RMS CURRENT
V
OUT1
0.2
V
OUT2
0
2
Figure 3. RMS Input Current Comparison
SINGLE PHASE
DUAL CONTROLER
DUAL CONTROLER
= 2.5V/2A
= 1.8V/2A
35
4
6
INPUT VOLTAGE (V)
2-PHASE
7
9
8
10
3736 F03
Figure 2. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736
3736fa
13
LTC3736
WUUU
APPLICATIO S I FOR ATIO
The typical LTC3736 application circuit is shown in Figure 13. External component selection for each of the
LTC3736’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
Power MOSFET Selection
Each of the LTC3736’s two controllers requires two external power MOSFETs: a P-channel MOSFET for the topside
(main) switch and an N-channel MOSFET for the bottom
(synchronous) switch. Important parameters for the power
MOSFETs are the breakdown voltage V
voltage V
capacitance C
, on-resistance R
GS(TH)
, turn-off delay t
RSS
BR(DSS)
DS(ON)
D(OFF)
and the total gate
, threshold
, reverse transfer
charge QG.
The gate drive voltage is the input supply voltage. Since the
LTC3736 is designed for operation down to low input
voltages, a sublogic level MOSFET (R
V
= 2.5V) is required for applications that work close to
GS
DS(ON)
guaranteed at
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3736 is less than the absolute maximum MOSFET VGS rating, which is typically 8V.
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current I
OUT(MAX)
current minus half the peak-to-peak ripple current I
is equal to the peak inductor
.
RIPPLE
The LTC3736’s current comparator monitors the drain-tosource voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆V
SENSE(MAX)
to
approximately 128mV when IPRG is floating (86mV when
IPRG is tied low; 213mV when IPRG is tied high).
The output current that the LTC3736 can provide is given
by:
A reasonable starting point is setting ripple current I
to be 40% of I
OUT(MAX)
. Rearranging the above equation
RIPPLE
yields:
R
DS ON MAX
()( )
5
6
•=
I
SENSE MAX
()
OUT MAX
()
V
∆
for Duty Cycle < 20%.
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of R
DS(ON)
to provide the required
amount of load current:
V
RSF
DS ON MAX
()( )
5
6
∆
SENSE MAX
••=
I
OUT MAX
()
()
where SF is a scale factor whose value is obtained from the
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determining the
required R
DS(ON)MAX
at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3736
and external component values:
V
RSF
DS ON MAX
()( )
5
•.• •
=
09
6
∆
SENSE MAX
()
I
OUT MAX T
•
()
ρ
The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 4. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ
80°C
~ 1.3 in
the above equation is a reasonable choice.
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736 is operating in continuous
mode, the duty cycles for the MOSFETs are:
I
OUT MAX
14
()
V
∆
SENSE MAX
R
DS ON
()
()
I
–=
RIPPLE
2
Top P-Channel Duty Cycle =
V
Bottom N-Channel Duty Cycle =
OUT
V
IN
V
–
V
IN
OUT
V
IN
3736fa
WUUU
APPLICATIO S I FOR ATIO
LTC3736
2.0
1.5
1.0
0.5
NORMALIZED ON RESISTANCE
T
ρ
0
–50
0
JUNCTION TEMPERATURE (°C)
Figure 4. R
50
vs Temperature
DS(ON)
100
150
3736 F04
The MOSFET power dissipations at maximum output
current are:
V
P
P
TOP
BOT
OUT
=+
•••
VV
=
IRV
••• •
OUT MAX T DS ON IN
V
IN
ICf
OUT MAX RSS OSC
()
–
IN OUT
V
IN
Both MOSFETs have I2R losses and the P
22
() ()
IR
•••
OUT MAX T DS ON
2
() ()
r
2r
equation
TOP
includes an additional term for transition losses, which are
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short circuit
when the bottom duty cycle is nearly 100%.
The LTC3736 utilizes a nonoverlapping, antishoot-through
gate drive control scheme to ensure that the P- and
N-channel MOSFETs are not turned on at the same time.
To function properly, the control scheme requires that the
MOSFETs used are intended for DC/DC switching applications. Many power MOSFETs, particularly P-channel
MOSFETs, are intended to be used as static switches and
therefore are slow to turn on or off.
MOSFET manufacturers, and in the variations in QG and
t
with gate drive (VIN) voltage, the P-channel MOSFET
D(OFF)
ultimately should be evaluated in the actual LTC3736
application circuit to ensure proper operation.
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage increases, if the input supply current increases dramatically,
then the likely cause is shoot-through. Note that some
MOSFETs that do not work well at high input voltages (e.g.,
> 5V) may work fine at lower voltages (e.g., 3.3V).
V
IN
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736 applications.
Selecting the N-channel MOSFET is typically easier, since
for a given R
, the gate charge and turn-on and turn-
DS(ON)
off delays are much smaller than for a P-channel MOSFET.
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736
Applications
PART
NUMBER MANUFACTURER TYPE PACKAGE
Si7540DP Siliconix Complementary PowerPak
P/N SO-8
Si9801DY Siliconix Complementary SO-8
P/N
FDW2520C Fairchild Complementary TSSOP-8
P/N
FDW2521C Fairchild Complementary TSSOP-8
P/N
Si3447BDV Siliconix Single P TSOP-6
Si9803DY Siliconix Single P SO-8
FDC602P Fairchild Single P TSOP-6
FDC606P Fairchild Single P TSOP-6
FDC638P Fairchild Single P TSOP-6
FDW2502P Fairchild Dual P TSSOP-8
FDS6875 Fairchild Dual P SO-8
HAT1054R Hitachi Dual P SO-8
NTMD6P02R2-D On Semi Dual P SO-8
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(t
) of less than approximately 140ns. However, due
D(OFF)
to differences in test and specification methods of various
Operating Frequency and Synchronization
The choice of operating frequency, f
, is a trade-off
OSC
between efficiency and component size. Low frequency
3736fa
15
LTC3736
WUUU
APPLICATIO S I FOR ATIO
operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss.
However, lower frequency operation requires more inductance for a given amount of ripple current.
The internal oscillator for each of the LTC3736’s controllers runs at a nominal 550kHz frequency when the PLLLPF
pin is left floating and the SYNC/FCB pin is a DC low or
high. Pulling the PLLLPF to V
selects 750kHz operation;
IN
pulling the PLLLPF to GND selects 300kHz operation.
Alternatively, the LTC3736 will phase-lock to a clock signal
applied to the SYNC/FCB pin with a frequency between
250kHz and 850kHz (see Phase-Locked Loop and Frequency Synchronization).
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
directly determine the
OSC
inductor’s peak-to-peak ripple current:
I
RIPPLE
⎛
V
=
VV
OUTININ OUT
⎜
⎝
V
fL
–
OSC
⎞
⎟
⎠
•
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
V
∆
1
SENSE MAX
I
BURST PEAK
()
•=
4
R
DS ON
()
()
The corresponding average current depends on the amount
of ripple current. Lower inductor values (higher I
RIPPLE
)
will reduce the load current at which Burst Mode operation
begins.
The ripple current is normally set so that the inductor
current is continuous during the burst periods. Therefore:
I
RIPPLE
≤ I
BURST(PEAK)
This implies a minimum inductance of:
VV
–
L
MIN
≤
IN OUT
fI
•
OSC BURST PEAK
A smaller value than L
()
MIN
V
OUT
•
V
IN
could be used in the circuit,
although the inductor current will not be continuous
during burst periods, which will result in slightly lower
efficiency. In general, though, it is a good idea to keep
I
comparable to I
RIPPLE
BURST(PEAK)
.
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molypermalloy or other cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will
increase.
VV
L
≥
fI
OSC RIPPLE
–
IN OUT
•
V
OUT
•
V
IN
Burst Mode Operation Considerations
The choice of R
and inductor value also determines
DS(ON)
the load current at which the LTC3736 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
16
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
3736fa
WUUU
APPLICATIO S I FOR ATIO
LTC3736
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
CIN and C
Selection
OUT
The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The controller with the highest (V
OUT
)(I
) product needs to be used
OUT
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V
)/(VIN). To
OUT
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
I
C
Required I
IN
Kool Mµ is a registered trademark of Magnetics, Inc.
RMS
MAX
≈
[]
V
IN
VVV
()( )
OUT IN OUT
–
/12
This formula has a maximum at VIN = 2V
= I
/2. This simple worst-case condition is commonly
OUT
, where I
OUT
RMS
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the LTC3736,
ceramic capacitors can also be used for CIN. Always
consult the manufacturer if there is any question.
The benefit of the LTC3736 2-phase operation can be calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3736, is also
suggested. A 10Ω resistor placed between C
(C1) and
IN
the VIN pin provides further isolation between the two
channels.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆V
∆≈ +
V I ESR
OUT RIPPLE
) is approximated by:
OUT
⎛
⎜
⎝
1
8
fC
OUT
⎞
⎟
⎠
3736fa
17
LTC3736
WUUU
APPLICATIO S I FOR ATIO
where f is the operating frequency, C
capacitance and I
is the ripple current in the induc-
RIPPLE
is the output
OUT
tor. The output ripple is highest at maximum input voltage
since I
increases with input voltage.
RIPPLE
Setting Output Voltage
The LTC3736 output voltages are each set by an external
feedback resistor divider carefully placed across the output, as shown in Figure 5. The regulated output voltage is
determined by:
VV
⎛
=+
OUT
06 1.•
⎜
⎝
⎞
R
B
⎟
R
⎠
A
To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
V
OUT
R
C
B
1/2 LTC3736
V
FB
R
3736 F05
Figure 5. Setting Output Voltage
FF
A
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736.
Pulling the RUN/SS pin below 0.65V puts the LTC3736
into a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3736 comes out of shutdown and
is given by:
C
tV
=
DELAY
07
.
SS
=µ065
A
µ
sFC
093.•
./•
SS
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 6 reduces the start delay but
allows CSS to ramp up slowly providing the soft-start
3.3V OR 5V RUN/SS RUN/SS
D1
C
C
SS
Figure 6. RUN/SS Pin Interfacing
SS
3736 F06
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
During soft-start, the start-up of V
is controlled by
OUT1
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing V
to rise smoothly from 0V
OUT1
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
600
tC
SS SS1
07=µ•.
mV
A
Tracking
The start-up of V
is controlled by the voltage on the
OUT2
TRACK pin. Normally this pin is used to allow the start-up
of V
to track that of V
OUT2
as shown qualitatively in
OUT1
Figures 7a and 7b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736 regulates the V
0.6V. The start-up of V
of V
OUT1
voltage to the TRACK pin voltage instead of
FB2
may ratiometrically track that
OUT2
, according to a ratio set by a resistor divider
(Figure 7c):
V
OUT
V
OUT TRACKA
RARRR
2
=
2
R
TRACKB
R
TRACKA
Figure 7a. Using the TRACK Pin
V
•
OUT1
TRACKA TRACKB1
RB RA
R1B
V
FB1
R1A
TRACK
22
LTC3736
+
+
V
OUT2
R2B
V
FB2
R2A
3736 F07a
3736fa
18
WUUU
APPLICATIO S I FOR ATIO
LTC3736
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
(7b) Coincident Tracking
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
For coincident tracking (V
R2A = R
R2B = R
The ramp time for V
TRACKA
TRACKB
OUT2
OUT1
= V
during start-up),
OUT2
to rise from 0V to its final value
is:
tt
=
SS SS
21
••
R
TRACKA
RA
1
RA RB
11
+
RR
TRACKA TRACKB
+
For coincident tracking,
V
OUT F
tt
= •
SS SS
21
where V
V
and V
OUT1
V
when using the TRACK pin. If no tracking function
OUT2
OUT1F
and V
OUT2
V
OUT F
. V
2
1
are the final, regulated values of
OUT2F
should always be greater than
OUT1
is desired, then the TRACK pin may be tied to VIN. However, in this situation there would be no (internal nor
external) soft-start on V
OUT2
.
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
(7c) Ratiometric Tracking
3736 F07b,c
between the external and internal oscillators. This type of
phase detector does not exhibit false lock to harmonics of
the external clock.
The output of the phase detector is a pair of complementary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristics table. Note that the LTC3736 can only be
synchronized to an external clock whose frequency is
within range of the LTC3736’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and variations, to be between 300kHz and
750kHz. A simplified block diagram is shown in Figure 9.
1400
1200
1000
Phase-Locked Loop and Frequency Synchronization
The LTC3736 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the external Pchannel MOSFET of controller 1 to be locked to the rising
edge of an external clock signal applied to the SYNC/FCB
pin. The turn-on of controller 2’s external P-channel
MOSFET is thus 180 degrees out of phase with the
external clock. The phase detector is an edge sensitive
digital type that provides zero degrees phase shift
800
600
FREQUENCY (kHz)
400
200
0
0
0.5 1 1.5 2
PLLLPF PIN VOLTAGE (V)
Figure 8. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
2.4
3736 F08
3736fa
19
LTC3736
WUUU
APPLICATIO S I FOR ATIO
EXTERNAL
OSCILLATOR
SYNC/
FCB
DIGITAL
PHASE/
FREQUENCY
DETECTOR
Figure 9. Phase-Locked Loop Block Diagram
2.4V
R
LP
PLLLPF
OSCILLATOR
C
3736 F09
LP
If the external clock frequency is greater than the internal
oscillator’s frequency, f
, then current is sourced con-
OSC
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less than
f
, current is sunk continuously, pulling down the PLLLPF
OSC
pin. If the external and internal frequencies are the same
but exhibit a phase difference, the current sources turn on
for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the
phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase
detector output is high impedance and the filter capacitor
CLP holds the voltage.
The loop filter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN SYNC/FCB PIN FREQUENCY
0V DC Voltage 300kHz
Floating DC Voltage 550kHz
V
IN
RC Loop Filter Clock Signal Phase-Locked to External Clock
DC Voltage 750kHz
Auxiliary Winding Control Using SYNC/FCB Pin
The SYNC/FCB can be used as an auxiliary feedback to
provide a means of regulating a flyback winding output.
When this pin drops below its ground-referenced 0.6V
threshold, continuous mode operation is forced.
During continuous mode, current flows continuously in
the transformer primary. The auxiliary winding draws
current only when the bottom, synchronous N-channel
MOSFET is on. When primary load currents are low and/or
the VIN/V
ratio is close to unity, the synchronous
OUT
MOSFET may not be on for a sufficient amount of time to
transfer power from the output capacitor to the auxiliary
load. Forced continuous operation will support an auxiliary winding as long as there is a sufficient synchronous
MOSFET duty factor. The FCB input pin removes the
requirement that power must be drawn from the transformer primary in order to extract power from the auxiliary
winding. With the loop in continuous mode, the auxiliary
output may nominally be loaded without regard to the
primary output load.
The auxiliary output voltage V
is normally set as shown
AUX
in Figure 10 by the turns ratio N of the transformer:
V
≅ (N + 1) V
AUX
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
V
AUX
VV
will droop. An external resistor divider from
AUX
to the FCB sets a minimum voltage V
AUX MIN()
⎛
.=+
06 1
⎜
⎝
⎞
R
6
⎟
R
5
⎠
AUX(MIN)
:
3736fa
20
WUUU
APPLICATIO S I FOR ATIO
V
+
3736 F10
AUX
+
1µF
V
OUT
C
OUT
AUX
V
IN
R6
R5
LTC3736
TG
SYNC/FCB
SW
BG
L1
1:N
Figure 10. Auxiliary Output Loop Connection
If V
drops below this value, the FCB voltage forces
AUX
temporary continuous switching operation until V
again above its minimum.
is
1/2 LTC3736
I
TH
V
R2
FB
+
R1
Figure 11. Foldback Current Limiting
105
V
100
95
90
REF
MAXIMUM
SENSE VOLTAGE
LTC3736
V
OUT
D
FB1
D
FB2
3736 F11
Table 3 summarizes the different states in which the
SYNC/FCB pin can be used
Table 3
SYNC/FCB PIN CONDITION
0V to 0.5V Forced Continuous Mode
Current Reversal Allowed
0.7V to V
Feedback Resistors Regulate an Auxiliary Winding
External Clock Signal Enable Phase-Locked Loop
IN
Burst Mode Operation Enabled
No Current Reversal Allowed
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding diodes D
shown in Figure 11. In a hard short (V
FB1
and D
between the output and the ITH pin as
FB2
= 0V), the current
OUT
will be reduced to approximately 50% of the maximum
output current.
Low Supply Operation
Although the LTC3736 can function down to below 2.4V,
the maximum allowable output current is reduced as V
IN
decreases below 3V. Figure 12 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V
REF
.
85
80
NORMALIZED VOLTAGE OR CURRENT (%)
75
2.2 2.4 2.6 2.8
INPUT VOLTAGE (V)
Figure 12. Line Regulation of V
REF
3.02.12.0 2.3 2.5 2.7 2.9
3736 F12
and
Maximum Sense Voltage for Low Input Supply
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN),
is the smallest amount of time
in which the LTC3736 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
V
t
ON MIN
()
OUT
<
fV
•
OSC IN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3736 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum ontime for the LTC3736 is typically about 250ns. However,
as the peak sense voltage (I
L(PEAK)
• R
DS(ON)
) decreases,
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
3736fa
21
LTC3736
WUUU
APPLICATIO S I FOR ATIO
con
tinuous mode is selected and the duty cycle falls below
the minimum on-time requirement, the output will be regulated by overvoltage protection.
Other losses, including CIN and C
ESR dissipative
OUT
losses and inductor core losses, generally account for less
than 2% total additional loss.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736 circuits: 1) LTC3736 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, and
4) transition losses.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that increases with VIN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, I
GATECHG
= f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the average output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET R
DS(ON)
s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from:
Transition Loss = 2 (VIN)2I
O(MAX)CRSS
(f)
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to (∆I
resistance of
charge C
OUT
)(ESR), where ESR is the effective series
LOAD
COUT
, which generates a feedback error signal. The
regulator loop then returns V
During this recovery time, V
immediately shifts by an amount
OUT
. ∆I
also begins to charge or dis-
LOAD
to its steady-state value.
OUT
can be monitored for over-
OUT
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH external components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
, causing a rapid drop in V
OUT
. No regulator can
OUT
3736fa
22
WUUU
APPLICATIO S I FOR ATIO
LTC3736
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736. These items are illustrated in the layout diagram
of Figure 13. Figure 14 depicts the current waveforms
present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
OUT1
OUT2
+
L1
MN1 MP1
C
VIN1
C
VIN
C
VIN2
MN2 MP2
L2
+
3736 F13
V
V
OUT1
OUT2
V
IN
LTC3736EGN
1
SW1
2
IPRG1
3
V
FB1
4
5
6
7
8
9
10
11
12
BOLD LINES INDICATE HIGH CURRENT PATHS
I
TH1
IPRG2
PLLLPF
SGND
V
IN
TRACK
V
FB2
I
TH2
PGOOD
SYNC/FCB
SENSE1
PGND
BG1
PGND
RUN/SS
BG2
PGND
SENSE2
SW2
TG1
TG2
24
+
23
22
21
20
19
18
17
16
15
14
+
13
Figure 13. LTC3736 Layout Diagram
C
C
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3736 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
output capacitor should be a Kelvin trace. The I
compen-
TH
sation components should also be very close to the
LTC3736.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
3736fa
23
LTC3736
WUUU
APPLICATIO S I FOR ATIO
V
IN
R
IN
+
C
IN
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
MP1
MP2
MN1
MN2
L1
V
OUT1
+
C
OUT1
L2
V
OUT2
+
C
OUT2
3736 F14
R
L1
R
L2
TYPICAL APPLICATIO S
R
FB1A
59k
C
ITH1A
100pF
C
ITH1
V
10µF
IN
5V
C
IN
×2
220pF
R
VIN
C
C
220pF
VIN
1µF
C
SS
C
ITH2B
10nF
100pF
R
FB2A
59k
Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter
Figure 14. Branch Current Waveforms
U
R
FB1B
187k
R
ITH2
15k
ITH1
10Ω
R
ITH2
15k
R
TRACKA
59k
22
23
24
R
1
2
3
4
5
9
7
8
6
FB2B
118k
SW1
IPRG1
V
FB1
I
TH1
IPRG2
PLLLPF
SGND
LTC3736EUF
V
IN
PGOOD
V
FB2
I
TH2
TRACK
R
TRACKB
118k
PGND
SENSE1
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
25
21
+
20
19
18
17
16
15
14
13
12
11
+
10
MP1
MP2
MN1
Si7540DP
MN2
Si7540DP
L1
1.5µH
L2
1.5µH
V
OUT1
2.5V
5A
+
C
OUT1
150µF
C
OUT2
+
150µF
V
OUT2
1.8V
5A
3736 F15
3736fa
24
U
TYPICAL APPLICATIO S
LTC3736
FB1A
FB2A
R
R
VIN
C
ITH2
470pF
C
ITH2A
100pF
ITH1
22k
10Ω
R
187k
FB1B
R
ITH2
22k
R
TRACKA
59k
22
23
24
R
1
2
3
4
5
9
7
8
6
118k
FB2B
SW1
IPRG1
V
I
TH1
IPRG2
PLLLPF
SGND
V
PGOOD
V
I
TH2
TRACK
FB1
SYNC/FCB
LTC3736EUF
IN
FB2
PGND
R
TRACKB
118k
SENSE1
PGND
BG1
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
25
MP1
Si3447BDV
21
+
20
19
18
17
16
15
14
13
12
11
+
MP2
Si3447BDV
10
L1, L2: VISHAY IHLP-2525CZ-01
MN1
Si3460DV
MN2
Si3460DV
L1
1.5µH
D1
D2
L2
1.5µH
C
OUT1
22µF
×2
C
OUT2
22µF
×2
3736 F16
V
OUT1
2.5V
2A
V
OUT2
1.8V
2A
V
3.3V
C
22µF
R
59k
C
ITH1A
100pF
C
ITH1
IN
IN
470pF
C
VIN
1µF
C
SS
10nF
R
59k
Figure 16. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors
V
3.3V
22µF
C
FF1
100pF
FB1A
FB2A
R
VIN
C
220pF
ITH2
10Ω
R
187k
R
FB1B
ITH1
15k
R
LP
15k
R
ITH2
15k
R
TRACKA
59k
12
10
11
R
1
2
3
4
5
6
7
5
9
FB2B
118k
SW1
IPRG1
V
FB1
I
TH1
IPRG2
PLLLPF
SGND
LTC3736EGN
V
IN
PGOOD
V
FB2
I
TH2
TRACK
R
TRACKB
118k
C
FF1
100pF
SENSE1
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
CLK IN
MP1
24
+
23
22
21
20
19
18
17
16
15
14
+
MP2
13
C
, C
OUT1
L1, L2: VISHAY IHLP-2525CZ-01
SW1
MN1
Si7540DP
MN2
Si7540DP
SW2
: SANYO 4TPB150MC
OUT2
L1
1.5µH
L2
1.5µH
V
OUT1
2.5V
3A
+
C
OUT1
150µF
C
OUT2
+
150µF
V
OUT2
1.8V
4A
3736 F17
R
59k
C
ITH1
220pF
C
LP
10nF
IN
C
IN
C
VIN
1µF
R
59k
Figure 17. 2-Phase, Synchronizable, Dual Output Synchronous DC/DC Converter
3736fa
25
LTC3736
TYPICAL APPLICATIO
2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter with Different Power Stage Input Supplies
U
V
IN1
5V
C
10µF
R
VIN
C
220pF
R
15k
ITH2
ITH1
10Ω
R
FB1B
187k
R
ITH2
15k
R
TRACKA
59k
22
23
24
1
2
3
4
5
9
7
8
6
R
118k
FB2B
SW1
IPRG1
V
I
TH1
IPRG2
PLLLPF
SGND
V
PGOOD
V
I
TH2
TRACK
FB1
SYNC/FCB
LTC3736EUF
IN
FB2
PGND
R
TRACKB
118k
SENSE1
PGND
BG1
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
25
L1
MP1
21
+
20
19
18
17
16
15
14
13
12
11
+
MP2
10
V
V
IN2
3.3V
V
IN1
IN2
≥ V
IN2
≥ 2.5V
MN1
Si7540DP
MN2
Si7540DP
1.5µH
+
L2
1.5µH
C
, C
OUT1
L1, L2: VISHAY IHLP-2525CZ-01
: SANYO 4TPB150MC
OUT2
C
OUT1
150µF
C
OUT2
+
150µF
3736 TA03
V
OUT1
2.5V
5A
V
OUT2
1.8V
4A
R
FB1A
59k
C
ITH1A
100pF
C
ITH1
220pF
IN
×2
C
VIN
1µF
C
ITH2B
100pF
C
SS
10nF
R
FB2A
59k
26
3736fa
PACKAGE DESCRIPTIO
4.50 ± 0.05
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
U
0.70 ±0.05
PACKAGE
OUTLINE
0.25 ±0.05
LTC3736
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
4.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 5)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.75 ± 0.05
2.45 ± 0.10
(4-SIDES)
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
23
0.23 TYP
(4 SIDES)
24
0.38 ± 0.10
1
2
(UF24) QFN 0603
0.25 ± 0.05
0.50 BSC
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 ±.005
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.007 – .0098
(0.178 – 0.249)
.016 – .050
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
(0.406 – 1.270)
(MILLIMETERS)
INCHES
.150 – .165
.015
± .004
(0.38 ± 0.10)
0° – 8° TYP
.0250 TYP.0165 ± .0015
× 45°
GN Package
.229 – .244
(5.817 – 6.198)
(1.351 – 1.727)
.008 – .012
(0.203 – 0.305)
.053 – .068
12
(8.560 – 8.738)
4
3
.337 – .344*
5
161718192021222324
15
14
13
678 9 10 11 12
.0250
(0.635)
BSC
.033
(0.838)
REF
.150 – .157**
(3.810 – 3.988)
.004 – .0098
(0.102 – 0.249)
GN24 (SSOP) 0502
3736fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3736
TYPICAL APPLICATIO
U
3.3V
10µF
2-Phase, Single Output Synchronous DC/DC Converter (3.3VIN to 1.8V
FB1A
59k
R
C
ITH1
15k
ITH2B
22pF
R
FB1B
118k
L1
22
SW1
23
IPRG1
24
V
FB1
1
I
TH1
2
IPRG2
3
PLLLPF
4
SGND
LTC3736EUF
5
V
IN
1M
9
PGOOD
7
V
FB2
8
I
TH2
6
TRACK
SENSE1
SYNC/FCB
RUN/SS
SENSE2
PGND
25
PGND
BG1
TG1
PGND
TG2
BG2
PGND
SW2
+
+
MP1
21
20
19
18
17
16
15
14
13
12
11
MP2
10
C
, C
OUT1
OUT2
L1, L2: VISHAY IHLP-2525CZ-01
MN1
Si7540DP
MN2
Si7540DP
: SANYO 4TPB150MC
1.5µH
L2
1.5µH
+
R
C
ITH1A
100pF
C
ITH1
V
IN
C
IN
×2
R
4.7nF
220pF
VIN
C
VIN
1µF
C
SS
10Ω
C
150µF
C
+
150µF
OUT1
OUT2
3736 TA02
OUT
at 8A)
V
OUT
1.8V
8A
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1622 Synchronizable Low Input Voltage Current Mode VIN 2V to 10V, Burst Mode Operation, 8-Lead MSOP
Step-Down DC/DC Controller
LTC1735 High Efficiency Synchronous Step-Down Controller Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection,
3.5V ≤ V
LTC1772 Constant Frequency Current Mode Step-Down 2.5V ≤ VIN ≤ 9.8V, I
DC/DC Controller
LTC1773 Synchronous Step-Down Controller 2.65V ≤ VIN ≤ 8.5V, I
LTC1778 No R
TM
Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor,
SENSE
Fast Transient Response, 4V ≤ VIN ≤ 36V
LTC1872 Constant Frequency Current Mode Step-Up Controller 2.5V ≤ VIN ≤ 9.8V, SOT-23 Package, 550kHz
LTC2923 Power Supply Tracking Controller Controls Up to Three Supplies, 10-Lead MSOP
LTC3411 1.25A (I
), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, IQ = 60µA, ISD = <1µA,
OUT
MS Package
LTC3416 4A (I
), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.25V to 5.5V, ISD = <1µA,
OUT
with Output Tracking TSSOP-20E Package
LTC3701 2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller 2.5V ≤ VIN ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
LTC3708 Fast 2-Phase, No R
Buck Controller with Constant On-Time Dual Controller, VIN Up to 36V, Very Low
SENSE
Output Tracking Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down Constant Frequency, VIN to 36V, 5V and 3.3V LDOs,
Switching Regulator 5mm × 5mm QFN or 28-Lead SSOP
LTC3736-1 Dual, 2-Phase, No R
Synchronous Controller with VIN: 2.75V to 9.8V, I
SENSE
Spread Spectrum Spread Spectrum Operation; Output Tracking
LTC3737 Dual, 2-Phase, No R
Controller with Non-Synchronous Constant Frequency With PLL, 4mm × 4mm
SENSE
Output Tracking QFN and 24-Lead SSOP Packages
LTC3776 Dual, 2-Phase, No R
Synchronous Controller for DDR/QDR Provides V
SENSE
Memory Termination Adjustable Constant Frequency With PLL Up to 850kHz; Spread
Spectrum Operation; 4mm × 4mm QFN and 24-Lead SSOP
Packages
LTC3808 No R
, Low EMI, Synchronous Step-Down Controller with 2.75V ≤ VIN ≤ 9.8V; Spread Spectrum Operation; 3mm × 4mm
SENSE
Output Tracking DFN and 16-Lead SSOP Packages
No R
is a trademark of Linear Technology Corporation.
SENSE
Linear Technology Corporation
28
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
≤ 36V
IN
Up to 4A, SOT-23 Package, 550kHz
OUT
Up to 4A, 10-Lead MSOP
OUT
Up to 5A, 4mm × 4mm QFN Package
OUT
and VTT With One IC; 2.75V ≤ VIN ≤ 9.8V;
DDQ
LT/TP 0305 500 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
3736fa
Loading...