LINEAR TECHNOLOGY LTC3736 Technical data
LTC3736
FEATURES
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
■
Tracking Function
■
Wide VIN Range: 2.75V to 9.8V
■
Constant Frequency Current Mode Operation
■
0.6V ±1.5% Voltage Reference
■
Low Dropout Operation: 100% Duty Cycle
■
True PLL for Frequency Locking or Adjustment
■
Selectable Burst Mode®/Forced Continuous Operation
■
Auxiliary Winding Regulation
■
Internal Soft-Start Circuitry
■
Power Good Output Voltage Monitor
■
Output Overvoltage Protection
■
Micropower Shutdown: IQ = 9µA
■
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages
U
APPLICATIO S
■
One or Two Lithium-Ion Powered Devices
■
Notebook and Palmtop Computers, PDAs
■
Portable Instruments
■
Distributed DC Power Systems
Dual 2-Phase, No R
SENSE
,
Synchronous Controller
with Output Tracking
U
DESCRIPTIO
The LTC®3736 is a 2-phase dual synchronous step-down
switching regulator controller with tracking that drives
external complementary power MOSFETs using few external components. The constant frequency current mode
architecture with MOSFET VDS sensing eliminates the
need for sense resistors and improves efficiency. Power
loss and noise due to the ESR of the input capacitance are
minimized by operating the two controllers out of phase.
Burst Mode operation provides high efficiency at light loads.
100% duty cycle capability provides low dropout operation,
extending operating time in battery-powered systems.
The switching frequency can be programmed up to 750kHz,
allowing the use of small surface mount inductors and capacitors. For noise sensitive applications, the LTC3736
switching frequency can be externally synchronized from
250kHz to 850kHz. Burst Mode operation is inhibited during synchronization or when the SYNC/FCB pin is pulled low
in order to reduce noise and RF interference. Automatic softstart is internally controlled.
The LTC3736 is available in the tiny thermally enhanced
(4mm × 4mm) QFN package or 24-lead SSOP narrow
package.
TM
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode
is a registered trademark of Linear Technology Corporation. No R
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258,
6304066, 6611131, 6498466.
is a trademark of
SENSE
TYPICAL APPLICATIO
High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
SENSE1
2.2µH
47µF
187k
220pF
59k
V
OUT1
2.5V
TG1 TG2
SW1 SW2
BG1 BG2
PGND PGND
V
FB1
I
TH1
15k
V
IN
+
SENSE2
LTC3736
SGND
U
Efficiency vs Load Current
V
IN
2.75V TO 9.8V
10µF
220pF
×2
2.2µH
59k
118k
47µF
3736 TA01a
V
1.8V
OUT2
+
V
FB2
I
TH2
15k
100
95
VIN = 3.3V
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
1 100 1000 10000
VIN = 4.2V
VIN = 5V
10
LOAD CURRENT (mA)
FIGURE 16 CIRCUIT
= 2.5V
V
OUT
3736 TA01b
3736fa
1
LTC3736
WWWU
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
PLLLPF, RUN/SS, SYNC/FCB,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages ................. – 0.3V to (V
V
, V
, I
, I
FB1
FB2
TH1
SW1, SW2 Voltages ............ – 2V to V
Voltages .................. – 0.3V to 2.4V
TH2
+ 1V or 10V Max
IN
+ 0.3V)
IN
PGOOD ..................................................... – 0.3V to 10V
UU
W
PACKAGE/ORDER I FOR ATIO
TOP VIEW
FB1
V
IPRG1
SW1
24 23 22 21 20 19
I
1
TH1
IPRG2
2
PLLLPF
3
SGND
4
V
5
IN
TRACK
6
24-LEAD (4mm × 4mm) PLASTIC QFN
T
JMAX
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
25
7 8 9
V
10 11 12
FB2
TH2
I
PGOOD
UF PACKAGE
= 125°C, θJA = 37°C/W
SENSE1+PGND
+
SW2
SENSE2
BG1
18
17
16
15
14
13
PGND
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
ORDER PART
NUMBER
LTC3736EUF
UF PART MARKING
3736
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. – 65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
(LTC3736EGN) ..................................................... 300°C
ORDER PART
NUMBER
LTC3736EGN
1
SW1
2
IPRG1
3
V
FB1
4
I
TH1
5
IPRG2
6
PLLLPF
7
SGND
8
V
IN
9
TRACK
10
V
FB2
11
I
TH2
12
PGOOD
24-LEAD PLASTIC SSOP
T
JMAX
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
GN PACKAGE
= 125°C, θJA = 130°C/ W
SENSE1
PGND
BG1
SYNC/FCB
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
SW2
+
+
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
Input DC Supply Current (Note 4)
Sleep Mode 300 425 µA
Shutdown RUN/SS = 0V 9 20 µA
UVLO V
= UVLO Threshold –200mV 3 10 µA
IN
Undervoltage Lockout Threshold VIN Falling ● 1.95 2.25 2.55 V
Rising ● 2.15 2.45 2.75 V
V
IN
Shutdown Threshold at RUN/SS 0.45 0.65 0.85 V
Start-Up Current Source RUN/SS = 0V 0.4 0.7 1 µA
Regulated Feedback Voltage 0°C to 85°C (Note 5) 0.591 0.6 0.609 V
–40°C to 85°C
● 0.588 0.6 0.612 V
Output Voltage Line Regulation 2.75V < VIN < 9.8V (Note 5) 0.05 0.2 mV/V
3736fa
2
LTC3736
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Load Regulation ITH = 0.9V (Note 5) 0.12 0.5 %
ITH = 1.7V –0.12 –0.5 %
V
Input Current (Note 5) 10 50 nA
FB1,2
TRACK Input Current TRACK = 0.6V 10 50 nA
Overvoltage Protect Threshold Measured at V
Overvoltage Protect Hysteresis 20 mV
Auxiliary Feedback Threshold SYNC/FCB Ramping Positive 0.525 0.6 0.675 V
Top Gate (TG) Drive 1, 2 Rise Time CL = 3000pF 40 ns
Top Gate (TG) Drive 1, 2 Fall Time CL = 3000pF 40 ns
Bottom Gate (BG) Drive 1, 2 Rise Time CL = 3000pF 50 ns
Bottom Gate (BG) Drive 1, 2 Fall Time CL = 3000pF 40 ns
Maximum Current Sense Voltage (∆V
(SENSE+ – SW) IPRG = 0V ● 70 85 100 mV
Soft-Start Time Time for V
Oscillator and Phase-Locked Loop
Oscillator Frequency Unsynchronized (SYNC/FCB Not Clocked)
Phase-Locked Loop Lock Range SYNC/FCB Clocked
Phase Detector Output Current
Sinking f
Sourcing f
PGOOD Output
PGOOD Voltage Low I
PGOOD Trip Level VFB with Respect to Set Output Voltage
SENSE(MAX)
) IPRG = Floating ● 110 125 140 mV
IPRG = V
PLLLPF = Floating ● 480 550 600 kHz
PLLLPF = 0V
PLLLPF = V
Minimum Synchronizable Frequency ● 200 250 kHz
Maximum Synchronizable Frequency
> f
OSC
< f
OSC
PGOOD
VFB < 0.6V, Ramping Positive –13 –10.0 –7 %
V
FB
VFB > 0.6V, Ramping Negative 7 10.0 13 %
V
FB
FB
IN
to Ramp from 0.05V to 0.55V 0.667 0.833 1 ms
FB1
IN
SYNC/FCB
SYNC/FCB
Sinking 1mA 125 mV
< 0.6V, Ramping Negative –16 –13.3 –10 %
> 0.6V, Ramping Positive 10 13.3 16 %
0.66 0.68 0.7 V
● 185 204 223 mV
● 260 300 340 kHz
● 650 750 825 kHz
● 850 1150 kHz
–4 µA
4 µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3736E is guaranteed to meet specified performance from
0°C to 70°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
Note 3: T
dissipation P
is calculated from the ambient temperature TA and power
J
according to the following formula:
D
TJ = TA + (PD • θJA°C/W)
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3736 is tested in a feedback loop that servos ITH to a
specified voltage and measures the resultant V
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
voltage.
FB
3736fa
3
LTC3736
INPUT VOLTAGE (V)
2
–5
NORMALIZED FREQUENCY SHIFT (%)
–4
–2
–1
0
5
2
4
6
7
3736 G08
–3
3
4
1
35
8
9
10
UW
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Efficiency and Power Loss
vs Load Current
100
FIGURE 15 CIRCUIT
95
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
1 100 1000 10000
VIN = 5V
SYNC/FCB = V
10
IN
LOAD CURRENT (mA)
V
OUT
V
OUT
V
OUT
V
OUT
Load Step (Pulse Skipping Mode)
V
OUT
AC-COUPLED
100mV/DIV
I
L
2A/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = 550kHz EXTERNAL CLOCK
FIGURE 17 CIRCUIT
= 3.3V
= 2.5V
= 1.8V
= 1.2V
3736 G01
100µs/DIV
10
AC-COUPLED
100mV/DIV
1
POWER LOSS (W)
0.1
0.01
0.001
Load Step (Burst Mode Operation)
V
OUT
I
L
2A/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = V
FIGURE 17 CIRCUIT
3736 G04
100µs/DIV
IN
SYNC/FCB = V
SKIPPING MODE
SYNC/FCB = 550kHz
Burst Mode
OPERATION
CONTINUOUS
SYNC/FCB = 0V
Load Step
(Forced Continuous Mode)
V
OUT
AC-COUPLED
100mV/DIV
I
L
2A/DIV
3736 G02
Inductor Current at Light Load
IN
FORCED
MODE
PULSE
= 3.3V
V
IN
= 1.8V
V
OUT
= 200mA
I
LOAD
FIGURE 17 CIRCUIT
4µs/DIV
= 3.3V
V
IN
= 1.8V
V
OUT
= 300mA TO 3A
I
LOAD
SYNC/FCB = 0V
FIGURE 17 CIRCUIT
100µs/DIV
3736 G05
I
L
1A/DIV
3736 G03
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
VIN = 5V
R
LOAD1
FIGURE 15 CIRCUIT
4
= R
LOAD2
200µs/DIV
= 1Ω
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
V
OUT1
2.5V
V
OUT2
1.8V
500mV/
DIV
3736 G06
VIN = 5V
= R
R
LOAD1
FIGURE 15 CIRCUIT
LOAD2
40ms/DIV
= 1Ω
3736 G07
V
OUT1
2.5V
V
OUT2
1.8V
500mV/
DIV
Oscillator Frequency
vs Input Voltage
3736fa
TEMPERATURE (°C)
–60
115
MAXIMUM CURRENT SENSE THRESHOLD (mV)
120
125
130
135
–40 –20 0 20
3736 G14
40 60 80 100
I
PRG
= FLOAT
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC3736
TA = 25°C unless otherwise noted.
Maximum Current Sense Voltage
Pin Voltage
vs I
TH
100
80
60
40
20
CURRENT LIMIT (%)
0
–20
Burst Mode OPERATION
(I
TH
Burst Mode OPERATION
(I
TH
FORCED CONTINUOUS
MODE
PULSE SKIPPING
MODE
0.5
RISING)
FALLING)
1 1.5
ITH VOLTAGE (V)
Shutdown (RUN) Threshold
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
RUN/SS VOLTAGE (V)
0.2
0.1
0
–60
–40 0
–20
20
TEMPERATURE (°C)
40
Regulated Feedback Voltage
Efficiency vs Load Current
3736 G09
2
100
95
90
85
80
75
70
EFFICIENCY (%)
65
60
55
50
Burst Mode
OPERATION
(SYNC/FCB = V
1 100 1000 10000
)
IN
PULSE SKIPPING
MODE
(SYNC/FCB = 550kHz)
FIGURE 15 CIRCUIT
V
V
10
LOAD CURRENT (mA)
FORCED
CONTINUOUS
(SYNC/FCB = 0V)
= 5V
IN
= 2.5V
OUT
3736 G10
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
RUN/SS PULL-UP CURRENT (µA)
80
60
100
3736 G12
0.4
–60
–20 20
–40 0
TEMPERATURE (°C)
60
40
80
100
3736 G13
vs Temperature
0.609
0.607
0.605
0.603
0.601
0.599
0.597
FEEDBACK VOLTAGE (V)
0.595
0.593
0.591
–60
–40
–20
20
0
TEMPERATURE (°C)
40
Maximum Current Sense Threshold
vs Temperature
80
3736 G11
100
60
Oscillator Frequency
vs Temperature
10
8
6
4
2
0
–2
–4
–6
NROMALIZED FREQUENCY (%)
–8
–10
–60
–40 0
–20
TEMPERATURE (°C)
Undervoltage Lockout Threshold
vs Temperature
2.50
2.45
2.40
2.35
2.30
) VOLTAGE (V)
IN
2.25
INPUT (V
2.20
2.15
80
20
60
40
100
3736 G15
2.10
–60
–40
VIN RISING
VIN FALLING
–20
20
0
TEMPERATURE (°C)
40
60
80
3736 G16
100
3736fa
5
LTC3736
UW
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Shutdown Quiescent Current
vs Input Voltage
20
RUN/SS = 0V
18
16
14
12
10
8
6
SHUTDOWN CURRENT (µA)
4
2
0
2
U
PI FU CTIO S
I
TH1/ITH2
(Pins 1, 8/ Pins 4, 11): Current Threshold and
35
4
6
INPUT VOLTAGE (V)
7
UU
(UF/GN Package)
9
8
10
3736 G17
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
PLLLPF (Pin 3/Pin 6): Frequency Set/PLL Lowpass Filter.
When synchronizing to an external clock, this pin serves
as the lowpass filter point for the phase-locked loop. Normally a series RC is connected between this pin and ground.
When not synchronizing to an external clock, this pin serves
as the frequency select input. Tying this pin to GND selects
300kHz operation; tying this pin to VIN selects 750kHz operation. Floating this pin selects 550kHz operation.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Controller. Allows the start-up of V
to “track” that of V
OUT2
OUT1
according to a ratio established by a resistor divider on
V
connected to the TRACK pin. For one-to-one track-
OUT1
ing of V
OUT1
and V
during start-up, a resistor divider
OUT2
RUN/SS Start-Up Current
vs Input Voltage
0.9
RUN/SS = 0V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
RUN/SS PIN PULL-UP CURRENT (µA)
0.1
0
3
2
4
with values equal to those connected to V
should be used to connect to TRACK from V
6
5
INPUT VOLTAGE (V)
7
9
3736 G18
10
from V
FB2
OUT1
OUT2
.
8
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
FB1
, V
FB2
) is not
within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/ Pins 15, 19, 23): Power
Ground. These pins serve as the ground connection for the
gate drivers and the negative input to the reverse current
comparators. The Exposed Pad (UF package) must be
soldered to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
TG1/ TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive
Output. These pins drive the gates of the external P-channel
MOSFETs. These pins have an output swing from PGND to
SENSE+.
SYNC/FCB (Pin 18/Pin 21): This pin performs three
functions: 1) auxiliary winding feedback input, 2) external
clock synchronization input for phase-locked loop, and 3)
Burst Mode operation or forced continuous mode select.
3736fa
6
LTC3736
U
PI FU CTIO S
UU
(UF/GN Package)
For auxiliary winding applications, connect to a resistor
divider from the auxiliary output. To synchronize with an
external clock using the PLL, apply a CMOS compatible
clock with a frequency between 250kHz and 850kHz. To
select Burst Mode operation at light loads, tie this pin to V
IN
.
Grounding this pin selects forced continuous operation,
which allows the inductor current to reverse. When
synchronized to an external clock, pulse-skipping operation
is enabled at light loads.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external Nchannel MOSFETs. These pins have an output swing from
PGND to SENSE
+
.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the external P-channel MOSFET.
SW1/ SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the external P-channel MOSFETs, the drain of the external N-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These pins
select the maximum allowed voltage drop between the
+
SENSE
and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to V
, GND or float to select 204mV, 85mV or 125mV
IN
respectively.
V
FB1/VFB2
(Pins 24, 7/Pins 3, 10): Feedback Pins. Receives
the remotely sensed feedback voltage for its controller from
an external resistor divider across the output.
U
U
W
FU CTIO AL DIAGRA
V
UNDERVOLTAGE
LOCKOUT
0.7µA
RUN/SS
SYNC/FCB
PLLLPF
IPRG1
IPRG2
0.6V
BURST DEFEAT/
SYNC DETECT
VOLTAGE
CONTROLLED
OSCILLATOR
–
FCB
+
VOLTAGE
MAXIMUM
CONTROLLED
SENSE VOLTAGE
OSCILLATOR
SELECT
(Common Circuitry)
R
SHDN
CLK1
CLK2
FCB
C
VIN
t
= 1ms
SEC
BURSTDIS
DETECTOR
IPROG1
IPROG2
0.6V
V
PHASE
IN
VOLTAGE
REFERENCE
EXTSS
VIN
V
IN
(TO CONTROLLER 1, 2)
REF
0.54V
+
–
SLOPE
COMP
V
V
INTSS
SLOPE1
SLOPE2
–
FB1
+
+
FB2
–
UV1
UV2
OV1
SHDN
OV2
PGOOD
3736 FD
3736fa
7
LTC3736
U
U
W
FU CTIO AL DIAGRA
CLK1
–
ICMP
+
IPROG1
BURSTDIS
0.3V
(Controller 1)
RS1
Q
S
R
OV1
SC1
FCB
SLOPE1
SW1
SENSE1
+
SWITCHING
LOGIC
BLANKING
CIRCUIT
SLEEP1
+
–
AND
IREV1
ANTISHOOT
THROUGH
SHDN
EAMP
PGND
SENSE1
–
+
+
SENSE1
TG1
SW1
BG1
PGND
+
0.6V
V
IN
C
IN
MP1
MN1
L1
C
OUT1
EXTSS
V
FB1
R1B
R1A
V
OUT1
SLEEP1
OV1
BURSTDIS
0.15V
INTSS
I
0.12V
V
FB1
TH1
R
ITH1
C
ITH1
–
+
SC1
+
SCP
–
V
+
FB1
IREV1
0.68V
–
RICMPOVP
IPROG1 FCB
–
+
PGND
SW1
3736 CONT1
8
3736fa
LTC3736
U
U
W
FU CTIO AL DIAGRA
CLK2
–
ICMP
+
BURSTDIS
0.3V
(Controller 2)
RS2
S
Q
R
OV2
SC2
FCB
SLOPE2
SW2
SENSE2
+
SWITCHING
LOGIC
BLANKING
CIRCUIT
SLEEP2
+
–
–
AND
IREV2
ANTISHOOT
THROUGH
SHDN
EAMP
PGND
SENSE2
–
+
0.6V
+
SENSE2
TG2
SW2
BG2
PGND
V
IN
+
MP2
MN2
V
FB2
TRACK
I
TH2
L2
C
OUT2
V
OUT1
R
R
TRACKB
TRACKA
R2B
R2A
V
OUT2
SLEEP2
OV2
BURSTDIS
OVP
R
+
SC2
0.15V
V
+
FB2
IREV2
0.68V
–
SCP
TRACK
IPROG2 FCB
+
–
–
+
0.12V
V
FB2
PGND
SW2
3736 CONT2
ITH2
C
ITH2
3736fa
9
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