LINEAR TECHNOLOGY LTC3732 Technical data

FEATURES

■

3-Phase Current Mode Controller with
Onboard MOSFET Drivers

■

±5% Output Current Matching Optimizes Thermal
Performance and Size of Inductors and MOSFETs

■

4.5V ≤ VCC ≤ 7V; 4.5V ≤ VIN ≤ 32V

■

Differential Amplifier Accurately Senses V

■

Reduced Input and Output Capacitance

■

Reduced Power Supply Induced Noise

■

VID DAC Programmable from 1.1V to 1.85V

OUT

(VRM9.0/9.1)

■

±10% Power Good Output Indicator

■

250kHz to 600kHz Per Phase, PLL, Fixed Frequency

■

PWM, Stage SheddingTM or Burst Mode® Operation

■

OPTI-LOOP® Compensation Minimizes C

■

Adjustable Soft-Start Current Ramping

■

Short-Circuit Shutdown Timer with Defeat Option

■

Overvoltage Soft Latch

■

Small 36-Lead Narrow (0.209") SSOP Package

■

QFN 5mm × 7mm 38-Lead Package

U

OUT

APPLICATIO S

■

Desktop Computers

■

High Performance Notebook Computers

■

High Output Current DC/DC Power Supplies

LTC3732

3-Phase, 5-Bit VID,

600kHz, Synchronous Buck

Switching Regulator Controller

U

DESCRIPTIO

The LTC®3732 is a PolyPhase® synchronous step-down
switching regulator controller that drives all N-channel
external power MOSFET stages in a phase-lockable fixed
frequency architecture. The 3-phase controller drives its
output stages with 120° phase separation at frequencies
of up to 600kHz per phase to minimize the RMS current
losses in both the input and output filter capacitors. The 3­phase technique effectively triples the fundamental fre­quency, improving transient response while operating
each controller at an optimal frequency for high efficiency
and ease of thermal design. Light load efficiency is opti­mized by using a choice of output Stage Shedding or Burst
Mode technology.

A differential amplifier provides true remote sensing of both
the high and low side of the output voltage at load points.

Soft-start and a defeatable, timed short-circuit shutdown
protect the MOSFETs and the load. A foldback current
circuit also provides protection for the external MOSFETs
under short-circuit or overload conditions.

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology
Corporation. Stage Shedding is a trademark of Linear Technology Corporation

TYPICAL APPLICATIO

V

CC

4.5V TO 7V

POWER GOOD INDICATOR

OPTIONAL SYNC IN

U

LTC3732

SW1

SENSE1
SENSE1

SW2

PGND

SENSE2
SENSE2

SW3

SENSE3
SENSE3

TG1V

BG1

TG2

BG2

TG3

BG3

1µH

0.003Ω

+
–

V

IN

1µH

0.003Ω

+
–

V

IN

1µH

0.003Ω

+
–

+

+

0.1µF

100pF

CC

BOOST1
BOOST2
BOOST3

PGOOD
PLLIN

PLLFLTR

VID0-VID4

I

TH

RUN/SS
SGND

EAIN

–

IN

+

IN

10µF

0.1µF

SW3 SW2 SW1

5 VID BITS

680pF

5k

Figure 1. High Current Triple Phase Step-Down Converter

22µF
35V

V

OUT

1.1V TO 1.85V
55A

C

OUT

470µF
4V

3732 F01

V

IN

5V TO 28V

3732f

1

LTC3732

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Topside Driver Voltages (BOOSTN)............38V to –0.3V

Switch Voltage (SWN)...................................32V to –5V

Boosted Driver Voltage (BOOSTN – SWN)....7V to –0.3V

Peak Output Current <1ms (TGN, BGN) ..................... 5A

Supply Voltage (VCC), PGOOD

Pin Voltage .................................................. 7V to –0.3V

RUN/SS, PLLFLTR, PLLIN, FCB Voltages .. VCC to –0.3V

ITH Voltage................................................2.4V to –0.3V

UU

W

PACKAGE/ORDER I FOR ATIO

1

VID1

2

PLLIN

3

PLLFLTR

4

FCB

+

5

IN

–

6

IN

7

DIFFOUT

8

EAIN

9

SGND

+

10

SENSE1

–

11

SENSE1

+

12

SENSE2

–

13

SENSE2

–

14

SENSE3

+

15

SENSE3

16

RUN/SS

17

I

TH

18

VID2

36-LEAD PLASTIC SSOP

T

= 125°C, θJA = 95°C/W

JMAX

TOP VIEW

G PACKAGE

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

VID0
PGOOD
BOOST1
TG1
SW1
BOOST2
TG2
SW2
V

CC

BG1
PGND
BG2
BG3
SW3
TG3
BOOST3
VID4
VID3

ORDER PART

NUMBER

LTC3732CG

Operating Ambient Temperature Range....... 0°C to 70°C

Junction Temperature (Notes 2, 3, 7) ................... 125°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature (Soldering, 10 sec)

SSOP Package.................................................. 300°C

Reflow Peak Body Temperature

QFN Package .................................................... 240°C

TOP VIEW

ORDER PART

NUMBER

FCB

PLLFLTR

PLLIN

VID1

VID0

PGOOD

17 18 19

VID3

VID4

BOOST1

TG3

BOOST3

31
30
29
28
27
26
25
24
23
22
21
20

TG1
SW1
BOOST2
TG2
SW2
V

CC

DRV

CC

BG1
PGND
BG2
BG3
SW3

LTC3732CUHF

38 37 36 35 34 33 32

+

1IN

–

IN

2

DIFFOUT

3

EAIN

4

PADDLE

5

SGND

6

+

SENSE1

7

–

SENSE1

8

+

SENSE2

9

–

SENSE2

10

–

SENSE3

11

+

SENSE3

12

(MUST BE CONNECTED TO PCB AND SGND PIN)

UNDERSIDE

PADDLE

IS SGND

13 14 15 16

TH

I

VID2

RUN/SS

UHF PACKAGE

38-LEAD (7mm × 5mm) PLASTIC QFN

PADDLE IS SGND

T

= 125°C, θJA = 34°C/W

JMAX

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

V

REGULATED

V

SENSEMAX

I

MATCH

V

LOADREG

V

REFLNREG

Regulated Voltage at IN

Maximum Current Sense Threshold V

Current Match Worst-Case Error at V
Output Voltage Load Regulation (Note 3)

Output Voltage Line Regulation VCC = 4.5V to 7V 0.03 %/V

+

(Note 3); VID Code = 11111, V

= 1.2V 1.067 1.075 1.083 V

ITH

● 1.064 1.075 1.086 V

= 0.5V, V

EAIN

V

SENSE1–, VSENSE2–, VSENSE3–

Measured in Servo Loop, ∆I
Measured in Servo Loop, ∆I

Open, 65 75 85 mV

ITH

= 0.6V, 1.8V ● 62 75 88 mV

SENSE MAX

TH
TH

Voltage = 1.2V to 0.7V ● 0.1 0.5 %
Voltage = 1.2V to 2V ● –0.1 –0.5 %

–5 5 %

3732f

2

LTC3732

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
g

m

g

mOL

V

FCB

I

FCB

V

BINHIBIT

Transconductance Amplifier g

m

ITH = 1.2V, Sink/Source 25µA (Note 3) ● 3.6 5 6.6 mmho

Transconductance Amplifier GBW ITH = 1.2V, (gm • ZL, ZL = Series 1k-100kΩ-1nF) 3 MHz
Forced Continuous Threshold ● 0.58 0.60 0.62 V
FCB Bias Current V
Burst Inhibit Threshold Measured at FCB pin VCC – 1.5 V

= 0.65V 0.2 0.7 µA

FCB

– 0.7 V

CC

– 0.3 V

CC

UVR Undervoltage RUN/SS Reset VCC Lowered Until the RUN/SS Pin is Pulled Low 3.3 3.8 4.5 V
I

Q

I

RUN/SS

V

RUN/SS

V

RUN/SSARM

Input DC Supply Current (Note 4)
Normal Mode V
Shutdown V

Soft-Start Charge Current V
RUN/SS Pin ON Threshold V
RUN/SS Pin Arming Threshold V

= 5V 2.2 3.5 mA

CC
RUN/SS

RUN/SS

RUN/SS

RUN/SS

= 0V, VID0 to VID4 Open 25 100 µA
= 1.9V –0.8 –1.5 –2.5 µA

, Ramping Positive 1 1.5 1.9 V
, Ramping Positive Until Short-Circuit 3.8 4.5 V

Latch-Off is Armed

V

RUN/SSLO

I

SCL

I

SDLHO

I

SENSE

DF

MAX

TG tR,t

BG t

R, tF

TG/BG t

F

RUN/SS Pin Latch-Off Threshold V
RUN/SS Discharge Current Soft-Short Condition V
Shutdown Latch Disable Current V
SENSE Pins Source Current SENSE1+, SENSE1–, SENSE2+, SENSE2–,1320µA

Maximum Duty Factor In Dropout; V
Top Gate Rise Time C

Top Gate Fall Time C
Bottom Gate Rise Time C

Bottom Gate Fall Time C
Top Gate Off to Bottom Gate On Delay All Controllers, C

1D

, Ramping Negative 3.2 V

RUN/SS

= 0.375V, V

EAIN

= 0.375V, V

EAIN

+

SENSE3

, SENSE3– All Equal 1.2V; Current at Each Pin

SENSEMAX

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 4.5V 1.5 5 µA

RUN/SS

≤ 30mV 95 98.5 %

= 3300pF Each Driver 50 ns

LOAD

= 4.5V –5 –1.5 µA

RUN/SS

Synchronous Switch-On Delay Time

BG/TG t

Bottom Gate Off to Top Gate On Delay All Controllers, C

2D

= 3300pF Each Driver 60 ns

LOAD

Top Switch-On Delay Time

t

ON(MIN)

Minimum On-Time Tested with a Square Wave (Note 5) 110 ns

VID Parameters

VID

IL

VID

IH

VID

PULLUP

ATTEN

ERR

Maximum Low Level Input Voltage 0.4 V
Minimum High Level Input Voltage 2 V
VID0 to VID4 Internal Pull-Up Current V

= 0V 3 µA

VID

VID0 to VID4 (Note 6) ● –0.25 0.25 %

Power Good Output Indication

V

PGL

I

PGOOD

V

PGTHNEG

V

PGTHPOS

V

PGDLY

PGOOD Voltage Output Low I
PGOOD Output Leakage V
PGOOD Trip Thesholds V

V

Ramping Negative VID Code = 11111, –7 –10 –13 %

DIFFOUT

V

Ramping Positive PGOOD Goes Low After V

DIFFOUT

Power Good Fault Report Delay After V

= 2mA 0.1 0.3 V

PGOOD

= 5V 1 µA

PGOOD

with Respect to Set Output Voltage,

DIFFOUT

Delay 7 11 13 %

UVDLY

is Forced Outside the PGOOD Thresholds 100 150 µs

EAIN

3732f

3

LTC3732

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VCC = V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

R

PLLTH

R

PLL IN

I

PLLFLTR

R

RELPHS

Nominal Frequency V
Lowest Frequency V
Highest Frequency V

= 1.2V 360 400 440 kHz

PLLFLTR

= 0V 190 225 260 kHz

PLLFLTR

= 2.4V 600 680 750 kHz

PLLFLTR

PLLIN Input Threshold Minimum Pulse Width >100ns 1 V
PLLIN Input Resistance 50 kΩ
Phase Detector Output Current

Sinking Capability f
Sourcing Capability f

PLLIN
PLLIN

< f
> f

OSC
OSC

20 µA
20 µA

Controller 2-Controller 1 Phase 120 Deg
Controller 3-Controller 1 Phase 240 Deg

Differential Amplifier

A

V

V

OS

Differential Gain 0.995 1.000 1.005 V/V
Input Offset Voltage IN+ = IN

–

= 1.2V, I

= 1mA, 0.5 5 mV

OUT

Input Referred; Gain = 1

CM Common Mode Input Voltage Range 0 V

+

CMRR Common Mode Rejection Ratio 0V < IN
I

CL

GBP Gain Bandwidth Product I

Output Current 10 40 mA

= 1mA 2 MHz

OUT

= IN

–

< 5V, I

= 1mA, Input Referred 50 70 dB

OUT

CC

SR Slew Rate RL = 2k 5 V/µs
V

O(MAX)

R

IN

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired. A maximum current of 200µA is allowed to
pull-up the RUN/SS pin to prevent overcurrent shutdown.

Note 2: TJ is calculated from the ambient temperature TA and power
dissipation P

LTC3732CG: TJ = TA + (PD × 95°C/W)
LTC3732CUHF: T

Note 3: The IC is tested in a feedback loop that includes the differential
amplifier in a unity-gain configuration loaded with 100µA to ground driving
the VID DAC into the error amplifier and servoing the resultant voltage to
the midrange point for the error amplifier (V

Maximum High Output Voltage I

= 1mA V

OUT

– 1.2 V

CC

–␣ 0.8 V

CC

Input Resistance Measured at IN+ Pin 80 kΩ

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 5: The minimum on-time condition corresponds to an inductor peak-

according to the following formula:

D

= TA + (PD × 34°C/W)

J

to-peak ripple current of ≥40% of I
considerations in the Applications Information Section).

Note 6: ATTEN

specification is in addition to the output voltage

ERR

accuracy specified at VID code = 11111.

(see minimum on-time

MAX

Note 7: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.

ITH

= 1.2V).

Continuous operation above the specified maximum operating junction
temperature may impair device reliability.

V

4

3732f

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3732

Efficiency vs I

100

V

= OPEN

FCB

90

V

= 5V

FCB

80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.1

V

= 0V

FCB

INDUCTOR CURRENT (A)

Reference Voltage vs
Temperature

610

605

600

(Figure 14)

OUT

VIN = 8V

= 1.5V

V

OUT

1 10 100

3732 G01

Efficiency vs V

100

95
90
85
80
75
70

EFFICIENCY (%)

65
60
55
50

0

IL = 50A

5

Error Amplifier gm vs
Temperature

6.0

5.5

(mmho)

m

5.0

(Figure 14)

IN

IL = 20A

10

VIN (V)

15

V

= 1.5V

OUT

f = 250kHz

20

3732 G02

Efficiency vs Frequency (Figure 14)

100

95

VIN = 5V

90

VIN = 12V

85

EFFICIENCY (%)

VIN = 20V

80

25

75

200

Maximum I

300

FREQUENCY (kHz)

SENSE

I

LOAD

V

OUT

VIN = 8V

400

500

Threshold vs

= 20A

= 1.5V

3732 G03

600

Temperature

85

80

VO = 1.8V

THRESHOLD (mV)

75

SENSE

VO = 0.6V

595

REFERENCE VOLTAGE (mV)

590

–30 10 50

–50

–10

TEMPERATURE (°C)

30

70

90

110

3732 G04

4.5

ERROR AMPLIFIER g

4.0
–30 0

–45

–15

15

TEMPERATURE (°C)

Oscillator Frequency vs
Temperature Oscillator Frequency vs V

700

V

PLLFLTR

600

500

400

V

PLLFLTR

300

FREQUENCY (kHz)

200

V

PLLFLTR

100

0

–30 0

–45 –15

= 2.4V

= 1.2V

= 0V

15

TEMPERATURE (°C)

V

= 5V

PLLFLTR

60

30 90

75

45

3732 G07

700

600

500

400

300

FREQUENCY (kHz)

200

100

0

0.6 1.2 2.4

0 1.8

V

60

30 90

45

PLLFLTR

PLLFLTR

75

3732 G05

3732 G08

70

MAXIMUM I

65

–30 0

–45 –15

TEMPERATURE (°C)

30 90

15

Undervoltage Reset Voltage vs
Temperature

5

4

3

2

UNDER VOLTAGE RESET (V)

1

0

–30 0

–45 –15

TEMPERATURE (°C)

30 90

15

60

75

45

3732 G06

60

45

75

3732 G09

3732f

5

LTC3732

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Short-Circuit Arming and Latchoff
vs Temperature Supply Current vs Temperature

5

ARMING

4

LATCHOFF

3

2

RUN/SS PIN VOLTAGE (V)

1

0

–30 0

–45 –15

TEMPERATURE (°C)

30 90

45

15

60

75

3732 G10

VCC = 5V

2.8

2.4

2.0

1.6

1.2

0.8

SUPPLY CURRENT (mA)

0.4

0

–30 0

–45 –15

TEMPERATURE (°C)

30 90

45

15

Maximum Current Sense

Maximum I

80

70

60

(mV)

50

SENSE

40

30

MAXIMUM I

20

10

0

0

1

SENSE

V

RUN/SS

2

vs V

RUN/SS

3

4

VOLTAGE (V)

56

3732 G13

Threshold vs Duty Factor

75

50

VOLTAGE (mV)

25

SENSE

I

0

0

20 40 60 80

DUTY FACTOR (%)

RUN/SS Pull-Up Current vs
Temperature

100

80

60

40

20

75

3732 G11

0

100

3732 G13a

60

2.5
V

RUN/SS

SHUTDOWN CURRENT (µA)

2.0

1.5

1.0

0.5

RUN/SS PULLUP CURRENT (mV)

0

–30 0

–45 –15

Peak Current Threshold vs V

75

60

45

30

15

VOLTAGE THRESHOLD (mV)

0

SENSE

I

–15

0

= 1.9V

60

30 90

45

15

TEMPERATURE (°C)

75

3732 G12

ITH

0.6 1.2 1.8 2.4
V

(V)

ITH

3732 G14

Percentage of Nominal Output vs
Peak I

80

70

60

50

40

VOLTAGE (mV)

30

SENSE

20

PEAK I

10

0

0

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)

(Foldback)

SENSE

2010 30 50 70 90

60

40

6

Maximum Duty Factor vs
Temperature

100

98

96

94

92

MAXIMUM DUTY FACTOR (%)

80

100

3732 G15

90

–30 0

–45 –15

15

TEMPERATURE (°C)

V

= 0V

PLLFLTR

60

30 90

45

75

3732 G16

PIN CURRENT (µA)

–10

SENSE

I

–20

–30

40

30

20

10

0

I

Pin Current vs V

SENSE

0

1

2

V

(V)

OUT

OUT

34

3732 G17

3732f

5

UW

TYPICAL PERFOR A CE CHARACTERISTICS

40

180

LTC3732

Differential Amplifier Gain-PhaseError Amplifier Gain-Phase

0

0

GAIN (dB)

V

OUT

AC, 20mV/DIV

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

35

30

25

20

15

10

RL = 10k AC LOAD

5

100

1k 10k 1M

FREQUENCY (Hz)

100k

Shed Mode at 1Amp, Light Load
Current (Circuit of Figure 14)

3732 G18

135

90

PHASE (DEG)

45

0

–45

–90

–135

GAIN (dB)

–12

–15

V

OUT

AC, 20mV/DIV

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

–3

–6

–9

0001

0.01

0.1

FREQUENCY (MHz)

1

Burst Mode at 1Amp, Light Load
Current (Circuit of Figure 14)

3732 G19

10

–45

–90

–135

–180

–225

PHASE (DEG)

V

OUT

AC, 20mV/DIV

V

SW1

10V/DIV

V

SW2

10V/DIV

V

SW3

10V/DIV

= 12V

V

IN

V

= 1.5V

OUT

= V

V

FCB

CC

FREQUENCY = 250kHz

4µs/DIV 4µs/DIV

3732 G20

Continuous Mode at 1Amp, Light
Load Current (Circuit of Figure 14)

VIN = 12V
V

= 1.5V

OUT

V

= 0V

FCB

FREQUENCY = 250kHz

4µs/DIV 20µs/DIV

3732 G22 3732 G23

V

OUT

AC, 20mV/DIV

20A/DIV

= 12V

V

IN

V

= 1.5V

OUT

= OPEN

V

FCB

FREQUENCY = 250kHz

3732 G21

Transient Load Current Response: 0Amp
to 50Amp (Circuit of Figure 14)

I

L

= 12V

V

IN

V

= 1.5V

OUT

V

= V

FCB

CC

FREQUENCY = 250kHz

3732f

7

LTC3732

U

UU

PI FU CTIO S

VID0 to VID4: Output Voltage Programming Input Pins. A
3µA internal pull-up current is provided on each input pin.
See Table 1 for details. Do not apply voltage to these pins
prior to the application of voltage on the VCC pin.

PLLIN: Synchronization Input to Phase Detector. This pin
is internally terminated to SGND with 50kΩ. The phase­locked loop will force the rising top gate signal of control­ler 1 to be synchronized with the rising edge of the PLLIN
signal.

PLLFLTR: The phase-locked loop’s lowpass filter is tied to
this pin. Alternatively, this pin can be driven with an AC or
DC voltage source to vary the frequency of the internal
oscillator. (Do not apply voltage directly to this pin prior to
the application of voltage on the VCC pin.)

FCB: Forced Continuous Control Input. The voltage ap­plied to this pin sets the operating mode of the controller.
The forced continuous current mode is active when the
applied voltage is less than 0.6V. Burst Mode operation
will be active when the pin is allowed to float and a stage
shedding mode will be active if the pin is tied to the VCC pin.
(Do not apply voltage directly to this pin prior to the
application of voltage on the VCC pin.)

IN+, IN–: Inputs to a precision, unity-gain differential
amplifier with internal precision resistors. This provides
true remote sensing of both the positive and negative load
terminals for precise output voltage control.

DIFFOUT: Output of the Remote Output Voltage Sensing
Differential Amplifier.

EAIN: This is the input to the error amplifier which com­pares the VID divided, feedback voltage to the internal

0.6V reference voltage.
PADDLE (UHF Package Only): This pin is connected to

the heat spreading metal pad at the center of the package
bottom and is tied to the IC’s substrate. It must be
connected to the SGND pin.

SGND: Signal Ground. This pin must be routed separately
under the IC to the PGND pin and then to the main ground
plane.

SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–,
SENSE3–: The Inputs to Each Differential Current Com-

parator. The ITH pin voltage and built-in offsets between
SENSE– and SENSE+ pins, in conjunction with R
the current trip threshold level.

SENSE

, set

RUN/SS: Combination of Soft-Start, Run Control Input
and Short-Circuit Detection Timer. A capacitor to ground
at this pin sets the ramp time to full current output as well
as the time delay prior to an output voltage short-circuit
shutdown. A minimum value of 0.01µF is recommended
on this pin.

ITH: Error Amplifier Output and Switching Regulator Com­pensation Point. All three current comparator’s thresholds
increase with this control voltage.

PGND: Driver Power Ground. This pin connects directly to
the sources of the bottom N-channel external MOSFETs
and the (–) terminals of CIN.

BG1 to BG3: High Current Gate Drives for Bottom N­Channel MOSFETs. Voltage swing at these pins is from
ground to VCC.

VCC: Main Supply Pin. Because this pin supplies both the
controller circuit power as well as the high power pulses
supplied to drive the external MOSFET gates, this pin
needs to be very carefully and closely decoupled to the IC’s
PGND pin.

DRVCC (UHF Package Only): This pin provides power to
the bottom MOSFET on-chip drivers. Tie this pin to the V
pin and carefully decouple this pin to the PGND pin with a
minimum of 5µF of ceramic capacitance immediately
adjacent to the IC package.

SW1 to SW3: Switch Node Connections to Inductors.
Voltage swing at these pins is from a Schottky diode
(external) voltage drop below ground to VIN (where V
the external MOSFET supply rail).

TG1 to TG3: High Current Gate Drives for Top N-channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to the boost voltage source superim­posed on the switch node voltage SW.

BOOST1 to BOOST3: Positive Supply Pins to the Topside
Floating Drivers. Bootstrapped capacitors, charged with
external Schottky diodes and a boost voltage source, are
connected between the BOOST and SW pins. Voltage
swing at the BOOST pins is from boost source voltage
(typically VCC) to this boost source voltage + VIN (where
V

is the external MOSFET supply rail).

IN

PGOOD: This open-drain output is pulled low when the
output voltage has been outside the PGOOD tolerance
window for the V

delay of approximately 100µs.

PGDLY

IN

CC

is

8

3732f

LTC3732

U

U

W

FU CTIO AL DIAGRA

F

IN

R

C

PGOOD

PLLIN

PLLFLTR

LP

LP

FCB

0.6V

100µs

DELAY

–

IN

+

IN

DIFFOUT

EAIN

0.600V

0.660V

I

TH

C

C

R

C

VID0 VID1 VID2 VID3 VID4

PHASE DET

50k

OSCILLATOR

+
–

PROTECTION

R1
20k

V

FB

–

EA

+

+

–

5-BIT VID DECODER

FCB

40k40k

–

A1

+

40k40k

OV

R2 VARIABLE

CLK1
CLK2

CLK3

–
+

–
+

0.66V

EAIN

0.54V

LATCH

DUPLICATE FOR SECOND AND THIRD

CONTROLLER CHANNELS

BOOST

DROP

OUT
DET

BOT

+
–

+–

B

+–

3mV

SHED

RUN

SOFT-

START

FORCE BOT

FCB

SHDN

–
+

54k54k

INTERNAL

I

2.4V

SUPPLY

6V

5(VFB)

1.5µA

SLOPE

COMP

CLAMP

SRQ

I

1

SS

5(V

Q

0.55V

–
+

SHDN

RST

FCB

)

FB

RS

V

CC

SWITCH

LOGIC

2

0.600V

UV/ OVERTEMP

TOP

VCC/DRVCC*

BOT

RESET

TG

SW

BG

PGND

V

CC

SENSE

36k

SENSE

36k

V

REF

V

SGND

RUN/SS

V

CC

+

R

SENSE

–

V

CC

CC

+

V

IN

D

B

C

B

L

+

C

IN

C

OUT

+

V

OUT

C

CC

C

SS

Figure 2

U

OPERATIO

Main Control Loop

The IC uses a constant frequency, current mode step­down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets each RS latch. The peak inductor

(Refer to Functional Diagram)

3732 F02

* UHF PACKAGE CONNECTION

current at which I1 resets the RS latch is controlled by the
voltage on the I

pin, which is the output of the error

TH

amplifier EA. The EAIN pin receives a portion of this
voltage feedback signal via the DIFFOUT pin through the
internal VID DAC and is compared to the internal reference

3732f

9

LTC3732

OPERATIO

U

(Refer to Functional Diagram)

voltage. When the load current increases, it causes a slight
decrease in the EAIN pin voltage relative to the 0.6V
reference, which in turn causes the ITH voltage to increase
until each inductor’s average current matches one third of
the new load current (assuming all three current sensing
resistors are equal). In Burst Mode operation and stage
shedding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara­tor I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which is normally recharged during
each off cycle, through an external Schottky diode. When
VIN decreases to a voltage close to V
may enter dropout and attempt to turn on the top MOSFET
continuously. The dropout detector counts the number of
oscillator cycles that the bottom MOSFET remains off and
periodically forces a brief on period to allow CB to re­charge.

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.5µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled and the
internally buffered ITH voltage is clamped but allowed to
ramp as the voltage on CSS continues to ramp. This “soft­start” clamping prevents abrupt current from being drawn
from the input power source. When the RUN/SS pin is low,
all functions are kept in a controlled state. The RUN/SS pin
is pulled low when the VCC input voltage is below 4V or
when the IC die temperature rises above 150°C.

Low Current Operation

The FCB pin is a multifunction pin: 1) an analog compara­tor input to provide regulation for a secondary winding by
forcing temporary forced PWM operation and 2) a logic
input to select between three modes of operation.

A) Burst Mode Operation

When the FCB pin voltage is below 0.6V, the controller
performs as a continuous, PWM current mode synchro­nous switching regulator. The top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the

, however, the loop

OUT

FCB pin is below VCC –␣ 1.5V but greater than 0.6V, the
controller performs as a Burst Mode switching regulator.
Burst Mode operation sets a minimum output current level
before turning off the top switch and turns off the synchro­nous MOSFET(s) when the inductor current goes nega­tive. This combination of requirements will, at low current,
force the ITH pin below a voltage threshold that will
temporarily shut off both output MOSFETs until the output
voltage drops slightly. There is a burst comparator having
60mV of hysteresis tied to the ITH pin. This hysteresis
results in output signals to the MOSFETs that turn them on
for several cycles, followed by a variable “sleep” interval
depending upon the load current. The resultant output
voltage ripple is held to a very small value by having the
hysteretic comparator after the error amplifier gain block.

B) Stage Shedding Operation

When the FCB pin is tied to the VCC pin, Burst Mode
operation is disabled and the forced minimum inductor
current requirement is removed. This provides constant
frequency, discontinuous current operation over the wid­est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the phase 1 controller alone
is active in discontinuous current mode. This “stage
shedding” optimizes efficiency by eliminating the gate
charging losses and switching losses of the other two
output stages. Additional cycles will be skipped when the
output load current drops below 1% of maximum de­signed load current in order to maintain the output voltage.
This stage shedding operation is not as efficient as Burst
Mode operation at very light loads, but does provide lower
noise, constant frequency operating mode down to very
light load conditions.

C) Continuous Current Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When forcing con­tinuous operation and sinking current, this current will be
forced back into the main power supply, potentially
boosting the input supply to dangerous voltage levels—
BEWARE!

10

3732f

OPERATIO

LTC3732

U

(Refer to Functional Diagram)

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator which
operates over a 250kHz to 600kHz range corresponding to
a voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing
the oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. An approximate 20µA discharge
current will be present at the pin with no PLLIN signal.

Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.

Differential Amplifier

This amplifier provides true differential output voltage
sensing. Sensing both V
tion in high current applications and/or applications hav­ing electrical interconnection losses. This sensing also
isolates the physical power ground from the physical
signal ground preventing the possibility of troublesome
“ground loops” on the PC layout and prevents voltage
errors caused by board-to-board interconnects, particu­larly helpful in VRM designs.

Power Good

The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on once an
internal delay has elapsed and the output voltage has been
away from its nominal value by greater than 10%. If the
output returns to normal prior to the delay timeout, the
timer is reset. There is no delay time for the rising of the
PGOOD output once the output voltage is within the ±10%
“window.”

OUT

+

and V

–

benefits regula-

OUT

Short-Circuit Detection

The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging,
assuming that the output is in a severe overcurrent and/or
short-circuit condition. If the condition lasts for a long
enough period, as determined by the size of the RUN/SS
capacitor, the controller will be shut down until the RUN/SS
pin voltage is recycled. This built-in latchoff can be over­ridden by providing >5µA at a compliance of 4V to the
RUN/SS pin. This additional current shortens the soft­start period but prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled. Foldback
current limit can be overridden by clamping the EAIN pin
such that the voltage is held above the (70%)(0.6V) or

0.42V level even when the actual output voltage is low.

Input Undervoltage Reset

The RUN/SS capacitor will be reset if the input voltage,
(VCC) is allowed to fall below approximately 3.8V. The
capacitor on the RUN/SS pin will be discharged until the
short-circuit arming latch is disarmed. The RUN/SS ca­pacitor will attempt to cycle through a normal soft-start
ramp up after the VCC supply rises above 3.8V. This circuit
prevents power supply latchoff in the event of input power
switching break-before-make situations. The PGOOD pin
is held low during startup until the RUN/SS capacitor rises
above the short-circuit latch-off arming threshold of ap­proximately 3.8V.

The basic application circuit is shown in Figure 1 on the
first page of this data sheet. External component selection
is driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output

3732f

11

LTC3732

OPERATIO

U

(Refer to Functional Diagram)

voltage ripple requirements. Once the inductors and
operating frequency have been chosen, the current sens­ing resistors can be calculated. Next, the power MOSFETs
and Schottky diodes are selected. Finally, CIN and C

OUT

WUUU

APPLICATIO S I FOR ATIO

Operating Frequency

The IC uses a constant frequency, phase-lockable archi­tecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to the Phase-Locked
Loop and Frequency Synchronization section for addi­tional information.

A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 3. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 680kHz.

700

600

500

400

300

OPERATING FREQUENCY (kHz)

200

0

0.5 1 1.5 2 2.5
PLLFLTR PIN VOLTAGE (V)

3731 F03

Figure 3. Operating Frequency vs V

Inductor Value Calculation and Output Ripple Current

PLLFLTR

are selected according to the required voltage ripple
requirements. The circuit shown in Figure 1 can be
configured for operation up to a MOSFET supply voltage
of 28V (limited by the external MOSFETs and possibly the
minimum on-time).

MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid­ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and in­creases with higher VIN or V



V

∆I

OUT OUT

=−

L

fL

V

1



V



IN

:

OUT






where f is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by the

output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

Figure 4 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure 4, the zero output ripple current is obtained when:

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of

12

V

OUT

V

k

==12 1, ,..., –

where k N

N

IN

So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica-

3732f

WUUU

APPLICATIO S I FOR ATIO

LTC3732

tions having a highly varying input voltage, additional
phases will produce the best results.

Accepting larger values of ∆IL allows the use of low
inductances but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(I
I

is the total load current. Remember, the maximum

OUT

)/N, where N is the number of channels and

OUT

∆IL occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.

1.0

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

I

0.4

0.3

0.2

0.1
0

0.1 0.2 0.3 0.4
DUTY FACTOR (V

Figure 4. Normalized Peak Output Current
vs Duty Factor [I

0.5 0.6 0.7 0.8 0.9

= 0.3(I

RMS

OUT/VIN

O(P-P)

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

)

]

3732 F04

Inductor Core Selection

Once the value for L1 to L3 is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite,
molypermalloy or Kool Mµ® cores. Actual core loss is
independent of core size for a fixed inductor value, but it
is very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.

Power MOSFET and D1, D2, D3 Selection

At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and “on” resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as the
actual position (main or synchronous) in which the MOSFET
will be used. A much smaller and much lower input
capacitance MOSFET should be used for the top MOSFET
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where VIN >> V

OUT

,
the top MOSFETs’ “on” resistance is normally less impor­tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac­turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch­ing regulators.

The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV

specification for the MOSFETs as well; many of the

DSS

logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”

resistance R

, input capacitance, input voltage and

DS(ON)

maximum output current.
MOSFET input capacitance is a combination of several

components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).

Kool Mµ is a registered trademark of Magnetics, Inc.

3732f

13

LTC3732

WUUU

APPLICATIO S I FOR ATIO

The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate­to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to­source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given VDS drain voltage, but can be
adjusted for different VDS voltages by multiplying by the
ratio of the application VDS to the curve specified V
values. A way to estimate the C

term is to take the

MILLER

change in gate charge from points a and b on a manufac­turers data sheet and divide by the stated VDS voltage
specified. C

is the most important selection criteria

MILLER

for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
and COS are specified sometimes but definitions of these
parameters are not included.

DS

RSS

2



I



N



RC

DR MILLER

()( )

N

11

() ()




N



R

+

1

()

DS ON

()

+

•



+

2






f



()





R

1δδ

+

()

DS ON

()

P

MAIN

P

SYNC

=



V



2

I

MAX

V

IN

2



V

OUTINMAX




VV V

–



CC TH IL TH IL



VVVI

–

IN OUTINMAX

=

where N is the number of output stages, δ is the tempera­ture dependency of R
resistance (approximately 2Ω at VGS = V
drain potential

and

the change in drain potential in the

particular application. V

, RDR is the effective top driver

DS(ON)

MILLER

is the data sheet specified

TH(IL)

), VIN is the

typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C

MILLER

is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.

V

IN

V

GS

MILLER EFFECT

ab

Q

C

MILLER

IN

= (QB – QA)/V

Figure 5. Gate Charge Characteristic

DS

V

+

V

+

V

GS

–

DS

–

3732 F05

When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:

V

Main Switch Duty Cycle

Synchronous Switch Duty Cycle

OUT

=

V

IN



VV

IN OUT

=





–
V

IN






The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:

Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for V

> 12V, the transition losses

IN

rapidly increase to the point that the use of a higher
R

device with lower C

DS(ON)

actually provides higher

MILLER

efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.

The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R

vs temperature curve, but

DS(ON)

δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.

The Schottky diodes, D1 to D3 shown in Figure 1 conduct
during the dead time between the conduction of the two
large power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.

14

3732f

WUUU

APPLICATIO S I FOR ATIO

LTC3732

A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi­tion loss due to their larger junction capacitance.

CIN and C

Selection

OUT

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V

OUT/VIN

.
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu­rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V

), is approximately equal to the

OUT

input voltage VIN or:

V

OUT

V

k

where k N

==12 1, , ..., –

N

IN

So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.

In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:

V

OUT

V

21

k

==

IN

where k N

N

12–, ,...,

These worst-case conditions are commonly used for de­sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re­quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.

The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and

therefore a 3-stage implementation results in 90% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci­tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages

DUTY FACTOR (V

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

OUT/VIN

0.9

)

3732 F06

Ceramic capacitors are becoming very popular for small
designs but several cautions should be observed. “X7R”,
“X5R” and “Y5V” are examples of a few of the ceramic
materials used as the dielectric layer, and these different
dielectrics have very different effect on the capacitance
value due to the voltage and temperature conditions
applied. Physically, if the capacitance value changes due
to applied voltage change, there is a concommitant piezo
effect which results in radiating sound! A load that draws
varying current at an audible rate may cause an attendant
varying input voltage on a ceramic capacitor, resulting in
an audible signal. A secondary issue relates to the energy
flowing back into a ceramic capacitor whose capacitance
value is being reduced by the increasing charge. The
voltage can increase at a considerably higher rate than the
constant current being supplied because the capacitance
value is decreasing as the voltage is increasing! Ceramic
capacitors, when properly selected and used however, can
provide the lowest overall loss due to their extremely low
ESR.

3732f

15

LTC3732

WUUU

APPLICATIO S I FOR ATIO

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (∆V

∆∆V I ESR

≈+

OUT RIPPLE






8

NfC

) is determined by:

OUT



1




OUT

where f = operating frequency of each stage, N is the
number of output stages, C

= output capacitance and

OUT

∆IL = ripple current in each inductor. The output ripple is
highest at maximum input voltage since ∆IL increases
with input voltage. The output ripple will be less than 50mV
at max VIN with ∆IL = 0.4I

C

required ESR < N • R

OUT

OUT(MAX)

SENSE

assuming:

and
C

> 1/(8Nf)(R

OUT

SENSE

)

The emergence of very low ESR capacitors in small,
surface mount packages makes very small physical imple­mentations possible. The ability to externally compensate
the switching regulator loop using the ITH pin allows a
much wider selection of output capacitor types. The
impedance characteristics of each capacitor type is sig­nificantly different than an ideal capacitor and therefore
requires accurate modeling or bench evaluation during
design.

Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have a good (ESR)(size) product.
Once the ESR requirement for C
RMS current rating generally far exceeds the I

has been met, the

OUT

RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden,
Murata and Tokin offer high capacitance value and very
low ESR, especially applicable for low output voltage
applications.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec­trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer

surface mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV, the KEMET T510
series of sur

face-mount tantalums or the Panasonic SP
series of surface mount special polymer capacitors avail­able in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POS-CAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturer for other specific recommendations.

R

Selection for Output Current

SENSE

Once the frequency and inductor have been chosen,
R

SENSE1, RSENSE2, RSENSE3

are determined based on the
required peak inductor current. The current comparator
has a maximum threshold of 75mV/R

SENSE

and an input
common mode range of SGND to (1.1) • VCC. The current
comparator threshold sets the peak inductor current,
yielding a maximum average output current I

MAX

equal to

the peak value less half the peak-to-peak ripple current,
∆IL.

Allowing a margin for variations in the IC and external
component values yields:

mV

RN

SENSE

The IC works well with values of R

50

=

I

MAX

from 0.002Ω to

SENSE

0.02Ω.

VCC Decoupling

The VCC pin supplies power not only to the internal circuits
of the controller but also to the top and bottom gate
drivers on the IC and therefore must be bypassed
very carefully to ground with a ceramic capacitor, type
X7R or X5R (depending upon the operating temperature
environment) of

at least 1µF imme

diately next to the IC

and preferably an additional 10µF placed very close to
the IC due to the extremely high instantaneous currents
involved. The total capacitance, taking into account the
voltage coefficient of ceramic capacitors, should be
100 times as large as the total combined gate charge
capacitance of ALL of the MOSFETs being driven. Good

3732f

16

WUUU

APPLICATIO S I FOR ATIO

LTC3732

bypassing close to the IC is necessary to supply the high
transient currents required by the MOSFET gate drivers
while keeping the 5V supply quiet enough so as not to
disturb the very small-signal high bandwidth of the current
comparators.

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors, CB, connected to the BOOST
pins, supply the gate drive voltages for the topside
MOSFETs. Capacitor CB in the Functional Diagram is
charged though diode DB from VCC when the SW pin is
low. When one of the topside MOSFETs turns on, the
driver places the CB voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply (V

BOOST

=
VCC + VIN). The value of the boost capacitor CB needs to be
30 to 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of DB must be
greater than V

IN(MAX).

Differential Amplifier

The IC has a true remote voltage sense capability. The
sensing connections should be returned from the load,
back to the differential amplifier’s inputs through a com­mon, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier out­put signal is divided down through the VID DAC and is
compared with the internal, precision 0.6V voltage refer­ence by the error amplifier.

The differential amplifier has a 0 to VCC common mode
input range and an output swing range of 0 to V

– 1.2V.

CC

The output uses an NPN emitter follower without any
internal pull-down current. A DC resistive load to ground
is required in order to sink current.

Output Voltage

The IC includes a digitally controlled 5-bit attenuator
producing output voltages as defined in Table 1. Output
voltages with 25mV increments are produced from 1.075V
to 1.850V.

Each VID digital input is pulled up to a logical high with an
internal 3µA. The input logic threshold is approximately

1.2V but the input circuit can withstand an input voltage of
up to 7V.

Table 1. VID Output Voltage Programming

CODE V

B4 B3 B2 B1 B0 B4 B3 B2 B1 B0

100001.450V 0 00001.850V

100011.425V 0 00011.825V

100101.400V 0 00101.800V

100111.375V 0 00111.775V

101001.350V 0 01001.750V

101011.325V 0 01011.725V

101101.300V 0 01101.700V

101111.275V 0 01111.675V

110001.250V 0 10001.650V

110011.225V 0 10011.625V

110101.200V 0 10101.600V

110111.175V 0 10111.575V

111001.150V 0 11001.550V

111011.125V 0 11011.525V

111101.100V 0 11101.500V

111111.075V 0 11111.475V

OUT

CODE V

OUT

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) ON/OFF, 2)
soft-start and 3) a defeatable short-circuit latch off timer.
Soft-start reduces the input power sources’ surge cur­rents by gradually increasing the controller’s current limit
(proportional to an internal buffered and clamped V

ITH

).
The latchoff timer prevents very short, extreme load
transients from tripping the overcurrent latch. A small
pull-up current (>5µA) supplied to the RUN/SS pin will
prevent the overcurrent latch from operating. A maximum
pullup current of 200µA is allowed into the RUN/SS pin
even though the voltage at the pin may exceed the absolute
maximum rating for the pin. This is because the current is
limited and an internal protection circuit is provided. The
following explanation describes how this function oper­ates.

An internal 1.5µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS reaches 1.5V, the

3732f

17

LTC3732

WUUU

APPLICATIO S I FOR ATIO

controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.5V, the internal current
limit is increased from 20mV/R

SENSE

to 75mV/R

SENSE

.

The output current limit ramps up slowly, taking an
additional 1s/µF to reach full current. The output current
thus ramps up slowly, eliminating the starting surge
current required from the input power supply. If RUN/SS
has been pulled all the way to ground, there is a delay
before starting of approximately:

15

.

t

DELAY SS SS

t

IRAMP SS SS

V

=

15

.

A

µ

315

VV

−

=

15

.

µ

CsFC

.
A

1

/

=µ

()

1

CsFC

/

=µ

()

By pulling the RUN/SS pin below 0.4V the IC is put into low
current shutdown (IQ < 100 µA). The RUN/SS pin can be
driven directly from logic as shown in Figure7. Diode, D1,
in Figure 7 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. The RUN/SS
pin has an internal 6V zener clamp (see the Functional
Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor is used initially to turn on and limit the
inrush current of all three output stages. After the control­lers have been started and been given adequate time to
charge up the output capacitor and provide full load
current, the RUN/SS capacitor is used for a short-circuit
timer. If the output voltage falls to less than 70% of its
nominal value, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
condition. If the condition lasts for a long enough period,
as determined by the size of the RUN/SS capacitor, the
discharge current, and the circuit trip point, the controller
will be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:

t

>> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS)

LO1

If the overload occurs after start-up, the voltage on the
RUN/SS capacitor will continue charging and will provide

additional time before latching off:

t

>> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin from V

CC

as shown in Figure 7. When VCC is 5V, a 200k resistance
will prevent the discharge of the RUN/SS capacitor
during an overcurrent condition but also shortens the
soft-start period, so a larger RUN/SS capacitor value may
be required.

RUN/SS

V

PIN

CC

R

SS

D1

C

SS

3732 F07

SHDN

3.3V OR 5V

RUN/SS

PIN

SHDN

C

SS

Figure 7. RUN/SS Pin Interfacing

5V

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem with
noise pick-up or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
foldback current limiting still remains active, thereby
protecting the power supply system from failure. A deci­sion can be made after the design is complete whether to
rely solely on foldback current limiting or to enable the
latchoff feature by removing the pull-up resistor.

The value of the soft-start capacitor CSS may need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

) (10–4) (R

OUT

SENSE

)

The minimum recommended soft-start capacitor of
CSS = 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the
internal current foldback function. A negative impedance
is experienced when powering a switching regulator.
That

is, the input current is higher at a lower VIN and
decreases as VIN is increased. Current foldback is de­signed to accommodate a normal, resistive load having

3732f

18

WUUU

APPLICATIO S I FOR ATIO

LTC3732

increasing current draw with increasing voltage. The EAIN
pin should be artificially held 70% above its nominal
operating level of 0.6V, or 0.42V in order to prevent the IC
from “folding back” the peak current level. A suggested
circuit is shown in Figure 8.

V

CC

CALCULATE FOR

0.42V TO 0.55V

Figure 8. Foldback Current Elimination

V

CC

Q1

LTC3732

EAIN

3732 F08

The emitter of Q1 will hold up the EAIN pin to a voltage in
the absence of V

that will prevent the internal sensing

OUT

circuitry from reducing the peak output current. Remov­ing the function in this manner eliminates the external
MOSFET’s protective feature under short-circuit condi­tions. This technique will also prevent the short-circuit
latchoff function from turning off the part during a short­circuit event and the output current will only be limited to
N • 75mV/R

SENSE

.

approximately 400kHz. The nominal operating frequency
range of the IC is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the exter­nal and internal oscillators. This type of phase detector will
not lock the internal oscillator to harmonics of the input
frequency. The PLL hold-in range, ∆fH, is equal to the
capture range, ∆fC:

∆fH = ∆fC = ±0.5 f

O

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 9.

R

3732 F09

LP

10k

PLLFLTR

C

LP

EXTERNAL

PLLIN

OSC

PHASE
DETECTOR/
OSCILLATOR

50k

2.4V

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

Undervoltage Reset

In the event that the input power source to the IC (VCC)
drops below 4V, the RUN/SS capacitor will be discharged
to ground. When VCC rises above 4V, the RUN/SS capaci­tor will be allowed to recharge and initiate another soft­start turn-on attempt. This may be useful in applications
that switch between two supplies that are not diode
connected, but note that this cannot make up for the
resultant interruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency fO. A voltage applied to
the PLLFLTR pin of 1.2V corresponds to a frequency of

Figure 9. Phase-Locked Loop Block Diagram

If the external frequency (f
lator frequency, f

, current is sourced continuously,

OSC

) is greater than the oscil-

PLLIN

pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

OSC

down the PLLFLTR pin. If the external and internal fre­quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond­ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point, the phase comparator output is
open and the filter capacitor CLP holds the voltage. The IC
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the

3732f

19

LTC3732

WUUU

APPLICATIO S I FOR ATIO

master’s frequency. A voltage of 1.7V or below applied to
the master oscillator’s PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency will be approximately 550kHz for 1.7V.

The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10k and CLP ranges from

LP

0.01µF to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t

ON(MIN)

, is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:

V

t

ON MIN

()

<

Vf

OUT

IN

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the IC will begin to skip every other
cycle, resulting in half-frequency operation. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.

The minimum on-time for the IC is generally about 110ns.
However, as the peak sense voltage decreases the mini­mum on-time gradually increases. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage

of input power.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

, generating the feedback error signal that

OUT

• ESR, where ESR is the effective

LOAD

OUT

. ∆I

also begins to charge or

LOAD

shifts by an

OUT

forces the regulator to adapt to the current change and
return V
time, V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

availability of the ITH pin not only allows optimization of
control loop behavior, but also provides a DC coupled
and AC filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping
factor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated by
examining the rise time at the pin. The ITH external com­ponents shown in the Figure 1 circuit will provide an
adequate starting point for most applications.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that is low enough
in value to provide sufficient ripple amplitude to meet the
minimum on-time requirement.

As a general rule, keep
the inductor ripple current equal to or greater than 30%
of I

OUT(MAX)

at V

IN(MAX)

.

20

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the

3732f

WUUU

µ

APPLICATIO S I FOR ATIO

LTC3732

loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full load current having a rise time
of <2µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step,
resulting from the step change in output current, may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the ITH pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over­all supply performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C
than 2% of C

, the switch rise time should be controlled

OUT

LOAD

is greater

so that the load rise time is limited to approximately
1000 • R
R

SENSE

SENSE

• C

. Thus a 250µF capacitor and a 2mΩ

LOAD

resistor would require a 500µs rise time, limiting

the charging current to about 1A.

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera­tion. But before you connect, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse battery and
double battery.

Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 10 is the most straightfor­ward approach to protect a DC/DC converter from the
ravages of an automotive battery line. The series diode
prevents current from flowing during reverse battery,
while the transient suppressor clamps the input voltage
during load dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the IC has a maximum input voltage
of 32V on the SW pins, most applications will be limited to
30V by the MOSFET BV

V

CC

5V

LTC3732

Figure 10. Automotive Application Protection

DSS

+

.

V

BAT

12V

3732 F10

Design Example

As a design example, assume V
20V(max), V

OUT

= 1.3V, I

MAX

= 12V(nominal), V

IN

IN

=

= 45A and f = 400kHz. The
inductance value is chosen first based upon a 30% ripple
current assumption. The highest value of ripple current in
each output stage occurs at the maximum input voltage.

=

fI

()

=

400 30 15

()()()

≥

068

.

−

1





∆

13

kHz A

H



V

OUT OUT

L



V



V



IN

V

.

%



1

−





13

.

20



V



V



3732f

21

LTC3732

WUUU

APPLICATIO S I FOR ATIO

Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.

R

SENSE1, RSENSE2

a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:

R

SENSE

Use a commonly available 0.003Ω sense resistor.
Next verify the minimum on-time is not violated. The

minimum on-time occurs at maximum VCC:

t

ON MIN

()

The output voltage will be set by the VID code according
to Table 1.

and R

SENSE3

mV

=

65



34

A

+

15 1





V

OUT

=

VfVV kHz

()

IN MAX

()=()

can be calculated by using

=Ω

0 0037

.



%



2



20 400

.13

=

162

ns

A short circuit to ground will result in a folded back current
of:



ns V

mV

I

SC

with a typical value of R

0.25. The resulting power dissipated in the bottom MOSFET
is:

P

SYNC

which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi­pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the layout
diagram of Figure 11. Check the following in the PC layout:

25

≈

Ω

m

+

23

()

= (7.5A)2(1.25)(0.007Ω) ≈ 0.5W

1

+

2

DS(ON)

150 20




0675.



and d = (0.005/°C)(50°C) =



()




H

µ



A

=

.

The power dissipation on the topside MOSFET can be
estimated. Using a Fairchild FDS6688 for example, R
= 7mΩ, C
voltage with T(estimated) = 50°C:

The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

P

P

MAIN

SYNC

MILLER

=

= 15nC/15V = 1000pF. At maximum input

18

.

≈

20

0 007 20

.




VV V

518118



VV

20 1 3

2

V

15 1 0 005 50 25

()+()

V

Ω

+

()

1

–. .

−

.

V

20

.

[]



2

45




23

()()



+

()()



()





2

AW

15 1 25 0 007 1 84

CC

°− °

()



A

2 1000

Ω



()( )





kHz W

400 2 2

.. .

=

()

Ω

DS(ON)

pF

.

=

1) Are the signal and power ground paths isolated? Keep the
SGND at one end of a printed circuit path thus preventing
MOSFET currents from traveling under the IC. The IC signal
ground pin should be used to hook up all control circuitry
on one side of the IC, routing the copper through SGND,
under the IC covering the “shadow” of the package, connect­ing to the PGND pin and then continuing on to the (–) plates
of C

and C

IN

placed immediately adjacent to the IC between the VCC pin
and PGND. A 1µF ceramic capacitor of the X7R or X5R type
is small enough to fit very close to the IC to minimize the ill
effects of the large current pulses drawn to drive the bottom
MOSFETs. An additional 5µF to 10uF of ceramic, tantalum
or other very low ESR capacitance is recommended in or­der to keep the internal IC supply quiet. The power ground
returns to the sources of the bottom N-channel MOSFETs,
anodes of the Schottky diodes and (–) plates of CIN, which
should have as short lead lengths as possible.

2) Does the IC IN+ pin connect to the (+) plates of C
A 30pF to 300pF feedforward capacitor between the
DIFFOUT and EAIN pins should be placed as close as
possible to the IC.

. The VCC decoupling capacitor should be

OUT

OUT

3732f

?

22

WUUU

APPLICATIO S I FOR ATIO

LTC3732

3) Are the SENSE– and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE+ and SENSE

–

for each channel should be as close as possible to the pins
of the IC. Connect the SENSE– and SENSE+ pins to the
pads of the sense resistor as illustrated in Figure 12.

4) Do the (+) plates of C

connect to the drains of the

PWR

topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.

SW1

D1

5) Keep the switching nodes, SWITCH, BOOST and TG
away from sensitive small-signal nodes (SENSE+, SENSE
IN+, IN–, EAIN). Ideally the SWITCH, BOOST and TG
printed circuit traces should be routed away and separated
from the IC and the “quiet” side of the IC. Separate the high
dV/dt traces from sensitive small-signal nodes with ground
traces or ground planes.

6) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.

L1

R

SENSE1

–

V

IN

R

IN

+

C

IN

BOLD LINES INDICATE HIGH,
SWITCHING CURRENT LINES.
KEEP LINES TO A MININMUM
LENGTH

SW2

SW3

L2

R

SENSE2

D2

L3

R

SENSE3

D3

C

OUT

3732 F11

V

OUT

+

R

L

Figure 11. Branch Current Waveforms

3732f

23

LTC3732

WUUU

APPLICATIO S I FOR ATIO

Figure 11 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after studying
the current waveforms why it is critical to keep the high
switching current paths to a small physical size. High elec­tric and magnetic fields will radiate from these “loops” just
as radio stations transmit signals. The output capacitor
ground should return to the negative terminal of the input
capacitor and not share a common ground path with any
switched current paths. The left half of the circuit gives rise
to the “noise” generated by a switching regulator. The
ground terminations of the synchronous MOSFETs and
Schottky diodes should return to the bottom plate(s) of the
input capacitor(s) with a short isolated PC trace since very
high switched currents are present. A separate isolated path
from the bottom plate(s) of the input and output capacitor(s)
should be used to tie in the IC power ground pin (PGND).
This technique keeps inherent signals generated by high
current pulses taking alternate current paths that have fi­nite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over­compensation for PC layouts which are not optimized but
this is not the recommended design procedure.

INDUCTOR

reduced by, and the effective ripple frequency is increased
by the number of phases used. Figure 13 graphically
illustrates the principle.

SINGLE PHASE

SW V

I

CIN

I

COUT

TRIPLE PHASE

SW1 V

SW2 V

SW3 V

I

L1

I

L2

I

L3

I

CIN

I

COUT

3732 F13

LTC3732

+

SENSE

SENSE

Figure 12. Kelvin Sensing R

1000pF

–

OUTPUT CAPACITOR

SENSE
RESISTOR

3732 F12b

SENSE

Simplified Visual Explanation of How a 3-Phase
Controller Reduces Both Input and Output RMS
Ripple Current

The effect of multiphase power supply design significantly
reduces the amount of ripple current in both the input and
output capacitors. The RMS input ripple current is divided
by, and the effective ripple frequency is multiplied up by
the number of phases used (assuming that the input
voltage is greater than the number of phases used times
the output voltage). The output ripple amplitude is also

Figure 13. Single and Polyphase Current Waveforms

The worst-case input RMS ripple current for a single stage
design peaks at twice the value of the output voltage. The
worst-case input RMS ripple current for a two stage
design results in peaks at 1/4 and 3/4 of the input voltage,
and the worst-case input RMS ripple current for a three
stage design results in peaks at 1/6, 1/2, and 5/6 of the
input voltage. The peaks, however, are at ever decreasing
levels with the addition of more phases. A higher effective
duty factor results because the duty factors “add” as long
as the currents in each stage are balanced. Refer to AN19
for a detailed description of how to calculate RMS current
for the single stage switching regulator.

Figure 6 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ration of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 2/3
in a 3-phase solution due to the current splitting between
the three stages.

3732f

24

WUUU

APPLICATIO S I FOR ATIO

LTC3732

The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the V

/L discharge currents

OUT

term from the stages that has their bottom MOSFETs on
subtract current from the (VCC – V

)/L charging current

OUT

resulting from the stage which has its top MOSFET on. The
output ripple current for a 3-phase design is:

V

I

P-P

OUT

=

fL

()()

DC V V

13 3–

()

>

IN OUT

The ripple frequency is also increased by three, further
reducing the required output capacitance when VCC < 3V

OUT

as illustrated in Figure 6.
The addition of more phases by phase locking additional

controllers, always results in no net input or output ripple
at V

OUT/VIN

ratios equal to the number of stages
implemented. Designing a system with multiple stages
close to the V

OUT/VIN

ratio will significantly reduce the
ripple voltage at the input and outputs and thereby
improve efficiency, physical size and heat generation of
the overall switching power supply. Refer to Application
Note 77 for more information on Polyphase circuits.

δ = 0.01%°C (MOSFET temperature coefficient)
N = 3
f = 400kHz

The main MOSFET is on for the duty factor V

OUT/VIN

and
the synchronous MOSFET is on for the rest of the period
or simply (1 – V

OUT/VIN

). Assuming the ripple current is
small, the AC loss in the inductor can be made small if a
good quality inductor is chosen. The average current,
I

is used to simplify the calaculations. The equation

OUT

below is not exact but should provide a good technique
for the comparison of selected components and give a
result that is within 10% to 20% of the final application.
The temperature of the MOSFET’s die temperature may
require interative calculations if one is not familiar typical
performance. A maximum operating junction tempera­ture of 90° to 100°C for the MOSFETs is recommended
for high reliability applications.

Common output path DC loss:

I

MAX

N

2



RR

+

L SENSE

()





PN

COMPATH

≈







Efficiency Calculation

To estimate efficiency, the DC loss terms include the input
and output capacitor ESR, each MOSFET R
tor resistance RL, the sense resistance R

SENSE

DS(ON)

, induc-

and the
forward drop of the Schottky rectifier at the operating
output current and temperature. Typical values for the
design example given previously in this data sheet are:

Main MOSFET R
Sync MOSFET R
C
C

= 20mΩ

INESR
OUTESR

= 3mΩ

= 7mΩ (9mΩ at 90°C)

DS(ON)

= 7mΩ (9mΩ at 90°C)

DS(ON)

RL = 2.5mΩ
R
V
V

= 3mΩ

SENSE

SCHOTTKY

= 1.3V

OUT

= 0.8V at 15A (0.7V at 90°C)

VIN = 12V
I

= 45A

MAX

+

C Loss

OUTESR

This totals 3.7W + C

OUTESR

loss.

Total of all three main MOSFET’s DC loss:

PN



=

MAIN





+

C Loss



V

OUTINMAX



V



INESR

This totals 0.66W + C






INESR

2



I



N



R

+

1 δ

()

DS ON

()

loss.

Total of all three synchronous MOSFET’s DC loss:



PN

SYNC

=

V

11

–









OUTINMAX





V





2



I



N



R

+

δ

DS ON

()

()

This totals 5.4W.

3732f

25

LTC3732

WUUU

APPLICATIO S I FOR ATIO

Total of all three main MOSFET’s AC loss:

A

45

PV

≈Ω

MAIN IN

2

3

()



1



VV V

–. .

518118



2 1000

()( )

23

()()

+

pF



kHz W

().

400 6 3





=

This totals 1W at VIN = 8V, 2.25W at VIN = 12V and 6.25W
at VIN = 20V.

Total of all three synchronous MOSFET’s AC loss:

V

G

V

IN

DSSPEC

fnC

=

() () ()( ) ( )361545Q

This totals 0.08W at V

= 8V, 0.12W at VIN = 12V and

IN

V

IN

V

DSSPEC

E

0.19W at VIN = 20V. The bottom MOSFET does not
experience the Miller capacitance dissipation issue that
the main switch does because the bottom switch turns on
when its drain is close to ground.

The Schottky rectifier loss assuming 50ns nonoverlap
time:

2 • 3(0.7V)(15A)(50ns)(4E5)
This totals 1.26W.
The total output power is (1.3V)(45A) = 58.5W and the

total input power is approximately 70W so the % loss of
each component is as follows:

Main switch AC loss (VIN = 12V) 2.25W 3.75%

Main switch DC loss 0.66W 1.1%

Synchronous switch AC loss 0.19W 0.3%

Synchronous switch DC loss 5.4W 9%

Power path loss 3.7W 6.1%
The numbers above represent the values at VIN = 12V. It

can be seen from this simple example that two things can
be done to improve efficiency: 1) Use two MOSFETs on the
synchronous side and 2) use a smaller MOSFET for the
main switch with smaller C

to better balance the AC

MILLER

loss with the DC loss. A smaller, less expensive MOSFET
can actually perform better in the task of the main switch.

PACKAGE DESCRIPTIO

7.8 – 8.2

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

MILLIMETERS

(INCHES)

0.42 ±0.03 0.65 BSC

0.09 – 0.25

(.0035 – .010)

U

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**
(.197 – .221)

0.55 – 0.95

(.022 – .037)

° – 8°

0

1.25 ±0.12

5.3 – 5.7

12.50 – 13.10*
(.492 – .516)

12345678 9 10 11 12 14 15 16 17 1813

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

2526 22 21 20 19232427282930313233343536

7.40 – 8.20

(.291 – .323)

2.0

(.079)

0.05

(.002)

G36 SSOP 0802

3732f

26

PACKAGE DESCRIPTIO

5.50 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

3.20 ± 0.05

(2 SIDES)

U

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701)

0.25 ± 0.05

0.50 BSC

5.20 ± 0.05 (2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

LTC3732

0.70 ± 0.05

PACKAGE
OUTLINE

7.00 ± 0.10

(2 SIDES)

0.75 ± 0.05

5.00 ± 0.10

(2 SIDES)

PIN 1
TOP MARK
(SEE NOTE 6)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

0.75 ± 0.05

0.00 – 0.05

5.15 ± 0.10

(2 SIDES)

0.200 REF

0.200 REF

0.00 – 0.05

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

0.25 ± 0.05

0.50 BSC

3.15 ± 0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

37

38

R = 0.115
TYP

0.435

0.18

1

0.23

2

0.40 ± 0.10

(UH) QFN 0303

0.18

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3732f

27

LTC3732

WUUU

APPLICATIO S I FOR ATIO

OPTIONAL FOR

SYNCHRONIZATION

1000pF

0.01µF

10k

14.7k

5V

2N3904

V

RON

0.01µF

60.4k

5V

11.8k

330pF

3.3nF

2.2k

PIN #s SHOWN ARE FOR THE 36 PIN SSOP PACKAGE

BAT54

100Ω, 1%

S1
S1
S2
S2
S3
S3

1

27pF

VID1

2
3
4
5

6
7
8

9
10
11
12
13
14
15
16
17
18

PLLIN
PLLFLTR
FCB

+

IN

–

IN
DIFFOUT
EAIN
SGND
SENSE1
SENSE1
SENSE2
SENSE2
SENSE3
SENSE3
RUN/SS
I

TH

VID2

LTC3732

+

–

+

–

–

+

PGOOD

BOOST1

BOOST2

BOOST3

+

–
+

–

–

+

1000pF

1000pF

1000pF

VID1 IN

SYNC IN

300kHz

VID2 IN

Figure 14. VRM9.0/9.1 65A Power Supply for Pentium® 4 Processors

VID0

TG1

SW1

TG2

SW2

V
BG1

PGND

BG2
BG3

SW3

TG3

VID4
VID3

V

CC

0.1µF

0.1µF

V

PGOOD

47k

1Ω

M1

V

CC

M2 D1

M3

10µF

CC

M4 D2

M5

M6 D3

V

CC

5V TO 7V

V

IN

L1

0.002Ω

–

+

S1

S1

V

IN

L2

0.002Ω

+

–

S2

S2

V

IN

L3

0.002Ω

+

–

S3

S3

V

OUT

+

10µF

C

6.3V
×3

10µF
25V
×5

VIN: 5V TO 20V

: 1.1V TO 1.85V, 65A

V

OUT

SWITCHING FREQUENCY: 300kHz

: SANYO OS-CON 25SP68M

C

IN

: 270µF/2V ×6 PANASONIC SP EEFSDOD271R

C

OUT

L1 TO L3: 0.8µH SUMIDA CEP125-0R8
M1, M3, M5: IRF7811W ×2 OR FDS6688 ×2
M2, M4, M6: IRF7822 ×2 OR Si7892DP ×2

OUT

V

IN

3.3V TO 20V

+

C

IN

68µF
25V

36

VID0 IN

35
34
33
32

31
30
29
28

CC

27

1µF

26
25
24
23
22

0.1µF

21
20

VID4 IN

19

VID3 IN

3732 TA01

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC1530 High Power Step-Down Synchronous DC/DC Controller High Efficiency 5V to 3.3V Conversion at Up to 15A, SO-8 Package
LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down Reduces CIN and C

LTC1628-SYNC DC/DC Controllers 3.5V ≤ VIN ≤ 36V, I
LTC1629/LTC1629-PG 20A to 200A PolyPhase Synchronous Controllers Expandable from 2-Phase to 12-Phase, No Heat Sink, VIN up to 36V
LTC1702A No R
LTC1703 No R

TM

2-Phase Dual Sync Step-Down Controller 550kHz, No Sense Resistor

SENSE

2-Phase Dual Synchronous Step-Down Mobile Pentium® III Processors, 550kHz,

SENSE

Controller with 5-Bit Mobile VID Control VIN ≤ 7V

LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ VIN ≤ 36V, VID Sets V
LT®1709/ High Efficiency, 2-Phase Synchronous Step-Down 1.3V ≤ V

≤ 3.5V, Current Mode Ensures

OUT

LT1709-8 Switching Regulators with 5-Bit VID Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V
LTC1735 High Efficiency Synchronous Step-Down Regulator Output Fault Protection, 16-Pin SSOP
LTC1736 High Efficiency Synchronous Controller with VID Control Output Fault Protection, 24-Pin SSOP, 3.5V ≤ VIN ≤ 36V
LTC1778 No R

Current Mode Sync Step-Down Controller ≤97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ V

SENSE

I

OUT

≤ 20A

LTC1929 2-Phase Synchronous Controllers Up to 42A, No Heat Sinks, 3.5V ≤ VIN ≤ 36V
LTC3711 No R

Controller with Digital 5-Bit Interface 0.925V ≤ V

Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium III Processors,

SENSE

OUT

LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, V
LTC3730 3-Phase, 5-Bit Intel Mobile VID 0.6V ≤ V

≤ 1.75V, IMVP3 Compatible

OUT

600kHz Synchronous Step-Down Controller Up to 60A Output Current, Integrated MOSFET Drivers

LTC3731 3-Phase 600kHz Synchronous Step-Down Controller 0.6V ≤ V

I

OUT

LTC3778 Optional R

Current Mode Synchronous 4V ≤ VIN ≤ 36V, Adjustable Frequency up to 1.2MHz,

SENSE

≤ 6V, 4.5V ≤ VIN ≤ 32V

OUT

up to 60A, Integrated MOSFET Drivers

Step-Down Controller TSSOP-20 Package

No R

is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

Linear Technology Corporation

28

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

, Power Good Output Signal, Synchronizable,

OUT

up to 20A, 0.8V ≤ V

OUT

, PGOOD

OUT1

≤ 2V, 4V ≤ VIN ≤ 36V, I

 LINEAR TECHNOLOGY CORPORATION 2002

≤ 5V

OUT

≤ (0.9) (VIN),

OUT

up to 20A

OUT

up to 36V

IN

LT/TP 0503 1K • PRINTED IN USA

3732f