Linear Technology LTC3729 User Manual

LTC3729

550kHz, PolyPhase,

High Efficiency, Synchronous

Step-Down Switching Regulator

FEATURES

■

Wide VIN Range: 4V to 36V Operation

■

Reduces Required Input Capacitance and Power
Supply Induced Noise

■

±

1% Output Voltage Accuracy

■

Phase-Lockable Fixed Frequency: 250kHz to 550kHz

■

True Remote Sensing Differential Amplifier

■

PolyPhaseTM Extends from Two to Twelve Phases

■

Reduces the Size and Value of Inductors

■

Current Mode Control Ensures Current Sharing

■

1.1MHz Effective Switching Frequency (2-Phase)

■

OPTI-LOOP® Compensation Reduces C

■

Power Good Output Voltage Indicator

■

Very Low Dropout Operation: 99% Duty Cycle

■

Adjustable Soft-Start Current Ramping

■

Internal Current Foldback Plus Shutdown Timer

■

Overvoltage Soft-Latch Eliminates Nuisance Trips

■

Available in 5mm × 5mm QFN

OUT

and 28-Lead SSOP Packages

U

APPLICATIO S

■

Desktop Computers/Servers

■

Large Memory Arrays

■

DC Power Distribution Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation.
PolyPhase is a trademark of Linear Technology Corporation.

U

DESCRIPTIO

The LTC®3729 is a multiple phase, synchronous step­down current mode switching regulator controller that
drives N-channel external power MOSFET stages in a
phase-lockable fixed frequency architecture. The PolyPhase
controller drives its two output stages out of phase at
frequencies up to 550kHz to minimize the RMS ripple
currents in both input and output capacitors. The output
clock signal allows expansion for up to 12 evenly phased
controllers for systems requiring 15A to 200A of output
current. The multiple phase technique effectively multi­plies the fundamental frequency by the number of chan­nels used, improving transient response while operating
each channel at an optimum frequency for efficiency.
Thermal design is also simplified.

An internal differential amplifier provides true remote
sensing of the regulated supply’s positive and negative
output terminals as required for high current applications.

A RUN/SS pin provides both soft-start and optional timed,
short-circuit shutdown. Current foldback limits MOSFET
dissipation during short-circuit conditions when the
overcurrent latchoff is disabled. OPTI-LOOP compensa­tion allows the transient response to be optimized over a
wide range of output capacitance and ESR values. The
LTC3729 includes a power good output pin that indicates
when the output is within ±7.5% of the designed set point.

TYPICAL APPLICATIO

0.1µF

S

LTC3729

V

IN

0.1µF

RUN/SS

PGOOD

I

1000pF

16k

OUT

D1, D2: UP5840

TH

SGND

V

DIFFOUT

EAIN
V

OS

V

OS

: T510E108K004AS

3.3k

S

S

16k

BOOST1

SW1

PGND
SENSE1
SENSE1

BOOST2

SW2

–
+

INTV
SENSE2
SENSE2

Figure 1. High Current Dual Phase Step-Down Converter

U

TG1

BG1

TG2

BG2

V

IN

10Ω

S

0.47µF

S

+
–

S

S

S

CC

+
–

L1, L2: CEPH149-IROMCC

0.47µF

S

10µF

+

M1, M3: IRF7811W
M2, M4: IRF7822

M1

D1

M2
×2

M3

M4
×2

L2

0.8µH

D2

L1

0.8µH

0.002Ω

0.002Ω

+

C
1000µF ×2
4V

10µF
35V
CERAMIC
×4

OUT

3729 TA01

5V TO 28V

V

OUT

1.6V/40A

sn3729 3729fas

1

LTC3729

WW

W

ABSOLUTE AXI U RATI GS

U

(Note 1)

Input Supply Voltage (VIN).........................36V to –0.3V

Topside Driver Voltages (BOOST1,2).........42V to –0.3V

Switch Voltage (SW1, 2) .............................36V to –5 V

SENSE1+, SENSE2+, SENSE1–,

SENSE2– Voltages........................ (1.1)INTVCC to –0.3V

+

EAIN, V

OS

–

, V

, EXTVCC, INTVCC,

OS

RUN/SS, PGOOD Voltages...........................7V to –0.3V

Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V

PLLFLTR, PLLIN, CLKOUT, PHASMD,
V

DIFFOUT

Voltages ................................ INTVCC to –0.3V

UUW

PACKAGE/ORDER I FOR ATIO

ORDER PART

NUMBER

LTC3729EG

RUN/SS
SENSE1
SENSE1

EAIN

PLLFLTR

PLLIN

PHASMD

I

SGND

V

DIFFOUT

V

OS

V

OS

SENSE2
SENSE2

TOP VIEW

1

+

2

–

3
4
5
6
7
8

TH

9

10

–

11

+

12

–

13

+

14

G PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θJA = 95°C/W

JMAX

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CLKOUT
TG1
SW1
BOOST1
V

IN

BG1
EXTV
INTV

CC

PGND
BG2
BOOST2
SW2
TG2
PGOOD

CC

ITH Voltage................................................2.7V to –0.3V

Peak Output Current <1µs(TGL1,2, BG1,2)................ 5A

INTVCC RMS Output Current................................ 50mA

Operating Ambient Temperature

Range (Note 6) ................................... –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

(G Package Only) ..................................................300°C

TOP VIEW

ORDER PART

NUMBER

NC

PLLFLTR

PLLIN

PHASMD

I

SGND

V

DIFFOUT

V

OS

SENSE1–SENSE1+NC

32 31 30 29 28 27 26 25
1EAIN
2
3
4
5

TH

6
7

–

8

9 10 11 12 13

+

NC

OS

V

32-LEAD 5mm × 5mm PLASTIC QFN

EXPOSED PAD IS SGND

(MUST BE SOLDERED TO PCB)

RUN/SS

–

+

PGOOD

SENSE2

SENSE2

UH PACKAGE

θJA = 34°C/W

CLKOUT

TG1

14 15 16

TG2

SW2

SW1

NC

24
23
22
21
20
19
18
17

BOOST1
V

IN

BG1
EXTV

CC

INTV

CC

PGND
BG2
BOOST2

LTC3729EUH

UH PART

MARKING

3729

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

V

EAIN

V

SENSEMAX

I

INEAIN

V

LOADREG

Regulated Feedback Voltage (Note 3); ITH Voltage = 1.2V ● 0.792 0.800 0.808 V
Maximum Current Sense Threshold V

Feedback Current (Note 3) –5 –50 nA
Output Voltage Load Regulation (Note 3)

2

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

–

= 5V ● 62 75 88 mV

SENSE

V

Measured in Servo Loop; I
Measured in Servo Loop; I

= 5V 65 75 85 mV

SENSE1, 2

Voltage = 0.7V ● 0.1 0.5 %

TH

Voltage = 2V ● –0.1 –0.5 %

TH

sn3729 3729fas

LTC3729

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

REFLNREG

V

OVL

Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.002 0.02 %/V
Output Overvoltage Threshold Measured at V

EAIN

● 0.84 0.86 0.88 V

UVLO Undervoltage Lockout VIN Ramping Down 3 3.5 4 V
g

m

g

mOL

I

Q

I

RUN/SS

V

RUN/SS

V

RUN/SSLO

I

SCL

I

SDLDO

I

SENSE

DF

MAX

Transconductance Amplifier g

m

ITH = 1.2V; Sink/Source 5µA; (Note 3) 3 mmho
Transconductance Amplifier Gain ITH = 1.2V; (gmxZL; No Ext Load); (Note 3) 1.5 V/mV
Input DC Supply Current (Note 4)

Normal Mode EXTV

Shutdown V
Soft-Start Charge Current V
RUN/SS Pin ON Threshold V
RUN/SS Pin Latchoff Arming V
RUN/SS Discharge Current Soft Short Condition V
Shutdown Latch Disable Current V
Total Sense Pins Source Current Each Channel; V

Tied to V

CC

= 0V 20 40 µA

RUN/SS

= 1.9V –0.5 –1.2 µA

RUN/SS

Rising 1.0 1.5 1.9 V

RUN/SS

Rising from 3V 3.8 4.5 V

RUN/SS

= 0.5V 1.6 5 µA

EAIN

; V

OUT

OUT

EAIN

SENSE1–, 2

= 5V 580 µA

= 0.5V; V

– = V

SENSE1+, 2

= 4.5V 0.5 2 4 µA

RUN/SS

+ = 0V –85 – 60 µA

Maximum Duty Factor In Dropout 98 99.5 %
Top Gate Transition Time:

TG1, 2 t
TG1, 2 t

Rise Time C

r

Fall Time C

f

= 3300pF 30 90 ns

LOAD

= 3300pF 40 90 ns

LOAD

Bottom Gate Transition Time:

BG1, 2 t
BG1, 2 t

TG/BG t

BG/TG t

t

ON(MIN)

Rise Time C

r

Fall Time C

f

Top Gate Off to Bottom Gate On Delay

1D

Synchronous Switch-On Delay Time C
Bottom Gate Off to Top Gate On Delay

2D

Top Switch-On Delay Time C
Minimum On-Time Tested with a Square Wave (Note 5) 100 ns

= 3300pF 30 90 ns

LOAD

= 3300pF 20 90 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

= 3300pF Each Driver 90 ns

LOAD

Internal VCC Regulator

V

INTVCC

V

INT INTVCC Load Regulation ICC = 0 to 20mA; V

LDO

V

EXT EXTVCC Voltage Drop ICC = 20mA; V

LDO

V

EXTVCC

V

LDOHYS

Internal VCC Voltage 6V < VIN < 30V; V

EXTVCC

EXTVCC Switchover Voltage ICC = 20mA, EXTV
EXTVCC Switchover Hysteresis ICC = 20mA, EXTV

= 4V 4.8 5.0 5.2 V

EXTVCC

= 4V 0.2 1.0 %

EXTVCC

= 5V 80 160 mV
Ramping Positive ● 4.5 4.7 V

CC

Ramping Negative 0.2 V

CC

Oscillator and Phase-Locked Loop

f

NOM

f

LOW

f

HIGH

R

PLLIN

I

PLLFLTR

R

RELPHS

Nominal Frequency V
Lowest Frequency V
Highest Frequency V

= 1.2V 360 400 440 kHz

PLLFLTR

= 0V 230 260 290 kHz

PLLFLTR

≥ 2.4V 480 550 590 kHz

PLLFLTR

PLLIN Input Resistance 50 kΩ
Phase Detector Output Current

Sinking Capability f

Sourcing Capability f
Controller 2-Controller 1 Phase V

< f

PLLIN

OSC

> f

PLLIN

OSC

= 0V, Open 180 Deg

PHASMD

= 5V 240 Deg

V

PHASMD

–15 µA
15 µA

sn3729 3729fas

3

LTC3729

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, V

The ● denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

RUN/SS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CLKOUT Phase (Relative to Controller 1) V

CLK
CLK

HIGH

LOW

Clock High Output Voltage 4 V
Clock Low Output Voltage 0.2 V

= 0V 60 Deg

PHASMD

V

= Open 90 Deg

PHASMD

= 5V 120 Deg

V

PHASMD

PGOOD Output

V

PGL

I

PGOOD

V

PG

PGOOD Voltage Low I
PGOOD Leakage Current V
PGOOD Trip Level, Either Controller V

= 2mA 0.1 0.3 V

PGOOD

= 5V ±1 µA

PGOOD

with Respect to Set Output Voltage

EAIN

V

Ramping Negative –6 –7.5 –9.5 %

EAIN

Ramping Positive 6 7.5 9.5 %

V

EAIN

Differential Amplifier

A

DA

CMRR
R

IN

Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.

Note 2: T
dissipation P

LTC3729EG: T
LTC3729EUH: T

Note 3: The LTC3729 is tested in a feedback loop that servos V
specified voltage and measures the resultant V

Gain 0.995 1 1.005 V/V
Common Mode Rejection Ratio 0V < VCM < 5V 46 55 dB

DA

Input Resistance Measured at VOS+ Input 80 kΩ

Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

is calculated from the ambient temperature TA and power

J

according to the following formulas:

D

= TA + (PD • 95°C/W)

J

= TA + (PD • 34°C/W)

J

ITH

EAIN

.

to a

Note 5: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).
Note 6: The LTC3729E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current
(Figure 12)

100

80

60

40

EFFICIENCY (%)

20

0

0.1

VIN = 5V
VIN = 8V
VIN = 12V
VIN = 20V

1 10 100

OUTPUT CURRENT (A)

V

= 3.3V

OUT

V

EXTVCC

I

= 20A

OUT

f = 250kHz

= 5V

3729 G01

Efficiency vs Output Current
(Figure 12)

100

V

= 5V

90

80

70

EFFICIENCY (%)

60

50

1

EXTVCC

V

EXTVCC

10 100

OUTPUT CURRENT (A)

= 0V

V

OUT

f = 250kHz

= 3.3V

3729 G02

Efficiency vs Input Voltage
(Figure 12)

100

90

EFFICIENCY (%)

80

70

5

10 15 20

VIN (V)

V

= 3.3V

OUT

= 5V

V

EXTVCC

I

= 20A

OUT

f = 250kHz

3729 G03

sn3729 3729fas

4

UW

TEMPERATURE (°C)

–50

INTV

CC

AND EXTV

CC

SWITCH VOLTAGE (V)

4.95

5.00

5.05

25 75

3729 G06

4.90

4.85

–25 0

50 100 125

4.80

4.70

4.75

INTVCC VOLTAGE

EXTVCC SWITCHOVER THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3729

Supply Current vs Input Voltage
and Mode EXTVCC Voltage Drop

1000

800

600

400

SUPPLY CURRENT (µA)

200

0

05

ON

SHUTDOWN

10

INPUT VOLTAGE (V)

20

15

25

30

35

3729 G04

250

200

150

100

VOLTAGE DROP (mV)

CC

EXTV

50

0

10

0

Maximum Current Sense Threshold

Internal 5V LDO Line Reg

5.1
I

= 1mA

LOAD

5.0

4.9

4.8

VOLTAGE (V)

4.7

CC

INTV

4.6

4.5

4.4

0

510

15 25

INPUT VOLTAGE (V)

20 30 35

3729 G07

vs Duty Factor

75

50

(mV)

SENSE

V

25

0

0

20 40 60 80

30

20

CURRENT (mA)

DUTY FACTOR (%)

INTVCC and EXTVCC Switch
Voltage vs Temperature

40

50

3729 G05

Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)

80

70

60

50

(mV)

40

SENSE

V

30

20

10

100

3729 G08

0

0

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

25

50

75

100

3729 G09

Maximum Current Sense Threshold
vs V

80

V

SENSE(CM)

60

(mV)

40

SENSE

V

20

0

0

(Soft-Start)

RUN/SS

= 1.6V

1234

V

(V)

RUN/SS

56

3729 G10

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

80

76

72

(mV)

SENSE

68

V

64

60

1

0

COMMON MODE VOLTAGE (V)

3

2

Current Sense Threshold
vs ITH Voltage

90
80
70
60
50
40

(mV)

30

20

SENSE

V

10

0
–10
–20

4

3729 G11

–30

5

0.5

0

1.5

2

1

V

(V)

ITH

sn3729 3729fas

2.5

3729 G12

5

LTC3729

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation V

0.0

–0.1

(%)

OUT

–0.2

NORMALIZED V

–0.3

–0.4

0

1

2

LOAD CURRENT (A)

FCB = 0V
V

= 15V

IN

FIGURE 1

3

4

5

3729 G13

Maximum Current Sense
Threshold vs Temperature

80

78

76

(mV)

SENSE

74

V

72

70

–50 –25

0

TEMPERATURE (°C)

50

25

(V)

ITH

V

2.5

2.0

1.5

1.0

0.5

vs V

ITH

RUN/SS

V

= 0.7V

OSENSE

0

0

234

1

V

RUN/SS

(V)

56

3729 G14

SENSE Pins Total Source Current

100

50

(µA)

0

SENSE

I

–50

–100

0

24

V

COMMON MODE VOLTAGE (V)

SENSE

6

3729 G15

RUN/SS Current vs Temperature

1.8

1.6

1.4

1.2

1.0

0.8

0.6

RUN/SS CURRENT (µA)

0.4

0.2

100

125

3729 G17

75

0

–50 –25

0 25 125

TEMPERATURE (°C)

75 10050

3729 G19

Soft-Start Up (Figure 12)

V

ITH

1V/DIV

V

OUT

2V/DIV

V

RUNSS

2V/DIV

100ms/DIV 3729 G20

6

I

OUT

O/30A

V

ITH

1V/DIV

V

OUT

200mV/DIV

Load Step (Figure 12)

10µs/DIV

3729 G21

sn3729 3729fas

UW

TEMPERATURE (°C)

–50

400

500

700

25 75

3729 G25

300

200

–25 0

50 100 125

100

0

600

FREQUENCY (kHz)

V

PLLFLTR

= 2.4V

V

PLLFLTR

= 1.2V

V

PLLFLTR

= 0V

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3729

Current Sense Pin Input Current
vs Temperature

35

V

= 5V

OUT

33

31

29

27

CURRENT SENSE INPUT CURRENT (µA)

25

–50 –25

0

TEMPERATURE (°C)

50

25

Undervoltage Lockout
vs Temperature

3.50

3.45

3.40

3.35

3.30

UNDERVOLTAGE LOCKOUT (V)

3.25

3.20
–50

–25 0

75

TEMPERATURE (°C)

125

100

3729 G23

50 100 125

25 75

EXTVCC Switch Resistance
vs Temperature

10

8

6

4

SWITCH RESISTANCE (Ω)

CC

2

EXTV

0

–50 –25

3729 G26

25

0

TEMPERATURE (°C)

Oscillator Frequency
vs Temperature

50

75

100

125

3729 G24

Shutdown Latch Thresholds
vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

SHUTDOWN LATCH THRESHOLDS (V)

0

–50 –25

LATCH ARMING

LATCHOFF

THRESHOLD

0 25 125

TEMPERATURE (°C)

75 10050

3729 G27

UUU

PI FU CTIO S

RUN/SS (Pin 1/Pin 28): Combination of Soft-Start, Run
Control Input and Short-Circuit Detection Timer. A capaci­tor to ground at this pin sets the ramp time to full current
output. Forcing this pin below 0.8V causes the IC to shut
down all internal circuitry. All functions are disabled in
shutdown.

SENSE1+, SENSE2+ (Pins 2,14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The ITH pin

voltage and built-in offsets between SENSE– and SENSE

G Package/UH Package

pins in conjunction with R

set the current trip thresh-

SENSE

old.
SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–)

Input to the Differential Current Comparators.
EAIN (Pin 4/Pin 1): Input to the Error Amplifier that

compares the feedback voltage to the internal 0.8V refer­ence voltage. This pin is normally connected to a resistive
divider from the output of the differential amplifier

+

(DIFFOUT).

sn3729 3729fas

7

LTC3729

PI FU CTIO S

UUU

G Package/UH Package

PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Low

Pass Filter is tied to this pin. Alternatively, this pin can be
driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.

PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.

PHASMD (Pin 7/Pin 4): Control Input to Phase Selector
which determines the phase relationships between con­troller 1, controller 2 and the CLKOUT signal.

ITH (Pin 8/Pin 5): Error Amplifier Output and Switching
Regulator Compensation Point. Both current comparator’s
thresholds increase with this control voltage. The normal
voltage range of this pin is from 0V to 2.4V.

SGND (Pin 9/Pin 6): Signal Ground, common to both
controllers, must be routed separately from the input
switched current ground path to the common (–)
terminal(s) of the C

V

DIFFOUT

that provides true remote output voltage sensing. This pin
normally drives an external resistive divider that sets the
output voltage.

V

OS

tional Amplifier. Internal precision resistors capable of
being electronically switched in or out can configure it as
a differential amplifier or an uncommitted Op Amp.

PGOOD (Pin 15/Pin 13): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the EAIN pin is not
within ±7.5% of its set point.

TG2, TG1 (Pins 16, 27/Pins 14, 26): High Current Gate
Drives for Top N-Channel MOSFETS. These are the out­puts of floating drivers with a voltage swing equal to
INTVCC superimposed on the switch node voltage SW.

(Pin 10/Pin 7): Output of a Differential Amplifier

–

+

, V

(Pins 11, 12/Pins 8, 9): Inputs to an Opera-

OS

capacitor(s).

OUT

SW2, SW1 (Pins 17, 26/Pins 15, 25): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to VIN.

BOOST2, BOOST1 (Pins 18, 25/Pins 17, 24):
Supplies to the Topside Floating Drivers. Capacitors are
connected between the Boost and Switch pins and Schot­tky diodes are tied between the Boost and INTVCC pins.
Voltage swing at the Boost pins is from INTVCC to
(VIN + INTVCC).

BG2, BG1 (Pins 19, 23/Pins 18, 22): High Current Gate
Drives for Bottom Synchronous N-Channel MOSFETS.
Voltage swing at these pins is from ground to INTVCC.

PGND (Pin 20/Pin 19): Driver Power Ground. Connect to
sources of bottom N-channel MOSFETS and the (–) termi­nals of CIN.

INTVCC (Pin 21/Pin 20): Output of the Internal 5V Linear
Low Dropout Regulator and the EXTVCC Switch. The driver
and control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.

EXTVCC (Pin 22/Pin 21): External Power Input to an
Internal Switch . This switch closes and supplies INTV
bypassing the internal low dropout regulator whenever
EXTVCC is higher than 4.7V. See EXTVCC Connection in the
Applications Information section. Do not exceed 7V on
this pin and ensure V

VIN (Pin 24/Pin 23): Main Supply Pin. Should be closely
decoupled to the IC’s signal ground pin.

CLKOUT (Pin 28/Pin 27): Output Clock Signal available to
daisychain other controller ICs for additional MOSFET
driver stages/phases.

EXTVCC

≤ V

INTVCC

Bootstrapped

CC,

.

8

sn3729 3729fas

LTC3729

UU

W

FU CTIO AL DIAGRA

F

IN

R

LP

C

LP

PLLIN

PLLLPF

CLKOUT

PHASMD

DIFFOUT

V

OS

V

OS

PGOOD

V

IN

V

IN

EXTV

INTV

5V

+

SGND

50k

±2µA

–

+

CC

CC

PHASE DET

OSCILLATOR

PHASE LOGIC

40k 40k

40k 40k

+

4.7V
–

–
+

0.80V

A1

CLK1
CLK2

–
+

–
+

V

REF

5V
LDO
REG

INTERNAL

SUPPLY

0.86V

EAIN

0.74V

DUPLICATE FOR SECOND
CONTROLLER CHANNEL

0.86V

4(VFB)

SLOPE

COMP

1.2µA

6V

SRQ

I1

INTV

BOOST

INTV

CC

30k

30k

CC

TG

SW

BG

PGND

SENSE

SENSE

EAIN

I

TH

RUN/SS

+

R

SENSE

–

R1

R2

C

C

DROP

OUT
DET

BOT FCB

FORCE BOT

Q

SHDN

–

+–

+

45k

SHDN

RST

4(VFB)

45k

2.4V

OV

RUN

SOFT

START

EA

SWITCH

LOGIC

–
+

+
–

TOP

BOT

INTV

0.80V

0.86V

V

CC

IN

D

B

C

B

L

+

C

IN

C

OUT

+

V

OUT

R

C

C

SS

3729

FBD

sn3729 3729fas

9

LTC3729

OPERATIO

U

(Refer to Functional Diagram)

Main Control Loop

The LTC3729 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the ITH pin, which is the output of the error
amplifier EA. The differential amplifier, A1, produces a
signal equal to the differential voltage sensed across the
output capacitor but re-references it to the internal signal
ground (SGND) reference. The EAIN pin receives a portion
of this voltage feedback signal at the DIFFOUT pin which
is compared to the internal reference voltage by the EA.
When the load current increases, it causes a slight de­crease in the EAIN pin voltage relative to the 0.8V refer­ence, which in turn causes the ITH voltage to increase until
the average inductor current matches the new load cur­rent. After the top MOSFET has turned off, the bottom
MOSFET is turned on for the rest of the period.

The top MOSFET drivers are biased from floating boot­strap capacitor CB, which normally is recharged during
each off cycle through an external Schottky diode. When
VIN decreases to a voltage close to V

, however, the loop

OUT

may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor.

The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with the
ITH voltage clamped at approximately 30% of its maximum
value. As CSS continues to charge, ITH is gradually re­leased allowing normal operation to resume. When the
RUN/SS pin is low, all LTC3729 functions are shut down.
If V

has not reached 70% of its nominal value when C

OUT

SS

has charged to 4.1V, an overcurrent latchoff can be
invoked as described in the Applications Information
section.

Low Current Operation

The LTC3729 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizes transient response at the expense of substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage, and fre­quency of operation.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 250kHz to 550kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.

The internal master oscillator runs at a frequency twelve
times that of each controller’s frequency. The PHASMD
pin determines the relative phases between the internal
controllers as well as the CLKOUT signal as shown in
Table␣ 1. The phases tabulated are relative to zero phase
being defined as the rising edge of the top gate (TG1)
driver output of controller 1.

Table 1.

V

PHASMD

Controller 2 180° 180° 240°
CLKOUT 60° 90° 120°

GND OPEN INTV

CC

The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution
feeding a single, high current output or separate outputs.
Input capacitance ESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by the
number of phases used and power loss is proportional to
the RMS current squared. A two stage, single output
voltage implementation can reduce input path power loss
by 75% and radically reduce the required RMS current
rating of the input capacitor(s).

10

sn3729 3729fas

OPERATIO

LTC3729

U

(Refer to Functional Diagram)

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTVCC. When the
EXTVCC pin is left open, an internal 5V low dropout
regulator supplies INTVCC power. If the EXTVCC pin is
taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTVCC to INTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu­lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTVCC to INTV
the specified INTVCC current. Voltages up to 7V can be
applied to EXTVCC for additional gate drive capability.

Differential Amplifier

This amplifier provides true differential output voltage
sensing. Sensing both V
tion in high current applications and/or applications hav­ing electrical interconnection losses.

Power Good (PGOOD)

The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET turns on when the output is not
within ±7.5% of its nominal output level as determined by

in applications requiring greater than

CC

OUT

+

and V

–

benefits regula-

OUT

the feedback divider. When the output is within ±7.5% of
its nominal value, the MOSFET is turned off within 10µs
and the PGOOD pin should be pulled up by an external
resistor to a source of up to 7V.

Short-Circuit Detection

The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the controllers
have been given time, as determined by the capacitor on
the RUN/SS pin, to charge up the output capacitors and
provide full load current, the RUN/SS capacitor is then
used as a short-circuit timeout circuit. If the output voltage
falls to less than 70% of its nominal output voltage the
RUN/SS capacitor begins discharging assuming that the
output is in a severe overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the RUN/SS capacitor, the
controller will be shut down until the RUN/SS pin voltage
is recycled. This built-in latchoff can be overidden by
providing a >5µA pull-up current at a compliance of 5V to
the RUN/SS pin. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
output voltage falls below 70% of its nominal level whether
or not the short-circuit latchoff circuit is enabled.

U

APPLICATIO S I FOR ATIO

The basic LTC3729 application circuit is shown in Figure␣ 1
on the first page. External component selection is driven
by the load requirement, and begins with the selection of
R

SENSE1, 2

chosen. Next, the power MOSFETs and D1 and D2 are
selected. The operating frequency and the inductor are
chosen based mainly on the amount of ripple current.
Finally, CIN is selected for its ability to handle the input
ripple current (that PolyPhase operation minimizes) and
C

OUT

ripple voltage and load step specifications (also minimized
with PolyPhase). The circuit shown in Figure␣ 1 can be
configured for operation up to an input voltage of 28V
(limited by the external MOSFETs).

. Once R

is chosen with low enough ESR to meet the output

SENSE1, 2

are known, L1 and L2 can be

WUU

R

R
current. The LTC3729 current comparator has a maxi­mum threshold of 75mV/R
mode range of SGND to 1.1( INTVCC). The current com­parator threshold sets the peak inductor current, yielding
a maximum average output current I
value less half the peak-to-peak ripple current, ∆IL.

Allowing a margin for variations in the LTC3729 and
external component values yields:

where N = number of stages.

Selection For Output Current

SENSE

SENSE1, 2

R

are chosen based on the required output

SENSE

= (50mV/I

MAX

)N

and an input common

SENSE

equal to the peak

MAX

sn3729 3729fas

11

LTC3729

∆I

V

fL

V

V

L

OUT OUT

IN

=−











1

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APPLICATIO S I FOR ATIO

When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
internal slope compensation required to meet stability
criterion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reduction
in peak output current level depending upon the operating
duty factor.

Operating Frequency

The LTC3729 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor­mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure␣ 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.

2.5

2.0

anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid­ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.

The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and in­creases with higher VIN or V

OUT

:

where f is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by the

output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.

1.5

1.0

PLLFLTR PIN VOLTAGE (V)

0.5

0

200 250 300 350 550400 450 500

OPERATING FREQUENCY (kHz)

3729 F02

Figure 2. Operating Frequency vs V

PLLFLTR

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter­related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would

Figure 3 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure␣ 3, the zero output ripple current is obtained when:

V

OUT

V

IN

k

=

N

where k = 1, 2, …, N – 1

So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica­tions having a highly varying input voltage, additional
phases will produce the best results.

sn3729 3729fas

12

LTC3729

Synchronous SwitchDuty Cycle

VV

V

IN OUT

IN

=











–

U

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APPLICATIO S I FOR ATIO

1.0

OUT/VIN

O(P–P)

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

)

)]

3729 F03

0.9

0.8

0.7

0.6

/fL

0.5

O

O(P-P)

V

∆I

0.4

0.3

0.2

0.1
0

0.1 0.2 0.3 0.4

Figure 3. Normalized Peak Output Current vs
Duty Factor [I

DUTY FACTOR (V

RMS

0.5 0.6 0.7 0.8 0.9

≈ 0.3 (∆I

Accepting larger values of ∆IL allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(I
I

is the total load current. Remember, the maximum

OUT

)/N, where N is the number of channels and

OUT

∆IL occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.

Inductor Core Selection

Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc­tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur­rent is exceeded. This results in an abrupt increase in

Kool Mµ is a registered trademark of Magnetics, Inc.

inductor ripple current and consequent output voltage
ripple.

Do not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu­facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be­cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.

Power MOSFET, D1 and D2 Selection

Two external power MOSFETs must be selected for each
controller with the LTC3729: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCC volt­age. This voltage is typically 5V during start-up (see
EXTVCC Pin Connection). Consequently, logic-level thresh­old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (VIN < 5V);
then, sublogic-level threshold MOSFETs (V

GS(TH)

should be used. Pay close attention to the BV

DSS

< 3V)

specifi­cation for the MOSFETs as well; most of the logic-level
MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”
resistance R

, reverse transfer capacitance C

DS(ON)

RSS

,
input voltage, and maximum output current. When the
LTC3729 is operating in continuous mode the duty factors
for the top and bottom MOSFETs of each output stage are
given by:

V

Main SwitchDuty Cycle

OUT

=

V

IN

The MOSFET power dissipations at maximum output
current are given by:

sn3729 3729fas

13

LTC3729

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APPLICATIO S I FOR ATIO



V

P

MAIN

P

SYNC

OUTINMAX

=

kV

=



V




2

IN

()





VVVI

–

IN OUTINMAX

where δ is the temperature dependency of R
constant inversely related to the gate drive current and N
is the number of stages.

Both MOSFETs have I2R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
increase to the point that the use of a higher R
with lower C

actual provides higher efficiency. The

RSS

synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for
low voltage MOSFETs. C
MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diodes, D1 and D2 shown in Figure 1 conduct
during the dead-time between the conduction of the two
large power MOSFETs. This helps prevent the body diode
of the bottom MOSFET from turning on, storing charge
during the dead-time, and requiring a reverse recovery
period which would reduce efficiency. A 1A to 3A (depend­ing on output current) Schottky diode is generally a good
compromise for both regions of operation due to the
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance.

2



I



N




I

MAX

Cf

()()



N






N



> 20V the transition losses rapidly

IN

DS(ON)

RSS

R

+

1 δ

()

DS ON

RSS

2



+

1 δ

()





()

R

DS ON

+

()

DS(ON)

IN

DS(ON)

< 20V the

vs. Temperature curve, but

is usually specified in the

, k is a

device

CIN and C

Selection

OUT

In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V

OUT

/
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for different
phase configurations with the output voltage fixed and
input voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the product of phase num­ber and output voltage, N(V

), is approximately equal to

OUT

the input voltage VIN or:

V

OUT

V

IN

k

=

N

where k = 1, 2, …, N – 1

So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.

In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:

V

OUT

V

IN

Figure 4. Normalized Input RMS Ripple Current vs
Duty Factor for 1 to 6 Output Stages

−21

k

=

2

N

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0

where k = 1, 2, …, N

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
DUTY FACTOR (V

1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE

OUT/VIN

0.9

)

3729 F04

These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.

sn3729 3729fas

14

LTC3729

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APPLICATIO S I FOR ATIO

This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.

The graph shows that the peak RMS input current is
reduced linearly, inversely proportional to the number, N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current
therefore a 2-stage implementation results in 75% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci­tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require­ment has been met, the RMS current rating generally far
exceeds the I
output ripple (∆V

∆∆V I ESR

OUT RIPPLE

RIPPLE(P-P)

OUT

≈+

requirements. The steady state

) is determined by:






8

NfC

1

OUT

Where f = operating frequency of each stage, N is the
number of phases, C
∆I

= combined inductor ripple currents.

RIPPLE

= output capacitance, and

OUT

The output ripple varies with input voltage since ∆IL is a
function of input voltage. The output ripple will be less than
50mV at max VIN with ∆IL = 0.4I

C
C

required ESR < 2N(R

OUT

> 1/(8Nf)(R

OUT

SENSE

)

OUT(MAX)

SENSE

) and

The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally
compensate the switching regulator loop using the I
pin(OPTI-LOOP compensation) allows a much wider
selection of output capacitor types. OPTI-LOOP compen­sation effectively removes constraints on output capacitor

squared






/N assuming:

and

TH

ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.

Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through­hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have the lowest (ESR)(size) product
of any aluminum electrolytic at a somewhat higher price.
An additional ceramic capacitor in parallel with OS-CON
type capacitors is recommended to reduce the inductance
effects.

In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surface mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D
series. Consult the manufacturer for other specific recom­mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. The INTV

CC

regulator powers the drivers and internal circuitry of the
LTC3729. The INTVCC pin regulator can supply up to 50mA
peak and must be bypassed to power ground with a
minimum of 4.7µF tantalum or electrolytic capacitor. An
additional 1µF ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta­neous currents required by the MOSFET gate drivers.

High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the

sn3729 3729fas

15

LTC3729

U

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APPLICATIO S I FOR ATIO

maximum junction temperature rating for the LTC3729 to
be exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTVCC pin. When the voltage applied to the EXTVCC pin
is less than 4.7V, all of the INTVCC load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (IIN)(VIN – INTVCC) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC3729 V
current is limited to less than 24mA from a 24V supply:

TJ = 70°C + (24mA)(24V)(95°C/W) = 125°C

Use of the EXTVCC pin reduces the junction temperature
to:

TJ = 70°C + (24mA)(5V)(95°C/W) = 81.4°C

The input supply current should be measured while the
controller is operating in continuous mode at maximum
V

and the power dissipation calculated in order to pre-

IN

vent the maximum junction temperature from being ex­ceeded.

EXTVCC Connection

The LTC3729 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
When the voltage applied to EXTV

rises above 4.7V, the

CC

internal regulator is turned off and the switch closes,
connecting the EXTV

pin to the INTV

CC

pin thereby

CC

supplying internal and MOSFET gate driving power. The
switch remains closed as long as the voltage applied to
EXTVCC remains above 4.5V. This allows the MOSFET
driver and control power to be derived from the output
during normal operation (4.7V < V

EXTVCC

< 7V) and from
the internal regulator when the output is out of regulation
(start-up, short-circuit). Do not apply greater than 7V to
the EXTVCC pin and ensure that EXTV

CC

< V

+ 0.3V when

IN

using the application circuits shown. If an external voltage
source is applied to the EXTVCC pin when the VIN supply is
not present, a diode can be placed in series with the
LTC3729’s V

pin and a Schottky diode between the

IN

IN

EXTV

and the V

CC

pin, to prevent current from backfeeding

IN

VIN.
Significant efficiency gains can be realized by powering

INTVCC from the output, since the VIN current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTVCC pin directly to V

OUT

. How­ever, for 3.3V and other lower voltage regulators, addi­tional circuitry is required to derive INTVCC power from the
output.

The following list summarizes the four possible connec­tions for EXTV

1. EXTVCC left open (or grounded). This will cause INTV

CC:

CC

to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.

2. EXTVCC connected directly to V

. This is the normal

OUT

connection for a 5V regulator and provides the highest
efficiency.

3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTVCC providing it is compatible with the MOSFET
gate drive requirements. VIN must be greater than or equal
to the voltage applied to the EXTVCC pin.

4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency gains
can still be realized by connecting EXTVCC to an output­derived voltage which has been boosted to greater than

4.7V but less than 7V. This can be done with either the
inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.

Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)

External bootstrap capacitors CB1 and CB2 connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor CB in the
Functional Diagram is charged though diode DB from
INTVCC when the SW pin is low. When the topside MOSFET
turns on, the driver places the CB voltage across the
gate-source of the desired MOSFET. This enhances the
MOSFET and turns on the topside switch. The switch node

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OPTIONAL EXTVCC CONNECTION

< 7V

5V < V

SEC

LTC3729

EXTV

CC

Figure 5a. Secondary Output Loop and EXTVCC Connection

C

V

TG1

SW1

BG1

PGND

+

IN

IN

N-CH

N-CH

voltage, SW, rises to VIN and the BOOST pin rises to VIN +
V

. The value of the boost capacitor CB needs to be

INTVCC

30 to 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of DB must be
greater than V

IN(MAX).

The final arbiter when defining the best gate drive ampli­tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.

Differential Amplifier/Output Voltage

The LTC3729 has a true remote voltage sense capablity.
The sensing connections should be returned from the load
back to the differential amplifier’s inputs through a com­mon, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier
output signal is divided down and compared with the
internal precision 0.8V voltage reference by the error
amplifier.

The differential amplifier utilizes a set of internal precision
resistors to enable precision instrumentation-type mea­surement of the output voltage. The output is an NPN
emitter follower without any internal pull-down current. A
DC resistive load to ground is required in order to sink
current. The output will swing from 0V to 10V. (VIN ≥
V

DIFFOUT

␣ +␣ 2V.) The output voltage is set by an external

resistive divider according to the following formula:

V

IN

1N4148

T1

6.8V

R

SENSE

V

SEC

+

1µF

V

OUT

+

C

OUT

3729 F05a

+

C

IN

LTC3729

EXTV

CC

Figure 5b. Capacitive Charge Pump for EXTV

VV

OUT

V

IN

TG1

N-CH

SW1

BG1

N-CH

PGND

=+



08 1

.





V

IN

BAT85 0.22µF

VN2222LL

L1

R

2






R

1

R

SENSE

+

1µF

BAT85

BAT85

V

OUT

+

C

OUT

3729 F05b

CC

where R1 and R2 are defined in Figure 2.

Soft-Start/Run Function

The RUN/SS pin provides three functions: 1) Run/Shut­down, 2) soft-start and 3) a defeatable short-circuit latchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I

TH(MAX)

. The latchoff timer prevents very short,

extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.

An internal 1.2µA current source charges up the C

SS

capacitor. When the voltage on RUN/SS reaches 1.5V, the
controller is permitted to start operating. As the voltage on
RUN/SS increases from 1.5V to 3.0V, the internal current
limit is increased from 25mV/R

SENSE

to 75mV/R

SENSE

.

The output current limit ramps up slowly, taking an
additional 1.4µs/µF to reach full current. The output
current thus ramps up slowly, reducing the starting surge
current required from the input power supply. If RUN/SS
has been pulled all the way to ground there is a delay before
starting of approximately:

15

.

t

DELAY SS SS

V

=

12

CsFC

.

A

µ

125

./

=µ

()

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The time for the output current to ramp up is then:

VV

−

315

12

.

.

CsFC

=µ

125

./

A

µ

()

SS

t

=

RAMP SS SS

By pulling the RUN/SS pin below 0.8V the LTC3729 is put
into low current shutdown (IQ < 40µA). RUN/SS can be
driven directly from logic as shown in Figure 6. Diode D1
in Figure 6 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. The RUN/SS
pin has an internal 6V zener clamp (see Functional Dia­gram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected. The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltage falls to less than 70% of its nominal value after C
reaches 4.1V, CSS begins discharging on the assumption
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of CSS, the controller will be shut down until the
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:

t

≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS)

LO1

If the overload occurs after start-up, the voltage on CSS will
continue charging and will provide additional time before
latching off:

V

3.3V OR 5V RUN/SS

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

IN

RSS*

D1

C

SS

Figure 6. RUN/SS Pin Interfacing

while eliminating the INTV

CC

INTV

CC

RSS*

D1*

RUN/SS

C

3729 F06

SS

loading from preventing

controller start-up.
Why should you defeat current latchoff? During the

prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com­plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.

The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci­tance is given by:

CSS > (C

OUT

)(V

)(10-4)(R

OUT

SENSE

)

The minimum recommended soft-start capacitor of CSS =

0.1µF will be sufficient for most applications.

Phase-Locked Loop and Frequency Synchronization

t

≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS)

LO2

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci­tor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from VIN as in
the figure, current latchoff is always defeated. Diode­connecting this pull-up resistor to INTVCC, as in Figure␣ 6,
eliminates any extra supply current during shutdown

18

The LTC3729 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency fO. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
400kHz. The nominal operating frequency range of the
LTC3729 is 250kHz to 550kHz.

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The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec­tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆f

∆fH = ∆fC = ±0.5 fO (250kHz-550kHz)

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.

2.4V

PHASE

50k

DETECTOR

DIGITAL

PHASE/

FREQUENCY

DETECTOR

) is greater than the oscil-

PLLIN

, current is sourced continuously,

0SC

EXTERNAL

OSC

PLLIN

Figure 7. Phase-Locked Loop Block Diagram

If the external frequency (f
lator frequency f
pulling up the PLLFLTR pin. When the external frequency
is less than f

, current is sunk continuously, pulling

0SC

down the PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time corre­sponding to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC3729 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple LTC3729’s for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability

R

LP

10k

PLLFLTR

C:

3729 F07

OSC

C

LP

to lock onto the master’s frequency. A DC voltage of 0.7V
to 1.7V applied to the master oscillator’s PLLFLTR pin is
recommended in order to meet this requirement. The
resultant operating frequency will be approximately 500kHz.

The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically R

=10kΩ and CLP is 0.01µF to

LP

0.1µF.

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest time duration
that the LTC3729 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:

V

t

ON MIN

()

<

Vf

OUT

IN

()

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3729 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.

The minimum on-time for the LTC3729 is approximately
100ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases. This is of particu­lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger current and voltage ripple.

If an application can operate close to the minimum on­time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement.

As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I

OUT(MAX)

/N at V

IN(MAX)

.

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Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3729 by loading the ITH pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifier, or

1.2V (see Figure 8).

INTV

CC

R

T2

I

TH

R

R

Figure 8. Active Voltage Positioning Applied to the LTC3729

C

T1

C

C

The resistive load reduces the DC loop gain while main­taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear-tech.com)

LTC3729

3729 F08

2) INTVCC regulator current, 3) I2R losses and 4) Topside
MOSFET transition losses.

1) The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control
currents; the second is the current drawn from the differ­ential amplifier output. VIN current typically results in a
small (<0.1%) loss.

2) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

= (QT + QB), where QT and Q

B

are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV
from an output-derived source will scale the V

power through the EXTVCC switch input

CC

current

IN

required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi­mately 3mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3729 circuits: 1) LTC3729 VIN current
(including loading on the differential amplifier output),

20

3) I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R

SENSE

,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi­mately the same R

, then the resistance of one

DS(ON)

MOSFET can simply be summed with the resistances of L,
R
R

and ESR to obtain I2R losses. For example, if each

SENSE

=10mΩ, RL=10mΩ, and R

DS(ON)

=5mΩ, then the

SENSE

total resistance is 25mΩ. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as
the inverse square of V

for the same external compo-

OUT

nents and output power level. The combined effects of

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increasingly lower output voltages and higher currents
required by high performance digital systems is not dou­bling but quadrupling the importance of loss terms in the
switching regulator system!

4) Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:

Transition Loss = (1.7) V
Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and a very low ESR at the
switching frequency. A 50W supply will typically require a
minimum of 200µF to 300µF of capacitance having a
maximum of 10mΩ to 20mΩ of ESR. The LTC3729
PolyPhase architecture typically halves to quarters this
input capacitance requirement over competing solutions.
Other losses including Schottky conduction losses during
dead-time and inductor core losses generally account for
less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, V
amount equal to ∆I
series resistance of C
discharge C

OUT

LOAD

OUT

generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
time V

to its steady-state value. During this recovery

OUT

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem.

availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response.

Assuming a predominantly second

order system, phase margin and/or damping factor can be

2

I

IN

O(MAX) CRSS

f

shifts by an

OUT

(ESR), where ESR is the effective

(∆I

) also begins to charge or

LOAD

The

estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The ITH external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.

The I

series RC-CC filter sets the dominant pole-zero

TH

loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon because the various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 80% of full-load current having a rise time
of <2µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
resulting from the step change in output current may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the Ith pin signal which is in the feedback
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the same
factor that CC is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.

A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C

, causing a rapid drop in V

OUT

. No regulator can

OUT

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

to C

is greater than1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited to
approximately 25 • C

. Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current to
about 200mA.

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Design Example (Using Two Phases)

As a design example, assume VIN = 5V (nominal), VIN␣ =␣ 5.5V
(max), V

The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR pin
to a resistive divider using the INTVCC pin to generate 1V
for 300kHz operation. The minimum inductance for 30%
ripple current is:

L

≥

≥

≥µ

A 2µH inductor will produce 20% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 11.5A. The minimum on-time
occurs at maximum VIN:

= 1.8V, I

OUT



V

OUT OUT

1

−





fI

∆

()

18

.

300 30 10

kHz A

()()()

135

.

H

= 20A, TA = 70°C and f␣ =␣ 300kHz.

MAX



V



V



IN

V

%



−

1





18

.

55

.



V



V



The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
R
voltage with Tj (estimated) = 110°C at an elevated ambient
temperature:

The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem­perature rise is:

A short-circuit to ground will result in a folded back current
of:

DS(ON)

P

MAIN

P

SYNC

= 0.013Ω, C

V

18

.

=

0 013 1 7 5 5 10 300

()

=
=

10 1 0 005 110 25

()+()

V

55

.

...

Ω

kHz W

310 0 61

..

VV

−

55 18

.

55

.

W

129

= 300pF. At maximum input

RSS

2

+

=

V

.

[]

()()( )

.

10 1 48 0 013

()()

()

2

VApF

2

..

A

CC

°− °

()

Ω

V

t

ON MIN

()

The R

SENSE

maximum current sense voltage specification with some
accomodation for tolerances:

R

SENSE

Choosing 1% resistors: R1 = 16.5k and R2 = 13.2k yields
an output voltage of 1.80V.

OUT

==

Vf

IN

resistors value can be calculated by using the

mV

50

=≈Ω

11 5

.

5 5 300

()( )

0 005

.

A

V

18

.

V kHz

.

s

=µ

11

.



ns V

200 5 5

SC

SYNC

=

25

0 005

.

=
=

55 18

360

I

The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi­ent temperature and estimated 50°C junction temperature
rise is:

P

1



+

Ω

..



2



VV

−

.

V

55
mW

mV

()

µ

2

...

5 28 1 48 0 013

()()



.




H



2

A

A

=

528

.

()

Ω

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which is much less than normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.

The duty cycles when the peak RMS input current occurs
is at D = 0.25 and D = 0.75 according to Figure 4. Calculate
the worst-case required RMS input current rating at the
input voltage, which is 5.5V, that provides a duty cycle
nearest to the peak.

From Figure 4, CIN will require an RMS current rating of:

C requiredI A

IN RMS

The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3 along
with the calculated duty factor. The output ripple in
continuous mode will be highest at the maximum input
voltage. From Figure 3, the maximum output current ripple
is:

V

∆∆I

COUT

I

COUTMAX

Note that the PolyPhase technique will have its maximum
benefit for input and output ripple currents when the
number of phases times the output voltage is approxi­mately equal to or greater than the input voltage.

OUT

=

=

20 0 2346.

()( )

A

=

.

RMS

034

.

()

fL

18034

..

=

()

kHz H

300 2

()

µ

()

A

=

1

1) Are the signal and power grounds segregated? The
LTC3729 signal ground pin should return to the (–) plate
of C
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of CIN, which should have
as short lead lengths as possible.

2) Does the LTC3729 V
of C
plate(s) of C
connected between the V
any feedforward capacitor across R1 should be as close as
possible to the LTC3729.

3) Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE+ and SENSE– pin pairs should be as close as
possible to the LTC3729. Ensure accurate current sensing
with Kelvin connections to the sense resistors.

4) Do the (+) plates of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.

5) Is the INTVCC 1µF ceramic decoupling capacitor con-
nected closely between INTVCC and the power ground pin?
This capacitor carries the MOSFET driver peak currents. A
small value is used to allow placement immediately adja­cent to the IC.

6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC3729.

separately. The power ground returns to the

OUT

+

pin connect to the (+) plate(s)

? Does the LTC3729 V

OUT

? The resistive divider R1, R2 must be

OUT

OS

DIFFOUT

–

pin connect to the (–)

OS

and signal ground and

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3729. These items are also illustrated graphically in
the layout diagram of Figure␣ 11. Check the following in
your layout:

7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.

8) Minimize the capacitive load on the CLKOUT pin to
minimize excess phase shift. Buffer if necessary with an
NPN emitter follower.

sn3729 3729fas

23

LTC3729

U

WUU

APPLICATIO S I FOR ATIO

The diagram in Figure 9 illustrates all branch currents in a
2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal
of the input capacitor and not share a common ground
path with any switched current paths. The left half of the
circuit gives rise to the “noise” generated by a switching
regulator. The ground terminations of the sychronous
MOSFETs and Schottky diodes should return to the

SW1

bottom plate(s) of the input capacitor(s) with a short
isolated PC trace since very high switched currents are
present. A separate isolated path from the bottom plate(s)
of the input capacitor(s) should be used to tie in the IC
power ground pin (PGND) and the signal ground pin
(SGND). This technique keeps inherent signals generated
by high current pulses from taking alternate current paths
that have finite impedances during the total period of the
switching regulator. External OPTI-LOOP compensation
allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.

L1

R

SENSE1

D1

V

IN

R

IN

+

C

IN

BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.

SW2

L2

D2

R

SENSE2

V

OUT

C

OUT

+

3729 F09

R

L

Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator

24

sn3729 3729fas

LTC3729

U

WUU

APPLICATIO S I FOR ATIO

Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current

A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
is greater than the number of phases used times the output
voltage). The output ripple amplitude is also reduced by,
and the effective ripple frequency is increased by the
number of phases used. Figure 10 graphically illustrates
the principle.

SINGLE PHASE

SW V

I

CIN

I

COUT

DUAL PHASE

SW1 V

SW2 V

currents are reduced by using an additional phase. The
input current peaks drop in half and the frequency is
doubled for a 2-phase converter. The input capacity
requirement is reduced theoretically by a factor of four!
A ceramic input capacitor with its unbeatably low ESR
characteristic can be used.

Figure 4 illustrates the RMS input current drawn from the
input capacitance versus the duty cycle as determined by
the ratio of input and output voltage. The peak input RMS
current level of the single phase system is reduced by 50%
in a 2-phase solution due to the current splitting between
the two stages.

An interesting result of the multi-phase solution is that the
VIN which produces worst-case ripple current for the input
capacitor, V

= VIN/2, in the single phase design pro-

OUT

duces zero input current ripple in the 2-phase design.
The output ripple current is reduced significantly when

compared to the single phase solution using the same
inductance value because the V

/L discharge current

OUT

term from the stage(s) that has its bottom MOSFET on
subtracts current from the (VIN - V

)/L charging current

OUT

resulting from the stage which has its top MOSFET on. The
output ripple current is:

I

L1

I

L2

I

CIN

I

COUT

3729 F10

RIPPLE

Figure 10. Single and PolyPhase Current Waveforms

The worst-case RMS ripple current for a single stage
design peaks at twice the value of the output voltage . The
worst-case RMS ripple current for a two stage design
results in peaks at 1/4 and 3/4 of input voltage. When the
RMS current is calculated, higher effective duty factor
results and the peak current levels are divided as long as
the currents in each stage are balanced. Refer to Applica­tion Note 19 for a detailed description of how to calculate
RMS current for the single stage switching regulator.
Figures 3 and 4 help to illustrate how the input and output

I

RIPPLE



DD

−−

12 1

V

2

OUT

=

fL






()

D

−+

12 1








where D is duty factor.
The input and output ripple frequency is increased by the

number of stages used, reducing the output capacity
requirements. When VIN is approximately equal to NV

OUT

as illustrated in Figures 3 and 4, very low input and output
ripple currents result.

Again, the interesting result of 2-phase operation results
in no output ripple at V

= VIN/2. The addition of more

OUT

phases by phase locking additional controllers always
results in no net input or output ripple at V

OUT/VIN

ratios
equal to the number of stages implemented. Designing a
system with a multiple of stages close to the V

OUT/VIN

ratio
will significantly reduce the ripple voltage at the input and
outputs and thereby improve efficiency, physical size, and
heat generation of the overall switching power supply.

sn3729 3729fas

25

LTC3729

U

TYPICAL APPLICATIO S

OPTIONAL

SYNC

CLOCK IN

0.33µF

8.06k, 1%

0.33µF

24k

47pF

0.01µF

47k

10k

1nF

75k

470pF

6800pF

100pF

25.5k, 1%

1000pF

1000pF

1000pF

100pF

1000pF

+

++

2X150µF
16V

2X150µF
16V

L1

M2 M3M1

GND

M5 M6M4

L2

L3

M8 M9M7

GND

M11 M12M10

L4

1

RUN/SS

2

+

SENSE1

3

–

SENSE1

4

EAIN

5

PLLFLTR

6

LTC3729

PLLIN

7

PHASMD

8

I

TH

9

SGND

10

V

DIFFOUT

11

–

V

OS

12

+

V

OS

13

–

SENSE2

14

+

SENSE2

1

RUN/SS

2

+

SENSE1

3

–

SENSE1

4

EAIN

5

PLLFLTR

6

LTC3729

PLLIN

7

PHASMD

8

I

TH

9

SGND

10

NC

V

DIFFOUT

11

–

V

OS

12

+

V

OS

13

–

SENSE2

14

+

SENSE2

CLKOUT

TG1

SW1

BOOST1

BG1
EXTV
INTV

PGND

BG2

BOOST2

SW2

TG2
PGOOD

CLKOUT

TG1

SW1

BOOST1

BG1
EXTV
INTV

PGND

BG2

BOOST2

SW2

TG2
PGOOD

28
27
26
25
24

V

IN

23
22

CC

21

CC

20
19
18
17
16
15

28
27
26
25
24

V

IN

23
22

CC

21

CC

20
19
18
17
16
15

0.47µF

D7

5V

1µF,6.3V

D8

0.47µF

0.47µF

D9

5V

1µF,6.3V

D10

0.47µF

10Ω

1µF

22µF

6.3V

+

10Ω

1µF

22µF

6.3V

+

0.003Ω

D1
MBRS
340T3

D2
MBRS
340T3

0.003Ω

0.003Ω

D3
MBRS
340T3

3X330µF, 6.3V

POSCAP

D4
MBRS
340T3

0.003Ω

+

+

3X330µF, 6.3V
POSCAP

V

OUT

3.3V/90A

V

IN

12V

1

47pF

10k

1nF

0.01µF

VIN: 12V

: 3.3V/90A

V

OUT

SWITCHING FREQUENCY = 400kHz

1000pF

1000pF

RUN/SS

2

SENSE1

3

SENSE1

4

EAIN

5

PLLFLTR

6

PLLIN

7

PHASMD

8

I

TH

9

100pF

SGND

10

NC

V

DIFFOUT

11

V

OS

12

V

OS

13

SENSE2

14

SENSE2

MI – M18: Si7440DP
L1 – L6: 1µH PANASONIC ETQP6F1R0S
D7 – D12: CENTROL CMDSH-3TR

Figure 11. High Current 3.3V/90A 6-Phase Application

26

–
+

+
–

LTC3729

–
+

CLKOUT

TG1

SW1

BOOST1

BG1
EXTV
INTV

PGND

BG2

BOOST2

SW2

TG2
PGOOD

28
27
26
25
24

V

IN

23
22

CC

21

CC

20
19
18
17
16
15

0.47µF

D11

5V

1µF,6.3V

D12

0.47µF

OUTPUT CAPACITORS: SANYO 6TPB330M

L5

M14 M15M13

10Ω

1µF

22µF

6.3V

+

2X150µF
16V

GND

M17 M18M16

L6

0.003Ω

D5
MBRS
340T3

3X330µF, 6.3V

POSCAP

D6
MBRS
340T3

0.003Ω

+

3729 TA03

sn3729 3729fas

PACKAGE DESCRIPTIO

5.20 – 5.38**
(0.205 – 0.212)

° – 8°

0

0.13 – 0.22

(0.005 – 0.009)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

0.55 – 0.95

(0.022 – 0.037)

U

(For purposes of clarity, drawings are not to scale)

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

1.73 – 1.99

(0.068 – 0.078)

0.65

(0.0256)

BSC

0.25 – 0.38

(0.010 – 0.015)

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.05 – 0.21

(0.002 – 0.008)

12345678 9 10 11 12 1413

(0.397 – 0.407)

2526 22 21 20 19 181716 1523242728

10.07 – 10.33*

LTC3729

7.65 – 7.90

(0.301 – 0.311)

G28 SSOP 1098

5.35 ±0.05

4.20 ±0.05

3.45 ±0.05

(4 SIDES)

0.57 ±0.05

PACKAGE OUTLINE

0.23 ± 0.05

RECOMMENDED SOLDER PAD LAYOUT

5.00 ± 0.10

(4 SIDES)

PIN 1
TOP MARK

NOTE:

1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

0.50 BSC

0.75 ± 0.05

0.00 – 0.05

3.45 ± 0.10

(4-SIDES)

0.200 REF

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

31

0.23 ± 0.05

0.50 BSC

0.40 ± 0.10

32

1
2

(UH) QFN 0102

sn3729 3729fas

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3729

TYPICAL APPLICATIO

U

1

0.1µF

13.2k

1000pF

33pF

3.3k

16.5k

100pF

VIN: 5V TO 16V
V

: 3.3V/30A

OUT

SWITCHING FREQUENCY = 250kHz

1000pF

1000pF

RUN/SS

2

SENSE1

3

SENSE1

4

EAIN

5

PLLFLTR

6

PLLIN

7

PHASMD

8

I

TH

9

SGND

10

V

DIFFOUT

11

V

OS

12

V

OS

13

SENSE2

14

SENSE2

MI, M3: IRF7811
M2, M4: IRF7809
L1, L2: 1µH SUMIDA CEP125-1R0MC-H

Figure 12. 3.3V/30A Power Supply with Active Voltage Positioning

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Burst Mode is a registered trademark of Linear Technology Corporation. Adaptive Power is a trademark of Linear Technology Corporation.

Linear Technology Corporation

28

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone] ● www.linear.com

Current Mode Synchronous Step-Down Controller Up to 97% Efficiency, 4V ≤ V2V ≤ 36V,

SENSE

28

CLKOUT

+
–

LTC3729

–
+

–
+

TG1

SW1

BOOST1

V

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

PGOOD

27
26
25
24

IN

23
22

5V

CC

21

CC

20
19
18
17
16
15

0.47µF

D3

1µF,6.3V

D4

100k

0.47µF

: OS CON 2-16SP270M

C

IN

C

: KEMET 3-T510 470µF

OUT

D3, D4: CENTRAL CMDSH-3TR

+

POWER
GOOD

0.1µF

4.7µF

6.3V

10Ω

L1

C

IN

+

L2

0.003Ω

M2M1

D1
UPS840

+

C

OUT

D2
UPS840

M4M3

0.003Ω

V

IN

5V TO
16V

V

OUT

3.3V/30A

3729TA02

at Up to 15A

Standby 5V, 3.3V, Power Good

≤ 36V

IN

Fault Protection, 3.5V ≤ V

24-Pin SSOP, 3.5V ≤ V

0.8V ≤ V

≤ (0.9)(VIN), I

OUT

IN

≤ 36V

IN

≤ 36V

up to 20A

OUT

SSOP and QFN Packages

sn3729 3729fas

LT/CPI 0302 1.5K REV A • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2001