LINEAR TECHNOLOGY LTC3718 Technical data

FEATURES

LTC3718

Low Input Voltage

DC/DC Controller for

DDR/QDR Memory Termination

U

DESCRIPTIO

■

Very Low V

■

Ultrafast Transient Response

■

True Current Mode Control

■

5V Drive for N-Channel MOSFETs Eliminates

IN(MIN)

: 1.5V

Auxillary 5V Supply

■

No Sense Resistor Required

■

Uses Standard 5V Logic-Level N-Channel MOSFETs

■

V

OUT(MIN)

■

V

OUT

■

Symmetrical Source and Sink Output Current Limit

■

Adjustable Switching Frequency

■

t

ON(MIN)

■

Power Good Output Voltage Monitor

■

Programmable Soft-Start

■

Output Overvoltage Protection

■

Optional Short-Circuit Shutdown Timer

■

Small 24-Lead SSOP Package

: 0.4V

Tracks 1/2 VIN or External V

<100ns

REF

U

APPLICATIO S

■

Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...

■

Servers, RAID Systems

■

Distributed Power Systems

■

Synchronous Buck with General Purpose Boost

The LTC®3718 is a high current, high efficiency synchro­nous switching regulator controller for DDR and QDR

TM

memory termination. It operates from an input as low as

1.5V and provides a regulated output voltage equal to
(0.5)VIN. The controller uses a valley current control
architecture to enable high frequency operation with very
low on-times without requiring a sense resistor. Operating
frequency is selected by an external resistor and is com­pensated for variations in VIN and V

. The LTC3718 uses

OUT

a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.

Forced continuous operation reduces noise and RF inter­ference. Fault protection is provided by internal foldback
current limiting, an output overvoltage comparator and an
optional short-circuit timer. Soft-start capability for sup­ply sequencing can be accomplished using an external
timing capacitor. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation. No R
trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a
new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.

SENSE

is a

U

TYPICAL APPLICATIO

V

IN

C

OUT

470µF
×2

2.5V

V

OUT

1.25V
±10A

V

IN

3718 TA01

C

L1 0.8µH

IN1

22µF

×2

D1
B340A

+

D

B

SHDN BOOST

LTC3718

RF2 37.4k

SENSE

SENSE

INTV

PGND2

SW1

V
V

SW2

TG

+

–

BG

CC

IN1
IN2

V

REF

R

ON

237k

I

ON

V

V

FB1

OUT

C

4.75k

PGOOD PGND1

RUN/SS

I

TH

SGND1

SGND2

V

FB2

C

SS

0.1µF

C1 820pF X7R

C

R

RF1 12.1k

: SANYO POSCAP 4TPB470M L1: SUMIDA CEP125-0R8MC L2: PANASONIC ELJPC4R7MF

OUT

CMDSH-3

C

B

0.33µF

C

4.7µF

C

VCC1

10µF

IN2

M1
Si7440DP

M2
Si7440DPD2B340A

L2

4.7µH

D3
MBR0520

Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply

Efficiency vs Load Current

100

VIN = 2.5V

90

= 1.25V

V

OUT

80
70
60
50
40

EFFICIENCY (%)

30
20
10

0

0.01 1 10 100

0.1

FIGURE 1 CIRCUIT

LOAD CURRENT (A)

3718 G05/TA01a

3718fa

1

LTC3718

WWWU

ABSOLUTE AXI U RATI GS

(Note 1)

Input Supply Voltage (V
Boosted Topside Driver Supply Voltage

(BOOST) ............................................... 42V to –0.3V

V

, ION, SW1 Voltage ............................. 36V to –0.3V

IN1

RUN/SS, PGOOD Voltages......................... 7V to –0.3V

VON, V
ITH, V

, V

REF

Voltages .................................... 2.7V to –0.3V

FB1

Voltages .......(INTVCC + 0.3V) to –0.3V

RNG

SW2 Voltage ............................................. 36V to – 0.4V

V

Voltage ................................................. V

FB2

SHDN Voltage ......................................................... 10V

TG, BG, INTVCC Peak Currents.................................. 2A

TG, BG, INTVCC RMS Currents ............................ 50mA

Operating Ambient Temperature

Range (Note 4) ................................... –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

) .......................10V to –0.3V

IN2

IN2

+ 0.3V

UU

W

PACKAGE/ORDER I FOR ATIO

TOP VIEW

RUN/SS

1
2

V

ON

3

PGOOD

4

V

RNG

5

I

TH

6

SGND1

7

I

ON

8

V

FB1

9

V

REF

10

SHDN

11

SGND2

12

V

FB2

24-LEAD PLASTIC SSOP

T

JMAX

G PACKAGE

= 125°C, θJA = 130°C/W

BOOST

24

TG

23

SW1

22
21
20
19
18
17
16
15
14
13

SENSE
SENSE
PGND1
BG
INTV
V

IN1

V

IN2

PGND2
SW2

+

–

CC

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER PART

NUMBER

LTC3718EG

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are TA = 25°C. V

The ● denotes specifications which apply over the full operating

= 15V, V

IN1

= 1.5V unless otherwise noted.

IN2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Buck Regulator

I

Q(VIN1)

Input DC Supply Current (V

IN1

)

Normal 1000 2000 µA

= 0V 15 30 µA

RUN/SS

= 4V to 36V, ITH = 1.2V (Note 3) 0.002 %/V

IN1

= 30µA, VON = 1.5V 400 500 600 ns

I

ON

V

V

RNG
RNG
RNG

RNG
RNG
RNG

= 1V, V
= 0V, V
= INTVCC, V

= 1V, V
= 0V, V
= INTVCC, V

FB1
FB1

FB1
FB1

= V

/2 – 50mV ● 108 135 162 mV

REF

= V

/2 – 50mV ● 76 95 114 mV

REF

= V

FB1

= V
= V

FB1

/2 – 50mV ● 148 185 222 mV

REF

/2 + 50mV –140 –165 –190 mV

REF

/2 + 50mV –97 –115 –133 mV

REF

= V

/2 + 50mV –200 –235 – 270 mV

REF

V

FB1

∆V

FB1(LINE)

∆V

FB1(LOAD)

g

m(EA)

t

ON

t

ON(MIN)

t

OFF(MIN)

V

SENSE(MAX)

V

SENSE(MIN)

∆V

FB1(OV)

∆V

FB1(UV)

V

RUN/SS(ON)

V

RUN/SS(LE)

Shutdown Supply Current V
Feedback Voltage Accuracy ITH = 1.2V (Note 3) ● –0.65 0.1 0.65 %
Feedback Voltage Line Regulation V
Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) ● –0.05 –0.3 %
Error Amplifier Transconductance ITH = 1.2V (Note 3) 0.93 1.13 1.33 mS
On-Time ION = 60µA, VON = 1.5V 200 250 300 ns

Minimum On-Time ION = 180µA 50 100 ns
Minimum Off-Time 300 400 ns
Maximum Current Sense Threshold V

– V

V

PGND

(Source) V

SW1

Minimum Current Sense Threshold V

– V

V

PGND

(Sink) V

SW1

Output Overvoltage Fault Threshold 8 10 12 %
Output Undervoltage Fault Threshold –25 %
RUN Pin Start Threshold ● 0.8 1.5 2 V
RUN Pin Latchoff Enable RUN/SS Pin Rising 4 4.5 V

2

3718fa

LTC3718

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are TA = 25°C. V

The ● denotes specifications which apply over the full operating

= 15V, V

IN1

= 1.5V unless otherwise noted.

IN2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

RUN/SS(LT)

I

RUN/SS(C)

I

RUN/SS(D)

V

IN(UVLO)

TG R

UP

TG R

DOWN

BG R

UP

BG R

DOWN

TG t

r

TG t

f

BG t

r

BG t

f

RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V
Soft-Start Charge Current V
Soft-Start Discharge Current V
V

Undervoltage Lockout VIN Falling ● 3.4 3.9 V

IN1

= 0V –0.5 –1.2 –3 µA

RUN/SS

= 4.5V, V

RUN/SS

Rising ● 3.5 4.0 V

V

IN

= 0V 0.8 1.8 3 µA

FB

TG Driver Pull-Up On Resistance TG High 2 3 Ω
TG Driver Pull-Down On Resistance TG Low 2 3 Ω
BG Driver Pull-Up On Resistance BG High 3 4 Ω
BG Driver Pull-Down On Resistance BG Low 1 2 Ω
TG Rise Time C
TG Fall Time C
BG Rise Time C
BG Fall Time C

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

Internal VCC Regulator

V

INTVCC

∆V

LDO(LOAD)

Internal VCC Voltage 6V < V

<30V ● 4.7 5 5.3 V

IN1

Internal VCC Load Regulation ICC = 0mA to 20mA –0.1 ±2%

PGOOD Output

∆V

FB1H

∆V

FB1L

∆V

FB1(HYS)

V

PGL

PGOOD Upper Threshold V
PGOOD Lower Threshold V
PGOOD Hysterisis V
PGOOD Low Voltage I

= Rising 8 10 12 %

FB1

= Falling –8 –10 – 12 %

FB1

= Returning 1 2 %

FB1

= 5mA 0.15 0.4 V

PGOOD

Boost Regulator

V

IN2(MIN)

V

IN2(MAX)

I

Q(VIN2)

Minimum Operating Voltage 0.9 1.5 V
Maximum Operating Voltage 10 V
Input DC Supply Current (V

IN2

)

Normal 3 4.5 mA

=0V 0.01 1 µA

SHDN

● 1.20 1.23 1.26 V

< 10V 0.02 0.2 %/V

IN2

● 0.9 1.4 1.9 MHz

ISW = 300mA 300 350 mV

= 3V 25 50 µA

SHDN

= 0V 0.01 0.1 µA

V

SHDN

V

FB2

I

VFB2

∆V

FB2(LINE)

f

BOOST

DC

BOOST(MAX)

I

LIM(BOOST)

V

CESAT(BOOST)

I

SWLKG(BOOST)

V

SHDN(HIGH)

V

SHDN(LOW)

I

SHDN

Shutdown Supply Current V
V

Feedback Voltage 0°C < T < 70°C 1.205 1.23 1.255 V

FB2

V

Pin Bias Current ● 27 80 nA

FB2

Boost Reference Line Regulation 1.5V < V
BOOST Switching Frequency 0°C < T < 70°C 1.0 1.4 1.8 MHz

BOOST Maximum Duty Cycle 82 86 %
BOOST Switch Current Limit (Note 5) 500 800 mA
BOOST Switch V

CESAT

BOOST Switch Leakage Current VSW = 5V 0.01 1 µA
SHDN Input Voltage High 1 V
SHDN Input Voltage Low 0.3 V
SHDN Pin Bias Current V

3718fa

3

LTC3718

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: T
dissipation P

is calculated from the ambient temperature TA and power

J

as follows:

D

LTC3718EG: TJ = TA + (PD • 130°C/W)

Note 3: The LTC3718 is tested in a feedback loop that adjusts V
achieve a specified error amplifier output voltage (I

Note 4: The LTC3718 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 5: Current limit guaranteed by design and/or correlation to static test.

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Boost Converter Oscillator
Frequency vs Temperature

2.00

1.75

1.50

1.25

1.00

0.75

0.50

SWITCHING FREQUENCY (MHz)

0.25

VIN = 5V

VIN = 1.5V

0

–50 –25 0 25 50 75 100

TEMPERATURE (°C)

3718 G01

SHDN Pin Current vs V

50

TA = 25°C

40

30

20

10

SHDN PIN BIAS CURRENT (µA)

0

012345

SHDN PIN VOLTAGE (V)

SHDN

3718 G02

).

TH

Boost Converter Current Limit
vs Duty Cycle

1000

900

800

700

600

500

CURRENT LIMIT (mA)

400

300

200

10 20 30 40 50 60 70 80

70°C

25°C

–40°C

DUTY CYCLE (%)

FB1

to

3718 G03

V

, Feedback Pin Voltage

FB2

1.25

1.24

1.23

1.22

FEEDBACK PIN VOLTAGE (V)

1.21

FIGURE 1 CIRCUIT

1.20
–25 0 25 50 75 100

–50

TEMPERATURE (°C)

3718 G04

Efficiency vs Load Current

100

VIN = 2.5V

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

= 1.25V

V

OUT

0

0.01 1 10 100

0.1
LOAD CURRENT (A)

FIGURE 1 CIRCUIT

3718 G05/TA01a

50.00

49.95

49.90

49.85

(%)

IN

/V

49.80

OUT

V

49.75

49.70

49.65

V

Tracking Ratio vs Input

OUT/VIN

Voltage

LOAD = 0A

LOAD = 1A

LOAD = 10A

FIGURE 1 CIRCUIT

1.5

1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)

3718 G06

3718fa

4

UW

LOAD CURRENT (A)

0

1 2 3 4 5 6 7 8 910

∆V

OUT

/V

OUT

(%)

3718 G08

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

VIN = 2.5V
V

OUT

= 1.25V

FIGURE 1 CIRCUIT

TYPICAL PERFOR A CE CHARACTERISTICS

Frequency vs Input Voltage Load Regulation

450

400

350

300

250

200

150

FREQUENCY (kHz)

100

V

OUT

50

FIGURE 1 CIRCUIT

0

1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

LOAD = 10A

LOAD = 0A

= 1.25V

INPUT VOLTAGE (V)

3718 G07

LTC3718

On-Time vs V

1000

I

ION

800

600

400

ON-TIME (ns)

200

0

0

200mV/DIV

= 30µA

Load-Step Transient

V

OUT

I

L

5A/DIV

VIN = 2.5V 20µs/DIV 3718 G10.eps
V

OUT

LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT

Voltage

ON

1

VON VOLTAGE (V)

= 1.25V

2

3718 G11

3

Start-Up Response

V

OUT

1V/DIV

I

L

2A/DIV

VIN = 2.5V 4ms/DIV 3718 G09.eps
V

= 1.25V

OUT

LOAD = 0.2Ω
FIGURE 1 CIRCUIT

On-Time vs Temperature On-Time vs I

300

I

ION

250

200

150

ON-TIME (ns)

100

50

0

–50

= 30µA

–25 0

50 100 125

25 75

TEMPERATURE (°C)

3718 G12

10k

1k

ON-TIME (ns)

100

10

1

Current

ON

10 100

ION CURRENT (µA)

V

= 0V

VON

3718 G13

3718fa

5

LTC3718

TEMPERATURE (°C)

–50

3.0

RUN/SS THRESHOLD (V)

3.5

4.0

4.5

5.0

–25 0 25 50

3718 G16

75 100 125

LATCHOFF ENABLE

LATCHOFF THRESHOLD

RUN/SS (V)

2.0

MAXIMUM CURRENT SENSE THRESHOLD (mV)

3.6

2718 G19

2.8 3.0 3.2 3.42.2

2.4

2.6

160

140

120

100

80

60

40

20

0

UW

TYPICAL PERFOR A CE CHARACTERISTICS

INTVCC Load Regulation

0

–0.1

–0.2

(%)

CC

–0.3

∆INTV

–0.4

–0.5

10

0

INTVCC LOAD CURRENT (mA)

30

20

Undervoltage Lockout Threshold
vs Temperature

4.0

3.5

RUN/SS Latchoff Thresholds
vs Temperature

3

2

PULL-DOWN CURRENT

1

0

FCB PIN CURRENT (µA)

–1

–2

40

50

3718 G14

–50 –25

PULL-UP CURRENT

50

25

0

TEMPERATURE (°C)

100

125

3718 G15

75

Maximum Current Sense Threshold
vs V

Voltage

RNG

300

250

200

RUN/SS Latchoff Thresholds
vs Temperature

Maximum Current Sense Threshold
vs RUN/SS Voltage, V

RNG

= 1V

3.0

2.5

UNDERVOLTAGE LOCKOUT THRESHOLD (V)

2.0
–50

–25 0 25 50

TEMPERATURE (C)

180

160

140

120

6

100

80

60

40

20

MAXIMUM CURRENT SENSE THRESHOLD (mV)

150

100

50

MAXIMUM CURRENT SENSE THRESHOLD (mV)

75 100 125

3718 G17

0

0.50

Maximum Current Sense Threshold
vs Temperature, V

0

–50 130

–30 –10

10 30 50 90

TEMPERATURE (°C)

RNG

= 1V

70

110

3718 G20

1.00 1.25 1.50

0.75
V

(V)

RNG

1.75 2.00

3718 G18

Error Amplifier gm
vs Temperature

1.50

1.40

1.30

1.20

1.10

gm (ms)

1.00

0.90

0.80

0.70
–50 130

–30 –10

10 30 50 90

TEMPERATURE (°C)

110

70

3718 G21

3718fa

LTC3718

U

UU

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.

VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to V
comparator input defaults to 0.7V when the pin is grounded,

2.4V when the pin is tied to INTVCC.
PGOOD (Pin 3): Power Good Output. Open-drain logic

output that is pulled to ground when the output voltage of
the buck section is not within ±10% of the regulation point.

V

(Pin 4): Sense Voltage Range Input. The voltage at

RNG

this pin is ten times the nominal sense voltage at maxi­mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.

I

(Pin 5): Current Control Threshold and Error Amplifier

TH

Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 1.2V corresponding to zero sense
voltage (zero current).

SGND (Pins 6, 11): Signal Ground. All small-signal com­ponents and compensation components should connect to
this ground, which in turn connects to PGND at one point.

ION (Pin 7): On-Time Current Input. Tie a resistor from V
to this pin to set the one-shot timer current and thereby set
the switching frequency.

V

(Pin 8): Error Amplifier Feedback Input. This pin

FB1

connects the negative error amplifier input to V

V

(Pin 9): Positive Input of Internal Error Amplifier.

REF

Reference voltage for output voltage, power good thresh­old, and short-circuit shutdown threshold. The output
voltage is set to V

SHDN (Pin 10): Shutdown, Active Low. Tie to 1V or more
to enable boost converter portion of the LTC3718. Ground
to shut down.

REF

/2.

OUT

OUT

. The

IN

.

V

(Pin 12): Boost Converter Feedback. The V

FB2

connected to INTVCC through a resistor divider to set the
voltage on INTVCC. Set INTVCC voltage according to:

V

SW2 (Pin 13): Boost Converter Switch Pin. Connect
inductor/diode for boost converter portion here. Minimize
trace area at this pin to keep EMI down.

PGND (Pins 14, 19): Power Ground. Connect these pins
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of C

V

IN2

Portion of LTC3718. Must be locally bypassed.

V

IN1

PGND with at least a 1µF ceramic capacitor.
INTVCC (Pin 17): Internal Regulator Output. The driver and

control circuits are powered from this voltage when VIN is
greater than 5V. Decouple this pin to power ground with a
minimum of 4.7µF low ESR tantalum or ceramic capacitor.

BG (Pin 18): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.

SENSE– (Pin 20): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
connected to power ground unless using a resistive di­vider from INTVCC (see Applications Information).

SENSE+ (Pin 21): Positive Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor
(see Applications Information).

SW1 (Pin 22): Switch Node. The (–) terminal of the
bootstrap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to VIN.

TG (Pin 23): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim­posed on the switch node voltage SW.

BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
V

IN

= 1.23V(1 + RF2/RF1)

INTVCC

and the (–) terminal of CIN.

VCC

(Pin 15): Input Supply Pin for Boost Converter

(Pin 16): Main Input Supply. Decouple this pin to

+ INTVCC.

FB2

pin is

3718fa

7

LTC3718

U

U

W

FU CTIO AL DIAGRA S

R

V

ON

2

tON = (10pF)

1.4V

V

RNG

4

0.7V

2.4V0.7V

V

VON

I

ION

+

I

CMP

–

ON

I

7

ON

R
SQ

20k

+

I

REV

–

×

5.7µA

SHDN

V

V

16

IN1

+

0.8V
REF

5V

REG

BOOST

24

C

TG

B

23

ON

SWITCH

LOGIC

OV

SW1

22

SENSE

21

INTV

17

BG

18

PGND1

19

SENSE

20

PGOOD

3

+

CC

C

VCC

–

IN

C

IN

M1

D

L1

B

+

M2

V

OUT

C

OUT

V

OUT2

1

240k

I

THB

V

REF

V

IN2

R7
(EXTERNAL)

FB2 12

R8
(EXTERNAL)

3/10V

+

–

+

11/30V

–

C

SS

COMPARATOR

A2

REF

R4
40k

REF

FF

RQ

S

20k

R3

V

FB1

8

SGND1

6

3718 FD01

SW2

13

DRIVER

Q3

+

0.15Ω

–

14

PGND2

3718 FD02

3718fa

Q2

Q1

EA

+

R2

80k

9

15

V

FB2

11

Q1

SGND2

R5
40k

R1
40k

Q2
x10

–

R6
40k

R9
30k

R10
140k

Q5

R

C2

C

C2

RUN

SHDN

0.6V

RAMP

GENERATOR

1.4MHz

OSCILLATOR

SS

–

+

+

–

0.6V

C

C1

I

5

TH

R

C

+

A1

g

m

–

1

SHDN

10

RUN/SS

Σ

UV

OV

1.2µA

6V

–

+

SHUTDOWN

8

OPERATIO

LTC3718

U

Main Control Loop

The LTC3718 is a current mode controller for DC/DC
step-down converters designed to operate from low input
voltages. It incorporates a boost converter with a buck
regulator.

Buck Regulator Operation

In normal operation, the top MOSFET is turned on for a
fixed interval determined by a one-shot timer OST. When
the top MOSFET is turned off, the bottom MOSFET is
turned on until the current comparator I
ing the one-shot timer and initiating the next cycle. Induc­tor current is determined by sensing the voltage between
the SENSE+ and SENSE– pins using the bottom MOSFET
on-resistance . The voltage on the ITH pin sets the com­parator threshold corresponding to inductor valley cur­rent. The error amplifier EA adjusts this voltage by com­paring the feedback signal V
with an internal reference generated from one half of the
voltage on V
drop in the feedback voltage relative to the reference. The
ITH voltage then rises until the average inductor current
again matches the load current.

The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on­time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.

Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.

Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing the
pin allows an internal 1.2µA current source to charge up an
external soft-start capacitor CSS. When this voltage reaches

1.5V, the controller turns on and begins switching, but
with the ITH voltage clamped at approximately 0.6V below
the RUN/SS voltage. As CSS continues to charge, the soft­start current limit is removed.

. If the load current increases, it causes a

REF

from the output voltage

FB1

trips, restart-

CMP

INTVCC Power

Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re­charged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off.

Boost Regulator Operation

The 5V power source for INTVCC can be provided by a
current mode, internally compensated fixed frequency
step-up switching regulator that has been incorporated
into the LTC3718.

Operation can be best understood by referring to the
Functional Diagrams. Q1 and Q2 form a bandgap refer­ence core whose loop is closed around the output of the
regulator. The voltage drop across R5 and R6 is low
enough such that Q1 and Q2 do not saturate, even when
V

is 1V. When there is no load, V

IN2

1.23V, causing VC (the error amplifier’s output) to de­crease. Comparator A2’s output stays high, keeping switch
Q3 in the off state. As increased output loading causes the
V

voltage to decrease, A1’s output increases. Switch

FB2

current is regulated directly on a cycle-by-cycle basis by
the VC node. The flip-flop is set at the beginning of each
switch cycle, turning on the switch. When the summation
of a signal representing switch current and a ramp gen­erator (introduced to avoid subharmonic oscillations at
duty factors greater than 50%) exceeds the VC signal,
comparator A2 changes state, resetting the flip-flop and
turn

ing off the switch. More power is delivered to the
output as switch current is increased. The output voltage,
attenuated by external resistor divider R7 and R8, appears
at the V
pensation is provided internally by RC and CC. Transient
response can be optimized by the addition of a phase lead
capacitor CPL in parallel with R7 in applications where
large value or low ESR output capacitors are used.

As the load current is decreased, the switch turns on for
a shorter period each cycle. If the load current is further
decreased, the boost converter will skip cycles to main­tain output voltage regulation. If the V
increased significantly above 1.23V, the boost converter
will enter a low power state.

pin, closing the overall loop. Frequency com-

FB2

rises slightly above

FB2

pin voltage is

FB2

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LTC3718

()

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APPLICATIO S I FOR ATIO

A typical LTC3718 application circuit is shown in
Figure 1. External component selection is primarily de­termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3718 uses the on-resistance of the
synchronous power MOSFET for determining the induc­tor current. The desired amount of ripple current and
operating frequency largely determines the inductor value.
Finally, CIN is selected for its ability to handle the large
RMS current into the converter and C
low enough ESR to meet the output voltage ripple and
transient specification.

Maximum Sense Voltage and V

RNG

Inductor current is determined by measuring the voltage
across a sense resistance that appears between the
SENSE+ and SENSE– pins. The maximum sense voltage
is set by the voltage applied to the V
to approximately (0.13)V
(0.17)V

for sinking current. The current mode control

RNG

for sourcing current and

RNG

loop will not allow the inductor current valleys to exceed
(0.13)V

RNG/RSENSE

for sourcing current and (0.17)V
for sinking current. In practice, one should allow some
margin for variations in the LTC3718 and external com­ponent values and a good guide for selecting the sense
resistance is:

V

10•

RNG

I

OUT MAX

R

SENSE

=

is chosen with

OUT

Pin

pin and is equal

RNG

RNG

the

SENSE+ and SENSE– pins as a Kelvin connection to the
sense resistor with SENSE+ at the source of the bottom
MOSFET and the SENSE– pin to PGND1. Using a sense
resistor provides a well defined current limit, but adds cost
and reduces efficiency. Alternatively, one can eliminate the
sense resistor and use the bottom MOSFET as the current
sense element by simply connecting the SE

NSE+ pin to the
drain and the SENSE– pin to the source of the bottom
MOSFET. This improves efficiency, but one must carefully
choose the MOSFET on-resistance as discussed in a later
section.

Power MOSFET Selection

The LTC3718 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
threshold voltage V
transfer capacitance C

, on-resistance R

(GS)TH

and maximum current I

RSS

DS(ON)

(BR)DSS

, reverse

DS(MAX)

,

.

The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3718 applications.

When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its
on-resistance. MOSFET on-resistance is typically speci­fied with a maximum value R

DS(ON)(MAX)

at 25°C. In this

case, additional margin is required to accommodate the
rise in MOSFET on-resistance with temperature:

when V

= 0.5 – 2V.

RNG

An external resistive divider from INTVCC can be used to
set the voltage of the V

pin between 0.5V and 2V

RNG

resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the V

pin can be tied to SGND or INTV

RNG

CC

in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.3 times this nominal value for positive
output current and 1.7 times the nominal value for nega­tive output current.

Connecting the SENSE+ and SENSE– Pins

The LTC3718 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect

10

R

R

DS ON MAX

()( )

=

SENSE

ρ

T

The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.

The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. During normal operation, the duty cycles
for the MOSFETs are:

3718fa

WUUU

f

V

VR pF

Hz

OUT

VON ON

=

[]

()10

f

VVV

VVRpF

IN OUT

VON IN ON

=

−

()

0710.•

•• ( )

APPLICATIO S I FOR ATIO

2.0

1.5

1.0

0.5

NORMALIZED ON-RESISTANCE

T

ρ

LTC3718

V

t

ON

Tying a resistor RON from VIN to the ION pin yields an on­time inversely proportional to VIN. For a step-down
converter, this results in approximately constant fre­quency operation as the input supply varies:

VON

= ()10

I

ION

pF

D

D

TOP

BOT

0

–50

Figure 2. R

V

OUT

=

V

IN

VV

–

IN OUT

=

V

IN

0

JUNCTION TEMPERATURE (°C)

50

vs Temperature

DS(ON)

100

150

3718 F02

The resulting power dissipation in the MOSFETs at maxi­mum output current are:

P

P

TOP

BOT

= D

TOP IOUT(MAX)

+ k V

IN

= D

BOT IOUT(MAX)

2

I

2

ρ

T(TOP) RDS(ON)(MAX)

OUT(MAX) CRSS

2

ρ

T(BOT) RDS(ON)(MAX)

f

Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.

Operating Frequency

The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.

The operating frequency of LTC3718 applications is deter­mined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the V

ON

pin according to:

To hold frequency constant during output voltage changes,
tie the VON pin to V

. The VON pin has internal clamps

OUT

that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.

Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To account for the 0.7V drop on the ION pin, the following
equation can be used to calculate frequency:

To correct for this error, an additional resistor R

ON2

connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.

V

R

ON ON2

07=.

5

R

V

Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By lengthening the on-time slightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and V

. The values

OUT

required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 3a. Place capacitance on the VON pin to

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11

LTC3718

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APPLICATIO S I FOR ATIO

R

VON1

30k

V

OUT

R

VON2

100k

R

C

C

C

(3a) (3b)

Figure 3. Adjusting Frequency Shift with Load Current Changes

C

VON

0.01µF

V

ON

LTC3718

I

TH

filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.

Inductor L1 Selection

Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:



∆=

I

L









V

OUT OUT

fL

V

−

1












V



IN

Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.

A reasonable starting point is to choose a ripple current
that is about 40% of I

OUT(MAX)

. The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:



L

V

=



fI

∆



L MAX





OUT




() ()

V

−

1



V



IN MAX

OUT






Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy or Kool Mµ® cores. A variety of inductors
designed for high current, low voltage applications are

Kool Mµ is a registered trademark of Magnetics, Inc.

R

VON1

V

INTV

OUT

3k

R

VON2

10k

10k

CC

2N5087

Q1

C

VON

0.01µF

R

C

C

C

V

ON

LTC3718

I

TH

3718 F03

available from manufacturers such as Sumida, Pana­sonic, Coiltronics, Coilcraft and Toko.

Schottky Diode D1, D2 Selection

The Schottky diodes, D1 and D2, shown in Figure 1
conduct during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diodes of the top and bottom MOSFETs from turning
on and storing charge during the dead time, which can
cause a modest (about 1%) efficiency loss. The diodes can
be rated for about one half to one fifth of the full load current
since they are on for only a fraction of the duty cycle. In
order for the diode to be effective, the inductance between
it and the bottom MOSFET must be as small as possible,
mandating that these components be placed adjacently.
The diodes can be omitted if the efficiency loss is tolerable.

CIN and C

Selection

OUT

The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.

V

II

≅

RMS OUT MAX

()

OUT

V

This formula has a maximum at VIN = 2V
I

RMS

= I

OUT(MAX)

/2. This simple worst-case condition is

IN

V

V

IN

OUT

–1

OUT

, where

commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.

The selection of C

is primarily determined by the ESR

OUT

required to minimize voltage ripple and load step

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APPLICATIO S I FOR ATIO

LTC3718

transients. The output ripple ∆V

is approximately

OUT

bounded by:

∆≤∆ +



V I ESR

OUT L





fC

8

1

OUT






Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coeffi­cient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
signifi

cant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom­mended to reduce the effect of their lead inductance.

Top MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTV

CC

when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the

top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.

Fault Condition: Current Limit

The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3718, the maximum sense voltage is controlled by
the voltage on the V

pin. With valley current control,

RNG

the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:

I

LIMITPOSITIVE

I

LIMITNEGATIVE

V

SNS MAX

=+∆

()

R

DS ON T

()

V

SNS MIN

=−∆

()

R

DS ON T

()

1

I

ρ

ρ

L

2

1

I

L

2

The current limit value should be checked to ensure that
I

LIMIT(MIN)

> I

OUT(MAX)

. The minimum value of current limit
generally occurs with the largest VIN at the highest ambi­ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I

which heats

LIMIT

the MOSFET switches.
Caution should be used when setting the current limit

based upon the R

of the MOSFETs. The maximum

DS(ON)

current limit is determined by the minimum MOSFET on­resistance. Data sheets typically specify nominal and
maximum values for R
reasonable assumption is that the minimum R

, but not a minimum. A

DS(ON)

DS(ON)

lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.

Minimum Off-time and Dropout Operation

The minimum off-time t

OFF(MIN)

is the smallest amount of
time that the LTC3718 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + t

OFF(MIN)

). If the maximum duty cycle is reached,

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APPLICATIO S I FOR ATIO

due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:

tt

+

VV

IN MIN OUT

=

()

ON OFF MIN

t

ON

()

Output Voltage Programming

When VFB is connected to V
regulated to one half of the voltage at the V
resistor connected between VFB and V

, the output voltage is

OUT

REF

can be used to

OUT

pin. A

further adjust the output voltage according to the follow­ing equation:

VV

=

OUT REF

If V
with the V

exceeds 3V, resistors should be placed in series

REF

REF



kR

60



120



pin and the VFB pin to avoid exceeding the



+

FB



k



input common mode range of the internal error amplifier.
To maintain the V
series with the V

= V

OUT

pin should be made twice as large as

REF

/2 relationship, the resistor in

REF

the resistor in series with the VFB pin.

R

FB

249k

R

FB

499k

Figure 4

V

V

FB1

LTC3718

REF

3718 F04

V

OUT

V

REF

External Gate Drive Buffers

The LTC3718 drivers are adequate for driving up to about
30nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.

10Ω

INTV

PGND

CC

Q3
FMMT619

Q4
FMMT720

GATE
OF M2

3718 F05

BOOST

Q1
FMMT619

10Ω

TG

Q2
FMMT720

SW

Figure 5. Optional External Gate Driver

GATE
OF M1

BG

Alternately, the external buffer circuit shown in Figure 5
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate.

Soft-Start and Latchoff with the RUN/SS Pin

The RUN/SS pin provides a means to shut down the
LTC3718 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3718 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:

15

.

t

DELAY SS SS

V

=

CsFC

12

.

A

µ

13

./

=µ

()

When the voltage on RUN/SS reaches 1.5V, the LTC3718
begins operating with a clamp on ITH of approximately

0.9V. As the RUN/SS voltage rises to 3V, the clamp on I

TH

is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back. During start-up, the maximum load current is re­duced until either the RUN/SS pin rises to 3V or the output
reaches 75% of its final value. The pin can be driven from
logic as shown in Figure 6. Diode D1 reduces the start
delay while allowing CSS to charge up slowly for the soft­start function.

INTV

CC

V

3.3V OR 5V RUN/SS

Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated

IN

RSS*

D1

C

SS

(6a) (6b)

RSS*

RUN/SS

D2*

C

SS

3718 F06

*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF

After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition

3718fa

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APPLICATIO S I FOR ATIO

LTC3718

persists until the RUN/SS pin drops to 3.5V, then the con­troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.

The overcurrent protection timer requires that the soft­start timing capacitor CSS be made large enough to guar­antee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:

CSS > C

Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or

desired. The feature can be overridden by adding a pull­up current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of CSS during a
fault and also shortens the soft-start period. Using a
resistor to VIN as shown in Figure 6a is simple, but slightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 6b eliminates the additional
shutdown current, but requires a diode to isolate CSS. Any
pull-up network must be able to pull RUN/SS above the

4.2V maximum threshold of the latchoff circuit and over­come the 4µA maximum discharge current.

INTVCC Supply

The 5V supply that powers the drivers and internal cir­cuitry within the LTC3718 can be supplied by either an
internal P-channel low dropout regulator if VIN is greater
than 5V or the internal boost regulator if VIN is less than 5V.
The INTVCC pin can supply up to 50mA RMS and must be
bypassed to ground with a minimum of 4.7µF tantalum or
other low ESR capacitor. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers. Applications using large MOSFETs with a
high input voltage and high frequency of operation may
cause the LTC3718 to exceed its maximum junction tem­perature rating or RMS current rating. In continuous mode
operation, this current is I
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics.

OUT VOUT RSENSE

(10–4 [F/V s])

GATECHG

= f(Q

g(TOP)

+ Q

g(BOT)

).

Inductor Selection for Boost Converter

For the boost converter, the inductance should be 4.7µH
for input voltages less then 3.3V and 10µH for inputs
above 3.3V. The inductor should have a saturation current
rating of approximately 0.5A or greater. A guide for select­ing an inductor for the boost converter is to choose a ripple
current that is 40% of the current supplied by the boost
converter. To ensure that the ripple current doesn’t exceed
a specified amount, the inductance can be chosen accord­ing to the following equation:



V

IN MAX

2

1

V

IN MIN

2

()

L

=

–




∆

Diode D3 Selection

A Schottky diode is recommended for use in the boost
converter section. The Motorola MBR0520 is a very good
choice.

Boost Converter Output Capacitor

Because the LTC3718’s boost converter is internally com­pensated, loop stability must be carefully considered when
choosing its output capacitor. Small, low cost tantalum
capacitors have some ESR, which aids stability. However,
ceramic capacitors are becoming more popular, having
attractive characteristics such as near-zero ESR, small size
and reasonable cost. Simply replacing a tantalum output
capacitor with a ceramic unit will decrease the phase margin,
in some cases to unacceptable levels. With the addition of
a phase-lead capacitor and isolating resistor, the boost
converter portion of the LTC3718 can be used success­fully with ceramic output capacitors.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3718 circuits:

()

V

OUT BOOST

()

If

•






3718fa

15

LTC3718

WUUU

APPLICATIO S I FOR ATIO

1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R

DS(ON)

, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if R

= 0.01Ω and RL = 0.005Ω, the

DS(ON)

loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.

2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci­tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:

Transition Loss ≅ (1.7A–1) V

IN

2

I

OUT CRSS

f

3. INTVCC current. This is the sum of the MOSFET driver
and control currents.

4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.

Other losses, including C

ESR loss, Schottky diode D1

OUT

conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.

When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.

Checking Transient Response

The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C

(ESR), where ESR is the effective series

LOAD

OUT

immediately shifts by an amount

OUT

. ∆I

also begins to charge or

LOAD

discharge C
by the regulator to return V
During this recovery time, V

generating a feedback error signal used

OUT

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 1 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.

Design Example

As a design example, take a supply with the following
specifications: VIN = 2.5V, V
I

OUT(MAX)

resistor with VON = V

R

= ±6A, f = 300kHz. First, calculate the timing

:

OUT

VV

−

25 07

ON

=

..

V kHz pF

2 5 300 10

( . )( )( )

= 1.25V ±100mV,

OUT

k

=

240

Next, use a standard value of 237k and choose the inductor
for about 40% ripple current at the maximum VIN:

125

L

300 0 4 6

( )( . )( )

.

kHz A

V



1

–





125

.

25

.



V

=µ

087



V



H=

.

Selecting a standard value of 1µH results in a maximum
ripple current of:

125

∆=

L

.

300 1

()()

kHz H



V

1

–



µ



125

.

25

.



V

21

.

=I



V



A

Next, choose the synchronous MOSFET switch. Choosing
an IRF7811A (R

DS(ON)

= 0.013Ω, C

= 60pF, θJA =

RSS

50°C/W) yields a nominal sense voltage of:

V

SNS(NOM)

Tying V

= (6A)(1.3)(0.013Ω) = 101.4mV

to 1V will set the current sense voltage range

RNG

for a nominal value of 100mV with current limit occurring
at 133mV. To check if the current limit is acceptable,
assume a junction temperature of about 10°C above a
50°C ambient with ρ

I

LIMIT

133

≥

1 15 0 013

(. )(. )

60°C

mV

= 1.15:

1

+=

Ω

AA

21 99

(. ) .

2

16

3718fa

WUUU

APPLICATIO S I FOR ATIO

LTC3718

and double check the assumed TJ in the MOSFET:

2



1 15 0 013

(. )(. )



2



Ω

P

BOT

VVVA

25 1252599

.–...

=

018

.

W

=






TJ = 50°C + (0.18W)(50°C/W) = 59°C

Now check the power dissipation of the top MOSFET at
current limit with ρ

125

V

P

TOP

.

=

25

V

.

17 25 99 60 300

+

.. .

()()()()( )

=

087

W

.

= 1.35:

90°C

2

99 135 0013

A

...

()()

()

Ω

2

V A pF kHz

TJ = 50°C + (0.87W)(50°C/W) = 93.5°C

CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low

ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:

∆V

OUT(RIPPLE)

= ∆I

L(MAX)

(ESR)

= (2.6A) (0.005Ω) = 13mV

However, a 0A to 6A load step will cause an output change
of up to:

∆V

OUT(STEP)

= ∆I

(ESR) = (6A) (0.005Ω) = 30mV

LOAD

The inductor for the boost converter is selected by first
choosing an allowable ripple current. The boost converter
will be operating in discontinous mode. If we select a ripple
current of 170mA for the boost converter, then:



V

33 1

L

()(.)

170 1 4

−

.





mA MHz

33

.

5



V



V



.

47

H=

=µ

The complete circuit is shown in Figure 7.

PGOOD

C

SS

R

R1

10k

C1 820pF

R

12.1k

F1

R

39.2k

R

4.75k

R

237k

R2

C

100pF

ON

D

0.1µF

1

RUN/SS

2

V

ON

3

PGOOD

4

V

RNG

5

I

R
10k

TH

6

SGND1

LTC3718

7

I

ON

8

V

FB1

9

V

REF

10

SHDN

11

SGND2

12

V

FB2

F3

R

37.4k

C

1000pF

C2

SENSE

SENSE

F2

F4

BOOST

SW1

PGND1

INTV

V

V

PGND2

SW2

24

23

TG

22

21

+

20

–

19

18

BG

17

CC

16

IN1

15

IN2

14

13

B

CMDSH-3

C

B

0.33µF

C

VCC1

10µF

C

IN2

4.7µF

R
100k

PG

Figure 7. Design Example: 1.25V/±6A at 300kHz from 2.5V

C

IN1

22µF
×2

1µH

D1
B340A

L1

M1
IRF7811A

M2
IRF7811AD2B340A

3718 F07

L2

4.7µH

D3
MBR0520

C

IN2

330µF

C

OUT

270µF
×2

V

IN

2.5V

V

OUT

1.25V
±6A

3718fa

17

LTC3718

WUUU

APPLICATIO S I FOR ATIO

PC Board Layout Checklist

When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power
MOSFETs.

• Place CIN, C

, MOSFETs, D1 and inductor all in one

OUT

compact area. It may help to have some components
on the bottom side of the board.

• Place LTC3718 chip with Pins 13 to 24 facing the

power components. Keep the components connected
to Pins 1 to 12 close to LTC3718 (noise sensitive
components).

• Use an immediate via to connect the components to

ground plane including SGND and PGND of LTC3718.
Use several bigger vias for power components.

• Use compact plane for switch node (SW) to improve

cooling of the MOSFETs and to keep EMI down.

• Use planes for VIN and V

to maintain good voltage

OUT

filtering and to keep power losses low.

• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (VIN, V

, GND or to any other DC

OUT

rail in your system).

When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera­tion of the controller. These items are also illustrated in
Figure 8.

• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.

• Place M2 as close to the controller as possible, keep­ing the PGND, BG and SW traces short.

• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.

• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.

• Connect the INTVCC decoupling capacitor C

VCC

closely

to the INTVCC and PGND pins.

• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.

18

V

3718 F08

IN

+

V

OUT

–

3718fa

C

SS

1

RUN/SS

2

V

ON

3

PGOOD

4

V

C1

R

C

C2

R

ON

R

F3

RNG

5

I

TH

6

SGND1

LTC3718

7

I

ON

8

V

FB1

9

V

REF

10

SHDN

11

SGND2

12

V

FB2

R

F5

R

SENSE

SENSE

F4

BOOST

SW1

PGND1

INTV

V

V

PGND2

SW2

24

C

23

TG

22

21

+

20

–

19

18

BG

17

CC

16

IN1

15

IN2

14

13

B

D

B

C

VCC

C

IN2

D3

L2 BOLD LINES INDICATE HIGH CURRENT PATHS

M1

L1

M2 D2

C

IN

C

OUT

Figure 8. LTC3718 Layout Diagram

TYPICAL APPLICATIO

R

PG

100k

PGOOD

*SANYO POSCAP 4TPB470M
**SUMIDA CEP125-0R8MC
***PANASONIC ELJPC4R7MF
****SANYO POSCAP 6TPB330M

C1

820pF

X7R

12.1k

LTC3718

U

One Half VIN, ±10A Bus Terminator

V

IN

OUT

2.5V

****

IN2

V

OUT

1.25V
±10A

*

22µF
X5R

C

IN1

L1**

0.8µH

22µF X5R
×2

D1
B340A

3718 TA02

C

SS

0.1µF X7R

1

RUN/SS

2

V

ON

3

PGOOD

4

V

R
10k

RNG

5

I

TH

6

SGND1

LTC3718

7

I

ON

8

V

FB1

9

V

REF

10

SHDN

11

SGND2

12

V

FB2

F3

R

37.4k

C

1000pF X7R

4.75k

R

C

C2

100pF

R

ON

237k

R

F1

SENSE

SENSE

F2

F4

BOOST

SW1

PGND1

INTV

V

V

PGND2

SW2

24

23

TG

22

21

+

20

–

19

18

BG

17

CC

16

IN1

15

IN2

14

13

D

B

CMDSH-3

C

0.33µF

B

X7R

C

VCC1

10µF 6.3V
X5R

M1
Si7440DP

M2
Si7440DPD2B340A

4.7µF

6.3V X7R

+

L2***

4.7µH

D3
MBR0520

C
330µF

C
470µF
×2

PACKAGE DESCRIPTIO

7.8 – 8.2

0.42 ±0.03

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60**

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

U

(.197 – .221)

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

G Package

24-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

7.90 – 8.50*

1.25 ±0.12

5.3 – 5.7

0.65
BSC

° – 8°

0

*

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE

**

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

12345678 9 10 11 12

0.65

(.0256)

BSC

(.311 – .335)

2122 18 17 16 15 14

19202324

0.22 – 0.38

(.009 – .015)

13

7.40 – 8.20

(.291 – .323)

2.0

(.079)

0.05

(.002)

G24 SSOP 0802

3718fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC3718

TYPICAL APPLICATIO

Dual Output 2.5V, ±10A Buck Converter and 5V to 12V/130mA Boost Converter

R

PG

100k

PGOOD

C1

3300pF

X7R

R

249k

FB

R

12.3k

F1

R

C

R
237k

R
499k

REF

U

0.1µF X7R

10k

100pF

ON

V

IN

6V TO 24V

C

****

F

+

L2***
10µH

D3
MBR0520

IN1

33µF
×2
25V

C

OUT

470µF
×2

*

V

OUT1

2.5V
±10A

V

IN2

5V

V

OUT2

12V
130mA

3718 TA03

C

SS

F2

F4

BOOST

SENSE

SENSE

PGND1

INTV

PGND2

SW1

V

V

SW2

24

23

TG

22

21

+

20

–

19

18

BG

17

CC

16

IN1

15

IN2

14

13

1

RUN/SS

2

V

ON

3

PGOOD

4

V

RNG

5

I

R
10k

TH

6

SGND1

LTC3718

7

I

ON

8

V

FB1

9

V

REF

10

SHDN

11

SGND2

12

V

FB2

F3

R

107k

C

200pF X7R

C2

C

VCC2

4.7µF

D

B

CMDSH-3

0.33µF

C

B

X7R

CF

0.1µF

C

VCC1

4.7µF
X5R

M1
Si7440DP

M2
Si7440DPD2B340A

C

IN2

22µF X5R

D1
B340A

L1**

1.8µH

R
1Ω

*SANYO POSCAP 4TPB470M
**TOKO D104C
***PANASONIC ELJPC4R7MF
****KEMET T495X336K025AS

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and ThinSOT are trademarks of Linear Technology Corporation.

SENSE

Synchronous Step-Down Controller 0.925V ≤ V

SENSE

Synchronous Controller No Sense Resistor Required, V

SENSE

OUT

from 1A to 20A

I

OUT

0.6V ≤ V

OUT

Tracks 1/2 VIN or V

OUT

I

from 1A to 20A

OUT

≤ 2V, 4V ≤ VIN ≤ 36V

OUT

≤ V

IN

Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2002

≤ 6V, SSOP-16

OUT

≤ VIN,

OUT

OUT

= 1.5V

IN(MIN)

Tracks VIN or V

, 3V ≤ VIN ≤ 8V,

REF

LT/TP 1103 1K REV A • PRINTED IN USA

REF

,

≤ V

OUT

≤ (0.9)V

3718fa

IN

IN