Datasheet LTC3717 Datasheet (LINEAR TECHNOLOGY)

FEATURES

■

V

= 1/2 VIN (Supply Splitter)

OUT

■

Adjustable and Symmetrical Sink/Source
Current Limit up to 20A

■

±0.65% Output Voltage Accuracy

■

Up to 97% Efficiency

■

No Sense Resistor Required

■

Ultrafast Transient Response

■

True Current Mode Control

■

2% to 90% Duty Cycle at 200kHz

■

t

ON(MIN)

■

Stable with Ceramic C

■

Dual N-Channel MOSFET Synchronous Drive

■

Power Good Output Voltage Monitor

■

Wide VCC Range: 4V to 36V

■

Adjustable Switching Frequency up to 1.5MHz

■

Output Overvoltage Protection

■

Optional Short-Circuit Shutdown Timer

■

Available in a 16-Pin Narrow SSOP Package

≤ 100ns

OUT

U

APPLICATIO S

■

Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...

■

Notebook Computers, Desktop Servers

■

Tracking Power Supply

LTC3717

Wide Operating Range,

No R

SENSE

TM

Step-Down Controller

for DDR/QDR Memory Termination

U

DESCRIPTIO

The LTC®3717 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data RateTM (QDRTM) memory termination. The controller
uses a valley current control architecture to deliver very
low duty cycles without requiring a sense resistor. Oper­ating frequency is selected by an external resistor and is
compensated for variations in VIN.

Forced continuous operation reduces noise and RF inter­ference. Output voltage is internally set to half of V
which is user programmable.

Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accom­plished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
V

input.

CC

, LTC and LT are registered trademarks of Linear Technology Corporation.

No R

is a trademark of Linear Technology Corporation.

SENSE

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.

REF

,

TYPICAL APPLICATIO

V

CC

5V TO 28V

C

470pF

1µF

C

C

SS

0.1µF

R

20k

V

CC

I

ON

V

REF

BOOST

LTC3717

INTV

PGND

SW

V

TG

CC

BG

+

FB

RUN/SS

I

TH

C

SGND

PGOOD

Figure 1. High Efficiency DDR Memory Termination Supply

R

ON

715k

= 2.5V

V

DD

CB 0.22µF

D

B

CMDSH-3

C

VCC

4.7µF

U

M1
Si7840DP

M2
Si7840DP

D2
B320A

L1

0.68µH

D1
B320A

3717 F01a

Efficiency vs Load Current

V

IN

2.5V TO 5.5V

C

+

IN

150µF

6.3V
×2

V

OUT

1.25V

C

±10A

OUT

+

180µF
4V
×2

100

90
80
70

VIN = 2.5V

60
50
40

EFFICIENCY (%)

30
20
10

0

0

V

= 1.25V

OUT

VIN = 5V

2 4 6 8 10 12 14

LOAD CURRENT (A)

3717 F01b

sn3717 3717fs

1

LTC3717

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

RUN/SS

PGOOD

V

RNG

I

TH

SGND

I

ON

V

FB

V

REF

BOOST
TG
SW
PGND
BG
INTV

CC

V

CC

EXTV

CC

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

UU

W

(Note 1)

Input Supply Voltage (VCC, ION) .................36V to –0.3V

Boosted Topside Driver Supply Voltage

(BOOST) ................................................... 42V to –0.3V

ORDER PART

NUMBER

LTC3717EGN

SW Voltage .................................................. 36V to –5V

EXTVCC, (BOOST – SW), RUN/SS,

PGOOD Voltages....................................... 7V to –0.3V

V

, V

REF

ITH, VFB Voltages...................................... 2.7V to –0.3V

TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A

TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA

Operating Ambient Temperature

Range (Note 4) ................................... –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Voltages ...............(INTVCC + 0.3V) to –0.3V

RNG

T

= 125°C, θJA = 130°C/W

JMAX

GN PART

MARKING

3717

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop

I

Q

V

FB

∆V

FB(LINEREG)

∆V

FB(LOADREG)

g

m(EA)

t

ON

t

ON(MIN)

t

OFF(MIN)

V

SENSE(MAX)

V

SENSE(MIN)

∆V

FB(OV)

∆V

FB(UV)

V

RUN/SS(ON)

V

RUN/SS(LE)

V

RUN/SS(LT)

I

RUN/SS(C)

I

RUN/SS(D)

2

Input DC Supply Current
Normal 1000 2000 µA
Shutdown Supply Current V

Feedback Voltage Accuracy ITH = 1.2V (Note 3), V
Feedback Voltage Line Regulation VCC= 4V to 36V, ITH = 1.2V (Note 3) 0.002 %/V
Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) ● –0.05 –0.3 %
Error Amplifier Transconductance ITH = 1.2V (Note 3) 0.93 1.13 1.33 mS
On-Time ION = 30µA 186 233 280 ns

Minimum On-Time ION = 180µA 50 100 ns
Minimum Off-Time ION = 30µA 300 400 ns
Maximum Current Sense Threshold (Source) V

V

– V

PGND

SW

Minimum Current Sense Threshold (Sink) V

– V

V

PGND

SW

Output Overvoltage Fault Threshold 8 10 12 %
Output Undervoltage Fault Threshold –25 %
RUN Pin Start Threshold ● 0.8 1.5 2 V
RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 4 4.5 V
RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V
Soft-Start Charge Current –0.5 –1.2 –3 µA
Soft-Start Discharge Current 0.8 1.8 3 µA

The ● denotes specifications which apply over the full operating

RUN/SS

= 60µA 95 115 135 ns

I

ON

RNG

V

RNG

V

RNG

RNG

V

RNG

V

RNG

Consult LTC Marketing for parts specified with wider operating temperature ranges.

= 0V 15 30 µA

= 2.4V –0.65 0.65 %

REF

= 1V, VFB = V
= 0V, VFB = V
= INTVCC, VFB = V

= 1V, VFB = V
= 0V, VFB = V
= INTVCC, VFB = V

– 50mV ● 108 135 162 mV

REF/2

– 50mV ● 76 95 114 mV

REF/2

REF/2
REF/2

– 50mV ● 148 185 222 mV

REF/2

+ 50mV ● – 140 –165 –190 mV
+ 50mV ● –97 – 115 –133 mV

+ 50mV ● –200 –235 – 270 mV

REF/2

sn3717 3717fs

LTC3717

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC(UVLO)

V

CC(UVLOR)

TG R

UP

TG R

DOWN

BG R

UP

BG R

DOWN

TG t

r

TG t

f

BG t

r

BG t

f

Internal VCC Regulator

V

INTVCC

∆V

LDO(LOADREG)

V

EXTVCC

∆V

EXTVCC

∆V

EXTVCC(HYS)

PGOOD Output

∆V

FBH

∆V

FBL

∆V

FB(HYS)

V

PGL

Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.

Note 2: T
dissipation P

LTC3717EGN: TJ = TA + (PD • 130°C/W)

Undervoltage Lockout Threshold VCC Falling ● 3.4 3.9 V
Undervoltage Lockout Threshold VCC Rising ● 3.5 4 V
TG Driver Pull-Up On Resistance TG High 2 3 Ω
TG Driver Pull-Down On Resistance TG Low 2 3 Ω
BG Driver Pull-Up On Resistance BG High 3 4 Ω
BG Driver Pull-Down On Resistance BG Low 1 2 Ω
TG Rise Time C
TG Fall Time C
BG Rise Time C
BG Fall Time C

Internal VCC Voltage 6V < VCC < 30V, V
Internal VCC Load Regulation ICC = 0mA to 20mA, V
EXTVCC Switchover Voltage ICC = 20mA, V
EXTVCC Switch Drop Voltage ICC = 20mA, V

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 3300pF 20 ns

LOAD

= 4V ● 4.7 5 5.3 V

EXTVCC

= 4V –0.1 ±2%

EXTVCC

Rising ● 4.5 4.7 V

EXTVCC

= 5V 150 300 mV

EXTVCC

EXTVCC Switchover Hysteresis 200 mV

PGOOD Upper Threshold VFB Rising (0% = 1/3 V
PGOOD Lower Threshold VFB Falling (0% = 1/3 V
PGOOD Hysteresis VFB Returning (0% = 1/3 V
PGOOD Low Voltage I

= 5mA 0.15 0.4 V

PGOOD

) 8 10 12 %

REF

)–8–10–12%

REF

)12%

REF

Note 3: The LTC3717 is tested in a feedback loop that adjusts VFB to achieve

).

TH

is calculated from the ambient temperature TA and power

J

as follows:

D

a specified error amplifier output voltage (I
Note 4: The LTC3717E is guaranteed to meet performance specifications from

0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.

sn3717 3717fs

3

LTC3717

ION CURRENT (µA)

1

10

ON-TIME (ns)

100

1k

10k

10 100

3717 G13

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Load Current

100

VIN = 2.5V

90
80
70
60
50
40

EFFICIENCY (%)

30
20
10

= 1.25V

V

OUT

0

0.01 1 10 100

0.1
LOAD CURRENT (A)

FIGURE 1 CIRCUIT

Load Regulation

(%)

OUT

/V

OUT

∆V

0

–0.1

–0.2

–0.3

–0.4

VIN = 2.5V
V

OUT

3717 G06

= 1.25V

(%)

IN

/V

OUT

V

50.00

49.95

49.90

49.85

49.80

49.75

49.70

49.65

V
Voltage

1.5

Tracking Ratio vs Input

OUT/VIN

LOAD = 0A

LOAD = 1A

LOAD = 10A

FIGURE 1 CIRCUIT

1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)

3717 G07

Frequency vs Input Voltage

450

400

350

300

250

200

150

FREQUENCY (kHz)

100

V

OUT

50

FIGURE 1 CIRCUIT

0

1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

Start-Up Response Load-Step Transient

V

OUT

1V/DIV

2A/DIV

I

L

V

OUT

200mV/DIV

5A/DIV

I

L

LOAD = 10A

LOAD = 0A

= 1.25V

INPUT VOLTAGE (V)

3717 G08

–0.5

FIGURE 1 CIRCUIT

–0.6

0

On-Time vs V

1000

I

ION

800

600

400

ON-TIME (ns)

200

0

0

1 2 3 4 5 6 7 8 910

LOAD CURRENT (A)

3717 G09

Voltage

ON

= 30µA

1

VON VOLTAGE (V)

2

3

3717 G11

VIN = 2.5V 4ms/DIV 3718 G09.eps
V

= 1.25V

OUT

LOAD = 0.2Ω
FIGURE 1 CIRCUIT

VIN = 2.5V 20µs/DIV 3718 G10.eps
V

OUT

LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT

On-Time vs Temperature On-Time vs I

300

I

= 30µA

ION

250

200

150

ON-TIME (ns)

100

50

0

–50

–25 0

TEMPERATURE (°C)

50 100 125

25 75

3717 G12

= 1.25V

ON

Current

sn3717 3717fs

4

UW

TEMPERATURE (°C)

–50

3.0

RUN/SS THRESHOLD (V)

3.5

4.0

4.5

5.0

–25 0 25 50

3717 G16

75 100 125

LATCHOFF ENABLE

LATCHOFF THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3717

INTVCC Load Regulation

0

–0.1

–0.2

(%)

CC

–0.3

∆INTV

–0.4

–0.5

10

0

INTVCC LOAD CURRENT (mA)

30

20

Undervoltage Lockout Threshold
vs Temperature

4.0

3.5

3.0

2.5

UNDERVOLTAGE LOCKOUT THRESHOLD (V)

2.0
–50

–25 0 25 50

TEMPERATURE (C)

75 100 125

RUN/SS Latchoff Thresholds
vs Temperature

3

2

PULL-DOWN CURRENT

1

0

FCB PIN CURRENT (µA)

–1

–2

40

50

3717 G14

–50 –25

PULL-UP CURRENT

50

25

0

TEMPERATURE (°C)

100

125

3717 G15

75

Maximum Current Sense Threshold
vs V

Voltage

RNG

300

250

200

150

100

50

MAXIMUM CURRENT SENSE THRESHOLD (mV)

3717 G17

0

0.50

1.00 1.25 1.50

0.75
V

(V)

RNG

1.75 2.00

3717 G18

RUN/SS Latchoff Thresholds
vs Temperature

Maximum Current Sense Threshold
vs RUN/SS Voltage, V

160

140

120

100

80

60

40

20

MAXIMUM CURRENT SENSE THRESHOLD (mV)

0

2.0

2.4

2.8 3.0 3.2 3.42.2

2.6
RUN/SS (V)

RNG

= 1V

3.6

3717 G19

MAXIMUM CURRENT SENSE THRESHOLD (mV)

Maximum Current Sense Threshold
vs Temperature, V

180

160

140

120

100

80

60

40

20

0

–50 130

–30 –10

10 30 50 90

TEMPERATURE (°C)

RNG

= 1V

70

110

3717 G20

Error Amplifier gm
vs Temperature

1.50

1.40

1.30

1.20

1.10

gm (ms)

1.00

0.90

0.80

0.70
–50 130

–30 –10

10 30 50 90

TEMPERATURE (°C)

70

110

3717 G21

sn3717 3717fs

5

LTC3717

U

UU

PI FU CTIO S

RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.

PGOOD (Pin 2): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.

V

(Pin 3): Sense Voltage Range Input. The voltage at

RNG

this pin is ten times the nominal sense voltage at maxi­mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.

I

(Pin 4): Current Control Threshold and Error Amplifier

TH

Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).

SGND (Pin 5): Signal Ground. All small-signal compo­nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.

ION (Pin 6): On-Time Current Input. Tie a resistor from V
to this pin to set the one-shot timer current and thereby set
the switching frequency.

VFB (Pin 7): Error Amplifier Feedback Input. This pin
connects to V
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than

1.5V on VFB. For higher output voltages, attach an external
resistor R2 (1/2 • R1 at V

V

(Pin 8): Positive Input of Internal Error Amplifier.

REF

This pin connects to an external reference and divides its
voltage to 1/3 V

and divides its voltage to 2/3 • V

OUT

) from V

REF

through precision internal resisters

REF

OUT

to VFB.

IN

FB

before it is applied to the positive input of the error
amplifier. Reference voltage for output voltage, power
good threshold, and short-circuit shutdown threshold. Do
not apply more than 3V on V
used, connect an external resistor (R1 ≥ 160k) from
voltage reference to V

EXTVCC (Pin 9): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTV
and shuts down the internal regulator so that controller
and gate drive power is drawn from EXTVCC. Do not exceed
7V at this pin and ensure that EXTVCC < VCC.

VCC (Pin 10): Bias Input Supply. 4V to 36V operating
range. Decouple this pin to PGND with an RC filter (1Ω,

0.1µF).
INTVCC (Pin 11): Internal 5V Regulator Output. The driver

and control circuits are powered from this voltage. De­couple this pin to power ground with a minimum of 4.7µF
low ESR tantalum or ceramic capacitor.

BG (Pin 12): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.

PGND (Pin 13): Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of C

SW (Pin 14): Switch Node. The (–) terminal of the boot­strap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to a diode voltage
drop above VIN.

TG (Pin 15): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim­posed on the switch node voltage SW.

BOOST (Pin 16): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
V

+ INTVCC.

IN

and the (–) terminal of CIN.

VCC

REF

.

. If higher voltages are

REF

CC

6

sn3717 3717fs

LTC3717

U

U

W

FU CTIO AL DIAGRA

R

ON

I

6

ON

0.7V

tON = (10pF)

1.4V

V

RNG

3

0.7V

I

I

ION

CMP

20k

+

–

×

R
SQ

+

I

REV

–

INTV

V

IN

V

BNGP

5V

REG

10

BOOST

16

TG

15

SW

14

INTV

11

BG

12

PGND

13

PGOOD

2

CC

+

C

IN

C

B

M1

L1

D

B

CC

V

OUT

+

C

C

VCC

M2

OUT

EXTV

9

4.7V

+

–

CC

FCNT

ON

SHDN

OV

CC

1.192V

SWITCH

LOGIC

5.7µA

1

240k

Q2

I

THB

Q1

Q5

SS

–

+

EA

–

+

V

REF

8

80k 40k

+

–

0.6V

C

I

4

C1

TH

R

C

RUN

SHDN

V

REF

4

1

UV

OV

1.2µA

RUN/SS

3

V

+

REF

10

–

+

11

V

–

REF

30

6V

C

SS

20k

40k

V

7

FB

5

SGND

3717 FD

sn3717 3717fs

7

LTC3717

OPERATIO

U

Main Control Loop

The LTC3717 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com­parator I
ating the next cycle. Inductor current is determined by
sensing the voltage between the PGND and SW pins using
the bottom MOSFET on-resistance . The voltage on the I
pin sets the comparator threshold corresponding to in­ductor valley current. The error amplifier EA adjusts this
ITH voltage by comparing 2/3 of the feedback signal V
from the output voltage with a reference equal to 1/3 of the
V

voltage. If the load current increases, it causes a drop

REF

in the feedback voltage relative to the reference. The I
voltage then rises until the average inductor current again
matches the load current. As a result in normal DDR
operation V

The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on­time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.

Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.

trips, restarting the one-shot timer and initi-

CMP

is equal to 1/2 of the V

OUT

voltage.

REF

TH

FB

TH

Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.

Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switch­ing, but with the ITH voltage clamped at approximately

0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re­charged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off. When the EXTV
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VCC. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
a high efficiency source connected to EXTVCC, such as an
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the VCC voltage is low and INTVCC drops below 3.4V,
undervoltage lockout circuitry prevents the power
switches from turning on.

CC

WUUU

APPLICATIO S I FOR ATIO

The basic LTC3717 application circuit is shown in
Figure 1. External component selection is primarily deter­mined by the maximum load current and begins with the
selection of the sense resistance and power MOSFET
switches. The LTC3717 uses the on-resistance of the syn­chronous power MOSFET for determining the inductor
current. The desired amount of ripple current and operating
frequency largely determines the inductor value. Finally, C
is selected for its ability to handle the large RMS current into
the converter and C
meet the output voltage ripple and transient specification.

is chosen with low enough ESR to

OUT

IN

8

Maximum Sense Voltage and V

Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and SW pins. The maximum sense voltage is set by the
voltage applied to the V
mately (0.13)V
sinking current. The current mode control loop will not
allow the inductor current valleys to exceed (0.13)V
R
practice, one should allow some margin for variations in

for sourcing and (0.17)V

SENSE

for sourcing current and (0.17)V

RNG

pin and is equal to approxi-

RNG

Pin

RNG

RNG/RSENSE

for

RNG

RNG

for sinking. In

sn3717 3717fs

/

WUUU

APPLICATIO S I FOR ATIO

LTC3717

the LTC3717 and external component values and a good
guide for selecting the sense resistance is:

V

R

SENSE

=

10•

RNG

I

()

OUT MAX

An external resistive divider from INTVCC can be used to set
the voltage of the V

pin between 0.5V and 2V resulting

RNG

in nominal sense voltages of 50mV to 200mV. Additionally,
the V

pin can be tied to SGND or INTVCC in which case

RNG

the nominal sense voltage defaults to 70mV or 140mV,
respectively. The maximum allowed sense voltage is about

1.3 times this nominal value for positive output current and

1.7 times the nominal value for negative output current.

Power MOSFET Selection

The LTC3717 requires two external N-channel power MOS­FETs, one for the top (main) switch and one for the bottom
(synchronous) switch. Important parameters for the power
MOSFETs are the breakdown voltage V
voltage V
capacitance C

, on-resistance R

(GS)TH

and maximum current I

RSS

(BR)DSS

, reverse transfer

DS(ON)

, threshold

DS(MAX)

.

The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3717 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.

When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on­resistance. MOSFET on-resistance is typically specified
with a maximum value R

DS(ON)(MAX)

at 25°C. In this case,

additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:

R

R

DS ON MAX

()( )

=

SENSE

ρ

T

The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.

The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and

the load current. During LTC3717’s normal operation, the
duty cycles for the MOSFETs are:

V

D

D

TOP

BOT

OUT

=

V

IN

VV

–

IN OUT

=

V

IN

The resulting power dissipation in the MOSFETs at maxi­mum output current are:

P

P

TOP

BOT

= D

TOP IOUT(MAX)

+ k V

IN

= D

BOT IOUT(MAX)

2

I

2

ρ

T(TOP) RDS(ON)(MAX)

OUT(MAX) CRSS

2

ρ

T(BOT) RDS(ON)(MAX)

f

Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.

2.0

1.5

1.0

0.5

NORMALIZED ON-RESISTANCE

T

ρ

0

–50

JUNCTION TEMPERATURE (°C)

Figure 2. R

0

50

vs. Temperature

DS(ON)

100

150

3717 F02

Operating Frequency

The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.

The operating frequency of LTC3717 applications is deter­mined implicitly by the one-shot timer that controls the

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LTC3717

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APPLICATIO S I FOR ATIO

on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin according to:

ON

07

=

I

ION

pF

()

10

t

V

(. )

Tying a resistor RON from VIN to the ION pin yields an on­time inversely proportional to VIN. For a step-down con­verter, this results in approximately constant frequency
operation as the input supply varies:

V

f

=

(. ) ( )

OUT

VR pF

07 10

ON

H

[]

Z

Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
A more exact equation taking in account the 0.7V drop on
the ION pin is:

VV V

(–.)

f

OUT IN

=

V R pF V

(. ) ( )

07 10

To correct for this error, an additional resistor R

07

ON IN

H

[]

Z

ON2

connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.

V

R

ON ON2

07=.

5

R

V

Inductor Selection

Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:



∆=

I

L






V



OUT OUT

fL

V

−

1














V

IN

that is about 40% of I

OUT(MAX)

. The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:



=



fI

∆



V

LMAX

L





OUT





() ()

V

−

1



V



IN MAX

OUT






Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af­ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ® cores. A variety of inductors designed for high
current, low voltage applications are available from manu­facturers such as Sumida, Panasonic, Coiltronics, Coilcraft
and Toko.

Schottky Diode D1 Selection

The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to
be effective, the inductance between it and the bottom
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can be
omitted if the efficiency loss is tolerable.

CIN and C

Selection

OUT

The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.

Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.

A reasonable starting point is to choose a ripple current

10

V

II

≅

RMS OUT MAX

()

OUT

V

This formula has a maximum at VIN = 2V
I

RMS

= I

OUT(MAX)

/2. This simple worst-case condition is

IN

V

V

IN

OUT

–1

OUT

, where

commonly used for design because even significant
deviations do not offer much relief. Note that ripple

Kool Mµ is a registered trademark of Magnetics, Inc.

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APPLICATIO S I FOR ATIO

LTC3717

current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.

The selection of C

is primarily determined by the ESR

OUT

required to minimize voltage ripple and load step
transients. The output ripple ∆V

is approximately

OUT

bounded by:

∆≤∆ +

V I ESR

OUT L






fC

8

1

OUT






Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi­cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom­mended to reduce the effect of their lead inductance.

Top MOSFET Driver Supply (CB, DB)

An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.

This capacitor is charged through diode DB from INTV

CC

when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1µF to 0.47µF, X5R or
X7R dielectric capacitor is adequate.

Fault Condition: Current Limit

The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3717, the maximum sense voltage is controlled by
the voltage on the V

pin. With valley current control,

RNG

the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limits are:

V

SNS MAX

I POSITIVE

LIMIT

I NEGATIVE

LIMIT

=+∆

=∆

()

R

DS ON T

()

V

SNS MIN

()

R

DS ON T

()

ρ12

–

ρ12

I

L

I

L

The current limit value should be checked to ensure that
I

LIMIT(MIN)

> I

OUT(MAX)

. The minimum value of current limit
generally occurs with the largest VIN at the highest ambi­ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I

which heats

LIMIT

the MOSFET switches.
Caution should be used when setting the current limit

based upon the R

of the MOSFETs. The maximum

DS(ON)

current limit is determined by the minimum MOSFET on­resistance. Data sheets typically specify nominal and
maximum values for R
reasonable assumption is that the minimum R

, but not a minimum. A

DS(ON)

DS(ON)

lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.

Minimum Off-time and Dropout Operation

The minimum off-time t

OFF(MIN)

is the smallest amount of

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APPLICATIO S I FOR ATIO

time that the LTC3717 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 300ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + t

OFF(MIN)

). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:

tt

+

VV

IN MIN OUT

=

()

ON OFF MIN

t

ON

()

INTVCC Regulator

An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3717. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applica­tions using large MOSFETs with a high input voltage and
high frequency of operation may cause the LTC3717 to
exceed its maximum junction temperature rating or RMS
current rating. Most of the supply current drives the
MOSFET gates unless an external EXTVCC source is used.
In continuous mode operation, this current is I
f(Q

g(TOP)

+ Q

). The junction temperature can be

g(BOT)

GATECHG

=

estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3717CGN
is limited to less than 14mA from a 30V supply:

TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C

1. EXTVCC grounded. INTV

is always powered from the

CC

internal 5V regulator.

2. EXTVCC connected to an external supply. A high effi­ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.

3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.

External Gate Drive Buffers

The LTC3717 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 4
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate, and benefit from an
increased EXTVCC voltage of about 6V.

BOOST

Q1
FMMT619

10Ω 10Ω

TG

SW

Figure 4. Optional External Gate Driver

Q2
FMMT720

GATE
OF M1

BG

INTV

PGND

CC

Q3
FMMT619

Q4
FMMT720

GATE
OF M2

3717 F04

For larger currents, consider using an external supply with
the EXTVCC pin.

EXTVCC Connection

The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTV

CC

pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTV

CC

pin to INTVCC. INTVCC power is supplied from EXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
the EXTVCC pin and ensure that EXTVCC≤VCC. The follow­ing list summarizes the possible connections for EXTVCC:

12

Soft-Start and Latchoff with the RUN/SS Pin

The RUN/SS pin provides a means to shut down the
LTC3717 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3717 into a low quiescent current shutdown (IQ <
30µA). Releasing the pin allows an internal 1.2µA current
source to charge up the external timing capacitor CSS. If
RUN/SS has been pulled all the way to ground, there is a
delay before starting of about:

15

.

t

DELAY SS SS

=

12

.

V

CsFC

A

µ

13

./

=µ

()

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APPLICATIO S I FOR ATIO

When the voltage on RUN/SS reaches 1.5V, the LTC3717
begins operating with a clamp on ITH of approximately

0.9V. As the RUN/SS voltage rises to 3V, the clamp on I
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF. The pin can be driven from logic as
shown in Figure 5. Diode D1 reduces the start delay while
allowing CSS to charge up slowly for the soft-start func­tion.

After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con­troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.

The overcurrent protection timer requires that the soft­start timing capacitor CSS be made large enough to guar­antee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:

CSS > C

OUT VOUT RSENSE

(10–4 [F/V s])

Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or

desired. The feature can be overridden by adding a pull­up current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of CSS during a
fault and also shortens the soft-start period. Using a
resistor to VIN as shown in Figure 5a is simple, but slightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 5b eliminates the additional
shutdown current, but requires a diode to isolate CSS . Any
pull-up network must be able to pull RUN/SS above the

4.5V maximum threshold that arms the latchoff circuit
and overcome the 4µA maximum discharge current.

TH

LTC3717

INTV

CC

V

3.3V OR 5V RUN/SS

Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated

IN

RSS*

D1

C

SS

(5a) (5b)

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3717 circuits:

1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if R

= 0.01Ω and RL = 0.005Ω, the

DS(ON)

loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.

2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci­tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:

Transition Loss ≅ (1.7A–1) V

IN

2

3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply­ing INTVCC current through the EXTVCC pin from a high

RSS*

RUN/SS

D2*

2N7002

*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF

DS(ON)

I

OUT CRSS

C

3717 F06

, then the

f

SS

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LTC3717

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APPLICATIO S I FOR ATIO

efficiency source, such as an output derived boost net­work or alternate supply if available.

4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.

Other losses, including C

ESR loss, Schottky diode D1

OUT

conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.

When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.

Checking Transient Response

The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ∆I
resistance of C
discharge C

(ESR), where ESR is the effective series

LOAD

OUT

generating a feedback error signal used by

OUT

the regulator to return V
During this recovery time, V

immediately shifts by an amount

OUT

. ∆I

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

overshoot or ringing that would indicate a stability prob­lem. The ITH pin external components shown in Figure 6
will provide adequate compensation for most applica­tions. For a detailed explanation of switching control loop
theory see Application Note 76.

Design Example

As a design example, take a supply with the following
specifications: VIN = V

1.25V ±5%, I

OUT(MAX)

the timing resistor with VON = V

VV V

125 25 07

R

==Ω

ON

.(.–.)

V kHz pF V

0 7 250 10 2 5

( . )( )( ) .

= 2.5V, V

REF

EXTVCC

= 5V, V

OUT

=

= 10A, f = 250kHz. First, calculate

:

OUT

k

514

and choose the inductor for about 40% ripple current at
the maximum VIN:

125

L

250 0 4 10

( )( . )( )

.

kHz A

V



1





125

.

25

.



V

=µ

063



V



H=−

.

Selecting a standard value of 0.68µH results in a maximum
ripple current of:

125

.

∆=

L

250 0 68

()(.)

V

kHz H



1

–



µ



125

.

25

.



V

37

.

=I



V



A

Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R

= 0.0083Ω (NOM) 0.010Ω (MAX),

DS(ON)

θJA = 40°C/W) yields a nominal sense voltage of:

V

SNS(NOM)

Tying V

= (10A)(1.3)(0.0083Ω) = 108mV

to 1.1V will set the current sense voltage range

RNG

for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ

mV

I

LIMIT

143

≥

14 0010

(.)(. )

= 1.4:

110°C

1

+=

3 7 12 1

(. ) .

Ω

2

AA

and double check the assumed TJ in the MOSFET:

VV

25 125

P

BOT

.–.

=Ω=

25

.

(.)(.)(. ) .

V

2

AW

12 1 1 4 0 010 1 02

TJ = 70°C + (1.02W)(40°C/W) = 111°C

Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.

The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.

CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of

0.013Ω to minimize output voltage changes due to induc­tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.

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14

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APPLICATIO S I FOR ATIO

LTC3717

(This is typically the case, since VIN is derived from
another DC/DC converter.) The ripple voltage will be only:

∆V

OUT(RIPPLE)

= ∆I

L(MAX)

(ESR)

= (4A) (0.013Ω) = 52mV

However, a 0A to 10A load step will cause an output
change of up to:

∆V

OUT(STEP)

= ∆I

(ESR) = (10A) (0.013Ω) = 130mV

LOAD

An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.

PC Board Layout Checklist

When laying out a PC board follow one of the two sug­gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.

• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.

• Place CIN, C

, MOSFETs, D1 and inductor all in one

OUT

compact area. It may help to have some components on
the bottom side of the board.

• Place LTC3717 chip with pins 9 to 16 facing the power
components. Keep the components connected to pins
1 to 8 close to LTC3717 (noise sensitive components).

•

Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3717.
Use several bigger vias for power components.

• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.

• Use planes for VIN and V

to maintain good voltage

OUT

filtering and to keep power losses low.

C

SS

0.1µF

R3

R4

11k

39k

C

C1

R

C

470pF

20k

C

C2

100pF

C

0.01µF

ON

R

ON

511k

CIN, C
L1: SUMIDA CEP125-0R68MC-H

: CORNELL DUBILIER ESRE181E04B

OUT1-2

R

PG

100k

(OPT)

0.1µF

1

2

3

4

5

6

7

8

LTC3717

RUN/SS

PGOOD

V

RNG

I

TH

SGND

I

ON

V

FB

V

REF

D

B

CMDSH-3

C

B

0.22µF

C

VCC

+

4.7µF

R
1Ω

C

F

0.1µF

M1
Si4874

M2
Si4874

F

V

5V

EXT

10Ω

BOOST

PGND

INTV

EXTV

SW

V

TG

BG

16

15

14

13

12

11

CC

10

CC

9

CC

Figure 6. Design Example: 1.25V/±10A at 250kHz

D2
B320A

L1

0.68µH
D1

B320A

= 2.5V

V

IN

C

IN

22µF

6.3V
X7R

C

OUT1-2

+

270µF
2V
×2

3717 F06a

C

+

IN

180µF
4V
×2

V

OUT

1.25V
±10A

C

OUT3

22µF

6.3V
X7R

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WUUU

APPLICATIO S I FOR ATIO

• Flood all unused areas on all layers with copper. Flood­ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (VIN, V

, GND or to any other DC rail in

OUT

your system).

When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera­tion of the controller. These items are also illustrated in
Figure 7.

• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.

• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.

C

SS

1

LTC3717

RUN/SS

BOOST

16

C

B

• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC cur­rent.

• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.

• Connect the INTVCC decoupling capacitor C

VCC

closely

to the INTVCC and PGND pins.

• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.

• Connect the VCC pin decoupling capacitor CF closely to
the VCC and PGND pins.

L

2

PGOOD

3

V

C

C1

R

C

C

ION

C

FB

BOLD LINES INDICATE HIGH CURRENT PATHS

RNG

4

I

TH

C

C2

5

SGND

6

I

ON

7

V

FB

8

V

REF

R

ON

PGND

INTV

EXTV

15

TG

D

B

C

VCC

M2

+

C

F

R

F

C

OUT

V

SW

BG

14

13

12

11

CC

10

CC

9

CC

Figure 7. LTC3717 Layout Diagram

M1

D2

D1

C

IN

+

V

IN

–
–

V

OUT

+

3717F07

16

sn3717 3717fs

TYPICAL APPLICATIO S

C

SS

0.1µF

R

R

R1

R2

11k

39k

C

C1

R

C

680pF

20k

C

C2

100pF

0.01µF

C

ON

3V

V

REF

10µF

6.3V
X7R

C

OUT

1

RUN/SS

R

PG

100k

2

PGOOD

3

V

4

I

5

SGND

6

I

7

V

8

V

R

ON

510k

: CORNELL DUBILIER ESRE271M02B

U

1.5V/±10A at 300kHz from 5V to 28V Input

D

B

CMDSH-3

C

B

0.22µF

C

VCC

4.7µF

RNG

TH

ON

FB

REF

LTC3717

BOOST

PGND

INTV

EXTV

SW

BG

V

16

15

TG

14

13

12

11

CC

10

CC

9

CC

M1
IRF7811W

M2
IRF7822

B320A

1.2µH

D1
B320A

LTC3717

V

IN

5V TO 28V

C

IN

10µF
35V

V

×3

OUT

L1

+

3717 TA01

C

OUT

270µF
2V
×2

1.5V
±10A

sn3717 3717fs

17

LTC3717

TYPICAL APPLICATIO S

C

SS

0.1µF

C

C1

R

470pF

R2

1M

C

20k

C

C2

100pF

0.01µF

C

ON

R

510k

C2

2200pF

CIN: TAIYO YUDEN TMK432BJ106MM

: SANYO, OS-CON 16SP270

C

OUT1

: TAIYO YUDEN JMK316BJ106ML

C

OUT2

L1: TOKO 919AS-1R8N

1

R

PG

100k

2

3

4

5

6

7

8

ON

U

High Voltage Half (VIN) Power Supply

D

B

LTC3717

RUN/SS

PGOOD

V

RNG

I

TH

SGND

I

ON

V

FB

V

REF

R1 2M

BOOST

PGND

INTV

EXTV

V

SW

BG

16

15

TG

14

13

12

11

CC

10

CC

9

CC

CMDSH-3

C

B

0.22µF

C

VCC

4.7µF

1Ω

C

F

0.1µF

R

F

M1
FDS6680S

1.8µH

M2
FDS6680S

L1

3717 TA02

V

IN

C

IN

10µF
25V
×2

+

C

OUT1

270µF
16V

5V TO 25V

V
VIN/2
±6A

C

OUT2

10µF
15V

OUT

18

sn3717 3717fs

PACKAGE DESCRIPTIO

LTC3717

U

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

INCHES

(MILLIMETERS)

.150 – .165

.0250 TYP.0165 ±.0015

.015

(0.38 ± 0.10)

0° – 8° TYP

± .004

× 45°

.229 – .244

(5.817 – 6.198)

.053 – .068

(1.351 – 1.727)

.008 – .012

(0.203 – 0.305)

16

15

12

.189 – .196*

(4.801 – 4.978)

14

12 11 10

13

5

4

3

678

.0250

(0.635)

BSC

.009

(0.229)

9

.150 – .157**
(3.810 – 3.988)

.004 – .0098

(0.102 – 0.249)

GN16 (SSOP) 0502

REF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

sn3717 3717fs

19

LTC3717

TYPICAL APPLICATIO

C

SS

0.1µF

C

C1

R

470pF

C

33k

C

C2

100pF

C

0.01µF

ON,

R

ON

92k

R

100k

U

Typical Application 1.25V/±3A at 1.4MHz

D

LTC3717

1

RUN/SS

PG

2

PGOOD

3

V

RNG

4

I

TH

5

SGND

6

I

ON

7

V

FB

8

V

REF

BOOST

PGND

INTV

EXTV

SW

V

TG

BG

16

15

14

13

12

11

CC

10

CC

9

CC

CMDSH-3

C

B

0.22µF

C

VCC

4.7µF

5V

1µF

B

V

IN

M1
1/2 Si9802

M2
1/2 Si9802

+

L1

0.7µH

+

C

IN

120µF
4V

C

OUT

120µF
4V

2.5V

V

OUT

1.25V
±3A

3717 TA03

CIN, C

: CORNELL DUBILIER ESRD121M04B

OUT

L1: TOKO A921CY-0R7M

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Linear Technology Corporation

20

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

TM

Current Mode Synchronous Step-Down Controller 97% Efficiency; No Sense Resistor; 99% Duty Cycle

SENSE

3.5V ≤ V

3.5V ≤ V

0.8V ≤ V

Step-Down Synchronous Controllers 4V ≤ VIN ≤ 36V, True Current Mode Control,

SENSE

≤ 36V

IN

≤ 2V

OUT

≤ 36V

IN

≤ 2V; 3.5V ≤ VIN ≤ 36V

OUT

≤ VIN, Synchronizable to 750kHz

OUT

OUT

2% to 90% Duty Cycle

LT/TP 0103 2K • PRINTED IN USA

●

www.linear.com

 LINEAR TECHNOL OGY CORPORATION 2001

≤ 3.5V

sn3717 3717fs