LINEAR TECHNOLOGY LTC3709 Technical data

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LTC3709

FEATURES

■

PolyPhase® Valley Current Mode Controller

■

Synchronizable to an External Clock with PLL

■

Coincident or Ratiometric Tracking

■

Sense Resistor Optional

■

2% to 90% Duty Cycle at 200kHz

■

ON(MIN)

■

True Remote Sensing Differential Amplifier

■

High Efficiency at Both Light and Heavy Loads

■

Power Good Output Voltage Monitor

■

0.6V ±1% Reference

■

Adjustable Current Limit

■

Programmable Soft-Start and Operating Frequency

■

Output Overvoltage Protection

■

Optional Short-Circuit Shutdown Timer

■

Available in 32-Lead (5mm × 5mm) QFN and 36-Lead

< 100ns

SSOP Packages

APPLICATIO S

■

Notebook Computers

■

Power Supply for DSP, ASIC, Graphic Processors

Fast 2-Phase, No R

SENSE

Synchronous DC/DC Controller

with Tracking/Sequencing

DESCRIPTIO

The LTC®3709 is a single output, dual phase, synchronous step-down switching regulator. The controller uses a constant on-time, valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. An internal phase-lock loop allows the LTC3709 to be synchronized to an external clock.

A TRACK pin is provided for tracking or sequencing the output voltage among several LTC3709 chips or an LTC3709 and other DC/DC regulators. Soft-start is accomplished using an external timing capacitor.

Fault protection is provided by an output overvoltage comparator and an optional short-circuit shutdown timer. The current limit level is user programmable. A wide supply range allows voltages as high as 31V to step down as low as 0.6V.

, LTC and LT are registered trademarks of Linear Technology Corporation. No R a trademark of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6476589, 6144194, 5847554, 6177678, 6304066, 6580258, 6674274, 6462525, 6593724.

SENSE

TYPICAL APPLICATIO

High Efficiency Dual Phase 1.5V/30A Step-Down Converter

47.5k

10k

100nF

680pF

4.7µF

0.1µF

3.32k

1µF

100k

20k

10k

15k

10Ω

VCCDRVCCI

TRACK TG1 V

RNG

FCB

BOOST1

SENSE1

PGOOD

RUN/SS

EXTLPF

SENSE1

INTLPF

LTC3709

SGND

BOOST2

DIFFOUT

SENSE2

–

SENSE2

SW1

BG1

PGND1

TG2

SW2

BG2

PGND2

324k

–

0.22µF

HAT2168H

HAT2165H

HAT2168H

HAT2165H

10µF 35V ×3

1.22µH

4.5V TO 28V

1.5V 30A

330µF

2.5V ×4

3709 TA01a

OUT

Efficiency and Power Loss

100

VIN = 12V

EFFICIENCY (%)

0.01 1 10 100

EFFICIENCY

POWER LOSS

0.1 LOAD CURRENT (A)

3709 TA01b

POWER LOSS (W)

3709fa

LTC3709

ABSOLUTE AXI U RATI GS

Input Supply Voltage (VCC, DRVCC) ............ 7V to – 0.3V

Boosted Topside Driver Supply Voltage

(BOOST1, BOOST2) .................................. 37V to –0.3V

Switch Voltage (SW1, 2) ............................. 31V to – 1V

SENSE1 SENSE1 I

, SENSE2+ Voltages....................... 31V to –1V

–

, SENSE2– Voltages.................... 10V to – 0.3V

Voltage ............................................... 31V to –0.3V

(BOOST – SW) Voltages ..............................7V to – 0.3V

RUN/SS, PGOOD Voltages .......................... 7V to – 0.3V

TRACK Voltage ............................................7V to –0.3V

Voltage ................................. VCC + 0.3V to –0.3V

RNG

PACKAGE/ORDER I FOR ATIO

TRACK

SGND

DIFFOUT

TOP VIEW

RNG

FCB

IONPGOOD

BOOST1

32 31 30 29 28 27 26 25

1RUN/SS

–

9 10 11 12

32-LEAD (5mm × 5mm) PLASTIC QFN

EXPOSED PAD IS SGND (PIN 33)

MUST BE SOLDERED TO PCB T

JMAX

13 14 15 16

INTLPF

EXTLPF

= 125°C, θJA = 34°C/ W

BOOST2

UH PACKAGE

TG1

TG2

SW1

SW2

SENSE1

SENSE2

SENSE1

PGND1

BG1

DRV

BG2

PGND2

SENSE2

–

(Note 1)

ITH Voltage ............................................... 2.7V to –0.3V

Voltage .............................................. 2.7V to – 0.3V

INTLPF, EXTLPF Voltages ........................ 2.7V to –0.3V

–

, V

Voltages ................................... 7V to – 0.3V

FCB Voltage ................................................ 7V to – 0.3V

Operating Temperature Range (Note 4) .. –40°C to 85°C

Junction Temperature (Note 2)............................ 125°C

Storage Temperature Range

UH Package ..................................... – 65°C to 125°C

G Package ....................................... – 65°C to 150°C

TOP VIEW

PGOOD

FCB

RNG

RUN/SS

TRACK

SGND

–

DIFFOUT

EXTLPF

INTLPF

36-LEAD PLASTIC SSOP

JMAX

G PACKAGE

= 125°C, θJA = 95°C/ W

BOOST1

TG1

SW1

SENSE1

PGND1

BG1

DRV

BG2

PGND2

SENSE2

SW2

TG2

BOOST2

–

ORDER PART NUMBER

LTC3709EUH

UH PART MARKING

3709

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ORDER PART NUMBER

LTC3709EG

3709fa

LTC3709

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. VCC = DRVCC = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

Input DC Supply Current Normal 2.4 3 mA

∆V

FB(LINEREG)

∆V

FB(LOADREG)

m(EA)

ON(MIN)

OFF(MIN)

SENSE(MAX)

SENSE(MIN)

∆V

FB(OV)

∆V

FB(UV)

RUN/SS(ON)

RUN/SS(LE)

RUN/SS(LT)

RUN/SS(C)

RUN/SS(D)

Shutdown 25 65 µA FB Pin Input Current ITH = 1.2V (Note 3) – 35 – 60 nA

Feedback Voltage ITH = 1.2V (Note 3)

●

0.594 0.600 0.606 V

Feedback Voltage Line Regulation VCC = 4.5V to 6.5V (Note 3) 0.02 %/V

Feedback Voltage Load Regulation ITH = 0.5V to 2V (Note 3) –0.12 – 0.2 %

Error Amplifier Transconductance ITH = 1.2V (Note 3) 1.3 1.45 1.6 mS

On-Time ION = 180µA, V

ION = 90µA, V

= 0V 90 116 140 ns

FCB

= 0V 180 233 280 ns

FCB

Minimum On-Time ION = 540µA 45 100 ns

Minimum Off-Time ION = 90µA 250 350 ns

Maximum Current Sense Threshold V

Minimum Current Sense Threshold V

= 1V 124 144 166 mV

RNG

= 0V 86 101 119 mV

RNG

= V

RNG

= 1V – 60 mV

RNG

= 0V – 40 mV

RNG

= V

RNG

177 202 234 mV

–80 mV

Overvoltage Fault Threshold 8.5 10 12.5 %

Undervoltage Fault Threshold –8.5 –10 –12.5 %

RUN Pin Start Threshold

●

0.8 1.4 2 V

RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising 3 V

RUN Pin Latchoff Threshold RUN/SS Pin Falling 2.3 V

Soft-Start Charge Current –0.5 –1.2 –3 µA

Soft-Start Discharge Current 0.8 2 4 µA

UVLO Undervoltage Lockout VCC Falling 3.9 4.2 V

UVLO

TG R

BG R

(HYS)

DOWN

Undervoltage Lockout Hysteresis Measured at VCC Pin 0.2 0.35 V TG Driver Pull-Up On-Resistance TG High (Note 5) 2 Ω TG Driver Pull-Down On-Resistance TG Low (Note 5) 1.5 Ω BG Driver Pull-Up On-Resistance BG High (Note 5) 3 Ω BG Driver Pull-Down On-Resistance BG Low (Note 5) 1.5 Ω

Tracking

TRACK

FB(TRACK)

TRACK Pin Input Current ITH = 1.2V, V Feedback Voltage at Tracking V

= 0.1V, ITH = 1.2V (Note 3) 90 100 110 mV

TRACK

= 0.3V, ITH = 1.2V (Note 3) 290 300 310 mV

TRACK

= 0.5V, ITH = 1.2V (Note 3) 490 500 510 mV

TRACK

= 0.2V (Note 3) –100 –150 nA

TRACK

PGOOD Output

∆V ∆V

FBH

FBL

PGOOD Upper Threshold VFB Rising 8.5 10 12.5 %

PGOOD Lower Threshold VFB Falling –8.5 –10 –12.5 %

PG Delay PGOOD Delay VFB Rising 100 µs ∆V

FB(HYS)

PGOOD

PGL

PGOOD Hysteresis VFB Returning 3.5 % PGOOD Leakage Current V

PGOOD Low Voltage I

= 7V ±1 µA

PGOOD

= 5mA 0.2 0.4 V

PGOOD

3709fa

LTC3709

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. VCC = DRVCC = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Phase-Lock Loop

INTPLL_SOURCE

INTPLL_SINK

EXTPLL_SOURCE

EXTPLL_SINK

FCB(DC)

FCB(AC)

ON(PLL)1

ON(PLL)2

Internal PLL Sourcing Current 20 µA

Internal PLL Sinking Current –20 µA

External PLL Sourcing Current 20 µA

External PLL Sinking Current –20 µA Forced Continuous Threshold Measured with a DC Voltage at FCB Pin 1.9 2.1 2.3 V Clock Input Threshold Measured with a AC Pulse at FCB Pin 1 1.5 2 V t

Modulation Range by External PLL

ON1

Up Modulation I Down Modulation I

Modulation Range by Internal PLL

ON2

Up Modulation I Down Modulation I

= 180µA, V

ON1

= 180µA, V

ON1

= 180µA, V

ON2

= 180µA, V

ON2

= 1.8V 186 233 ns

EXTPLL

= 0.6V 58 80 ns

EXTPLL

= 1.8V 186 233 ns

INTPLL

= 0.6V 58 80 ns

INTPLL

Differential Amplifier A

Differential Gain 0.995 1.000 1.005 V/V Input Offset Voltage IN+ = IN

–

= 1.2V, I

= 1mA, 0.5 7 mV

OUT

Input Referred; Gain = 1 CM Common Mode Input Voltage Range I CMRR Common Mode Rejection Ratio 0V < IN

= 1mA 0 5 V

OUT

–

= IN

< 5V, I

= 1mA, 45 70 dB

OUT

Input Referred I

GBP Gain Bandwidth Product I

Output Current 10 40 mA

= 1mA 2 MHz

OUT

SR Slew Rate RL = 2k 5 V/µs V

O(MAX)

Maximum High Output Voltage I

= 1mA V

OUT

– 1.2 V

– 0.8 V

Input Resistance Measured at IN+ Pin 80 kΩ

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: T dissipation P

is calculated from the ambient temperature TA and power

as follows:

LTC3709EUH: T

= TA + (PD • 34°C/W)

LTC3709EG: TJ = TA + (PD • 95°C/W)

Note 3: The LTC3709 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (I

Note 4: The LTC3709E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.

Note 5: R

limit is guaranteed by design and/or correlation to static

DS(ON)

test.

3709fa

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3709

RUN/SS

5V/DIV

OUT

1V/DIV

10A/DIV

LOAD

3A-18A

OUT

50mV/DIV

SW1

20V/DIV

SW2

20V/DIV

Start-Up

1ms/DIV

3709 G01

Transient Response (CCM) Efficiency vs Load Current

50mV/DIV

20µs/DIV

3709 G04

Continuous Current Mode (CCM) Discontinuous Current Mode (DCM)

SW1

5V/DIV

SW2

5V/DIV

2µs/DIV

3709 G02

SW1

5V/DIV

SW2

1V/DIV

10µs/DIV

Transient Response (DCM)

100

LOAD

3A-18A

OUT

SW1

20V/DIV

SW2

20V/DIV

20µs/DIV

3709 G05

VIN = 12V

= 1.5V

OUT

f = 220kHz

EFFICIENCY (%)

10 1000 10000 100000

100

LOAD (mA)

3709 G03

3709 G06

Power Loss vs Load Current Quiescent Current at VCC = 5VEfficiency vs V

VIN = 12V

= 1.5V

OUT

f = 220kHz

0.1

POWER LOSS (W)

0.01

0.001 10 1000 10000 100000

100

LOAD CURRENT (mA)

3709 G07

100

OUT

LOAD

f = 220kHz

EFFICIENCY (%)

= 1.5V

= 10A

VIN (V)

3.0

2.8

2.6

2.4

QUIESCENT CURRENT (mA)

2.2

2.0

3709 G08

–40 –20

TEMPERATURE (°C)

3709 G09

3709fa

LTC3709

TEMPERATURE (°C)

–40 –20

EA LOAD REGULATION (%)

0.1

0.4

3709 G12

0.3

0.2

TEMPERATURE (°C)

–40 –20

2.0

ARMED THRESHOLD (V)

2.5

4.0

3709 G15

3.5

3.0

TYPICAL PERFOR A CE CHARACTERISTICS

Shutdown Current at VCC = 5V Error Amplifier g

SHUTDOWN CURRENT (µA)

–40 –20

TEMPERATURE (°C)

3709 G10

1.6

1.5

(mS)

1.4

EA g

1.3

1.2 –40 –20

TEMPERATURE (°C)

3709 G11

EA Load Regulation

VFB Pin Input Current RUN/SS Threshold Armed Threshold

–20

–25

–30

–35

–40

PIN INPUT CURRENT (nA)

–45

1.8

1.6

1.4

1.2

RUN/SS THRESHOLD (V)

1.0

–50

–40 –20

UVLO Threshold On-Time vs ION Current

4.5

4.3

4.1

3.9

UVLO THRESHOLD (V)

3.7

3.5 –40 –20

TEMPERATURE (°C)

0.8

3709 G13

–40 –20

TEMPERATURE (°C)

3709 G14

Current Sense Threshold vs I

Voltage

10000

1000

ON-TIME (ns)

100

3709 G16

100 1000

ION CURRENT (µA)

3709 G17

300

250

200

150

100

–50

CURRENT SENSE THRESHOLD (mV)

–100

–150

0.6

RNG

= 1V

RNG

= 0V

RNG

1.2

ITH VOLTAGE (V)

= V

= 2V

RNG

= 0.5V

RNG

1.8

2.4

3709 G18

3709fa

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3709

Maximum Current Sense Threshold Voltage vs V

350

300

250

200

150

100

THRESHOLD VOLTAGE (mV)

MAXIMUM CURRENT SENSE

0.5

PI FU CTIO S

0.8 1.1 1.4 2.0 V

(QFN/SSOP)

RNG

1.7

(V)

3709 G19

RUN/SS (Pin 1/Pin 6): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.5s/µF) and the time delay for overcurrent latch-off (see Applications Information). Forcing this pin below 1.4V shuts down the device.

(Pin 2/Pin 7): Error Amplifier Compensation Point. The

current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current).

(Pin 3/Pin 8): Error Amplifier Feedback Input. This pin

connects to the error amplifier input. It can be used to attach additional compensation components if desired.

TRACK (Pin 4/Pin 9): Tie the TRACK pin to a resistive divider connected to the output of another LTC3709 for either coincident or ratiometric output tracking (see Applications Information). To disable this feature, tie the pin to

Do Not Float this pin

Minimum Current Sense Threshold Voltage vs V

–20

–40

–60

–80

–100

THRESHOLD VOLTAGE (mV)

MINIMUM CURRENT SENSE

–120

–140

0.8 1.1 1.4 2.0

0.5 V

RNG

1.7

(V)

3709 G20

SGND (Pins 5, 6, 33/Pins 10, 11): Signal Ground. All small-signal components such as C

and compensation

components should connect to this ground and eventually connect to PGND at one point. The Exposed Pad of the QFN package must be soldered to PCB ground.

–

(Pin 7/Pin 12): The (–) Input to the Differential

Amplifer.

DIFFOUT (Pin 8/Pin 13): The Output of the Differential Amplifier.

(Pin 9/Pin 14): The (+) Input to the Differential

Amplifier.

EXTLPF (Pin 10/Pin 15): Filter Connection for the PLL. This PLL is used to synchronize the LTC3709 with an external clock.

INTLPF (Pin 11/Pin 16): Filter Connection for the PLL. This PLL is use to phase shift the second channel to the first channel by 180°.

3709fa

LTC3709

PI FU CTIO S

(QFN/SSOP)

NC (Pin 12/Pins 1, 17, 18, 19, 20): No Connect.

(Pin 17/Pin 25): Main Input Supply. Decouple this pin

to SGND with an RC filter (1Ω, 0.1µF).

DRV

(Pin 21/Pin 29): Driver Supply. Provides supply to

the driver for the bottom gate. Also used for charging the bootstrap capacitor.

BG1, BG2 (Pins 22, 20/Pins 30, 28): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRV

PGND1, PGND2 (Pins 23, 19/Pins 31, 27): Power Ground. Connect this pin closely to the source of the bottom Nchannel MOSFET, the (–) terminal of C minal of C

SENSE1

–

, SENSE2– (Pins 24, 18/Pins 32, 26): Current

and the (–) ter-

DRVCC

Sense Comparator Input. The (–) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET.

SENSE1

, SENSE2+ (Pins 25, 16/Pins 33, 24): Current

Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information).

TG1, TG2 (Pins 27, 14/Pins 35, 22): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to DRV

superimposed on the switch node voltage

SW.

BOOST1, BOOST2 (Pins 28, 13/Pins 36, 21): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor C voltage drop below DRV

connects here. This pin swings from a diode

up to V

+ DRVCC.

PGOOD (Pin 29/Pin 2): Power Good Output. Open-drain logic output that is pulled to ground when output voltage is not within ±10% of the regulation point. The output voltage must be out of regulation for at least 100µs before the power good output is pulled to ground.

(Pin 30/Pin 3): On-Time Current Input. Tie a resistor

from V

to this pin to set the one-shot timer current and

thereby set the switching frequency.

FCB (Pin 31/Pin 4): Forced Continuous and External Clock Input. Tie this pin to ground to force continuous synchronous operation or to V

to enable discontinuous mode

operation at light load. Feeding an external clock signal into this pin will synchronize the LTC3709 to the external clock and enable forced continuous mode.

SW1, SW2 (Pins 26, 15/Pins 34, 23): Switch Node. The (–) terminal of the bootstrap capacitor C

connects here.

This pin swings from a Schottky diode voltage drop below ground up to V

(Pin 32/Pin 5): Sense Voltage Range Input. The volt-

RNG

age at this pin is ten times the nominal sense voltage at maximum output current and can be programmed from 0.5V to 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to V

3709fa

LTC3709

FU CTIO AL DIAGRA

FCB

CLOCK DETECTOR

FROM CHANNEL 2

EXTLPF

OST

0.7

tON = (30pF)

ION

DUPLICATE FOR

SECOND CHANNEL

CMP

PLL2

20k

–

PLL1

TO CHANNEL 2 OST

REV

INTLPF

FCNT

SHDN

0.6V REF

SWITCH

LOGIC

VCC

BOOST

SENSE

DRV

PGND

DRVCC

OUT

1.4V

RNG

SHDN TO

CHANNEL 2

SWITCH LOGIC

SENSE

–

×

0.7V

3.3µA

–

240k

TRACK

Q1 Q2 Q30.6V

REF

SHED

THB

RUN

SHDN

–

+ –

RUN/SS

1.4V

–

0.66V

SGND

–

1.2µA

0.54V

100µs

BLANKING

40k

–

40k

PGOOD

DISABLE

DIFFOUT

–

40k

3709 FD

3709fa

LTC3709

OPERATIO

(Refer to Functional Diagram)

MAIN CONTROL LOOP

The LTC3709 is a constant on-time, current mode stepdown controller with two channels operating 180 degrees out of phase. In normal operation, each top MOSFET is turned on for a fixed interval determined by its own oneshot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator I

trips, restarting the one-shot timer and repeating the

CMP

cycle. The trip level of the current comparator is set by the

voltage, which is the output of error amplifier EA.

Inductor current is determined by sensing the voltage between the SENSE bottom MOSFET on-resistance or a separate sense resistor. At light load, the inductor current can drop to zero and become negative. This is detected by current reversal comparator I resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled when the FCB pin is tied to ground, forcing continuous synchronous operation.

The main control loop is shut down by pulling the RUN/SS pin low, turning off both top MOSFET and bottom MOSFET. Releasing the pin allows an internal 1.2µA current source to charge an external soft-start capacitor CSS. When this voltage reaches 1.4V, the LTC3709 turns on and begins operating with a clamp on the noninverting input of the error amplifier. This input is also the reference input of the error amplifier. As the voltage on RUN/SS continues to rise, the voltage on the reference input also rises at the same rate, effectively controlling output voltage slew rate.

Operating Frequency

The operating frequency is determined implicitly by the top MOSFET on time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding the frequency approximately constant with changes in V

external resistor RON.

REV

. The nominal frequency can be adjusted with an

–

and SENSE+ pins using either the

, which then shuts off the bottom MOSFET,

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this condition, the top MOSFET is turned off and the bottom MOSFET is turned on and held on until the condition is cleared.

Power Good (PGOOD) Pin

Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. In addition, the output feedback voltage must be out of this window for a continuous duration of at least 100µs before the PGOOD is pulled low. This is to prevent any glitch on the feedback voltage from creating a false power bad signal. The PGOOD will indicate a good power immediately when the feedback voltage is in regulation.

Short-Circuit Detection and Protection

After the controller has been started and been given adequate time to charge the output capacitor, the RUN/SS capacitor is used in a short-circuit time-out circuit. If the output voltage falls to less than 67% of its nominal output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latch off can be overridden by providing a >5µA pull-up at a compli- ance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during an overcurrent and/or shortcircuit condition.

DRV

Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the DRVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from DRVCC through an external Schottky diode DB when the top MOSFET is turned off.

3709fa

OPERATIO

SENSE

RNG

OUT MAX

210•

•

()

LTC3709

(Refer to Functional Diagram)

Differential Amplifier

This amplifier provides true differential output voltage sensing. Sensing both V

OUT

and V

–

benefits regula-

OUT

tion in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground, preventing the possibility of troublesome “ground loops” on the PC layout and preventing voltage errors caused by board-to-board interconnects.

Dual Phase Operation

An internal phase-lock loop (PLL1) ensures that channel 2 operates exactly at the same frequency as channel 1 and is also phase shifted by 180°, enabling the LTC3709 to operate optimally as a dual phase controller. The loop filter connected to the INTLPF pin provides stability to the PLL. For external clock synchronization, a second PLL (PLL2) is incorporated into the LTC3709. PLL2 will adjust the ontime of channel 1 until its frequency is the same as the external clock. When locked, the PLL2 aligns the turn on

of the top MOSFET of channel 1 to the rising edge of the external clock. Compensation for PLL2 is through the EXTLPF pin.

The loop filter components tied to the INTLPF and EXTLPF pins are used to compensate the internal PPL and external PLL respectively. The typical value ranges are:

INTLPF: R EXTLP: R

= 2kΩ to 10kΩ, C

IPLL

≤ 1kΩ, C

EPLL

IPLL

= 10nF to 100nF

EPLL

= 10nF to 100nF

For noise suppression, a capacitor with a value of 1nF or less should be placed from INTLPF to ground and EXTLPF to ground.

Second Channel Shutdown During Light Loads

When FCB is tied to V

, discontinuous mode is selected.

In this mode, no reverse current is allowed. The second channel is off when I

is less than 0.8V for better

efficiency. When FCB is tied to ground, forced continuous mode is selected, both channels are on and reversed current is allowed.

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APPLICATIO S I FOR ATIO

The basic LTC3709 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum load current and begins with the selection of the power MOSFET switches and/or sense resistor. The inductor current is determined by the R while the user has the option to use a sense resistor for a more accurate current limiting. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, C ability to handle the large RMS current into the converter and C

is chosen with low enough ESR to meet the

OUT

output voltage ripple specification.

Maximum Sense Voltage and V

Inductor current is determined by measuring the voltage across the R

of the synchronous MOSFET or through

DS(ON)

a sense resistance that appears between the SENSE

of the synchronous MOSFET

DS(ON)

is selected for its

RNG

–

and

the SENSE voltage applied to the V mately V allow the inductor current valleys to exceed V R

SENSE

pins. The maximum sense voltage is set by the

pin and is equal to approxi-

RNG

/7.5. The current mode control loop will not

RNG

/(7.5 •

RNG

). In practice, one should allow some margin for variations in the LTC3709 and external component values. A good guide for selecting the sense resistance for each channel is:

The voltage of the V resistive divider from V

pin can be set using an external

RNG

between 0.5V and 2V resulting

in nominal sense voltages of 50mV to 200mV. Additionally, the V

pin can be tied to ground or VCC, in which

RNG

case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.3 times this nominal value.

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APPLICATIO S I FOR ATIO

Connecting the SENSE+ and SENSE– Pins

2.0

The LTC3709 provides the user with an optional method to sense current through a sense resistor instead of using the R

of the synchronous MOSFET. When using a sense

DS(ON)

resistor, it is placed between the source of the synchronous MOSFET and ground. To measure the voltage across this resistor, connect the SENSE+ pin to the source end of

–

the resistor and the SENSE

resistor. The SENSE

and SENSE– pin connections pro-

pin to the other end of the

vide the Kelvin connections, ensuring accurate voltage measurement across the resistor. Using a sense resistor provides a well-defined current limit, but adds cost and reduces efficiency. Alternatively, one can use the synchronous MOSFET as the current sense element by simply connecting the SENSE SENSE

–

pin to the source of the synchronous MOSFET,

pin to the switch node SW and the

eliminating the sense resistor. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed in the Power MOSFET Selection section.

Power MOSFET Selection

The LTC3709 requires four external N-channel power MOSFETs, two for the top (main) switches and two for the bottom (synchronous) switches. Important parameters for the power MOSFETs are the breakdown voltage V

(BR)DSS

reverse transfer capacitance C I

DS(MAX)

The gate drive voltage is set by the 5V DRV

, threshold voltage V

, on-resistance R

(GS)TH

and maximum current

RSS

DS(ON)

supply.

Consequently, logic-level threshold MOSFETs must be used in LTC3709 applications. If the driver’s voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be used.

When the bottom MOSFETs are used as the current sense elements, particular attention must be paid to their onresistance. MOSFET on-resistance is typically specified with a maximum value R

DS(ON)(MAX)

at 25°C. In this case additional margin is required to accommodate the rise in MOSFET on-resistance with temperature:

DS ON MAX

()( )

SENSE

1.5

1.0

0.5

NORMALIZED ON-RESISTANCE

–50

JUNCTION TEMPERATURE (°C)

Figure 1. R

vs Temperature

DS(ON)

100

150

3709 F01

The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C. Junction-tocase temperature is about 20°C in most applications. For a maximum junction temperature of 100°C, using a value

= 1.3 is reasonable (Figure 1).

100°C

The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3709 is operating in continuous mode, the duty cycles for the MOSFETs are:

TOP

BOT

OUT

–

IN OUT

The maximum power dissipation in the MOSFETs per channel is:

⎞

⎟

() ()( )

T TOP DS ON MAX

⎠

⎞

OUT

⎛ ⎜

⎜

()

⎝

RSS

⎟

⎠

DRV V

–

CC GS TH

⎞

⎟

()

•

(

BOTBOT DS ON MAX

) ( )( )

GS TH

⎞ ⎟

⎟ ⎠

⎠

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TOP TOP

BOT BOT

•••

(.)• • • • •

()_

DS ON DRV

••

⎛

OUT MAX

⎜ ⎝

⎛

OUT MAX

⎜ ⎝

()

⎛ ⎜

⎝

()

WUUU

∆ =

⎛ ⎝

⎜

⎞ ⎠

⎟

⎛ ⎝

⎜

⎞ ⎠

⎟

OUT OUT

•

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APPLICATIO S I FOR ATIO

LTC3709

Both top and bottom MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are the largest at maximum input voltages. The bottom MOSFET losses are the greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where V the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low “on” resistance with significantly reduced input capacitance for the main switch application in switching regulators.

Operating Frequency

The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage.

The operating frequency of LTC3709 applications is determined implicitly by the one-shot timer that controls the on time, t the current into the I

, of the top MOSFET switch. The on-time is set by

pin according to:

0730.

ION

()

>> V

OUT

locking and phase separation between the two channels while the second PLL is for locking onto an external clock. Since the LTC3709 is a constant on-time architecture, the error signal generated by the phase detector of the PLL is used to vary the on-time to achieve frequency locking and 180° phase separation.

The synchronization is set up in a “daisy chain” manner whereby channel 2’s on-time will be varied with respect to channel 1. If an external clock is present, then channel 1’s on-time will be varied and channel 2 will follow suit. Both PLLs are set up with the same capture range and the frequency range that the LTC3709 can be externally synchronized to is between 2 • f frequency setting of the two channels. It is advisable to set initial frequency as close to external frequency as possible.

A limitation of both PLLs is when the on-time is close to the minimum (100ns). In this situation, the PLL will not be able to synchronize up in frequency.

To ensure proper operation of the internal phase-lock loop when no external clock is applied to the FCB pin, the INTLPF pin may need to be pulled down while the output voltage is ramping up. One way to do this is to connect the anode of a silicon diode to the INTLPF pin and its cathode to the PGOOD pin and connect a pull-up resistor between the PGOOD pin and VCC. Refer to Figure 9 for an example.

Inductor Selection

Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current:

and 0.5 • fC, where fC is the initial

Tying a resistor from VIN to the ION pin yields an on-time inversely proportional to V results in approximately constant frequency operation as the input supply varies:

07 30.•

PLL and Frequency Synchronization

In the LTC3709, there are two on-chip phase-lock loops (PLLs). One of the PLLs is used to achieve frequency

OUT

RpF

()

. For a down converter, this

Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency.

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APPLICATIO S I FOR ATIO

A reasonable starting point is to choose a ripple current that is about 40% of I

OUT(MAX)

ripple current occurs at the highest V

/2. Note that the largest

. To guarantee that

ripple current does not exceed a specified maximum, the inductance should be chosen according to:

⎛

⎜ ⎝

OUT

∆

•

L MAX

⎞

⎛

–

⎟

⎜

⎠

() ()

⎝

IN MAX

OUT

⎞ ⎟

⎠

Once the value for L is known, the inductors must be selected (based on the RMS saturation current ratings). A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Toko and Panasonic.

Schottky Diode Selection

The Schottky diodes conduct during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which causes a modest (about 1%) efficiency loss. The diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between the diode and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable.

and C

Selection

OUT

In continuous mode, the current of each top N-channel MOSFET is a square wave of duty cycle V

OUT/VIN

. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 2 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the input voltage is twice the output voltage.

In the Figure 2 graph, the local maximum input RMS capacitor currents are reached when:

OUT

–

where k 1, 2

These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question.

It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor 2 due to the effective increase in the frequency of the current pulses.

0.6

0.5

0.4

0.3

0.2

DC LOAD CURRENT

RMS INPUT RIPPLE CURRNET

0.1

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Figure 2. RMS Input Current Comparison

DUTY FACTOR (V

1-PHASE 2-PHASE

OUT/VIN

0.9

)

3709 F02

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APPLICATIO S I FOR ATIO

LTC3709

The selection of C

is primarily determined by the ESR

OUT

required to minimize voltage ripple and load step transients. The output ripple ∆V

⎛

∆∆V I ESR

≤ +

OUT L

⎜ ⎝

is approximately bounded by:

OUT

⎞

OUT

⎟ ⎠

Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating.

Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and longterm reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance.

Top MOSFET Driver Supply (C

, DB)

Discontinuous Mode Operation and FCB Pin

The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin to VCC enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which inductor current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current. The ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages.

Tying the FCB pin to ground forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation.

Besides providing a logic input to force continuous operation, the FCB pin acts as the input for external clock synchronization. Upon detecting a TTL level clock and the frequency is higher than the minimum allowable, channel 1 will lock on to this external clock. This will be followed by channel 2 (see PLL and Frequency Synchronization). The LTC3709 will be forced to operate in forced continuous mode in this situation.

Fault Conditions: Current Limit

The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3709, the maximum sense voltage is controlled by the voltage on the V

pin. With valley current control,

RNG

the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is:

An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRV

when the switch node is low. Note that the average voltage across C turns on, the switch node rises to V

is approximately DRVCC. When the top MOSFET

and the BOOST pin

rises to approximately VIN + DRVCC. The boost capacitor needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1µF to 0.47µF is adequate.

⎛

LIMIT

SNS MAX

=+∆

⎜

⎝

()

DS ON T

()

•

ρ12

⎞

••

⎟

⎠

The current limit value should be checked to ensure that I

LIMIT(MIN)

generally occurs with the largest V

> I

OUT(MAX).

The minimum value of current limit

at the highest ambi-

ent temperature, conditions which cause the largest power loss in the converter. Note that it is important to check for

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LTC3709

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APPLICATIO S I FOR ATIO

self-consistency between the assumed junction temperature and the resulting value of I junction.

Caution should be used when setting the current limit based upon the R

of the MOSFETs. The maximum current

DS(ON)

limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for R is that the minimum R

, but not a minimum. A reasonable assumption

DS(ON)

lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines.

For a more accurate current limiting, a sense resistor can be used. Sense resistors in the 1W power range are easily available with 5%, 2% or 1% tolerance. The temperature coefficient of these resistors are very low, ranging from ± 250ppm/°C to ±75ppm/°C. In this case, the denominator in the above equation can simply be replaced by the R

SENSE

value.

Minimum Off-Time and Dropout Operation

, which heats the

LIMIT

2.0

1.5

1.0

0.5

SWITCHING FREQUENCY (MHz)

0 0.25 0.50 0.75

Figure 3. Maximum Switching Frequency vs Duty Cycle

DUTY CYCLE (V

DROPOUT

REGION

OUT/VIN

)

1.0

3709 F03

Pulling the RUN/SS pin below 1.4V puts the LTC3709 into a low quiescent current shutdown (IQ < 30µA). Releasing the pin allows an internal 1.2µA internal current source to charge the external capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about:

The minimum off-time t

OFF(MIN)

is the smallest amount of time that the LTC3709 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of t

/(tON + t

OFF(MIN)

). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation in order to maintain the duty cycle at its limit. The minimum input voltage to avoid dropout is:

IN MIN OUT

()

–•

OFF MIN

()

A plot of maximum duty cycle vs frequency is shown in Figure 3.

Soft-Start and Latchoff with the RUN/SS Pin

The RUN/SS pin provides a means to shut down the LTC3709 as well as a timer for soft-start and overcurrent latchoff.

DELAY SS SS

•./

CsFC

=µ

()

When the RUN/SS voltage reaches the ON threshold (typically 1.4V), the LTC3709 begins operating with a clamp on EA’s reference voltage. The clamp level is one ON threshold voltage below RUN/SS. As the voltage on RUN/SS continues to rise, EA’s reference is raised at the same rate, achieving monotonic output voltage soft-start (Figure 4).

RUN/SS

∆V = 0.6V

ON THRESHOLD

TIME

OUT1

TIME

3709 F04

Figure 4. Monotonic Soft-Start Waveforms

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APPLICATIO S I FOR ATIO

3.3V OR 5V RUN/SS

Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated

RSS*

(5a) (5b)

When RUN/SS rises 0.6V above the ON threshold, the reference clamp is invalidated and the internal precision reference takes over.

After the controller has been started and given adequate time to charge the output capacitor, C circuit timer. After the RUN/SS pin charges above 3V, and if the output voltage falls below 67% of its regulated value, then a short-circuit fault is assumed. A 2µA current then begins discharging C

. If the fault condition persists until

the RUN/SS pin drops to 2.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation.

The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time C

RSS*

RUN/SS

D2*

2N7002

*OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF

is used as a short-

3709 F05

has

LTC3709

reached the 3V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from:

> C

OUT VOUT RSENSE

Overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current of >5µA to the RUN/SS pin. The additional current pre- vents the discharge of C the soft-start period. Using a resistor to V Figure 5 is simple, but slightly increases shutdown current. Any pull-up network must be able to pull RUN/SS above the 3V threshold that arms the latchoff circuit and overcome the 2µA maximum discharge current.

Output Voltage Tracking

The feedback voltage, V voltage when the TRACK pin voltage is less than the reference voltage, V voltage is greater than V servo to V

. When selecting components for the TRACK

REF

pin, ensure the final steady-state voltage on the TRACK pin is greater than V

at the end of the tracking interval.

REF

The LTC3709 allows the user to set up start-up sequencing among different supplies in either coincident tracking or ratiometric tracking as shown in Figure 6. To implement the coincident tracking, connect an extra resistor divider

(10–4 [F/VS])

during a fault and also shortens

as shown in

, will follow the TRACK pin

(0.6V). When the TRACK pin

REF

, the feedback voltage will

REF

OUTPUT VOLTAGE

TIME

(6a) Coincident Tracking

Figure 6. Two Different Forms of Output Voltage Sequencing

OUT1

OUT2

OUTPUT VOLTAGE

TIME

(6b) Ratiometric Tracking

3709 F06

OUT1

OUT2

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LTC3709

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APPLICATIO S I FOR ATIO

to the output of supply 1. This resistor divider is selected to be the same as the divider across supply 2’s output. The TRACK pin of supply 2 is connected to this extra resistor divider. For the ratiometric tracking, simply connect the TRACK pin of supply 2 to the V

pin of supply 1. Figure

7 shows this implementation. Note that in the coincident tracking, output voltage of supply 1 has to be set higher than output voltage of supply 2.

Note that since the shutdown trip point varies from part to part, the “slave” part’s RUN/SS pin will need to be connected to VCC. This eliminates the possibility that different LTC3709s may shut down at different times.

If output sequencing is not needed, connect the TRACK pins to V

Do Not Float these pins

SUPPLY 1

OUT1

SUPPLY 2

LTC3709

TRACK

OUT2

3709 F07

resistance of one MOSFET can simply be summed with the

resistances of L and the board traces to obtain the DC I loss. For example, if R

= 0.01Ω and RL = 0.005Ω, the

DS(ON)

loss will range from 0.1% up to 10% as the output current varies from 1A to 10A for a 1.5V output.

2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from:

TransitionLoss V I C f

(.)• • • • •

≈

⎛

DS ON DRV

()_

⎜

DRV V V

⎝

CC GS TH GS TH

IN OUT RSS

−

() ()

⎞ ⎟

⎠

3. Gate driver supply current. The driver current supplies the gate charge Q

required to switch the power MOSFETs.

This current is typically much larger than the control circuit current. In continuous mode operation:

Figure 7. Setup for Coincident and Ratiometric Tracking

COINCIDENTLY TRACKS V

OUT2

RATIOMETRIC POWER UP BETWEEN V

OUT1

AND V

OUT2

OUT1

Efficiency Considerations

The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement.

Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3709 circuits:

1. DC I

R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same R

DS(ON)

, then the

GATECHG

4. C

= f (Q

g(TOP)

+ Q

g(BOT)

)

loss. The input capacitor has the difficult job of

filtering the large RMS input current to the regulator. It

must have a very low ESR to minimize the AC I

R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including C

ESR loss, Schottky conduc-

OUT

tion loss during dead time and inductor core loss generally account for less than 2% additional loss.

When making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency.

Checking Transient Response

The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V

immediately shifts by an amount

OUT

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APPLICATIO S I FOR ATIO

LTC3709

equal to ∆I resistance of C discharge C the regulator to return V During this recovery time, V overshoot or ringing that would indicate a stability problems. The I will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76.

Design Example

As a design example, take a supply with the following specifications: V

2.5V, I timing resistor:

and choose the inductor for about 40% ripple current at the maximum V channel is 10A:

Selecting a standard value of 1.8µH results in a maximum ripple current of:

Next, choose the synchronous MOSFET switch. Choosing a Si4874 (R q

Tying V for a nominal value of 110mV with current limit occurring at 146mV. To check if the current limit is acceptable, assume a junction temperature of about 80°C above a 70°C ambient with ρ

OUT(MAX)

250 0 4 10

()()()

∆ =

= 40°C/W) yields a nominal sense voltage of:

SNS(NOM)

RNG

(ESR), where ESR is the effective series

LOAD

. ∆I

OUT

generating a feedback error signal used by

OUT

pin external components shown in Figure 9

= 7V to 28V (15V nominal), V

= 20A, f = 250kHz. First, calculate the

V kHz pF

0 7 250 30

()( )()

. Maximum output current for each

kHz A

250 1 8

()

to 1.1V will set the current sense voltage range

kHz H

DS(ON)

= (10A)(1.3)(0.0083Ω) = 108mV

()

= 0.0083Ω (NOM) 0.010Ω (MAX),

150°C

also begins to charge or

LOAD

to its steady-state value.

OUT

can be monitored for

OUT

= 1.5:

476

⎞

⎟

⎠

⎞

⎟

⎠

=µ

⎛

−

⎜ ⎝

⎛

–

⎜ ⎝

OUT

⎛

≥

LIMIT

and double check the assumed TJ in the MOSFET:

BOT

TJ = 70°C + (1.97W)(40°C/W) = 149°C

Because the top MOSFET is on for such a short time, an Si4884 R 40°C/W will be sufficient. Checking its power dissipation at current limit with ρ

TOP

TJ = 70°C + (0.7W)(40°C/W) = 98°C

The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit.

CIN is chosen for an RMS current rating of about 10A at 85°C. The output capacitors are chosen for a low ESR of 0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only:

∆V

However, a 0A to 10A load step will cause an output change of up to:

∆V

An optional 22µF ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 9.

⎜ ⎜

15 0010

()

⎝

28 2 52824

DS(ON)(MAX)

252824

1 7 28 12 100 250

()( )( )( )( )

...

=+=

030 040 07

OUT(RIPPLE)

OUT(STEP)

146

()

–.

VVVA

WWW

= ∆I

⎛ ⎜

⎝

= 0.0165Ω, C

100°C

⎞

⎛

⎟

⎜

⎠

⎝

V A pF kHz

= ∆I

L(MAX)

= (5.1A) (0.013Ω) = 66mV

(ESR) = (10A) (0.013Ω) = 130mV

LOAD

Ω

⎞

()

⎟

⎠

= 1.4:

1 4 0 0165

()

(ESR)

⎞

51 2 24

.•

()

.. .

15 0010 197

()

RSS

⎟ ⎟

⎠

Ω

= 100pF, θJA =

Ω

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PC Board Layout Checklist

When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components.

• The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs.

• Place CIN, C

, MOSFETs, D1, D2 and inductors all in

OUT

one compact area. It may help to have some components on the bottom side of the board.

• Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3709. Use several larger vias for power components.

• Use a compact plane for switch node (SW) to keep EMI down.

• Use planes for V

and V

to maintain good voltage

OUT

filtering and to keep power losses low.

• Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point, which is then tied to a “clean” point in the power ground such as the “–” node of CIN.

• Minimize impedance between input ground and output ground.

• Connect PGND1 to the source of M2 or RS1 (QFN) directly. This also applies to channel 2.

• Place M2 as close to the controller as possible, keeping the PGND1, BG1 and SW1 traces short. The same for the other channel. SW2 trace should connect to the drain of M2 directly.

• Connect the input capacitor(s) C

close to the power

MOSFETs: (+) node to drain of M1, (–) node to source of M2. This capacitor carries the MOSFET AC current.

• Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes.

• Connect the DRV to the DRV

and PGND pins.

decoupling capacitor C

VCC

closely

• Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to

, V

any DC net (V

, GND or to any other DC rail in

OUT

your system).

When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 9.

SENSE+SENSE

(8a) Sensing the Bottom MOSFET

MOSFET

–

• Connect the top driver boost capacitor C

closely to the

BOOST and SW pins.

• Connect the V the V

and PGND pins.

• Are the SENSE

pin decoupling capacitor CF closely to

–

and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE

and SENSE+ (C

) should be as close

SENSE

–

as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor as shown in Figure 8.

SENSE

SENSE+SENSE

(8b) Sensing a Resistor

–

3709 F08

Figure 8. Kelvin Sensing

3709fa

WUUU

APPLICATIO S I FOR ATIO

LTC3709

CC 470pF

100pF

10k

100nF

CSS 0.1µF

470pF

0.22µF

1nF

RC 20k

TRACK

100pF

RF1 31.6k

475Ω

3.32k

MMSD4148 (OPTIONAL)

RUN/SS

TRACK

SGND

DIFFOUT

EXTLPF

INTLPF

BOOST2

TG2

SW2

SENSE2

PGOOD

BOOST1

–

SENSE1

LTC3709EUH

PGND1

DRV

PGND2

SENSE2

100pF

RNG

FCB

TG1

SW1

BG1

BG2

10nF

PGOOD

–

RON 476k

PGOOD

CB1 0.22µF

100pF

1µF

10Ω

1µF

100k

1µF

CMDSH-3

10k

35.7k

7V TO 28V

DRV

10µF

35V ×3

M3 M4

B340A

OUT

180µF

4V ×4

1.8µH

OUT

2.5V 20A

L1, L2: PANASONIC ETQP6FIR8BFA

: PANASONIC EEFUEOG181R

OUT

M1, M3: SILICONIX Si4884DY M2, M4: SILICONIX Si4874DY

Figure 9. 2-Phase 2.5V/20A Supply at 250kHz with Tracking and External Synch

3709 F09

3709fa

LTC3709

PACKAGE DESCRIPTIO

G Package

36-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

12.50 – 13.10* (.492 – .516)

2526 22 21 20 19232427282930313233343536

7.8 – 8.2

0.42 ±0.03 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT

5.00 – 5.60** (.197 – .221)

0.09 – 0.25

(.0035 – .010)

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE *

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

0.55 – 0.95

(.022 – .037)

MILLIMETERS

(INCHES)

5.3 – 5.7

0° – 8°

12345678 9 10 11 12 14 15 16 17 1813

0.65

(.0256)

BSC

0.22 – 0.38

(.009 – .015)

TYP

7.40 – 8.20

(.291 – .323)

2.0

(.079)

MAX

0.05

(.002)

MIN

G36 SSOP 0204

3709fa

PACKAGE DESCRIPTIO

5.50 ±0.05

4.10 ±0.05

3.45 ±0.05 (4 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

5.00 ± 0.10 (4 SIDES)

PIN 1 TOP MARK (NOTE 6)

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

0.75 ± 0.05

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

LTC3709

0.23 TYP

(4 SIDES)

0.40 ± 0.10

3.45 ± 0.10 (4-SIDES)

0.200 REF

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.25 ± 0.05

(UH) QFN 0603

0.50 BSC

3709fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3709

TYPICAL APPLICATIO

0.1µF

220pF

100nF

10k

1nF

0.22µF

3.32k

470pF

191k

20k

RUN/SS

TRACK

SGND

DIFFOUT

EXTLPF

INTLPF

BOOST2

TG2

SW2

SENSE2

Low Output Ripple, 2-Phase 12V/25A Supply

LTC3709

–

100pF

PGOOD

BOOST1

SW1

SENSE1

PGND1

DRV

PGND2

SENSE2

RNG

FCB

TG1

BG1

BG2

PGOOD

–

100pF

1µF

10Ω

1µF

100k

0.22µF

1µF

CMDSH-3

10nF

2.86M

26.1k

10k

DRV 5V

20V–28V

35V ×3

10µF

B340A

OUT

180µF 16V ×2

3.5µH

OUT

B340A

M1-M4: RENESAS HAT2167

: SANYO 16SVP180MX

OUT

L1, L2: SUMIDA CDEP147-3R5MC-H

3709 TA02

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≤ 5V

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

3709fa

LT/LT 0605 • PRINTED IN USA

LINEAR TECHNOLOGY LTC3709 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual