Datasheet LTC3704 Datasheet (LINEAR TECHNOLOGY)

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LTC3704

Positive-to-Negative DC/DC Controller

FEATURES

■

High Efficiency Operation (No Sense Resistor Required)

■

Wide Input Voltage Range: 2.5V to 36V

■

Current Mode Control Provides Excellent Transient Response

■

High Maximum Duty Cycle (Typ 92%)

■

±1% Internal Voltage Reference

■

±2% RUN Pin Threshold with 100mV Hysteresis

■

Micropower Shutdown: IQ = 10µA

■

Programmable Switching Frequency (50kHz to 1MHz) with One External Resistor

■

Synchronizable to an External Clock Up to 1.3 × f

■

User-Controlled Pulse Skip or Burst Mode® Operation

■

Internal 5.2V Low Dropout Voltage Regulator

■

Capable of Operating with a Sense Resistor for High Output Voltage Applications (V

■

Small 10-Lead MSOP Package

>36V)

APPLICATIO S

■

SLIC Power Supplies

■

Telecom Power Supplies

■

Portable Electronic Equipment

■

Cable and DSL Modems

■

Router Supplies

OSC

Wide Input Range, No R

SENSE

DESCRIPTIO

The LTC®3704 is a wide input range, current mode, positive-to-negative DC/DC controller that drives an N-channel power MOSFET and requires very few external components. Intended for low to high power applications, it eliminates the need for a current sense resistor by utilizing the power MOSFET’s on-resistance, thereby maximizing efficiency.

The IC’s operating frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 2.5V and a low shutdown quiescent current of 10µA make the LTC3704 ideally suited for battery-operated systems.

For applications requiring constant frequency operation, the Burst Mode operation feature can be defeated using the MODE/SYNC pin. Higher than 36V switch voltage applications are possible with the LTC3704 by connecting the SENSE pin to a resistor in the source of the power MOSFET.

The LTC3704 is available in the 10-lead MSOP package.

, LTC, LT and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. No R registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5847554, 5731694.

SENSE

is a

TYPICAL APPLICATIO

4.7nF

, C

: TDK C5750X5R1C476M

: TDK C5750X5R0J107M

OUT

: TAIYO YUDEN LMK316BJ475ML

VCC

Figure 1. High Efficiency Positive to Negative Supply

80.6k 1%

1.21k

FB1

RUN

NFB

FREQ

MODE/SYNC

LTC3704

FB2

3.65k 1%

SENSE

INTV

GATE

GND

L1*

VCC

47µF

4.7µF

D1: MBRD835L (ON SEMICONDUCTOR) L1, L2: BH ELECTRONICS BH510-1009 M1: Si4884 (SILICONIX/VISHAY)

3704 TA01

5V to 15V

OUT

–5.0V 3A to 5A

OUT

100µF (X2)

GND

Conversion Efficiency

100

VIN = 5V

EFFICIENCY (%)

0.001

VIN = 15V

VIN = 10V

0.01 1.0 OUTPUT CURRENT (A)

0.1

3704 TA01b

3704fa

•

L2*

47µF

LTC3704

1 2 3 4 5

RUN

NFB

FREQ

MODE/

SYNC

10 9 8 7 6

SENSE V

INTV

GATE GND

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

VIN Voltage ............................................... –0.3V to 36V

INTV INTV

GATE Voltage ........................... – 0.3V to V

NFB Voltage .............................................. –2.7V to 2.7V

RUN, MODE/SYNC Voltages ....................... –0.3V to 7V

FREQ Voltage ............................................– 0.3V to 1.5V

SENSE Pin Voltage ................................... – 0.3V to 36V

Voltage ........................................... –0.3V to 7V

Output Current ........................................ 50mA

+ 0.3V

INTVCC

Voltage ............................................... – 0.3V to 2.7V

ORDER PART

NUMBER

= 125°C, θJA = 120°C/ W

JMAX

MS PART MARKING

Operating Temperature Range (Note 2) .. – 40°C to 85°C

LTC3704E ............................................ –40°C to 85°C

LTC3704I........................................... –40°C to 125°C

Junction Temperature (Note 3)............................ 125°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

LTC3704EMS LTC3704IMS

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTYT LTCFW

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V

= V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Main Control Loop

IN(MIN)

RUN

–

RUN

RUN(HYST)

RUN

NFB

∆V

NFB

∆V

NFB

∆V

ITH

ITH(BURST)

SENSE(MAX)

SENSE(ON)

SENSE(OFF)

= 5V, V

INTVCC

Minimum Input Voltage 2.5 V

Input Voltage Supply Current (Note 4) Continuous Mode V Burst Mode Operation, No Load V Shutdown Mode V

Rising RUN Input Threshold Voltage 1.348 V

Falling RUN Input Threshold Voltage 1.223 1.248 1.273 V

RUN Pin Input Threshold Hysteresis 50 100 150 mV

RUN Input Current 1 100 nA

Negative Feedback Voltage V

NFB Pin Input Current V Line Regulation 2.5V ≤ VIN ≤ 30V 0.002 0.02 %/V

Load Regulation V

Error Amplifier Transconductance ITH Pin Load = ±5µA (Note 5) 650 µmho

Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) 0.3 V

Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV

SENSE Pin Current (GATE High) V

SENSE Pin Current (GATE Low) V

= 1.5V, RT = 80k, V

RUN

MODE/SYNC

= 0V, unless otherwise specified.

MODE/SYNC MODE/SYNC RUN

ITH

LTC3704I (Note 2)

ITH

MODE/SYNC

SENSE

= 5V, V = 0V, V

= 0V 10 20 µA

= 0.2V (Note 5) –1.218 –1.230 –1.242 V = 0.2V (Note 5)

= 0.2V (Note 5) 7.5 15 µA

= 0V, VTH = 0.5V to 0.90V (Note 5)

= 0V 40 75 µA

= 30V 0.1 5 µA

= 0.75V 550 1000 µA

ITH

= 0.2V (Note 5) 250 500 µA

ITH

●

1.198 1.298 V

●

–1.212 –1.248 V

●

–1.205 –1.255 V

●

–1 –0.1 %

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LTC3704

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

= V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Oscillator

OSC

MAX

SYNC/fOSC

SYNC(MIN)

SYNC(MAX)

IL(MODE)

IH(MODE)

MODE/SYNC

FREQ

Low Dropout Regulator

INTVCC

∆V

INTVCC

∆V

IN1

∆V

INTVCC

∆V

IN2

LDO(LOAD)

DROPOUT

INTVCC

GATE Driver

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime.

Note 2: The LTC3704E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3704I is guaranteed over the full –40°C to 125°C operating temperature range.

Note 3: T dissipation P

= 5V, V

INTVCC

Oscillator Frequency R

= 1.5V, R

RUN

FREQ

= 80k, V

MODE/SYNC

= 0V, unless otherwise specified.

= 80k 250 300 350 kHz

FREQ

Oscillator Frequency Range 50 1000 kHz Maximum Duty Cycle 87 92 97 % Recommended Maximum Synchronized f

= 300kHz (Note 6) 1.25 1.30

OSC

Frequency Ratio MODE/SYNC Minimum Input Pulse Width V

MODE/SYNC Maximum Input Pulse Width V

= 0V to 5V 25 ns

SYNC

= 0V to 5V 0.8/f

SYNC

OSC

Low Level MODE/SYNC Input Voltage 0.3 V High Level MODE/SYNC Input Voltage 1.2 V MODE/SYNC Input Pull-Down Resistance 50 kΩ Nominal FREQ Pin Voltage 0.62 V

INTVCC Regulator Output Voltage VIN = 7.5V 5.0 5.2 5.4 V

INTVCC Regulator Line Regulation 7.5V ≤ VIN ≤ 15V 8 25 mV

INTVCC Regulator Line Regulation 15V ≤ VIN ≤ 30V 70 200 mV

INTVCC Load Regulation 0 ≤ I

≤ 20mA –2 – 0.2 %

INTVCC

INTVCC Regulator Dropout Voltage VIN = 5V, INTVCC Load = 20mA 280 mV

Bootstrap Mode INTVCC Supply RUN = 0V, SENSE = 5V 10 20 µA Current in Shutdown

GATE Driver Output Rise Time CL = 3300pF (Note 7) 17 100 ns GATE Driver Output Fall Time CL = 3300pF (Note 7) 8 100 ns

Note 4: The dynamic input supply current is higher due to power MOSFET

• f

gate charging (Q

). See Applications Information.

OSC

Note 5: The LTC3704 is tested in a feedback loop that servos V reference voltage with the I

pin forced to a voltage between 0V and 1.4V

(the no load to full load operating voltage range for the I

1.23V). Note 6: In a synchronized application, the internal slope compensation

gain is increased by 25%. Synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in

is calculated from the ambient temperature TA and power

according to the following formula:

subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels.

= TA + (PD • 120°C/W)

NFB

pin is 0.3V to

to the

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LTC3704

TYPICAL PERFOR A CE CHARACTERISTICS

NFB Voltage vs Temp NFB Voltage Line Regulation NFB Pin Current vs Temperature

–1.25

–1.24

–1.23

NFB VOLTAGE (V)

–1.22

–1.21

–50

–25

TEMPERATURE (°C)

–1.231

–1.230

NFB VOLTAGE (V)

–1.229

100

125

150

3704 G01

5101520

VIN (V)

25 30 35

3704 G02

8.0

7.9

7.8

7.7

7.6

7.5

7.4

NFB CURRENT (µA)

7.3

7.2

7.1

7.0 –50

–25

250 50 10075

TEMPERATURE (°C)

125 150

3704 G03

Shutdown Mode IQ vs V

(µA)

SHUTDOWN MODE I

10 20

VIN (V)

Burst Mode IQ vs Temperature

500

400

(µA)

300

200

Burst Mode I

100

–50

–25 25

TEMPERATURE (°C)

3704 G04

Shutdown Mode IQ vs Temperature

VIN = 5V

(µA)

SHUTDOWN MODE I

–50

–25 0 25 50

TEMPERATURE (°C)

75 100 125 150

3704 G05

Burst Mode IQ vs V

600

500

400

(µA)

300

200

Burst Mode I

100

10 20

30 40

VIN (V)

3704 G06

Gate Drive Rise and Fall Time

Dynamic IQ vs Frequency

CL = 3300pF

= 550µA + Qg • f

Q(TOT)

(mA)

125

100

150

3704 G07

400 1200

200 1000

FREQUENCY (kHz)

600

800

3704 G08

vs C

TIME (ns)

4000 6000 8000

2000

RISE TIME

FALL TIME

10000 12000

CL (pF)

3704 G09

3704fa

INTVCC LOAD (mA)

DROPOUT VOLTAGE (mV)

150

200

250

500

350

3704 G18

100

400

450

300

150°C

75°C

125°C

25°C

–50°C

0°C

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3704

RUN Thresholds vs V

1.5

1.4

1.3

RUN THRESHOLDS (V)

1.2 0

10 20

VIN (V)

Frequency vs Temperature

325

320

315

310

305

300

295

290

GATE FREQUENCY (kHz)

285

280

275

–50

–25 25

TEMPERATURE (°C)

INTV

Load Regulation

TA = 25°C

3704 G10

RUN Thresholds vs Temperature

1.40

1.35

1.30

RUN THRESHOLDS (V)

1.25

1.20 –50

–25

TEMPERATURE (°C)

100

125

150

3704 G11

RT vs Frequency

1000

100

(kΩ)

100

200 1000

400

500

300

FREQUENCY (kHz)

800700600

900

3704 G12

Maximum Sense Threshold vs Temperature

160

155

150

145

MAX SENSE THRESHOLD (mV)

140

–50

125

100

150

3704 G13

–25 0 25 50

INTV

5.4 TA = 25°C

TEMPERATURE (°C)

Line Regulation

75 100 125 150

3704 G14

SENSE Pin Current vs Temperature

GATE HIGH

= 0V

SENSE

SENSE PIN CURRENT (µA)

–50

–25 25

INTV

Dropout Voltage

TEMPERATURE (°C)

100

vs Current, Temperature

125

150

3704 G15

5.2

VOLTAGE (V)

5.1

INTV

5.0 0

10 20

30 50 80

INTVCC LOAD (mA)

60 70

3704 G16

5.3

VOLTAGE (V)

5.2

INTV

5.1 0

515

10 20

VIN (V)

3704 G17

3704fa

LTC3704

PI FU CTIO S

RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the VIN supply current is kept to a low value (typ 10µA). The Absolute Maximum Rating for the voltage on this pin is 7V.

ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V.

NFB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulation is –1.230V.

FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.62V.

MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the

operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTV or if an external logic-level synchronization signal is applied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode.

GND (Pin 6): Ground Pin.

GATE (Pin 7): Gate Driver Output.

NTVCC (Pin 8): The Internal 5.20V Regulator Output. The

gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7µF low ESR tantalum or ceramic capacitor.

(Pin 9): Main Supply Pin. Must be closely decoupled

to ground.

SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to the drain of the power MOSFET for V SENSE pin may be connected to a resistor in the source of the power MOSFET. Internal leading edge blanking is provided for both sensing methods.

sensing and highest efficiency. Alternatively, the

3704fa

BLOCK DIAGRA

FREQ

MODE/SYNC

NFB

200k

1.230V

INTV

2.00V

0.62V

5.2V

–

BUFFER

–

200k

LDO

OSC

0.30V

1.230V

TO START-UP CONTROL

SLOPE

COMPENSATION

OSCV-TO-I

50k

–

BURST

COMPARATOR

V-TO-I

SLOPE

BIAS V

LOOP

1.230V

REF

BIAS AND

START-UP

CONTROL

PWM LATCH

100mV HYSTERESIS (1.348V RISING)

LOGIC

CURRENT

COMPARATOR

LTC3704

RUN

1.248V

–

INTV

GATE

GND

SENSE

–

LOOP

GND

3704 BD

3704fa

LTC3704

OPERATIO

Main Control Loop

The LTC3704 is a constant frequency, current mode controller for DC/DC positive-to-negative converter applications. The LTC3704 is distinguished from conventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power MOSFET switch instead of across a discrete sense resistor, as shown in Figure 2. This sensing technique improves efficiency, increases power density, and reduces the cost of the overall solution.

SENSE

GATE

GND

2a. SENSE Pin Connection for Maximum Efficiency (V

GATE

SENSE

GND

2b. SENSE Pin Connection for Precise Control of Peak I

Figure 2. Using the SENSE Pin On the LTC3704

IN/IOUT

< 36V)

SENSE

3704 F02

or for VSW > 36V

For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error amplifier EA, which outputs an error signal at the ITH pin. The voltage on the ITH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the NFB voltage relative to the reference voltage causes the I

pin to rise, which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation.

The nominal operating frequency of the LTC3704 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple.

The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V, the chip is off and the input supply current is typically only 10µA.

The LTC3704 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET, the user is able to program output voltages significantly greater than the 36V maximum input voltage rating for the IC.

Programming the Operating Mode

For applications where maximizing the efficiency at very light loads (e.g., <100µA) is a high priority, Burst Mode operation should be applied (i.e., the MODE/SYNC pin should be connected to ground). In applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the MODE/SYNC pin should be connected to the INTV

pin. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by the chip’s

3704fa

OPERATIO

LTC3704

minimum on-time (about 175ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Figures 3 and 4 show the light load switching waveforms for Burst Mode and Pulse-Skip Mode operation for the converter in Figure 1.

Burst Mode Operation

Burst Mode operation is selected by leaving the MODE/ SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the ITH pin corresponding to no load to full load is 0.30V to 1.2V. In Burst Mode operation, if the error amplifier EA drives the I

voltage

below 0.525V, the buffered ITH input to the current comparator C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is then held at approximately 30mV divided by the power MOSFET R

. If the ITH pin drops below 0.30V,

DS(ON)

the Burst Mode comparator B1 will turn off the power MOSFET and scale back the quiescent current of the IC to 250µA (sleep mode). In this condition, the load current will be supplied by the output capacitor until the I

voltage

rises above the 50mV hysteresis of the burst comparator. At light loads, short bursts of switching (where the average inductor current is 25% of its maximum value) followed by long periods of sleep will be observed, thereby greatly improving converter efficiency. Oscilloscope waveforms illustrating Burst Mode operation are shown in Figure 3.

MODE/SYNC = 0V (Burst Mode OPERATION)

OUT

50mV/DIV

5A/DIV

buffered I

burst clamp is removed, allowing the ITH pin

to directly control the current comparator from no load to full load. With no load, the I

pin is driven below 0.30V,

the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4.

MODE/SYNC = INTV (PULSE-SKIP MODE)

OUT

50mV/DIV

5A/DIV

2µs/DIV

Figure 4. LTC3704 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTV

3704 F04

)

When an external clock signal drives the MODE/SYNC pin at a rate faster than the chip’s internal oscillator, the oscillator will synchronize to it. In this synchronized mode, Burst Mode operation is disabled. The constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads.

When the oscillator’s internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal oscillator ramp is terminated early and the slope compensation is increased by approximately 30%. As a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an external frequency (above 1.3fO) can result in inadequate slope compensation and possible subharmonic oscillation (or jitter).

10µs/DIV 3704 F03

Figure 3. LTC3704 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current

Pulse-Skip Mode Operation

With the MODE/SYNC pin tied to a DC voltage above 2V, Burst Mode operation is disabled. The internal, 0.525V

The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal.

3704fa

LTC3704

WUUU

APPLICATIO S I FOR ATIO

MODE/

SYNC

GATE

MIN

= 25ns

D = 40%

0.8T

T T = 1/f

2V TO 7V

3404 F05

Figure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized Operation

Programming the Operating Frequency

The choice of operating frequency and inductor value is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET and diode switching losses. However, lower frequency operation requires more inductance for a given amount of load current.

The LTC3704 uses a constant frequency architecture that can be programmed over a 50kHz to 1000kHz range with a single external resistor from the FREQ pin to ground, as shown in Figure 1. The nominal voltage on the FREQ pin is

0.6V, and the current that flows into the FREQ pin is used to charge and discharge an internal oscillator capacitor. A graph for selecting the value of R

for a given operating

frequency is shown in Figure 6.

1000

100

(kΩ)

INTVCC Regulator Bypassing and Operation

An internal, P-channel low dropout voltage regulator produces the 5.2V supply which powers the gate driver and logic circuitry within the LTC3704, as shown in Figure 7. The INTV

regulator can supply up to 50mA and must be

bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7µF tantalum or ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver.

1.230V

–

DRIVER

P-CH

5.2V

INTV

GATE

GND

PLACE AS CLOSE AS

POSSIBLE TO DEVICE PINS

VCC

4.7µF

LOGIC

Figure 7. Bypassing the LDO Regulator and Gate Driver Supply

INPUT SUPPLY

2.5V TO 30V

GND

3704 F07

For input voltages that don’t exceed 7V (the absolute maximum rating for this pin), the internal low dropout regulator in the LTC3704 is redundant and the INTVCC pin can be shorted directly to the VIN pin. With the INTVCC pin shorted to VIN, however, the divider that programs the regulated INTV

voltage will draw 10µA of current from

the input supply, even in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. Regardless of whether the INTV

pin is shorted to VIN or not, it is

always necessary to have the driver circuitry bypassed with a 4.7µF tantalum or low ESR ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins.

200 1000

100

400

500

300

FREQUENCY (kHz)

800700600

900

3704 F06

Figure 6. Timing Resistor (RT) Value

In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. As a result, high input voltage applications in which a large power MOSFET is being driven at high frequencies can

3704fa

WUUU

APPLICATIO S I FOR ATIO

LTC3704

cause the LTC3704 to exceed its maximum junction temperature rating. The junction temperature can be estimated using the following equations:

≈ IQ + f • Q

Q(TOT)

PIC = VIN • (IQ + f • QG)

= TA + PIC • R

The total quiescent current I supply current (I

TH(JA)

consists of the static

Q(TOT)

) and the current required to charge and

discharge the gate of the power MOSFET. The 10-pin MSOP package has a thermal resistance of R

TH(JA)

120°C/W.

As an example, consider a power supply with V V

SW(MAX)

= 12V. The switching frequency is 500kHz, and

= 5V and

the maximum ambient temperature is 70°C. The power MOSFET chosen is the IRF7805, which has a maximum R

of 11mΩ (at room temperature) and a maximum

DS(ON)

total gate charge of 37nC (the temperature coefficient of the gate charge is low).

= 600µA + 37nC • 500kHz = 19.1mA

Q(TOT)

= 5V • 19.1mA = 95mW

TJ = 70°C + 120°C/W • 95mW = 81.4°C

This demonstrates how significant the gate charge current can be when compared to the static quiescent current in the IC.

To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high VIN. A tradeoff between the operating frequency and the size of the power MOSFET may need to be made in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their latest-and-greatest low QG, low R

devices. Power MOSFET manu-

DS(ON)

facturing technologies are continually improving, with newer and better performance devices being introduced almost yearly.

Output Voltage Programming

The output voltage is set by a resistor divider according to the following formula:

O REF NFB

where V

REF

⎛ ⎜

⎝

= –1.230V, and I

out of the NFB pin (I

⎞

+••1

⎟ ⎠

= –7.5µA). In order to properly

NFB

is the current which flows

NFB

dimension R2, including the effect of the NFB pin current, the following formula can be used:

−

21=

OUT REF

⎛

REF

⎜ ⎝

NFB

⎞ ⎟

⎠

The nominal 7.5µA current which flows out of the NFB pin has a production tolerance of approximately ±2.5µA, so an output divider current of 500µA (R1 = 2.49k) results in a

0.5% uncertainty in the output voltage. For low power applications where the output voltage tolerance is less important, efficiency can be increased by increasing the value of R1.

Programming Turn-On and Turn-Off Thresholds with the RUN Pin

The LTC3704 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off. The falling threshold voltage on the RUN pin is equal to the internal reference voltage of 1.248V. The comparator has 100mV of hysteresis to increase noise immunity.

The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas:

IN OFF

()

.•

1 248 1

⎛ ⎜

⎝

⎞ ⎟

⎠

IN ON

()

.•

1 348 1

⎛ ⎜

⎝

⎞ ⎟

⎠

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LTC3704

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APPLICATIO S I FOR ATIO

The resistor R1 is typically chosen to be less than 1M.

For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V

INPUT

SUPPLY

OPTIONAL

FILTER

CAPACITOR

–

Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

RUN

GND

Absolute Maximum Rating for this pin! The RUN pin can be connected to the input voltage through an external 1M resistor, as shown in Figure 8c, for “always on” operation.

RUN

COMPARATOR

–

1.248V

µPOWER

REFERENCE

BIAS AND START-UP CONTROL

3704 F08a

RUN

COMPARATOR

–

3704 F08b

EXTERNAL

LOGIC CONTROL

RUN

1.248V

Figure 8b. On/Off Control Using External Logic

RUN

GND

1.248V

–

COMPARATOR

INPUT

SUPPLY

R2 1M

–

Figure 8c. External Pull-Up Resistor On RUN Pin for “Always On” Operation

RUN

3704 F08c

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LTC3704

Applications Circuits

A simple positive-to-negative application circuit for the LTC3704 is shown in Figure 1. The basic operation of this circuit is shown in Figure 9. During the on-time the inductor currents flow through the switch, and during the off-time these currents flow through the output diode. The use of inductors in series with both the input and output results in continuous currents in these capacitors, resulting in low input and output noise. Discontinuous currents flow in the switch, the coupling capacitor, and the diode.

a) Current Flow During The Switch On-Time

OFF

b) Current Flow During The Switch Off-Time

Figure 9. Positive-to-Negative Converter Operation

L1 L2

+–

L1 L2

+–

OUT

3704 F09

Peak and Average Input and Switch Currents

The control loop in the LTC3704 is measuring the peak switch current (either by using the R

DS(ON)

of the power MOSFET or by using a sense resistor in the MOSFET source), so the output current needs to be reflected back to the switch in order to dimension the power MOSFET and inductors properly. Based on the fact that, ideally, the input power is equal to the output power, the maximum average input current is:

() ()

IN MAX O MAX

where I

–•

is a negative number. The peak input

O(MAX)

–=1

MAX

current is:

⎛

() ()

IN PEAK O MAX

= − +

⎞

⎜ ⎝

••

⎟ ⎠

–

MAX

In a positive-to-negative converter, however, the switch current is equal to I

+ IO, so the maximum average switch

current is:

SW MAX O MAX

() ()

•= −

−11

MAX

and the peak switch current is:

⎛

SW PEAK O MAX

() ()

= − +

The maximum duty cycle, D

⎞

⎜ ⎝

••

⎟ ⎠

, should be calculated at

MAX

–

MAX

minimum VIN.

Duty Cycle Considerations

For the positive-to-negative converter shown in Figure 1, the duty cycle of the main switch in CCM is:

–

OIN

where VO is a negative number. The maximum output voltage for this converter (in CCM) is:

O MAX IN MIN

() ()

MAX

• D

–=1

MAX

The maximum duty cycle capability of the LTC3704 is typically 92%.

Ripple Current ∆I

and the ‘χ’ Factor

The constant ‘χ’ in the equation above represents the percentage peak-to-peak total ripple current in the inductor, relative to its maximum value. For example, if 30% ripple current is chosen, then χ = 0.30, and the peak current is 15% greater than the average.

For a current mode converter operating in CCM, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. For the LTC3704, this ramp compensation is internal. Having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. If too large an inductor is used, the resulting current ramp (∆I

) will be small relative to the

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LTC3704

IN MIN

MAX

()

••

•

∆

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APPLICATIO S I FOR ATIO

internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). If too small an inductor is used, but the converter is still operating in CCM (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. To ensure good current mode gain and avoid subharmonic oscillation, it is recommended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average switch current. For example, if the maximum average switch current is 1A, choose a ∆I value ‘χ’ between 0.2 and 0.4.

between 0.2A and 0.4A, and a

⎞

⎛

L PEAK O MAX

() ()

L PEAK O MAX

= − +

() ()

= − +

⎜ ⎝

⎛

⎜ ⎝

••

⎟

⎠

⎞

•

⎟

⎠

–

MAX

where “χ” represents the percentage of ripple current. In a positive-to-negative converter, however, the switch current is the sum of the two inductor currents. Therefore,

⎞

⎛

SW PEAK O MAX

() ()

–••

⎟

⎜

⎠

⎝

–

MAX

Inductor Selection

Selecting inductors for a positive-to-negative converter is slightly more complicated than for a single-inductor topology like a buck or boost. The use of separate, uncoupled inductors can reduce the size of the solution, at the expense of input and output ripple. Using a coupled inductor complicates the design procedure, but can result in significantly lower input and/or output ripple. It will also reduce the number of components that the purchasing department has to keep track of.

Regardless of the design goals, however, the inductor selection process is an iterative one. The best recommendation is to use the equations as a guideline, and then to build a solution and measure the circuit’s performance. If the measured performance deviates from the design guidelines, substitute a bigger (or smaller) inductor, as appropriate, and repeat the measurements. In addition, do your best to minimize layout parasitics, which can have a significant effect on circuit performance.

The inductor currents for a positive-to-negative converter are calculated at full load current and minimum input voltage. The peak inductor currents can be significantly higher than the output current, especially with smaller inductors and lighter loads. The following formulae assume uncoupled inductors and CCM operation.

Since the control loop is looking at the switch current, and since the internal slope compensation is acting on this switch current, the ripple current percentage should be between 20% and 40% of the maximum average current at V

IN(MIN)

and I

. This corresponds to a value of “χ”

O(MAX)

in the equations above between 0.20 and 0.40. Expressing this ripple current as a function of the output current results in the following equation for calculating the inductor value:

12==

()

∆

•

MAX

•

IN MIN

where:

∆II

= –• •

SW O MAX

()

–

MAX

By using a coupled inductor with a 1:1 turns ratio, the value of inductance in the equation above can be replaced by 2L due to mutual inductance. Doing this maintains the same total ripple current and energy storage in the inductor. Substituting 2L yields the following equation for 1:1 coupled inductors:

For the case of uncoupled inductors, choose minimum saturation currents based on the peak currents outlined in

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DS ON

SENSE MAX

SW PEAK

()

≤

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APPLICATIO S I FOR ATIO

LTC3704

the initial equations for I

L1(PEAK)

and I

L2(PEAK)

. If a coupled inductor is used, make sure that the minimum saturation current for the parallel configuration exceeds the maximum switch current, or:

LSAT MIN O MAX

() ( )

–••

≥ +

⎜ ⎝

⎛

⎞

⎟

⎠

–

MAX

The saturation current rating should be checked at minimum input voltage (which results in the highest average inductor current) and maximum load current.

Operating in Discontinuous Mode

Discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in Figure 10. Once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1MHz to 10MHz. If the off-time is long enough, the drain voltage will settle to the input voltage.

Depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power MOSFET to go below ground where it is clamped by the body diode. This ringing is not harmful to the IC and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a snubber will degrade the efficiency.

Power MOSFET or Sense Resistor Selection

If the maximum voltage on the drain of the power MOSFET (which is V

IN(MAX)

+ V

, plus any transients) is less than

OUT

36V then the circuit can take advantage of the LTC3704’s No R

technology in order to improve efficiency and

SENSE

eliminate the sense resistor. For higher switch voltages the SENSE pin should be connected to a resistor in the source of the power MOSFET, as shown in Figure 2. Internal leading-edge blanking is provided in the LTC3704 to eliminate the need for filtering components on the SENSE pin.

In both positive-to-negative and flyback converters the maximum switch current is equal to the input current plus the output current. As a result, the peak switch current is:

⎞

⎛

SW PEAK O MAX

() ()

where I

O(MAX)

–••

⎟

⎜

⎠

⎝

is a negative number.

–

MAX

During the switch on-time, the control circuit limits the maximum voltage drop across the power MOSFET to 150mV (at low duty cycles). The peak switch current is therefore limited to 150mV/R

. The relationship be-

DS(ON)

tween the maximum load current, the duty cycle and the R

of the power MOSFET is:

DS(ON)

10V/DIV

1A/DIV

VIN = 15V NO LOAD

Figure 10. Discontinuous Mode Waveforms (MODE/SYNC = INTV for the Circuit in Figure 1.

1µs/DIV

, Pulse-Skip Mode)

3704 F10

DS ON SENSE MAX

again, where I

≤

() ( )

O(MAX)

•

⎛ ⎜

⎝

MAX

⎞

⎟

⎠

is a negative number. The V

−

••

OMAX

()

SENSE(MAX)

term is typically 150mV at low duty cycle, and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 11. The ρ counts for the temperature coefficient of the R

term ac-

DS(ON)

of the MOSFET, which is typically 0.4%/°C. Figure 12 illustrates the variation of R

over temperature for a typical

DS(ON)

power MOSFET (normalized for simplicity).

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APPLICATIO S I FOR ATIO

200

150

100

MAXIMUM CURRENT SENSE VOLTAGE (mV)

0.2

Figure 11. Maximum SENSE Threshold Voltage vs Duty Cycle

0.5

0.4 DUTY CYCLE

0.8

1.0

3704 F11

Another method of choosing which power MOSFET to use is to check the maximum output current for a given R

, since MOSFET on-resistances are generally

DS(ON)

available in discrete values.

–

() ()

O MAX SENSE MAX

–•

⎛

⎜ ⎝

MAX

⎞

••

DS ON

⎟

⎠

()

2.0

1.5

1.0

0.5

NORMALIZED ON RESISTANCE

–50

Figure 12. Normalized R

JUNCTION TEMPERATURE (°C)

100

vs Temperature

DS(ON)

150

3704 F12

As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the

troller is using the MOSFET as both a switching and a

con sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for V and the R

of the MOSFET listed in the manufacturer’s

DS(ON)

SENSE(MAX)

data sheet.

For the case where a conventional sense resistor is used,

–•1

SENSE SENSE MAX

()

•

MAX

⎞

⎛

⎜ ⎝

⎟ ⎠

O MAX

()

Sense resistors are generally low TC and are available with different ranges of tolerance depending on price. The power dissipated in the sense resistor is:

PI RD

SENSE SW PEAK SENSE MAX

()

••

Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures

In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its R

DS(ON)

The power dissipated by the MOSFET in a positive-tonegative converter is:

MAX

⎞

•••

()

DS ON MAX T

⎟

⎠

()

OMAX

185

–

••

RSS

MAX

FET

where I

⎛

–

OMAX

O(MAX)

()

⎜

–

⎝

kV V

•( – ) •

IN O

and VO are negative numbers.

The first term in the equation above represents the

R losses in the device, and the second term, the switch-

I ing losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current.

From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula:

TJ = TA + P

FET

• R

TH(JA)

3704fa

∆I

MAX O

= –

–

•

∆V

V L

ESR

OP P

MAX O

(–)

–

•

––

••

⎡

⎣

⎢

⎤

⎦

⎥

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APPLICATIO S I FOR ATIO

LTC3704

The R the R the case to the ambient temperature (R of T

can then be compared to the original, assumed value

to be used in this equation normally includes

TH(JA)

for the device plus the thermal resistance from

TH(JC)

). This value

TH(CA)

used in the iterative calculation process.

Output Diode Selection

To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. The output diode in a positive-to-negative converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to V

IN(MAX)

– VO. The average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current.

⎞

⎛

D PEAK O MAX

() ()

–•

⎟

⎜

⎠

⎝

–

MAX

The power dissipated by the diode is:

= I

O(MAX)

• V

and the diode junction temperature is:

= TA + PD • R

TH(JA)

1A/DIV

500ns/DIV

Figure 13. Ripple Current in the DC Coupling Capacitor

3704 F13

A low ESR and ESL, X5R- or X7R-type ceramic capacitor is recommended here.

Selecting the Output Capacitor

The output ripple voltage appears as a triangular waveform riding on V

, due to the ripple current of L2 (the DC

component of the current in L2 equals the output current). This ripple current flows through the ESR and bulk capacitance of the output capacitor to produce the overall ripple voltage on this node. Using the off-time to calculate this ripple current results in the following equation for ∆I

The R the R the board to the ambient temperature in the enclosure.

Remember to keep the diode lead lengths short and to observe proper switch-node layout (see Board Layout Checklist) to avoid excessive ringing and increased dissipation.

Selecting the DC Coupling Capacitor

The voltage on the coupling capacitor in a positive-tonegative converter is V due to the ripple currents in the inductors. Generally, the DC coupling capacitor is dimensioned based on the high RMS ripple which flows in it, as shown in Figure 13.

The minimum RMS current rating of this capacitor must exceed:

to be used in this equation normally includes

TH(JA)

for the device plus the thermal resistance from

TH(JC)

IN(MAX)

() ( )

RMS CAP O MAX

–•

– VO, plus any additional ∆V

MAX

–=1

MAX

where VO is a negative number. The output ripple voltage is therefore:

The ESR can be minimized by using high quality, X5R- or X7R-dielectric ceramic capacitor in parallel with a larger value tantalum or aluminum electrolytic bulk capacitor. Depending upon the application, it may be that the ceramic capacitor alone will be sufficient.

The RMS ripple current rating of the output capacitor needs to be greater than:

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LTC3704

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APPLICATIO S I FOR ATIO

RMS COUT

()

(– )

1121

•

MAX O

•≥

It should be noted that these equations assume no coupling between the inductors. If the inductors are wound on the same core, the ripple currents at the input and output can be tuned to very low values, and so the equations above would be extremely conservative. It is highly recommended that the user experiment in the lab with the same magnetics and capacitors which will be used in production.

Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This

Table 1. Recommended Component Manufacturers

VENDOR COMPONENTS TELEPHONE WEB ADDRESS

AVX Capacitors (207) 282-5111 avxcorp.com BH Electronics Inductors, Transformers (952) 894-9590 bhelectronics.com Coilcraft Inductors (847) 639-6400 coilcraft.com Coiltronics Inductors (407) 241-7876 coiltronics.com Diodes, Inc Diodes (805) 446-4800 diodes.com Fairchild MOSFETs (408) 822-2126 fairchildsemi.com General Semiconductor Diodes (516) 847-3000 generalsemiconductor.com International Rectifier MOSFETs, Diodes (310) 322-3331 irf.com IRC Sense Resistors (361) 992-7900 irctt.com Kemet Tantalum Capacitors (408) 986-0424 kemet.com Magnetics Inc Toroid Cores (800) 245-3984 mag-inc.com Microsemi Diodes (617) 926-0404 microsemi.com Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp Nichicon Capacitors (847) 843-7500 nichicon.com On Semiconductor Diodes (602) 244-6600 onsemi.com Panasonic Capacitors (714) 373-7334 panasonic.com Sanyo Capacitors (619) 661-6835 sanyo.co.jp Sumida Inductors (847) 956-0667 sumida.com Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com TDK Capacitors, Inductors (562) 596-1212 component.tdk.com Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com Tokin Capacitors (408) 432-8020 tokin.com Toko Inductors (847) 699-3430 tokoam.com United Chemicon Capacitors (847) 696-2000 chemi-com.com Vishay/Dale Resistors (605) 665-9301 vishay.com Vishay/Siliconix MOSFETs (800) 554-5565 vishay.com Vishay/Sprague Capacitors (207) 324-4140 vishay.com Zetex Small-Signal Discretes (631) 543-7100 zetex.com

makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design.

Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest product of ESR and size of any aluminum electrolytic, at a somewhat higher price.

In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application.

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LTC3704

Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. An excellent choice is AVX TPS series of surface mount tantalum. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings.

Input Capacitor Selection

The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10µF to 100µF. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor.

The RMS input capacitor ripple current for a positive-tonegative converter is:

IN MIN

RMS CIN

12 1

•

()

•

•=

MAX()

Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to

specify surge-tested capacitors!

causes the inductor current to quickly decay to zero. However, because ∆I the current to ramp back up to I

is small, it takes multiple cycles for

BURST(PEAK)

. During this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. Generally, it is a good idea to choose a value of inductor ∆I I

IN(MAX)

. The alternative is to either increase the value of

between 20% and 40% of

the output capacitor or disable Burst Mode operation using the MODE/SYNC pin.

Burst Mode operation can be defeated by connecting the MODE/SYNC pin to a high logic-level voltage (either with a control input or by connecting this pin to INTV

). In this

mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduction mode (CCM) at full load, down into deep discontinuous conduction mode (DCM) at light load. Prior to skipping pulses at very light load (i.e., < 5-10% of full load), the controller will operate with a minimum switch on-time in DCM. Pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple.

Checking Transient Response

Burst Mode Operation and Considerations

The choice of MOSFET R

and inductor value also

DS(ON)

determines the load current at which the LTC3704 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately:

BURST PEAK

()

DS ON

()

which represents about 20% of the maximum 150mV SENSE pin voltage. The corresponding average current depends upon the amount of ripple current. Lower inductor values (higher ∆IL) will reduce the load current at which Burst Mode operations begins, since it is the peak current that is being clamped.

The output voltage ripple can increase during Burst Mode operation if ∆IL is substantially less than I

BURST

. This can occur if the input voltage is very low or if a very large inductor is chosen. At high duty cycles, a skipped cycle

The regulator loop response can be verified by looking at the load transient response. Switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. When the load step occurs, VO immediately shifts by an amount equal to (∆I and then C

begins to charge or discharge (depending on

LOAD

)(ESR),

the direction of the load step) as shown in Figure 14. The

(AC)

OUT

100mV/DIV

OUT

= –5V

0.5A

250µs/DIV

3704 F14

3704fa

(DC)

OUT

1A/DIV

VIN = 5V V

Figure 14. Load Step Response for the Circuit in Figure 1.

LTC3704

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APPLICATIO S I FOR ATIO

regulator feedback loop acts on the resulting error amp output signal to return V this recovery time, V

to its steady-state value. During

can be monitored for overshoot or

ringing that would indicate a stability problem.

A second, more severe transient can occur when connecting loads with large (> 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C

, causing a nearly instantaneous drop in VO. No

regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load.

Design Example: A 5V to 15V Input, –5V at 2A Output Positive-to-Negative Converter

The design example presented here will be for the circuit shown in Figure 1. The input voltage range is 5V to 15V, and the output is -5V. The maximum load current is 2A at an input voltage of 5V (3A peak), and 3A at an input voltage of 15V (5A peak).

IN MIN

()

∆

••

==µ

208300

•.•

•

MAX

05 52

•. .

The minimum saturation current for this inductor is:

–

MAX

⎛

LSAT MIN O MAX

() ( )

–••

≥ +

12 20

⎞

⎜

⎟

⎝

⎠

.•.•

–.

105

The inductor chosen is a BH Electronics part # 510-1009, which has an open circuit parallel inductance of 4.56µH and a maximum dc current rating of 6.5A.

5. For the power MOSFET,

–

DS ON SENSE MAX

≤

() ( )

•

⎛

⎜ ⎝

MAX

⎞

••

⎟

OMAX

()

⎠

1. The maximum duty cycle of the main switch is:

–

MAX

OUT

−

OUT IN MIN

()

–

2. Pulse-Skip operation is chosen, so the MODE/SYNC pin is connected to the INTV

pin.

3. The operating frequency is chosen to be 300kHz to reduce the size of the inductors. From Figure 5, the resistor from the FREQ pin to ground is 80.6k.

4. A total inductor ripple current of 40% of the maximum is chosen, so the inductor ripple current is:

∆ = −

∆ ==

χ ••

LOMAX

L11

()

04 20

.•.•

105

–

–.

MAX

For a standard 1:1 coupled inductor, the inductance is therefore:

At the maximum duty cycle of 50%, the maximum SENSE pin voltage is reduced to 130mV due to slope compensation, as shown in Figure 11. Assuming a maximum junction temperature of 125°C for the power MOSFET,

= 1.5, and

.–

DS ON()

.•

05 1

–. • . •.

12 20 15

.≤ = Ω0 130

18 1

The MOSFET chosen was Siliconix/Vishay’s Si4884, which has a maximum R The minimum BV is Q

= 20nC.

DSS

= 16.5mΩ at VGS = 4.5V at 25°C.

DS(ON)

= 30V and the maximum gate charge

6. The output diode must withstand a reverse voltage of V

IN(MAX)

O(MAX)

– VO = 20V and a continuous current of

= 5.0A (peak output current at VIN = 15V). The peak

current in the diode is:

IIA

D PEAK O MAX() ()

⎛ ⎜

⎝

⎞

•=+

⎟ ⎠

The power dissipated in this diode at full load is:

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APPLICATIO S I FOR ATIO

LTC3704

PD = I

O(MAX)

• V

Assuming a maximum junction temperature of 125°C and a forward voltage of approximately 0.33V at 3A (the maximum output current at V

= 15V), this diode will

dissipate 1W at full load. The diode selected was the MBRD835L from On Semiconductor, packaged in a D-Pak.

4.7nF

1nF

68.1k 1%

SS1

750Ω

154k

80.6k 1%

1.21k

RUN

NFB

FREQ

MODE/SYNC

FB1

LTC3704

FB2

3.65k 1%

SENSE

INTV

GATE

GND

7. The DC coupling capacitor must be capable of handling an RMS current of:

() ()

D PEAK O MAX

VCC

4.7µF X5R

–•

•

L1*

47µF

X5R

47µF X5R

L2*

3704 F15

–

MAX

5V to 15V

OUT

–5.0V 2A to 3A (5A PEAK)

OUT

100µF X5R (X2)

GND

SS2

100Ω

Figure 15. 5V to 15V Input, –5V Output at 2A-3A(5A Peak) Positive-to-Negative Converter with Soft-Start and Undervoltage Lockout.

100

EFFICIENCY (%)

0.001

VIN = 5V

VIN = 15V

VIN = 10V

FET = Si4884 L = BH510-1009

= –5V

FREQ = 300kHz

0.01 1

0.1

OUTPUT CURRENT (A)

3704 F16

Figure 16. Efficiency vs Output Current

10nF

: TDK C5750X5R1C476M

: TDK C5750X7R1C476M

: TDK C5750X5R0J107M

OUT

: TAIYO YUDEN LMK316BJ475ML

VCC

(A)

O(MAX)

D1: ON SEMICONDUCTOR MBRD835L D2: CDMSH-3 L1, L2: BH ELECTRONICS BH510-1009 M1: SILICONICS/VISHAY Si4884 Q1: MMBT3904

510

INPUT VOLTAGE (V)

3704 F17

Figure 17. Maximum Output Current vs Input Voltage

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LTC3704

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APPLICATIO S I FOR ATIO

(AC)

OUT

10mV/DIV

(AC)

OUT

100mV/DIV

(DC)

1A/DIV

(AC)

OUT

100mV/DIV

(DC)

OUT

1A/DIV

VIN = 5V

= –2V

OUT

1µs/DIV

3704 F18

Figure 18. Output Ripple Voltage and Inductor Current for the Circuit in Figure 15

0.5A

VIN = 15V

Figure 20. Load Step Response at V

250µs/DIV

3704 F20

= 15V

for the Circuit in Figure 15

OUT

(DC)

1A/DIV

VIN = 5V

0.5A

250µs/DIV

Figure 19. Load Step Response at V for the Circuit in Figure 15

OUT

1V/DIV

OUT

1A/DIV

VIN = 5V

OUT

1ms/DIV

Figure 21. Soft-Start for the Circuit in Figure 15

3704 F19

3704 F21

= 5V

The capacitor used was a TDK 47µF, 16V X5R-dielectric ceramic (C5750X5R1C476M), mainly because of its low ESR (2.4mΩ) and high RMS current capability.

8. The peak-to-peak output ripple is:

∆V

OP P

()

−

⎡

––

ESR

⎢ ⎣

••

MAX O

• L

⎤ ⎥ ⎦

–

As a first try, a TDK 100µF, 6.3V X5R-dielectric ceramic capacitor was chosen (C5750X5R0J107M). This capacitor has a very low 1.6mΩ of ESR. As a result, the peak-topeak output ripple voltage is:

105

∆V

OP P()

−

⎡

0 0016

–. –

⎢ ⎣

–.•.

3005035

8 300 100

••

⎤

13 7

⎥

⎦

This ripple voltage calculation also assumes no coupling between the inductors, making the 13.7mV number very conservative.

Figure 15 illustrates the same basic application shown in Figure 1, with the added features of soft-start and undervoltage lockout on the input supply. Figures 16 through 21 illustrate the measured performance for this converter. The peak efficiency is 87% at a load current of 2A and the peak-to-peak output ripple is less than 10mV. Figures 19 and 20 illustrate the load step response at 5V and 15V input, and Figure 21, the start-up characteristics with a resistive load.

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APPLICATIO S I FOR ATIO

LTC3704

PC Board Layout Checklist

1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC3704 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the

PIN 1

LTC3704

VCC

OUT

SIGNAL GROUND

PSEUDO-KELVIN

CONNECTION

source of the power MOSFET or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance.

TRUE REMOTE

OUTPUT SENSING

VIAS TO GROUND PLANE

Figure 22. LTC3704 Positive-to-Negative Converter Suggested Layout

PSEUDO-KELVIN

GROUND CONNECTION

BOLD LINES INDICATE HIGH CURRENT PATHS

RUN

LTC3704

NFB

FREQ

MODE/ SYNC

SENSE

INTV

GATE

GND

OUT

3704 F??

OUT

VCC

OUT

GND

3704 F23

Figure 23. LTC3704 Positive-to-Negative Converter Layout Diagram

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LTC3704

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APPLICATIO S I FOR ATIO

2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane is to be used for high DC currents, choose a path away from the small-signal components.

3. Place the C INTV carries high di/dt MOSFET gate drive currents. A low ESR X5R-dielectric 4.7µF ceramic capacitor works well here.

4. The high di/dt loop from the drain of the power MOSFET, through the coupling capacitor and back through the diode to ground should be kept as tight as possible to reduce inductive ringing. Excess inductance can cause increased stress on the power MOSFET and increase HF noise on the drain node. It is also important to keep the cathode of the diode as close as possible to the MOSFET source or the bottom of the sense resistor.

5. Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. Not all MOSFETs are created equal (some are more equal than others).

and GND pins on the IC package. This capacitor

capacitor immediately adjacent to the

VCC

6. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 22, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. This also allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTV small-signal currents flow in the other direction.

7. If a sense resistor is used in the source of the power MOSFET, minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC3704 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications.

8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC3704 in order to keep the high impedance FB node short.

9. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC3704 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC3704. A few inches of PC trace or wire (L ≈ 100nH) between the C V

should be sufficient to prevent current sharing

problems.

of the LTC3704 and the actual source

decoupling capacitor) and

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APPLICATIO S I FOR ATIO

RUN

LTC3704

80.6k 1%

2.49k

NFB

FREQ

MODE/SYNC

FB1

FB2

13.7k 1%

14.7k

4.7nF

D1: DIODES INC B320B L1, L2: BH ELECTRONICS BH 510-1009 M1: SILICONIX Si9426

SENSE

INTV

GATE

GND

LTC3704

3V to 5V

OUT

3704 F24

–8.0V

1.2A to 2.5A

OUT

100µF X5R

GND

•

L1*

VCC

4.7µF X5R

47µF X5R

22µF

X5R

L2*

Figure 24. 3V to 5V Input, –8V at 1.2A Output Converter

(A)

O(MAX)

3.0

3.5

4.0

INPUT VOLTAGE (V)

4.5

5.0

3704 F25

Figure 25. Maximum Output Current vs Input Voltage

(AC)

OUT

100mV/DIV

100

EFFICIENCY (%)

0.001

0.01 1 OUTPUT CURRENT (A)

VIN = 5V

VIN = 3V

0.1

Figure 26. Output Efficiency at 3V and 5V Input

(AC)

OUT

100mV/DIV

3704 F26

(DC)

OUT

0.5A/DIV

1.2A

VIN = 3V

0.6A

250µs/DIV

3704 F27

(DC)

OUT

0.5A/DIV

1.2A

VIN = 3V

Figure 28.Load Step Response at 5V InputFigure 27. Load Step Response at 3V Input

0.6A

250µs/DIV

3704 F27

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LTC3704

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APPLICATIO S I FOR ATIO

UV + = 5.4V

100pF

82k

1nF

49.9k 1%

UV – = 5.0V

120k

FB1

2.49k 1%

150k

RUN

LTC3704

NFB

FREQ

MODE/SYNC



f = 200kHz

45.3k 1%

FB2

SENSE

INTV

GATE

GND

* VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL)

GND

•

10BQ060

7V TO 12V

220µF 16V TPS

4.7µF 10V X5R

IRL2910

0.012Ω

T1*

1, 2, 3

•

10BQ060

•

10BQ060

4.7µF 50V X5R

10µF 25V X5R

OUT1

–24V 200mA

10µF 25V X5R

3704 F29

OUT

3.3µF 100V

OUT2

–72V 200mA

Figure 29. High Power SLIC Supply

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PACKAGE DESCRIPTIO

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889 ± 0.127 (.035 ± .005)

LTC3704

5.23

(.206)

MIN

0.305 ± 0.038

(.0120 ± .0015)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.254

(.010)

GAUGE PLANE

0.18

(.007)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3.2 – 3.45

(.126 – .136)

DETAIL “A”

0.50

(.0197)

BSC

° – 6° TYP

0.53 ± 0.01

(.021 ± .006)

SEATING

PLANE

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

4.88 ± 0.10

(.192 ± .004)

0.17 – 0.27

(.007 – .011)

1.10

(.043)

MAX

0.50

(.0197)

TYP

0.497 ± 0.076

(.0196 ± .003)

REF

3.00 ± 0.102

(.118 ± .004)

NOTE 4

0.86

(.034)

REF

0.13 ± 0.05

(.005 ± .002)

MSOP (MS) 1001

8910

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3704fa

LTC3704

TYPICAL APPLICATIO

High Efficiency Positive-to-Negative Converter

1nF

OPTIONAL

68.1k 1%

9.1k

330pF

10nF

1.21k 1%

RELATED PARTS

80.6k 1%

3.65k 1%

RUN

NFB

FREQ

MODE/SYNC

: TDK C5570X5R1C476M

OUT1

OUT2

: TDK C5750X7R1E226M

VCC

154k

SENSE

LTC3704

INTV

GATE

GND

: TDK C5750X5R0J107M : PANASONIC EEFUE0J151R

: TDK C2012X5R0J475K

L1*

22µF

25V

X7R

L2*

OUT1

100µF

6.3V

3704 TA02

47µF

16V

VCC

4.7µF

D1: FAIRCHILD MBR2035CT L1, L2: COILTRONICS VP5-0053 (*COUPLED INDUCTORS, WITH 3 WINDINGS IN PARALLEL ON PRIMARY AND SECONDARY) M1: INTERNATIONAL RECTIFIER IRF7822

5V TO 15V

OUT

–5V 5A

OUT2

150µF

6.3V

GND

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SENSE

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SENSE

Programmable f

from 50kHz to 1MHz

OSC

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5-Lead ThinSOT

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ThinSOT is a trademark of Linear Technology Corporation.

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

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LT 0306 • PRINTED IN USA

Datasheet LTC3704 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual