14-Bit ADC for Monitoring System Voltages/Currents,
Capacitance and ESR
n
Active Overvoltage Protection Shunts
n
Internal Active Balancers—No Balance Resistors
n
VIN: 4.5V to 35V, V
: Up to 5V per Capacitor,
CAP(n)
Charge/Backup Current: 10+A
n
Programmable Input Current Limit Prioritizes System
Load Over Capacitor Charge Current
n
Dual Ideal Diode PowerPath™ Controller
n
All N-FET Charger Controller and PowerPath Controller
n
Compact 38-Lead 5mm × 7mm QFN Package
applicaTions
n
High Current 12V Ride-Through UPS
n
Servers/Mass Storage/High Availability Systems
The LT C®3350 is a backup power controller that can charge
and monitor a series stack of one to four supercapacitors.
The LTC3350’s synchronous step-down controller drives
N-channel MOSFETs for constant current/constant voltage
charging with programmable input current limit. In addition,
the step-down converter can run in reverse as a step-up
converter to deliver power from the supercapacitor stack
to the backup supply rail. Internal balancers eliminate the
need for external balance resistors and each capacitor has
a shunt regulator for overvoltage protection.
The LTC3350 monitors system voltages, currents, stack
capacitance and stack ESR which can all be read over
2
C/SMBus. The dual ideal diode controller uses
the I
N-channel MOSFETs for low loss power paths from the
input and supercapacitors to the backup system supply.
The LTC3350 is available in a low profile 38-lead 5mm ×
7mm × 0.75mm QFN surface mount package.
L, LT , LT C , LT M, Linear Technology and the Linear logo are registered trademarks and
PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents pending.
Typical applicaTion
High Current Supercapacitor Charger and Backup Supply
(STEP-DOWN)I
I
CHG
V
IN
INFET VOUTSP VOUTSN
PFIOUTFB
OUTFET
TGATE
SW
BGATE
LTC3350
ICAP
VCAP
I2C
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
V
< V
CAP
(STEP-UP)
BACKUP
OUT
10F
10F
10F
10F
3350 TA01a
> V
V
CAP
(DIRECT
CONNECT)
V
CAP
V
OUT
Backup Operation
P
= 25W
BACKUP
OUT
V
OUT
2V/DIV
V
CAP
2V/DIV
V
IN
2V/DIV
0V
BACK PAGE APPLICATION CIRCUIT
V
IN
400ms/DIV
V
OUT
V
CAP
3350 TA01a
3350fc
For more information www.linear.com/LTC3350
1
Page 2
LTC3350
Table oF conTenTs
Features ..................................................... 1
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
JMAX
39
PGND
17 18 19
CAP3
CAP4
CFP
CAP2
UHF PACKAGE
= 125°C, θJA = 34°C/W
LTC3350
VOUTM5
31
VOUTSP
VOUTSN
30
INTV
29
DRV
28
BGATE
27
BST
26
TGATE
25
SW
24
VCC2P5
23
22
ICAP
21
VCAP
20
OUTFET
CFN
VCAPP5
CC
CC
orDer inForMaTion
LEAD FREE FINISHTAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE
LTC3350EUHF#PBFLTC3350EUHF#TRPBF3350
LTC3350IUHF#PBFLTC3350IUHF#TRPBF3350
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LT C Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
–40°C to 125°C
–40°C to 125°C
3350fc
For more information www.linear.com/LTC3350
3
Page 4
LTC3350
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
noted.
Regulated Input Current Sense Voltage
(VOUTSP – VOUTSN)
Regulated Charge Current Sense Voltage
V
CAP
= 10V
(ICAP – VCAP)
Common Mode Range (ICAP, VCAP)020V
Peak Inductor Current Sense Voltage
Reverse Inductor Current Sense VoltageStep-Down Mode
ICAP Pin CurrentStep-Down Mode, V
Step-Up Mode, V
V
Voltage Loop Transconductance1mmho
CAP
SNSC
= 32mV
SNSC
= 32mV
Charge Current Loop Transconductance64μmho
Input Current Loop Transconductance64μmho
V
Voltage Loop Transconductance400μmho
OUT
Switching FrequencyRT = 107k
Maximum Programmable Frequency R
Minimum Programmable FrequencyR
= 53.6k1MHz
T
= 267k200kHz
T
= 12V, V
OUT
l
l
l
l
l
l
l
l
l
l
l
l
l
l
DRVCC
= V
unless otherwise
INTVCC
4.535V
1.188
1.176
1.200
1.200
1.212
1.224
–5050nA
1.188
1.176
1.200
1.200
1.212
1.224
–5050nA
4.535V
3.85
3.75
4.3
4
4.2
3.9
4.45V
4.35V
145 55185 90225
125
37.7
36.3
38.6
37.2
39.5
38.1
mV
mV
≤ 20V 5V
31.36
l
31.04
31.36
l
31.04
l
l
3.867710mV
495
l
490
32.00
32.00
32.00
32.00
32.64
32.96
32.64
32.96
mV
mV
mV
mV
515865mV
30
135
500
500
505
510
µA
µA
kHz
kHz
V
V
V
V
V
V
V
V
4
3350fc
For more information www.linear.com/LTC3350
Page 5
LTC3350
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
noted.
PFI Falling to PFO Low Delay85ns
PFI Rising to PFO High Delay0.4μs
CAPGD Rising Threshold as % of Regulated V
CAP
V
capfb_dac
= Full Scale (1111b)
Feedback Voltage
CAPGD Hysteresis at CAPFB as a % of Regulated
V
Feedback Voltage
CAP
CAPGD Output Low VoltageI
CAPGD High-Z Leakage CurrentV
V
SINK
= Full Scale (1111b)1.25%
capfb_dac
= 5mA200mV
= 5V
CAPGD
= 12V, V
OUT
DRVCC
97
87
= V
unless otherwise
INTVCC
98
93
99.5%
= 3.3nF 0.13µs
= 3.3nF0.26µs
l
1.1471.171.193V
l
–5050nA
l
l
909294%
l
1μA
1μA
%
For more information www.linear.com/LTC3350
3350fc
5
Page 6
LTC3350
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
noted.
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Analog-to-Digital Converter
V
RES
V
GPI
I
GPI
R
GPI
Measurement System Error
V
ERR
CAP1 to CAP4
R
SHNT
DV
CAPMAX
Programming Pins
V
ITST
2
C/SMBus – SDA, SCL, SMBALERT
I
I
IL,SDA,SCL
I
IH,SDA,SCL
V
IH
V
IL
f
SCL
t
LOW
t
HIGH
t
BUF
t
HD,STA
t
SU,STA
Measurement Resolution16Bits
General Purpose Input Voltage RangeUnbuffered
Buffered
General Purpose Input Pin Leakage CurrentBuffered Input 1 μA
GPI Pin ResistanceBuffer Disabled2.5MΩ
Measurement Error (Note 5)VIN = 0V
V
= 30V
IN
= 5V
V
OUTSP
V
= 30V
OUTSP
= 0V
V
CAP
V
= 10V
CAP
= 0V, Unbuffered
V
GPI
V
= 3.5V, Unbuffered
GPI
= 0V
V
CAP1
V
= 2V
CAP1
= 0V
V
CAP2
V
= 2V
CAP2
= 0V
V
CAP3
V
= 2V
CAP3
= 0V
V
CAP4
V
= 2V
CAP4
= 0mV
V
SNSI
V
= 32mV
SNSI
= 0mV
V
SNSC
V
= 32mV
SNSC
Shunt Resistance0.5Ω
Maximum Capacitor Voltage with Shunts Enabled 2 or More Capacitors in Stack3.6V
ITST VoltageR
= 121Ω1.1851.1971.209V
TST
Input Leakage Low–11µA
Input Leakage High–11µA
Input High Threshold1.5V
Input Low Threshold0.8V
SCL Clock Frequency400kHz
Low Period of SCL Clock1.3µs
High Period of SCL Clock0.6µs
Bus Free Time Between Start and Stop Conditions1.3µs
Hold Time, After (Repeated) Start Condition0.6µs
Setup Time After a Repeated Start Condition0.6µs
= 12V, V
OUT
DRVCC
0
0
= V
unless otherwise
INTVCC
5
3.5
100
1.5
100
1.5
100
1.5
2
1
2
1
2
1
2
1
2
1
200
2
200
2
V
V
mV
%
mV
%
mV
%
mV
%
mV
%
mV
%
mV
%
mV
%
µV
%
µV
%
6
3350fc
For more information www.linear.com/LTC3350
Page 7
LTC3350
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = V
noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3350 is tested under pulsed load conditions such that
T
≈ TA. The LTC3350E is guaranteed to meet specifications from
J
0°C to 125°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3350I is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
Note 3: The LTC3350 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125˚C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications Information
section.
Note 5: Measurement error is the magnitude of the difference between the
actual measured value and the ideal value. V
VOUTSP and VOUTSN, representing input current. V
between ICAP and VCAP, representing charge current. Error for V
V
is expressed in μV, a conversion to an equivalent current may be
SNSC
made by dividing by the sense resistors, R
(TJ, in °C) is calculated from the ambient temperature (TA, in °C) and
power dissipation (P
T
= TA + (PD • θJA)
J
where θ
= 34°C/W for the UHF package.
JA
, in Watts) according to the formula:
D
Typical perForMance characTerisTics
TA = 25°C, Application Circuit 4 unless otherwise noted.
is the voltage between
SNSI
SNSI
and R
is the voltage
SNSC
, respectively.
SNSC
SNSI
and
Supercapacitor Backup OperationHV Electrolytic Backup OperationShunt Operation Using V
SCL (Pin 1): Clock Pin for the I2C/SMBus Serial Port.
2
SDA (Pin 2): Bidirectional Data Pin for the I
C/SMBus
Serial Port.
SMBALERT (Pin 3): Interrupt Output. This open-drain
output is pulled low when an alarm threshold is exceeded,
and will remain low until the acknowledgement of the part’s
response to an SMBus ARA.
CAPGD (Pin 4): Capacitor Power Good. This open-drain
output is pulled low when CAPFB is below 92% of its
regulation point.
VC (PIN 5): Control Voltage Pin. This is the compensation
node for the charge current, input current, supercapacitor
stack voltage and output voltage control loops. An RC
network is connected between VC and SGND. Nominal
voltage range for this pin is 1V to 3V.
CAPFB (Pin 6): Capacitor Stack Feedback Pin. This pin
closes the feedback loop for constant voltage regulation.
An external resistor divider between VCAP and SGND with
the center tap connected to CAPFB programs the final
supercapacitor stack voltage. This pin is nominally equal
to the output of the V
DAC when the synchronous
CAP
controller is in constant voltage mode while charging.
RT (Pin 9): Timing Resistor. The switching frequency of
the synchronous controller is set by placing a resistor, R
,
T
from this pin to SGND. This resistor is always required.
If not present the synchronous controller will not start.
GPI (Pin 10): General Purpose Input. The voltage on this
pin is digitized directly by the ADC. For high impedance
inputs an internal buffer can be selected and used to drive
the ADC. The GPI pin can be connected to a negative
temperature coefficient (NTC) thermistor to monitor the
temperature of the supercapacitor stack.
resistor
is required from INTV
to GPI and a thermistor
CC
A low drift bias
is required from GPI to ground. Connect GPI to SGND if
not used. The digitized voltage on this pin can be read in
the meas_gpi register.
ITST (Pin 11): Programming Pin for Capacitance Test Cur
rent. This
tor
This
A resistor, R
current. R
current is used to partially discharge the capaci-
stack at a precise rate for capacitance measurement.
pin servos to 1.2V during a capacitor measurement.
, from this pin to SGND programs the test
TST
must be at least 121Ω.
TST
-
CAPRTN (Pin 12): Capacitor Stack Shunt Return Pin. This
pin is connected to the grounded bottom plate of the first
super capacitor in the stack through a shunt resistor.
OUTFB (Pin 7): Step-Up Mode Feedback Pin. This pin
closes the feedback loop for voltage regulation
of V
OUT
during input power failure using the synchronous controller
in step-up mode. An external resistor divider between
and SGND with the center tap connected to OUTFB
V
OUT
programs the minimum backup supply rail voltage when
input power is unavailable. This pin is nominally 1.2V when
in backup and the synchronous controller is not in current
limit. To disable step-up mode tie OUTFB to INTV
CC
.
SGND (Pin 8): Signal Ground. All small-signal and compensation components
should be connected to this pin,
which in turn connects to PGND at one point. This pin
should also Kelvin to the bottom plate of the capacitor stack.
CAP1 (Pin 13): First Supercapacitor Pin. The top plate of
the first supercapacitor and the bottom plate of the second
supercapacitor are connected to this pin through a shunt
resistor. CAP1 and CAPRTN are used to measure the voltage
across the first super capacitor and to shunt current around
the capacitor to provide balancing and prevent overvoltage.
The voltage between this pin and CAPRTN is digitized and
can be read in the meas_vcap1 register.
CAP2 (
Pin 14): Second Supercapacitor Pin. The top plate
of the second supercapacitor and the bottom plate of the
third supercapacitor are connected to this pin through a
shunt resistor. CAP2 and CAP1 are used to measure the
voltage across the second supercapacitor and to shunt
3350fc
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For more information www.linear.com/LTC3350
Page 11
pin FuncTions
LTC3350
current around the capacitor to provide balancing and
prevent overvoltage. If not used this pin should be shorted
to CAP1. The voltage between this pin and CAP1 is digitized
and can be read in the meas_vcap2 register.
CAP3 (Pin 15): Third Supercapacitor Pin. The top plate of
the third supercapacitor and the bottom plate of the fourth
supercapacitor are connected to this pin through a shunt
resistor. CAP3 and CAP2 are used to measure the voltage
across the third supercapacitor and to shunt current around
the capacitor to provide balancing and prevent overvoltage.
If not used this pin should be shorted to CAP2. The voltage
between this pin and CAP2 is digitized and can be read in
the meas_vcap3 register.
CAP4 (Pin 16): Fourth Supercapacitor Pin. The top plate of
the fourth supercapacitor is connected to this pin through
a shunt resistor. CAP4 and CAP3 are used to measure
the voltage on the capacitor and to shunt current around
the supercapacitor to provide balancing and prevent
overvoltage. If not used this pin should be shorted to CAP3.
The voltage between this pin and CAP3 is digitized and
can be read in the meas_vcap4 register. The capacitance
current set by the ITST pin is pulled from this pin.
test
CFP (Pin 17): VCAPP5 Charge Pump Flying Capacitor
Positive Terminal. Place a 0.1μF between CFP and CFN.
CFN (Pin 18): VCAPP5 Charge Pump Flying Capacitor
Negative Terminal. Place a 0.1μF between CFP and CFN.
VCAPP5 (Pin 19): Charge Pump Output. The internal
charge pump drives this pin to VCAP + INTV
which is
CC
used as the high side rail for the OUTFET gate drive and
charge current sense amplifier. Connect a 0.1μF capacitor
from VCAPP5 to VCAP.
CAP
-
.
OUTFET (Pin 20): Output Ideal Diode Gate Drive Out
put. This
MOSFET
pin controls the gate of an external N-channel
used as an ideal diode between V
OUT
and V
The gate drive receives power from the internal charge
pump output VCAPP5. The source of the N-channel
MOSFET should be connected to VCAP and the drain should
be connected to VOUTSN. If the output ideal diode MOSFET
is not used, OUTFET should be left floating.
VCAP (Pin 21): Supercapacitor Stack Voltage and Charge
Current Sense Amplifier Negative Input. Connect this pin
to the top of the supercapacitor stack. The voltage at this
pin is digitized and can be read in the meas_
vcap register.
ICAP (Pin 22): Charge Current Sense Amplifier Positive
Input. The ICAP and VCAP pins measure the voltage across
the sense resistor, R
, to provide instantaneous cur-
SNSC
rent signals for the control loops and ESR measurement
system. The maximum charge current is 32mV/R
SNSC
.
VCC2P5 (Pin 23): Internal 2.5V Regulator Output. This
regulator provides power to the internal logic circuitry.
Decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
SW (Pin 24): Switch Node Connection to the Inductor.
The negative terminal of the boot-strap capacitor, C
B
, is
connected to this pin. The voltage on this pin is also used
as the source reference for the top side N-channel MOS
FET gate drive. In step-down mode, the voltage swing on
this pin is from a diode (external) forward voltage below
ground to V
ground to a diode forward voltage above V
. In step-up mode the voltage swing is from
OUT
.
OUT
TGATE (Pin 25): Top Gate Driver Output. This pin is the
output of a floating gate driver for the top external N-channel
MOSFET. The voltage swing at this pin is ground to V
CC
.
+ DRV
OUT
BST (Pin 26): TGATE Driver Supply Input. The positive
terminal
of the boot-strap capacitor, C
, is connected to
B
this pin. This pin swings from a diode voltage drop below
DRV
up to V
CC
+ DRVCC.
OUT
BGATE (Pin 27): Bottom Gate Driver Output. This pin
drives the bottom external N-channel MOSFET between
PGND and DRV
(Pin 28): Power Rail for Bottom Gate Driver. Con-
DRV
CC
nect to INTV
.
CC
or to an external supply. Decouple this pin
CC
to ground with a minimum 2.2μF low ESR tantalum or
ceramic capacitor. Do not exceed 5.5V on this pin.
For more information www.linear.com/LTC3350
3350fc
11
Page 12
LTC3350
pin FuncTions
INTVCC (Pin 29): Internal 5V Regulator Output. The control
circuits and gate drivers (when connected to DRV
powered from this supply. If not connected to DRV
CC
) are
CC
,
decouple this pin to ground with a minimum 1μF low ESR
tantalum or ceramic capacitor.
VOUTSN (Pin 30): Input Current Limiting Amplifier Nega
tive Input. A sense resistor, R
, between VOUTSP and
SNSI
-
VOUTSN sets the input current limit. The maximum input
current is 32mV/R
. An RC network across the sense
SNSI
resistor can be used to modify loop compensation. To
disable input current limit, connect this pin to VOUTSP.
VOUTSP (Pin 31): Backup System Supply Voltage and
Input Current Limiting Amplifier Positive Input. The voltage
across the VOUTSP and VOUTSN pins are used to regulate
input current. This pin also serves as the power supply
for the IC. The voltage at this pin is digitized and can be
read in the meas_vout register.
VOUTM5 (Pin 32): V
lated to 5
V below V
– 5V Regulator. This pin is regu-
OUT
or to ground if V
OUT
< 5V. This
OUT
rail provides power to the input current sense amplifier.
Decouple this pin with at least 1μF to V
OUT
.
INFET (Pin 33): Input Ideal Diode Gate Drive Output. This
controls the gate of an external N-channel MOSFET
pin
used as an ideal diode between V
and V
IN
. The gate
OUT
drive receives power from an internal charge pump. The
source of the N-channel MOSFET should be connected
and the drain should be connected to VOUTSP. If
to V
IN
the input ideal diode MOSFET is not used, INFET should
be left floating.
(Pin 34): External DC Power Source Input. Decouple
V
IN
this pin with at least 0.1μF to ground. The voltage at this
pin is digitized and can be read in the meas_vin register.
CAP_SLCT0, CAP_SLCT1 (Pins 35, 36): CAP_SLCT0 and
CAP_SLCT1 set the number of super-capacitors used.
Refer to Table 1 in the Applications Information section.
PFI (Pin 37): Power-Fail Comparator Input. When the
voltage at this pin drops below 1.17V, PFO is pulled low
and step-up mode is enabled.
PFO (Pin 38): Power-Fail Status Output. This open-drain
output is pulled low when a power fault has occurred.
PGND (Exposed Pad Pin 39): Power Ground. The exposed
pad must be connected to a continuous ground plane on
the second layer of the printed circuit board by
directly
under the LTC3350 for rated thermal performance.
several vias
It must be tied to the SGND pin.
12
3350fc
For more information www.linear.com/LTC3350
Page 13
block DiagraM
3433313230201718
INFETVOUTSPVOUTM5VOUTSN
IN
+
–
+
–
D/A
vcapfb_dac[3:0]
CAPFB
6
OUTFB
7
VC
5
RT
9
INTV
29
V
30mV
V
REF
CC
V
–
REF
x37.5
+
Vcapfb_dac
V
REF
–5V LDO
I
IN
+
–
+
–
+
–
OSC
5V LDO
OUTFETCFM
+
–
+
–
30mV
INTV
CC
–
x37.5
+
+
I
REF
–
I
CHG
BIDIRECTIONAL
SWITCHING
CONTROLLER
V
OUTSP
CFP
CHARGE
PUMP
LTC3350
VCAPP5
19
VCAP
21
22
ICAP
BST
26
TGATE
25
SW
24
DRV
CC
28
BGATE
27
VCC2P5
23
CAPGD
4
PFI
37
PFO
38
CAP_SLCT0
35
CAP_SLCT1
36
SMBALERT
3
SDA
2
SCL
1
GPI
10
SGND
8
CAP4
CAP3
CAP2
CAP1
CAPRTN
ITST
16
15
14
13
12
11
2.5V LDO
INTV
CC
+
Vcapfb_dac
CAPFB
–
INTV
CC
+
V
REF
–
LOGIC
V
REF
A/D
BANDGAP
MULTIPLEXER
V
I
IN
ICHG
VCAP
V
OUT
V
IN
CAP4
CAP3
CAP2
CAP1
CAPRTN
DTEMP
REF
BALANCER
BALANCER
BALANCER
BALANCER
SHUNT
CONTROLLER
SHUNT
CONTROLLER
SHUNT
CONTROLLER
SHUNT
CONTROLLER
+
V
REF
–
–
+
GPIBUF
PGND
39
For more information www.linear.com/LTC3350
3350 BD
3350fc
13
Page 14
LTC3350
TiMing DiagraM
SDA
Definition of Timing for F/S Mode Devices on the I2C Bus
t
HIGH
t
SU(DAT)
t
f
t
SU(STA)
t
t
f
SCL
SSrPS
S = START, Sr = REPEATED START, P = STOP
LOW
t
HD(SDA)
t
r
t
HD(DAT)
operaTion
Introduction
The LTC3350 is a highly integrated backup power controller
and system monitor. It features a bidirectional switching
controller, input and output ideal diodes, supercapacitor
shunts/balancers, a power-fail comparator, a 14-bit ADC
2
C/SMBus programmability with status reporting.
and I
is above an externally programmable PFI threshold
If V
IN
voltage, the synchronous controller operates in step-down
OUT
-
.
mode and charges a stack of supercapacitors. A program
mable input current limit ensures that the supercapacitors
will automatically be charged at the highest possible charge
current that the input can support. If V
is below the PFI
IN
threshold, then the synchronous controller will run in
reverse as a step-up converter to deliver power from the
supercapacitor stack to V
OUT
.
The two ideal diode controllers drive external MOSFETs to
provide low loss power paths from V
and V
IN
CAP
to V
The ideal diodes work seamlessly with the bidirectional
controller to provide power from the supercapacitors to
without backdriving VIN.
V
OUT
The LTC3350 provides balancing and overvoltage protec-
a series stack of one to four supercapacitors. The
tion to
internal
capacitor voltage balancers eliminate the need
for external balance resistors. Overvoltage protection is
provided by
shunt regulators that use an internal switch
and an external resistor across each supercapacitor.
t
HD(SDA)
t
SP
t
SU(STO)
t
t
BUF
r
3350 TD
The LTC3350 monitors system voltages, currents, and
die temperature. A general purpose input (GPI) pin is
provided to measure an additional system parameter or
implement a thermistor measurement. In addition, the
LTC3350 can measure the capacitance and resistance of the
supercapacitor stack. This provides indication of the health
of the supercapacitors and, along with the V
voltage
CAP
measurement, provides information on the total energy
stored and the maximum power that can be delivered.
Bidirectional Switching Controller—Step-Down Mode
The bidirectional switching controller is designed to charge
a series stack of supercapacitors (Figure 1). Charging
proceeds at a constant current until the supercapacitors
reach their maximum charge voltage determined by the
CAPFB servo voltage and the resistor divider between V
CAP
and CAPFB. The maximum charge current is determined
by the value of the sense resistor, R
, used in series
SNSC
with the inductor. The charge current loop servos the
voltage across the sense resistor to 32mV. When charging
begins, an internal soft-start ramp will increase the charge
current from zero to full current in 2ms. The V
CAP
voltage
and charge current can be read from the meas_vcap and
meas_ichrg registers, respectively.
14
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Page 15
operaTion
LTC3350
V
V
IN
R
SNSI
OUT
(TO SYSTEM)
LTC3350
INPUT
CURRENT
CONTROLLER
CHARGE
CURRENT
CONTROLLER
CAPACITOR
VOLTAGE
CONTROLLER
V
IN
INFETVOUTSP VOUTSN
+
+
–
30mV
V
+
REF
–
I
IN
BIDIRECTIONAL
SWITCHING
CONTROLLER
STEP-DOWN MODE
I
+
REF
–
I
CHG
D/A
+
–
–
+
–
+
37.5
–
V
REF
vcapfb_dac[3:0]
TGATE
BGATE
ICAP
VCAP
CAPFB
R
SNSC
+
+
VC
+
+
3350 F01
Figure 1. Power Path Block Diagram—Power Available from V
The LTC3350 provides constant power charging (for a fixed
) by limiting the input current drawn by the switching
V
IN
controller in step-down mode. The input current limit will
reduce charge current to limit the voltage across the input
sense resistor, R
, to 32mV. If the combined system
SNSI
load plus supercapacitor charge current is large enough to
cause the switching controller to reach the programmed
input current limit, the input current limit loop will reduce
the charge current by precisely the amount necessary
to enable the external load to be satisfied. Even if the
charge current is programmed to exceed the allowable
input current, the input current will not be violated; the
supercapacitor charger will reduce its current as needed.
Note that the part’s quiescent and gate drive currents are
not included in the input current measurement.The input
current can be read from the meas_iin register.
IN
Bidirectional Switching Controller—Step-Up Mode
The bidirectional switching controller acts as a step-up
converter to provide power from the supercapacitors to
when input power is unavailable (Figure 2). The PFI
V
OUT
comparator enables step-up mode. V
by a resistor divider between V
step-up mode tie OUTFB to INTV
OUT
CC
regulation is set
OUT
and OUTFB. To disable
.
Step-up mode can be used in conjunction with the output
ideal diode. The V
regulation voltage can be set below
OUT
the capacitor stack voltage. Upon removal of input power,
power to V
stack via the output ideal diode. V
will be provided from the supercapacitor
OUT
CAP
and V
will fall as
OUT
the load current discharges the supercapacitor stack. The
output ideal diode will shut off when the voltage on OUTFB
falls below 1.3V and V
below V
. If OUTFB falls below 1.2V when the output
CAP
will fall a PN diode (~700mV)
OUT
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15
Page 16
LTC3350
operaTion
OUTPUT
VOLTAGE
CONTROLLER
BIDIRECTIONAL
SWITCHING
CONTROLLER
STEP-UP MODE
–
+
+
30mV
V
< V
CAP
OUT
V
OUT
(TO SYSTEM)
LTC3350
VOUTSN
OUTFB
V
REF
–
OUTFET
–
+
TGATE
R
SNSC
BGATE
+
+
> V
V
CAP
OUT
ICAP
VCAP
VC
Figure 2. Power Path Block Diagram—Power Backup
ideal diode shuts off, the synchronous controller will turn
on immediately. If OUTFB is above 1.2V when the output
ideal diode shuts off, the load current will flow through the
body diode of the output ideal diode N-channel MOSFET for
a period of time until OUTFB falls to 1.2V. The synchronous
controller will regulate OUTFB to 1.2V when it turns on,
holding up V
while the supercapacitors discharge to
OUT
ground.
The synchronous controller in step-up mode will run
nonsynchronously when V
. It will run synchronously when V
V
OUT
below V
OUT
.
is less than 100mV below
CAP
falls 200mV
CAP
Ideal Diodes
The LTC3350 has two ideal diode controllers that drive
external N-channel MOSFETs. The ideal diodes consist of
a precision amplifier that drives the gates of N-channel
MOSFETs whenever the voltage at V
is approximately
OUT
+
+
3350 F02
30mV (V
) below the voltage at VIN or V
FWD
. Within
CAP
the amplifier’s linear range, the small-signal resistance
of the ideal diode will be quite low, keeping the forward
drop near 30mV. At higher current levels, the MOSFETs
will be in full conduction.
The input ideal diode prevents the supercapacitors from
back
driving V
parator shuts
below V
OUT
during backup mode. A Fast-Off com-
IN
off the N-channel MOSFET if VIN falls 30mV
. The PFI comparator also shuts off the MOSFET
during power failure.
The output ideal diode provides a path for the supercapaci
tors to power V
when VIN is unavailable. In addition to a
OUT
-
Fast-Off comparator, the output ideal diode also has a FastOn comparator that turns on the external MOSFET when
drops 65mV below V
V
OUT
. The output ideal diode will
CAP
shut off when OUTFB is just above regulation allowing the
synchronous controller to power V
in step-up mode.
OUT
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Page 17
operaTion
53.5
LTC3350
Gate Drive Supply (DRVCC)
The bottom gate driver is powered from the DRV
is normally connected to the INTV
pin. An external LDO
CC
pin. It
CC
can also be used to power the gate drivers to minimize
power dissipation inside the IC. See the Applications
Information section for details.
Undervoltage Lockout (UVLO)
Internal undervoltage lockout circuits monitor both the
INTV
off until INTV
and DRVCC pins. The switching controller is kept
CC
rises above 4.3V and DRVCC rises above
CC
4.2V. Hysteresis on the UVLOs turn off the controller if
either INTV
falls below 4V or DRVCC falls below 3.9V.
CC
Charging is not enabled until VOUTSN is 185mV above the
supercapacitor voltage and V
is above the PFI threshold.
IN
Charging is disabled when VOUTSN falls to within 90mV of
the supercapacitor voltage or V
is below the PFI threshold.
IN
RT Oscillator and Switching Frequency
The RT pin is used to program the switching frequency.
A resistor, R
, from this pin to ground sets the switching
T
frequency according to:
defaults to full scale (1.2V) and is programmed via the
vcapfb_dac register.
Supercapacitors lose capacitance as they age. By initially
setting the V
DAC to a low setting, the final charge
CAP
voltage on the supercapacitors can be increased as they
age to maintain a constant level of stored backup energy
throughout the lifetime of the supercapacitors.
Power-Fail (PF) Comparator
The LTC3350 contains a fast power-fail (PF) comparator
which switches the part from charging to backup mode in
the event the input voltage, V
, falls below an externally
IN
programmed threshold voltage. In backup mode, the input
ideal diode shuts off and the supercapacitors power the load
either directly through the output ideal diode or through
the synchronous controller in step-up mode.
The PF comparator threshold voltage is programmed by
an external resistor divider via the PFI pin. The output of
the PF comparator also drives the gate of an open-drain
NMOS transistor to report the status via the PFO pin. When
input power is available the PFO pin is high impedance.
When V
falls below the PF comparator threshold, PFO
IN
is pulled down to ground.
fSWMHz
()
=
RTkΩ
()
RT also sets the scale factor for the capacitor measurement
value reported in the meas_cap register, described in the
Capacitance and ESR Measurement section of this data
sheet.
Input Overvoltage Protection
The LTC3350 has overvoltage protection on its input. If
exceeds 38.6V, the switching controller will hold the
V
IN
switching MOSFETs off. The controller will resume switch-
V
ing if
falls below 37.2V. The input ideal diode MOSFET
IN
remains on during input overvoltage.
DAC
V
CAP
The feedback reference for the CAPFB servo point can
be programmed using an internal 4-bit digital-to-analog
converter (DAC). The reference voltage can be programmed
from 0.6375V to 1.2V in 37.5mV increments. The DAC
The output of the PF comparator may also be read from
the chrg_pfo bit in the chrg_status register.
Charge Status Indication
The LTC3350 includes a comparator to report the status
of the supercapacitors via an open-drain NMOS transistor
on the CAPGD pin. This pin is pulled to ground until the
CAPFB pin voltage rises to within 8% of the V
CAP
DAC
setting. Once the CAPFB pin is above this threshold, the
CAPGD pin goes high impedance.
The output of this comparator may also be read from the
chrg_cappg bit in the chrg_status
Capacitor V
oltage Balancer
register.
The LTC3350 has an integrated active stack balancer. This
balancer slowly balances all of the capacitor voltages to
within about 10mV of each other. This maximizes the life
of the supercapacitors by keeping the voltage on each as
low as possible to achieve the needed total stack voltage.
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17
Page 18
LTC3350
operaTion
When the difference between any two capacitor voltages exceeds
voltage is discharged with a resistive balancer at about
until all capacitor voltages are within 10mV. The
10mA
balancers are disabled in backup mode.
Capacitor Shunt Regulators
In addition to balancing, there is a need to protect each
capacitor from overvoltage during charging. The capacitors
in the stack will not have exactly the same capacitance due
to manufacturing tolerances or uneven aging. This will
cause the capacitor voltages to increase at different rates
with the same charge current. If this mismatch is severe
enough or if the capacitors are being charged to near their
maximum voltage, it becomes necessary to limit the volt
age increase on some capacitors while still charging the
other capacitors. Up to 500mA of current may be shunted
around a capacitor whose voltage is approaching the pro
grammable shunt voltage. This shunt current reduces the
charge rate of that capacitor relative to the other capacitors.
If a capacitor continues to approach its shunt voltage, the
charge current is reduced. This protects the capacitor
from overvoltage while still charging the other capacitors,
although at a reduced rate of charge.
programmable
to 3.6V may be programmed in 183.5µV increments. The
shunt regulators can be disabled by programming vshunt
to zero (0x0000). The default value is 0x3999, resulting
in a shunt voltage of 2.7V.
2
C/SMBus and SMBALERT
I
The LTC3350 contains an I
communication with the LTC3350 for configuration and
reading back telemetry data. The port supports two SMBus
formats, read word and write word. Refer to the SMBus
specification for details of these formats. The registers
accessible via this port are organized on an 8-bit address
bus and each register is 16 bits wide. The “command code”
(or sub-address) of the SMBus read/write word formats is
the 8-bit address of each of these registers. The address
of the LTC3350 is 0b0001001.
about 10mV, the capacitor with the largest
The shunt voltage is
in the vshunt register. Shunt voltages up
2
C/SMBus port. This port allows
-
-
happens (see Limit Check and Alarms and Monitor Status
Register). The LTC3350 will deassert the SMBALERT
pin only after responding to an SMBus alert response
address (ARA), an
SMBALERT. The host will read from the ARA (0b0001100)
each part asserting SMBALERT will begin to respond
and
with its address. The responding parts arbitrate in such a
way that only the part with the lowest address responds.
Only when a part has responded with its address does it
release the SMBALERT signal. If multiple parts are as
serting the SMBALERT signal then multiple reads from
the ARA are needed. For more information refer to the
SMBus specification.
Details on the registers accessible through this interface
are available in the Register Map and Register Descriptions
sections of this data sheet.
Analog-to-Digital Converter
The LTC3350 has an integrated 14-bit sigma-delta analogto-digital converter (ADC). This converter is automatically
multiplexed between all of the measured channels and
its results are stored in registers accessible via the I
SMBus port. There are 11 channels measured by the ADC,
each of which takes approximately 1.6ms to measure. In
addition to providing status information about the system
voltages and currents, some of these measurements are
used by the LTC3350 to balance, protect, and measure
the capacitors in the stack.
The result of the analog-to-digital conversion is stored in
a 16-bit register as
The
lower two bits of this number are sub-bits. These bits
are ADC outputs which are too noisy to be reliably used
on any single conversion, however, they may be included
if multiple samples are averaged.
The measurements from the ADC are directly stored in the
meas_vcap1, meas_vcap2, meas_vcap3, meas_vcap4,
meas_gpi, meas_vin, meas_vcap, meas_vout, meas_iin,
meas_ichg and meas_dtemp registers.
Capacitance and ESR Measurement
SMBus protocol used to respond to a
a signed, two’s complement number.
-
2
C/
The SMBALERT pin is asserted (pulled low) whenever an
enabled limit is exceeded or when an enabled status event
18
For more information www.linear.com/LTC3350
The LTC3350 has the ability to measure the capacitance
and equivalent series resistance (ESR) of its supercapacitor
3350fc
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operaTion
R
R
R
64
LTC3350
stack. This measurement is performed with minimal impact
to the system, and can be done while the supercapacitor
backup system is online. This measurement discharges
the capacitor stack by a small amount (200mV). If input
power fails during this test, the part will go into backup
mode and the test will terminate.
The capacitance test is performed only once the
supercapacitors have finished charging. The test
temporarily disables the charger, then discharges the
supercapacitors by 200mV with a precision current.
The discharge time is measured and used to calculate
the capacitance with the result of this measurement
stored in the meas_cap register. The number reported is
proportional to the capacitance of the entire stack. Two
different scales can be set using the ctl_cap_scale bit in
the ctl_reg register. If ctl_cap_scale is set to 0 (for large
value capacitor stacks), use the following equation to
convert the meas_cap value to Farads:
C
STACK
T
=
•336µF •meas_ cap
R
TST
If ctl_cap_scale is set to 1 (for small value capactor stacks),
use the following equation to convert the meas_cap value
to Farads:
C
STACK
T
=
•3.36µF •meas_ cap
R
TST
In the two previous equations RT is the resistor on the RT
pin and R
is the resistor on the ITST pin.
TST
The ESR test is performed immediately following the
capacitance test. The switching controller is switched on
and off several times. The changes in charge current and
stack voltage are measured. These measurements are
used to calculate the ESR relative to the charge current
sense resistor. The result of this measurement is stored
in the meas_esr register. The value reported in meas_esr
can be converted to ohms using the following equation:
R
ESR
SNSC
=
•meas_ esr
where R
is the charge current sense resistor in series
SNSC
with the inductor.
The capacitance and capacitor ESR measurements do not
automatically run as the other measurements do. They
must be initiated by setting the ctl_strt_capesr bit in the
ctl_reg register. This bit will automatically clear once the
measurement begins. If the cap_esr_per register is set to
a non-zero value, the measurement will be repeated after
the time programmed in the cap_esr_per register. Each
LSB in the cap_esr_per register represents 10 seconds.
The capacitance and ESR measurements may fail to
complete for several reasons, in which case the respective
mon_cap_failed or mon_esr_failed bit will be set. The ca
pacitance test may
fail due to a power failure or if the 200mV
-
discharge trips the CAPGD comparator. The ESR test will also
fail if the capacitance test fails. The ESR test uses the charger
to supply a current and then measures the supercapacitor
stack voltage with and without that current. If the ESR is
greater than 1024 times R
, the ESR measurement will
SNSC
fail. The ESR measurement is adaptive; it uses knowledge of
ESR from
the
previous measurements to program the test
current. The capacitance and ESR tests should initially be
run several times when first powering up to get the most
accuracy out of the system. It is possible for the first few
measurements to give low quality results or fail to complete
and after running several times will complete with a quality
result. The leakage on supercapacitors is initially very high
after being charged. Many supercapacitor manufacturers
specify the leakage current after being charged for 72 hours.
It is expected that capacitor measurements conducted prior
to this time will read low.
Monitor Status Register
The LTC3350 has a monitor status register (mon_status)
which contains status bits indicating the state of the ca
pacitance and
ESR monitoring system. These bits are set
-
and cleared by the capacitor monitor upon certain events
during a capacitor and ESR measurement, as described
in the Capacitance and ESR Measurement section.
There is a corresponding msk_mon_status register. Writing
a one to any of these bits will cause the SMBALERT pin to
pull low when the corresponding bit in the msk_mon_sta
-
tus register has a rising edge. This allows reduced polling
the LTC3350 when waiting
of
for a capacitance or ESR
measurement to complete.
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19
Page 20
LTC3350
operaTion
Details of the mon_status and msk_mon_status registers
can be found in the Register Descriptions section of this
data sheet.
Charge Status Register
The LTC3350 charger status register (chrg_status) contains
data about the state of the charger, switcher, shunts, and
balancers. Details of this register may be found in the
Register Description sections of this data sheet.
Limit Checking and Alarms
The LTC3350 has a limit checking function that will check
each measured value against I
limits. This feature is optional, and all the limits are disabled by
system
poll the LTC3350 for measurement data.
If a measured parameter goes outside of the programmed
level of an enabled limit, the associated bit in the alarm_reg
register is set high and the SMBALERT pin is pulled low.
This informs the I
The alarms register may then be read to determine exactly
which programmed limits have been exceeded.
A single ADC is shared between the 11 channels with about
18ms between consecutive measurements of the same
channel. In a transient condition, it
parameters
consecutive ADC measurements without setting the alarm.
Once the LTC3350 has responded to an SMBus ARA the
SMBALERT pin is released. The part will not pull the pin
low again until another limit is exceeded. To reset a limit
that has been exceeded, it must be cleared by writing a
one to the respective bit in the clr_alarms register.
A number of the LTC3350’s registers are used for limit
checking. Individual limits are enabled or disabled in the
msk_alarms registers. Once an enabled alarm’s measured
value exceeds the programmed level for that alarm the alarm
is set. That alarm may be cleared by writing a one to the
appropriate bit of the clr_alarms register or by writing a
zero to the appropriate bit to the msk_alarms register. All
alarms that have been set and have not yet been cleared
may be read in the alarm_reg register.
default. The limit checking is designed to simplify
monitoring, eliminating the need to continuously
2
C/SMBus host a limit has been exceeded.
to exceed their programmed levels in between
2
C/SMBus programmable
is possible for these
All of the individual measured voltages have a corresponding
undervoltage (uv) and overvoltage (ov) alarm level. All of
the individual capacitor voltages are compared to the same
nd cap_uv_lvl registers.
alarm levels, set in the cap_ov
The input current measurement has an overcurrent (oc)
alarm programmed in the iin_oc_lvl register. The charge
current has an undercurrent alarm programmed in the
ichg_uc_lvl register.
Die Temperature Sensor
The LTC3350 has an integrated die temperature sensor
monitored by the ADC and digitized to the meas_dtemp
register. An alarm may be set on die temperature by
setting the dtemp_cold_lvl and/or dtemp_hot_lvl registers
and enabling their respective alarms in the msk_alarms
register. To convert the code in the meas_dtemp register
to degrees Celsius use the following:
(°C) = 0.028 • meas_dtemp – 251.4
T
DIE
General Purpose Input
The general purpose input (GPI) pin can be used to measure
an additional system parameter. The voltage on this pin is
directly digitized by the ADC. For high impedance inputs,
an internal buffer may be selected and used to drive the
ADC. This buffer is enabled by setting the ctl_gpi_buffer_en
bit in the ctl_reg register. With this buffer, the input range
is limited from 0V to 3.5V. If this buffer is not used, the
range is from 0V to 5V, however, the input stage of
ADC will draw about 0.4µA per volt from this pin. The ADC
input is a switched capacitor amplifier running at about
1MHz, so this current draw will be at that frequency. The
pin current can be eliminated at the cost of reduced range
and increased offset by enabling the buffer.
Alarms are available for this pin voltage with levels
programmed using the gpi_uv_lvl and gpi_ov_lvl registers.
These alarms are enabled using the msk_gpi_uv and
msk_gpi_ov bits in the msk_alarms register.
To monitor the temperature of the supercapacitor stack,
the GPI pin can be connected to a negative temperature
coefficient (NTC) thermistor. A low drift bias resistor is
required from INTV
from GPI to ground. Connect GPI to SGND if not used.
to GPI and a thermistor is required
CC
_lvl a
the
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20
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Page 21
applicaTions inForMaTion
2
32mV
SNSC
LTC3350
Digital Configuration
Although the LTC3350 has extensive digital features, only
a few are required for basic use. The shunt voltage should
be programmed via the vshunt register if a value other
than the default 2.7V is required. The capacitor voltage
feedback reference defaults to 1.2V; it may be changed
in the vcapfb_dac register.
All other digital features are optional and used for monitoring. The ADC automatically runs and stores conversions to registers (e.g., meas_vcap). Capacitance and ESR
measurements only run if requested, however, they may
be scheduled to repeat if desired (ctl_strt_capesr and cap_
esr_per). Each measured parameter has programmable
limits (e.g., vcap_uv_lvl and vcap_ov_lvl) which may
trigger an alarm and SMBALERT when enabled. These
alarms are disabled by default.
Capacitor Configuration
The LTC3350 may be used with one to four supercapacitors. If less than four capacitors are used, the capacitors
must be populated from CAPRTN to CAP4, and the unused
CAP pins must be tied to the highest used CAP pin. For
example, if three capacitors are used, CAP4 should be tied
to CAP3. If only two capacitors are used, both CAP4 and
3 should be tied to CAP2. The number of capacitors
CAP
used
must be programmed on the CAP_SLCT0 and
CAP_SLCT1 pins by tying the pins to VCC2P5 for a one
and ground for a zero as shown in Table 1. The value
programmed on these pins may be read back from the
2
num_caps register via I
C/SMBus.
V
. CAPRTN, CAP1, CAP2, CAP3 and CAP4 must be
SHUNT
connected to the supercapacitors through resistors which
serve as ballasts for the internal shunts. The shunt cur
rent is approximately V
resistance value. For a V
divided by twice the shunt
SHUNT
of 2.7V, 2.7Ω resistors
SHUNT
-
should be used for 500mA of shunt current. The shunts
have a duty cycle of up to 75%. The power dissipated in
a single shunt resistor is approximately:
3V
≈
16R
SHUNT
SHUNT
P
SHUNT
and the resistors should be sized accordingly. If the shunts
are disabled, make R
SHUNT
100Ω.
Since the shunt current is less than what the switcher can
supply, the on-chip logic will automatically reduce the
charging current to allow the shunt to protect the capacitor.
This greatly reduces the charge rate once any one shunt is
activated. For this reason, V
should be programmed
SHUNT
as high as possible to reduce the likelihood of it activating
during a charge cycle. Ideally, V
would be set high
SHUNT
enough so that any likely capacitor mismatches would not
cause the shunts to turn on. This keeps the charger operat
ing at the highest possible charge current and reduces the
charge time. If the shunts never turn on, the charge cycle
completes quickly and the balancers eventually equalize
the voltage on the capacitors. The shunt setting may also
be used to discharge the capacitors for testing, storage
or other purposes.
Setting Input and Charge Currents
Table 1
CAP_SLCT1CAP_SLCT0
0001
0112
1023
1134
num_caps
REGISTER VALUE
NUMBER OF
CAPACITORS
Capacitor Shunt Regulator Programming
V
defaults to 2.7V at initial power-up. V
is programmed via the I2C/SMBus interface and
SHUNT
serves to limit
SHUNT
the voltage on any individual capacitor by turning on a
shunt around that capacitor as the voltage approaches
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The maximum input current is determined by the resis
tance across
the VOUTSP and VOUTSN pins, R
SNSI
maximum charge current is determined by the value of
the sense resistor, R
, used in series with the induc-
SNSC
tor. The input and charge current loops servo the voltage
across
their respective sense resistor to 32mV. Therefore,
the maximum input and charge currents are:
I
IN(MAX )
I
CHG(MAX)
=
R
=
SNSI
R
32mV
-
. The
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21
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LTC3350
58mV
32mV
R
applicaTions inForMaTion
The peak inductor current limit, I
, is 80% higher than
PEAK
the maximum charge current and is equal to:
I
=
PEAK
R
SNSC
Note that the input current limit does not include the part’s
quiescent and gate drive currents. The total current drawn
by the part will be I
IN(MAX)
+ IQ + IG, where IQ is the non-
switching quiescent current and IG is the gate drive current.
Low Current Charging and High Current Backup
The LTC3350 can accommodate applications requiring
low charge currents and high backup currents. In these
applications, program the desired charge current using
. The higher current needed during backup can be
R
SNSI
set using R
. The input current limit will override the
SNSC
charge current limit when the supercapacitors are charging
while the charge current limit provides sufficient current
capability for backup operation.
The charge current will be limited to I
(i.e., low duty cycles). As V
V
CAP
rises, the switching
CAP
CHG(MAX)
at low
controller’s input current will increase until it reaches
I
IN(MAX)
and the charge current will decrease as V
. The input current will be maintained at I
rises further.
CAP
IN(MAX)
Some applications may want to use only a portion of the
input current limit to charge the supercapacitors. Tw o input
current sense resistors placed in series can
be used to
accomplish this as shown in Figure 3. VOUTSP is kelvin
connected to the positive terminal of R
is kelvin connected to the negative terminal of R
The load current is pulled across R
SNSI1
current to the charger is pulled across R
and VOUTSN
SNSI1
while the input
and R
SNSI1
SNSI2
SNSI2
The input current limit is:
32mV = R
SNSI1
• I
LOAD
+ (R
SNSI1
+ R
SNSI2
) • I
INCHG
For example, suppose that only 2A of input current is desired to charge th
e supercapacitors but the system load
and charger combined can pull a total of up to 4A from the
supply. Setting R
SNSI1
= R
= 8mΩ will set a 4A cur-
SNSI2
rent limit for the load + charger while setting a 2A limit for
charger. With no system load, the charger can pull up
the
to 2A of input current. As the load pulls 0A to 4A of current
the charger’s input current will reduce from 2A down to 0A.
The following equation can be used to determine charging
input current as a function of system load current:
SNSI1
R
SNSI1+RSNSI2
•I
I
INCHG
=
R
SNSI1+RSNSI2
–
The contact resistance of the negative terminal of R
the positive terminal of R
as well as the resistance of
SNSI2
the trace connecting them will cause variability in the input
current limit. To minimize the error, place both input current
sense resistors close together with a large PCB pad area
between them as the system load current is pulled from the
trace connecting the two sense resistors.
Note that the backup current will flow through R
package should be sized accordingly to handle the
R
SNSI2
power dissipation.
V
(TO SYSTEM)
OUT
I
LOAD
V
IN
V
INFET VOUTSP
IN
Setting V
CAP
Voltage
The LTC3350 V
resistor divider, as shown in Figure 4. The regulated output
.
R
SNSI1RSNSI2
VOUTSN
LTC3350
voltage is set by an external feedback
CAP
TGATE
BGATE
Figure 3
I
INCHG
3350 F03
voltage is determined by:
.
V
where CAPFBREF is the output of the V
CAP
⎛
= 1+
⎜
⎝
R
R
FBC1
FBC2
⎞
CAPFBREF
⎟
⎠
DAC, pro-
CAP
grammed in the vcapfb_dac register. Great care should
be taken to route the CAPFB line away from noise sources,
such as the SW line.
Power-Fail Comparator Input Voltage Threshold
The input voltage threshold below which the power-fail
status pin, PFO, indicates a power-fail condition and the
LOAD
SNSI1
SNSI2
and
. The
3350fc
22
For more information www.linear.com/LTC3350
Page 23
applicaTions inForMaTion
LTC3350
V
CAP
R
FBC1
R
FBC2
3350 F04
Figure 4. V
LTC3350
CAPFB
Voltage Feedback Divider
CAP
LTC3350 bidirectional controller switches to step-up mode
is programmed using a resistor divider from the V
IN
pin
to SGND via the PFI pin such that:
VIN= 1+
where V
⎛
⎜
⎝
PFI(TH)
⎞
R
PF1
V
PFI(TH)
⎟
R
⎠
PF2
is 1.17V. Typical values for R
PF1
and R
PF2
are in the range of 40k to 1M. See Figure 5.
The input voltage above which the power-fail status pin
PFO is high impedance and the bidirectional controller
switches to step-down mode is:
VIN= 1+
where V
⎛
⎜
⎝
PFI(HYS)
⎞
R
R
PF1
V
()
PFI(TH)
⎟
⎠
PF2
+ V
PFI(HYS)
is the hysteresis of the PFI comparator
and is equal to 30mV.
V
IN
LTC3350
PFI
R
PF1
R
PF2
3350 F05
V
IN
R
PF1
PFI
V
DD
LTC3350
PFO
Figure 6. PFI Threshold Divider with Added Hystersis
MP1
R
MN1
PF3
R
PF2
3350 F06
MN1 and MP1 can be implemented with a single pack-
-channel and P-channel MOSFET pair such as the
age N
Si1555DL or Si1016CX. The drain leakage current of MN1,
when its gate voltage is at ground, can introduce an offset
in the threshold. To minimize the effect of this leakage cur
rent R
PF1
Setting V
and R
PF2
Voltage in Backup Mode
OUT
should be between 1k and 100k.
PF3
, R
The output voltage for the controller in step-up mode is
set by an external feedback resistor divider, as shown in
Figure 7. The regulated output voltage is determined by:
V
⎛
= 1+
OUT
⎜
⎝
R
R
FBO1
FBO2
⎞
⎟
⎠
1.2V
Great care should be taken to route the OUTFB line away
from noise sources, such as the SW line.
-
V
R
(OPT)
C
(OPT)
R
C
(OPT)
C
3350 F07
OUT
R
FO
FBO1
FO
R
FBO2
C
C
FBO1
3350fc
23
Figure 5. PFI Threshold Voltage Divider
Additional hysteresis can be added by switching in an
additional resistor, R
, in parallel with R
PF3
when the
PF2
voltage at PFI falls below 1.17V as shown in Figure 6. The
falling V
threshold becomes:
V
IN
VIN= 1+
threshold is the same as before but the rising
IN
⎛
R
PF1
R
+
RP2
⎜
⎝
⎞
R
PF1
V
()
PFI(TH)
⎟
R
⎠
PF3
+ V
PFI(HYST)
For more information www.linear.com/LTC3350
Figure 7. V
LTC3350
OUTFB
–
VC
+
V
REF
Voltage Divider and Compensation Network
OUT
Page 24
LTC3350
1
1
V
applicaTions inForMaTion
Compensation
The input current, charge current, V
voltage, and V
CAP
OUT
voltage loops all require a 1nF to 10nF capacitor from the
VC node to ground. When using the output ideal diode and
backing up to low voltages (<8V) use 8.2nF to 10nF on
VC. When not using the output ideal diode 4.7nF to 10nF
on VC is recommended. For very high backup voltages
(>15V) 1nF to 4.7nF is recommended.
In addition to the VC node capacitor, the V
requires a phase-lead capacitor, C
FBO1
voltage loop
OUT
, for stability and
improved transient response during input power failure
(Figure 7). The product of the top divider resistor and the
phase-lead capacitor should be used to create a zero at
approximately 2kHz:
R
• C
FBO1
Choose an R
FBO1
FBO1
≈
2π 2kHz
()
such that C
is ≥ 100pF to minimize
FBO1
the effects of parasitic pin capacitance. Because the phaselead capacitor introduces a larger ripple at the input of
the V
lowpass filter from the V
transconductance amplifier, an additional RC
OUT
divider to the OUTFB pin may
OUT
be needed to eliminate voltage ripple spikes. The filter time
constant should be located at the switching frequency of
the synchronous controller:
RFO•CFO=
2πf
SW
with CFO > 10pF to minimize the effects of parasitic pin
capacitance. For back up applications where the V
OUT
regulation voltage is low (~5V to 6V), an additional 1k to
3k resistor, R
, in series with the VC capacitor can improve
C
stability and transient response.
Minimum V
Voltage in Backup Mode
CAP
In backup mode, power is provided to the output from the
supercapacitors either through the output ideal diode or
the synchronous controller operating in step-up mode.
The output ideal diode provides a low loss power path
from the supercapacitors to V
. The minimum internal
OUT
(open-circuit) supercapacitor voltage will be equal to
the minimum V
necessary for the system to operate
OUT
plus the voltage drops due to the output ideal diode and
equivalent series resistance, R
, of each supercapacitor
SC
in the stack.
Example: System needs 5V to run and draws 1A during
backup. There are four supercapacitors in the stack, each
with an R
regulation voltage is 30mV (OUTFET R
of 45mΩ. The output ideal diode forward
SC
< 30mΩ).
DS(ON)
The minimum open-circuit supercapacitor voltage is:
V
CAP(MIN)
= 5V + 0.030V + (1A • 4 • 45mΩ) = 5.21V
Using the synchronous controller in step-up mode allows
the supercapacitors to be discharged to a voltage much
lower than the minimum V
needed to run the system.
OUT
The amount of power that the supercapacitor stack can
deliver at its minimum internal (open-circuit) voltage should
be greater than what is needed to power the output and
the step-up converter.
According to the maximum power transfer rule:
2
P
CAP(MIN)
=
4• n •R
CAP(MIN)
SC
P
>
BACKUP
η
In the equation above η is the efficiency of the synchronous controller
in step-up mode and n is the number of
supercapacitors in the stack.
Example: System needs 5V to run and draws 1A during
backup. There are four supercapacitors in the stack (n=4),
each with an R
of 45mΩ. The converter efficiency is
SC
90%. The minimum open-circuit supercapacitor voltage is:
4• 4 •45mΩ• 5V •1A
=
0.9
= 2.0V
V
CAP(MIN)
In this case, the voltage seen at the terminals of the capacitor stack
is half this voltage, or 1V, according to the
maximum power transfer rule.
3350fc
24
For more information www.linear.com/LTC3350
Page 25
applicaTions inForMaTion
1
2
P
⎣
⎦
V
n
n
LTC3350
Note the minimum V
voltage can also be limited by the
CAP
peak inductor current limit (180% of maximum charge cur-
the
rent) and
maximum duty cycle in step-up mode (~90%).
Optimizing Supercapacitor Energy Storage Capacity
In most systems the supercapacitors will provide backup
power to one or more DC/DC converters. A DC/DC converter
presents a constant power load to the supercapacitor. When
the supercapacitors are near their maximum voltage, the
loads will draw little current. As the capacitors discharge,
the current drawn from supercapacitors will increase to
maintain constant power to the load. The amount of energy
required in back up mode is the product of this constant
backup power, P
BACKUP
, and the backup time, t
BACKUP
.
The energy stored in a stack of n supercapacitors available
for backup is:
nC
()
SC
where CSC, V
2
V
CELL(MAX )
CELL(MAX)
–
V
and V
2
CELL(MIN)
CELL(MIN)
are the capacitance,
maximum voltage and minimum voltage of a single capacitor in
on
voltage on the stack is V
the stack, respectively. The maximum voltage
the stack is V
CAP(MAX)
= n • V
CAP(MIN)
CELL(MAX)
= n • V
. The minimum
CELL(MIN)
.
Some of this energy will be dissipated as conduction loss
in the ESR of the supercapacitor stack. A higher backup
power requirement leads to a higher conduction loss for
a given stack ESR.
The amount of capacitance needed can be found by solving
the following equation for C
SC
:
where:
4R
γ
= 1+ 1–
MAX
= 1+ 1–
γ
Min
SC•PBACKUP
2
n
V
CELL(MAX )
4R
SC•PBACKUP
2
n
V
CELL(MIN)
and,
RSC is the equivalent series resistance (ESR) of a single
supercapacitor in the stack. Note that the maximum power
transfer rule limits the minimum cell voltage to:
V
CELL(MIN)
=
CAP(MIN)
4R
≥
SC•PBACKUP
To minimize the size of the capacitance for a given amount
of backup energy, the maximum voltage on the stack,
V
CELL(MAX)
, can be increased. However, the voltage is
limited to a maximum of 2.7V and this may lead to an
unacceptably low capacitor lifetime.
An alternative option would be to keep V
CELL(MAX)
at a
voltage that leads to reasonably long lifetime and increase
the capacitor utilization ratio of the supercapacitor stack.
The capacitor utilization ratio, α
αB=
2
V
CELL(MAX )
V
2
CELL(MAX )
2
–
V
CELL(MIN)
, can be defined as:
B
If the synchronous controller in step-up mode is used then
the supercapacitors can be run down to a voltage set by the
BACKUP
• t
BACKUP
1
=
4
⎡
nCSCγ
⎢
⎢
MAX
2
•
V
CELL(MAX )
– γ
MIN
For more information www.linear.com/LTC3350
2
•
V
CELL(MIN)
4R
SC•PBACKUP
–
n
ln
⎛
⎜
⎝
γ
γ
MAX
MIN
• V
CELL(MAX )
• V
CELL(MIN)
⎤
⎞
⎥
⎟
⎠
⎥
3350fc
25
Page 26
LTC3350
P
1
⎣
⎦
BACKUP
2P
• t
⎣
⎦
V
applicaTions inForMaTion
maximum power transfer rule to maximize the utilization
ratio. The minimum voltage in this case is:
4R
SC•PBACKUP
nη
V
CELL(MIN)
=
where η is the efficiency of the boost converter
(~90% to 96%).
substitute P
BACKUP/η
For the backup equation, γ
for P
BACKUP
. In this case the energy
MAX
and γ
MIN
needed for backup is governed by the following equation:
BACKUP
η
⎡
α
B
⎢
⎢
+α
2
t
BACKUP
B
–
1–α
2
≤
nCSC•
2
B
ln
⎛
⎜
⎝
V
1+ α
1–α
2
CELL(MAX )
⎤
⎞
B
⎥
⎟
⎠
⎥
B
•
Once a capacitance is found using the above equation the
maximum ESR allowed needs to be checked:
B
4P
2
n
V
CELL(MAX )
RSC≤
η 1– α
()
Capacitor Selection Procedure
1. Determine backup requirements P
BACKUP
and t
BACKUP
2. Determine maximum cell voltage that provides acceptable capacitor lifetime.
Choose number of capacitors in the stack.
3.
7. If a suitable capacitor is not available, iterate by choosing
more capacitance, a higher cell voltage, more capacitors
in the stack and/or a lower utilization ratio.
8. Make sure to take into account the lifetime degrada
tion of ESR and capacitance, as well as the maximum
discharge
The switching frequency and inductor selection are interrelated. Higher
switching
frequencies allow the use of
smaller inductor and capacitor values, but generally results
in lower efficiency due to MOSFET switching and gate charge
losses. In addition, the effect of inductor value on ripple
current must also be considered. The inductor ripple cur
.
with
rent decreases
and increases with higher V
higher inductance or higher frequency
. Accepting larger values of
IN
ripple current allows the use of low inductances but results
in higher output voltage ripple and greater core losses.
-
-
4. Choose a desired utilization ratio, α
pacitor (e.g., 80%).
Solve for capacitance, C
5.
CSC≥
⎡
α
B
⎢
⎢
+α
2
BACKUP
nη
B
BACKUP
2
V
CELL(MAX )
1–α
–
2
B
:
SC
⎛
1+ α
()
ln
⎜
⎜
⎝
•
1–α
6. Find supercapacitor with sufficient capacitance CSC and
η 1– α
:
SC
()
B
4P
2
n
V
CELL(MAX )
BACKUP
minimum R
26
RSC≤
, for the superca-
B
–1
⎤
⎞
B
⎥
⎟
⎟
⎥
B
⎠
For more information www.linear.com/LTC3350
For the LTC3350, the best overall performance will be
attained if the inductor is chosen to be:
L =
for V
L = 1–
for V
tor stack voltage, V
I
CHG(MAX)
is the switching frequency. Using these equations, the
f
SW
inductor ripple will be at most 25% of I
IN(MAX )
I
CHG(MAX)
IN(MAX)
⎛
⎜
⎝
IN(MAX)
≤ 2V
V
CAP
V
IN(MAX )
≥ 2V
• f
SW
CAP
⎞
⎟
⎠
, where V
CAP
IN(MAX)
and:
V
CAP
0.25•I
CHG(MAX)
CAP
• f
SW
is the final supercapaci-
is the maximum input voltage,
is the maximum regulated charge current, and
CHG(MAX)
.
3350fc
Page 27
V
⎣
⎦
V
applicaTions inForMaTion
LTC3350
Using the above equation, the inductor may be too large
to provide a fast enough transient response to hold up
when input power goes away. This occurs in cases
V
OUT
where the maximum V
can be high (e.g. 25V) and the
IN
backup voltage low (e.g. 6V). In these situations it would
be best to choose an inductor that is smaller resulting in
maximum peak-to-peak ripple as high as 40% of I
CHG(MAX)
.
Once the value for L is known, the type of inductor core
must be selected. Ferrite cores are recommended for their
very low core loss. Selection criteria should concentrate
on minimizing copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This causes an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate. The saturation current
for the inductor should be at least 80% higher than the
maximum regulated current, I
CHG(MAX)
. A list of inductor
suppliers is provided in Table 3.
Table 3. Inductor Vendors
VENDORURL
Coilcraftwww.coilcraft.com
Muratawww.murata.com
Sumidawww.sumida.com
TDKwww.tdk.com
Tokowww.toko.com
Vishaywww.vishay.com
Würth Electronicwww.we-online.com
C
and C
OUT
serves as the input to the synchronous controller in
V
OUT
Capacitance
CAP
step-down mode and as the output in step-up (backup)
mode. If step-up mode is used, place 100µF of bulk
(aluminum electrolytic, OS-CON, POSCAP) capacitance
for every 2A of backup current desired. For 5V system
applications, 100µF per 1A of backup current is recom
mended. In addition, a certain amount of high frequency
bypass capacitance is needed to minimize voltage ripple.
The voltage ripple in step-up mode is:
Maximum ripple occurs at the lowest V
I
OUT(BACKUP)
. Multilayer ceramics are recommended for
that can supply
CAP
high frequency filtering.
If step-up mode is unused, then the specification for
will be determined by the desired ripple voltage in
C
OUT
step-down mode:
∆
V
V
OUT
CAP
OUT
=
CAP
OUT
I
⎞
CHG(MAX)
⎟
C
⎠
OUT
• f
+I
CHG(MAX)•RESR
SW
⎛
V
1–
⎜
V
⎝
In continuous conduction mode, the source current of the
top MOSFET is a square wave of duty cycle V
CAP/VOUT
.
To prevent large voltage transients, a low ESR capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
I
RMS≅ICHG(MAX)
V
V
OUT
This formula has a maximum at V
= I
I
RMS
CHG(MAX)
commonly used for
/2. This simple worst-case condition is
design because even significant devia-
CAP
V
V
OUT
CAP
–1
OUT
= 2V
CAP
, where
tions do not offer much relief.
Medium
voltage (20V to 35V) ceramic, tantalum, OS-CON,
and switcher-rated electrolytic capacitors can be used as
input capacitors. Sanyo OS-CON SVP, SVPD series, Sanyo
POSCAP TQC series, or aluminum electrolytic capacitors
from Panasonic WA series or Cornel Dublilier SPV series
in parallel with a couple of high performance ceramic
capacitors can be used as an effective means of achieving
low ESR and high bulk capacitance.
serves as the input to the controller in step-up mode
V
CAP
and as the output in step-down mode. The purpose of the
capacitor is to filter the inductor current ripple. The
V
CAP
V
CAP
∆V
ripple (∆V
≈ ∆I
CAP
) is approximated by:
CAP
PP
⎛
⎜
⎝
8C
CAP
1
• f
SW
+R
ESR
⎞
⎟
⎠
∆
⎡
⎢
=
OUT
⎛
1–
⎜
⎝
V
V
CAP
OUT
⎞
1
⎟
⎠
C
OUT
• f
SW
V
OUT
+
V
CAP
•R
⎤
I
⎥
ESR
OUT(BACKUP)
For more information www.linear.com/LTC3350
where fSW is the switching frequency, C
V
pacitance on
and ∆IPP is the ripple current in the
CAP
inductor. The output ripple is highest at maximum input
voltage since ∆I
increases with input voltage.
PP
is the ca-
CAP
3350fc
27
Page 28
LTC3350
V
k
2
applicaTions inForMaTion
Because supercapacitors have low series resistance, it is
important that C
be sized properly so that the bulk of
CAP
the inductor current ripple flows through the filter capacitor and not the supercapacitor. It is recommended that:
⎛
⎜
⎝
8C
CAP
1
• f
+R
SW
ESR
⎞
n•R
SC
≤
⎟
5
⎠
where n is the number of supercapacitors in the stack and
is the ESR of each supercapacitor. The capacitance
R
SC
on VCAP can be a combination of bulk and high frequency
capacitors. Aluminum electrolytic, OS-CON and POSCAP
capacitors are suitable for bulk capacitance while multilayer
ceramics are recommended for high frequency filtering.
Power MOSFET Selection
Tw o external power MOSFETs must be selected for
the LTC3350’s synchronous controller: one N-channel
MOSFET for
for
the bottom switch. The selection criteria of the external
the top switch and one N-channel MOSFET
N-channel power MOSFETs include maximum drain-source
voltage (V
), threshold voltage, on-resistance (R
DSS
reverse transfer capacitance (C
), total gate charge (QG),
RSS
DS(ON)
),
and maximum continuous drain current.
of both MOSFETs should be selected to be higher
V
DSS
than the maximum input supply voltage (including
transient). The peak-to-peak drive levels are set by the
DRV
be used because DRV
voltage. Logic-level threshold MOSFETs should
CC
is powered from either INTVCC
CC
(5V) or an external LDO whose output voltage must be
less than 5.5V.
MOSFET power losses are determined by R
and Q
. The conduction loss at maximum charge current
G
DS(ON)
, C
RSS
for the top and bottom MOSFET switches are:
P
COND(TOP)
P
COND(BOT)
CAP
=
V
OUT
⎛
= 1–
⎜
⎝
I
CHG(MAX)
V
CAP
V
OUT
⎞
I
CHG(MAX)
⎟
⎠
2
•R
DS(ON)
2
•R
1+δ∆T
()
DS(ON)
1+δ∆T
()
The term (1+ δ∆T) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
Both MOSFET switches have conduction loss. However,
transition loss occurs only in the top MOSFET in stepdown mode and only in the bottom MOSFET in step-up
2
mode. These losses are proportional to V
be considerably large in high voltage applications (V
OUT
and can
OUT
> 20V). The maximum transition loss is:
P
TRAN
≈
V
OUT
2
•I
CHG(MAX)•CRSS
• f
SW
where k is related to the drive current during the Miller
plateau and is approximately equal to one.
The synchronous controller can operate in both step-down
and step-up mode with different voltages on V
mode. If V
is 12V in step-down mode (input power
OUT
OUT
in each
available) and 10V in step-up mode (backup mode) then
both MOSFETs can be sized to minimize conduction loss. If
can be as high as 25V while charging and V
V
OUT
OUT
is held
to 6V in backup mode, then the MOSFETs should be sized
to minimize losses during backup mode. This may lead to
choosing a high side MOSFET with significant transition
loss which may be tolerable when input power is avail
able so
factor.
long as thermal issues do not become a limiting
The bottom MOSFET can be chosen to minimize
-
conduction loss. If step-up mode is unused, then choosing
a high side MOSFET that that has a higher R
and lower C
would minimize overall losses.
RSS
DS(ON)
device
Another power loss related to switching MOSFET selection
is the power lost to driving the
gates. The total gate charge,
QG, must be charged and discharged each switching cycle.
The power is lost to the internal LDO and gate drivers within
the LTC3350. The power lost due to charging the gates is:
≈ (Q
P
G
where Q
+ Q
GTOP
is the top MOSFET gate charge and Q
GTOP
GBOT
) • fSW • V
OUT
GBOT
is the bottom MOSFET gate charge. Whenever possible,
utilize MOSFET switches that minimize the total gate charge
to limit the internal power dissipation of the LTC3350.
Schottky Diode Selection
Optional Schottky diodes can be placed in parallel with the
top and bottom MOSFET switches. These diodes clamp
SW during the non-overlap times between conduction of
the top and bottom MOSFET switches. This prevents the
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applicaTions inForMaTion
LTC3350
body diodes of the MOSFET switches from turning on,
storing charge during the non-overlap time and requiring
a reverse recovery period that could cost as much as 3%
in efficiency at high V
. One or both diodes can be omit-
IN
ted if the efficiency loss can be tolerated. The diode can
rated for about one-third to one-fifth of the full load
be
current since it is on for only a fraction of the duty cycle.
Larger diodes result in additional switching losses due to
their larger junction capacitance. In order for the diodes
to be effective, the inductance between them and the top
and bottom MOSFETs must be as small as possible. This
mandates that these components be placed next to each
other on the same layer of the PC board.
Top MOSFET Driver Supply (C
An external bootstrap capacitor, C
, DB)
B
, connected to the BST
B
pin supplies the gate drive voltage for the top MOSFET.
Capacitor C
diode, D
of the bootstrap capacitor, C
, in Figure 8, is charged though an external
B
, from DRVCC when the SW pin is low. The value
B
, needs to be 20 times that
B
of the total input capacitance of the top MOSFET.
the top MOSFET on, the BST voltage is above the
With
system supply rail:
V
BST
= V
OUT
+ V
DRVCC
The reverse break down of the external diode, DB, must
be greater than V
OUT(MAX)
+ V
DRVCC(MAX)
.
The step-up converter can briefly run nonsynchronously
when used in conjunction with the output ideal diode. Dur
ing this time the BST to SW voltage can pump up to voltages
exceeding 5.5V if D
is a Schottky diode. Fast switching PN
B
diodes are recommended due to their low leakage and junc-
. A
tion capacitance
Schottky diode can be used if the step-up
converter runs synchronous throughout backup mode.
INTVCC/DRVCC and IC Power Dissipation
The LTC3350 features a low dropout linear regulator
(LDO) that supplies power to INTV
ply. INTV
DRV
CC
powers the gate drivers (when connected to
CC
) and much of the LTC3350’s internal circuitry. The
LDO regulates the voltage at the INTV
from the V
CC
pin to 5V. The
CC
OUT
sup-
LDO can supply a maximum current of 50mA and must
be bypassed to ground with a minimum of 1μF when not
connected to DRV
. DRVCC should have at least a 2.2μF
CC
ceramic or low ESR electrolytic capacitor. No matter what
type of bulk capacitor is used on DRV
, an additional
CC
0.1μF ceramic capacitor placed directly adjacent to the
pin is highly recommended. Good bypassing is
DRV
CC
needed to supply the high transient currents required by
the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi
mum junction
exceeded. The INTV
temperature rating for the LTC3350 to be
current, which is dominated by the
CC
-
gate charge current, is supplied by the 5V LDO.
Power dissipation for the IC in this case is highest and is
approximately equal to (V
non-switching quiescent current of ~4mA and I
) • (IQ + IG), where IQ is the
OUT
G
is gate
charge current. The junction temperature can be estimated
by using the equations given in Note 2 of the Electrical
Characteristics. For example, the I
supplied by the INTVCC
G
LDO is limited to less than 42mA from a 35V supply in the
QFN package at a 70°C ambient temperature:
= 70°C + (35V)(4mA + 42mA)(34°C/W) = 125°C
T
J
To prevent the maximum junction temperature from being
exceeded, the INTV
LDO current must be checked while
CC
operating in continuous conduction mode at maximum
.
V
OUT
BST
C
LTC3350
SW
DRV
CC
INTV
CC
Figure 8. Bootstrap Capacitor/Diode and DRVCC Connections
B
0.1µF
1µF
OPT
D
B
>2.2µF
3350 F07
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The power dissipation in the IC is drastically reduced if
is powered from an external LDO. In this case the
DRV
CC
power dissipation in the IC is equal to power dissipation
due to I
(V
DRVCC
and the power dissipated in the gate drivers,
Q
) • (IG). Assuming the external DRVCC LDO output
is 5V and is supplying 42mA to the gate drivers, the junction temperature rises to only 82°C:
= 70°C + [(35V)(4mA)+(5V)(42mA)](34°C/W) = 82°C
T
J
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LTC3350
V
applicaTions inForMaTion
The external LDO should be powered from V
be enabled after the INTV
output must be less than 5.5V. INTV
be tied to DRV
CC
.
LDO has powered up and its
CC
should no longer
CC
. It must
OUT
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration that the LTC3350 is capable of turning on the top
MOSFET
in step-down mode. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3350 is
approximately 85ns. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
CAP
<
V
• f
OUT
SW
t
ON(MIN)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The charge current and V
voltage will continue to
CAP
be regulated, but the ripple voltage and current will increase.
Ideal Diode MOSFET Selection
An external N-channel MOSFET is required for the input and
output ideal diodes. Important parameters for the selection
of these MOSFETs are the maximum drain-source voltage,
, gate threshold voltage and on-resistance (R
V
DSS
DS(ON)
).
When the input is grounded, either the supercapacitor stack
voltage or the step-up controller’s backup voltage is applied
across the input ideal diode MOSFET. Therefore, the V
DSS
of
the input ideal diode MOSFET must withstand the maximum
voltage on V
in backup mode. When the supercapaci-
OUT
tors are at 0V, the input voltage is applied across the output
diode MOSFET. Therefore, the V
ideal
diode MOSFET must withstand the highest voltage on V
of the output ideal
DSS
IN
Achieving forward regulation will minimize power loss and
heat dissipation, but it is not a necessity. If a forward voltage drop
MOSFET
of more than 30mV is acceptable, then a smaller
can be used but must be sized compatible with
the higher power dissipation. Care should be taken to
ensure that the power dissipated is never allowed to rise
above the manufacturer’s recommended maximum level.
During backup mode, the output ideal diode shuts off
when the voltage on OUTFB falls below 1.3V. For high
backup voltages (>8.4V), the output ideal diode will
V
OUT
shut off when V
above the V
OUT
is more than a diode drop (~700mV)
CAP
regulation point (i.e., OUTFB > 1.2V). The
body diode of the output ideal diode N-channel MOSFET
will carry the load current until V
diode drop of the V
regulation voltage at which point
OUT
drops to within a
CAP
the synchronous controller takes over. During this period
the power dissipation in the output ideal diode MOSFET
increases significantly. Diode conduction time is small
compared to the overall backup time but can be significant
when discharging very large supercapacitors (>600F). Care
should be taken to properly heat sink the MOSFET to limit
the temperature rise.
PCB Layout Considerations
When laying out the printed circuit board, the following
guidelines should be used to ensure proper operation of
the IC. Check the following in your layout:
1. Keep MN1, MN2, D1, D2 and C
close together.
OUT
The high di/dt loop formed by the MOSFETs, Schottky
diodes and the V
capacitance, shown in Figure9,
OUT
should have short, wide traces to minimize high
frequency noise and voltage stress from inductive
ringing. Surface mount components are preferred to
reduce parasitic inductances from component leads.
.
D1
The gate drive for both ideal diodes is 5V. This allows the
use of logic-level threshold N-channel MOSFETs.
As a general rule, select MOSFETs with a low enough
R
to obtain the desired VDS while operating at full
DS(ON)
load current. The LTC3350 will regulate the forward voltage
V
OUT
C
OUT
MN1
HIGH
FREQUENCY
CIRCULATING
PATH
MN2
R
L1
SNSC
D2
V
CAP
+
+
C
CAP
+
+
drop across the input and output ideal diode MOSFETs to
30mV if R
is low enough. The required R
DS(ON)
DS(ON)
can be
calculated by dividing 0.030V by the load current in amps.
30
For more information www.linear.com/LTC3350
Figure 9. High Speed Switching Path
3350 F09
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LTC3350
Connect the drain of the top MOSFET and cathode of
the top diode directly to the positive terminal of C
OUT
Connect the source of the bottom MOSFET and anode
of the bottom diode directly to the negative terminal
of C
. This capacitor provides the AC current to the
OUT
MOSFETs.
2. Ground is referenced to the negative terminal of the
decoupling capacitor in step-down mode and to
V
CAP
the negative terminal of the V
in step-up mode. The negative terminal of C
decoupling capacitor
OUT
OUT
should
be as close as possible to the negative terminal of
by placing the capacitors next to each other and
C
CAP
away from the switching loop described above. The
combined IC SGND pin/PGND paddle and the ground
returns of C
INTVCC
bined negative
and C
terminal of C
must return to the com-
DRVCC
and C
OUT
CAP
.
3. Effective grounding techniques are critical for success-
/DC
ful DC
converter layouts. Orient power components
such that switching current paths in the ground plane
do not cross through the SGND pin and exposed pad
on the backside of the LTC3350 IC. Switching path
currents can be controlled by orienting the MOSFET
switches, Schottky
decoupling capacitors in close proximity to each
V
CAP
diodes, the inductor, and V
OUT
and
other.
4. Locate V
CAP
and V
dividers near the part and away
OUT
from switching components. Kelvin the top of resistor
dividers to the positive terminals of C
CAP
and C
OUT
respectively. The bottom of the resistive dividers should
go back to the SGND pin. The feedback resistor con
nections should not be run along the high current feeds
from the C
capacitor.
OUT
5. Route ICAP and VCAP sense lines together, keep them
short. Same with VOUTSP and VOUTSN. Filter com
ponents should be placed near the part and not near
the sense resistors. Ensure accurate current sensing
with Kelvin connections at the sense resistors. See
Figure10.
6. The trace from the positive terminal of the input current
sense resistor, R
, to the VOUTSP pin carries the
SNSI
part’s quiescent and gate drive currents. To maintain
accurate measurement of the input current keep this
trace short and wide by placing R
near the part.
SNSI
DIRECTION OF SENSED CURRENT
.
R
SNSC
OR
R
SNSI
3350 F10
TO VCAP
TO ICAP
VOUTSP
Figure 10. Kelvin Current Sensing
OR
OR
VOUTSN
7. Locate the DRVCC and BST decoupling capacitors in
close proximity to the IC. These capacitors carry the
MOSFET drivers’ high peak currents. An additional 0.1μF
ceramic capacitor placed immediately next
to the DRVCC
pin can help improve noise performance substantially.
8. Locate the small-signal components away from high
frequency switching nodes (BST, SW, TG, and BG). All
of these nodes have very large and fast moving signals
and should be kept on the output side of the LTC3350.
9. The input ideal diode senses the voltage between V
and VOUTSP. V
should be connected near the source
IN
of the input ideal diode MOSFET. VOUTSP is used for
Kelvin sensing the input current. Place the input cur
rent sense resistor, R
, near the input ideal diode
SNSI
MOSFET with a short, wide trace to minimize resistance
between the drain of the ideal diode MOSFET and R
10. The output ideal diode senses the voltage between
,
-
VOUTSN and VCAP. VCAP is used for Kelvin sensing
the charge current. Place the output ideal diode near
the charge current sense resistor, R
, with a short,
SNSC
wide trace to minimize resistance between the source
of the ideal diode MOSFET and R
SNSC
.
11. The INFET and OUTFET pins for the external ideal diode
-
controllers have extremely limited drive current. Care
must be taken to minimize leakage to adjacent PC board
traces. 100nA of leakage
from these pins
will introduce
an additional offset to the ideal diodes of approximately
10mV. To minimize leakage, the INFET trace can be
guarded on the PC board by surrounding it with VOUT
connected metal. Similarly, the OUTFET trace should be
guarded by surrounding it with VCAP connected metal.
12. The VCC2P5 bypass capacitor should return to ground
away from switching and gate drive current paths.
num_caps 0x1A R 1:0Number of capacitors configured–36
chrg_status 0x1B R 11:0Charger status register–36
mon_status 0x1C R 9:0Monitor status register–37
alarm_reg 0x1D R 15:0Active alarms register0x0000 37
meas_cap 0x1E R 15:0Measured capacitance value–38
meas_esr 0x1F R 15:0Measured ESR value–38
meas_vcap1 0x20 R 15:0Measured capacitor one voltage–38
meas_vcap2 0x21 R 15:0Measured capacitor two voltage–38
meas_vcap3 0x22 R 15:0Measured capacitor three voltage–38
meas_vcap4 0x23 R 15:0Measured capacitor four voltage–38
meas_gpi 0x24 R 15:0Measured
meas_vin 0x25
meas_vcap 0x26 R 15:0Measured V
meas_vout 0x27 R 15:0Measured V
meas_iin 0x28 R 15:0Measured I
meas_ichg 0x29 R 15:0Measured I
meas_dtemp 0x2A R 15:0Measured die temperature–38
Registers at sub address 0x03, 0x18, 0x19, 0x2B-0xFF are unused.
R 15:0Measured V
15:0V
voltage reference DAC setting0xF34
CAP
undervoltage alarm level0x0000 35
IN
overvoltage alarm level0x0000 35
IN
undervoltage alarm level0x0000 35
CAP
overvoltage alarm level0x0000 35
CAP
undervoltage alarm level0x0000 35
OUT
overvoltage alarm level0x0000 35
OUT
overcurrent alarm level0x0000 35
IN
undercurrent alarm level0x0000 35
CHG
GPI pin voltage–38
voltage–38
IN
voltage–38
CAP
voltage–38
OUT
current–38
IN
current–38
CHG
32
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LTC3350
regisTer DescripTions
clr_alarms (0x00)
Clear Alarms Register: This register is used to clear alarms caused by exceeding a programmed limit. Writing a one to any bit in this register will cause its
respective alarm to be cleared. The one written to this register is automatically cleared when its respective alarm is cleared.
BIT(S)BIT NAMEDESCRIPTION
0clr_cap_uvClear capacitor undervoltage alarm
1clr_cap_ovClear capacitor overvoltage alarm
2clr_gpi_uvClear GPI undervoltage alarm
3clr_gpi_ovClear GPI overvoltage alarm
4clr_vin_uvClear V
5clr_vin_ovClear V
6clr_vcap_uvClear V
7clr_vcap_ovClear V
8clr_vout_uvClear V
9clr_vout_ovClear V
10clr_iin_ocClear input overcurrent alarm
11clr_ichg_ucClear charge undercurrent alarm
12clr_dtemp_coldClear die temperature cold alarm
13clr_dtemp_hotClear die temperature hot alarm
14clr_esr_hiClear ESR high alarm
15clr_cap_loClear capacitance low alarm
undervoltage alarm
IN
overvoltage alarm
IN
undervoltage alarm
CAP
overvoltage alarm
CAP
undervoltage alarm
OUT
overvoltage alarm
OUT
msk_alarms (0x01)
Mask Alarms Register: Writing a one to any bit in the Mask Alarms Register enables its respective alarm to trigger an SMBALERT.
BIT(S)BIT NAMEDESCRIPTION
0msk_cap_uvEnable capacitor undervoltage alarm
1msk_cap_ovEnable capacitor over
2msk_gpi_uvEnable GPI undervoltage alarm
3msk_gpi_ovEnable GPI overvoltage alarm
4msk_vin_uvEnable V
5msk_vin_ovEnable V
6msk_vcap_uvEnable V
7msk_vcap_ovEnable V
8msk_vout_uvEnable V
9msk_vout_ovEnable V
10msk_iin_ocEnable input overcurrent alarm
11msk_ichg_ucEnable charge undercurrent alarm
12msk_dtemp_coldEnable die temperature cold alarm
13msk_dtemp_hotEnable die temperature hot alarm
14msk_esr_hiEnable ESR high alarm
15msk_cap_loEnable capacitance low alarm
undervoltage alarm
IN
overvoltage alarm
IN
undervoltage alarm
CAP
overvoltage alarm
CAP
undervoltage alarm
OUT
overvoltage alarm
OUT
voltage alarm
For more information www.linear.com/LTC3350
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LTC3350
regisTer DescripTions
msk_mon_status (0x02)
Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an
SMBALERT.
BIT(S)BIT NAMEDESCRIPTION
0msk_mon_capesr_activeSet the SMBALERT when there is a rising edge on mon_capesr_active
1msk_mon_capesr_scheduledSet the SMBALERT when there is a rising edge on mon_capesr_scheduled
2msk_mon_capesr_pendingSet the SMBALERT when there is a rising edge on mon_capesr_pending
3msk_mon_cap_doneSet the SMBALERT when there is a rising edge on mon_cap_done
4msk_mon_esr_doneSet the SMBALERT when there is a rising edge on mon_esr_done
5msk_mon_cap_failedSet the SMBALERT when there is a rising edge on mon_cap_failed
6msk_mon_esr_failedSet the SMBALERT when there is a rising edge on mon_esr_failed
7–Reserved, write to 0
8msk_mon_power_failedSet the SMBALERT when there is a rising edge on mon_power_failed
9msk_mon_power_returnedSet the SMBALERT when there is a rising edge on mon_power_returned
15:10–Reserved, write to 0
cap_esr_per (0x
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10
seconds. Capacitance and ESR measurements will not repeat if this register is zero.
Regulation Reference: This register is used to program the capacitor voltage feedback loop’s reference voltage. Only bits 3:0 are active.
V
CAP
vshunt (0x06) 183.5µV per LSB
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will
shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be
programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt.
cap_uv_lvl (0x07) 183.5µV per LSB
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below
this level will trigger an alarm and an SMBALERT.
cap_ov_lvl (0x08) 183.5µV per LSB
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor
will trigger an alarm and an SMBALER
gpi_uv_lvl (0x09) 183.5µV per LSB
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm
and an SMBALERT.
04) 10 seconds per LSB
voltage rising above this level
T.
gpi_ov_lvl (0x0A) 183.5µV per LSB
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and
an SMBALERT.
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LTC3350
regisTer DescripTions
vin_uv_lvl (0x0B) 2.21mV per LSB
Undervoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage falling below this level will trigger an alarm and an
V
IN
SMBALERT.
vin_ov_lvl (0x0C) 2.21mV per LSB
Overvoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage rising above this level will trigger an alarm and an
V
IN
SMBALERT.
vcap_uv_lvl (0x0D) 1.476mV per LSB
Undervoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage falling below this level will trigger an alarm and
V
CAP
an SMBALERT.
vcap_ov_lvl (0x0E) 1.476mV per LSB
Overvoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage rising above this level will trigger an alarm and
V
CAP
an SMBALERT.
vout_uv_lvl (0x0F) 2.21mV per LSB
Undervoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage falling below this level will trigger an alarm and an
V
OUT
SMBALERT.
vout_ov_lvl (0x10) 2.21mV per LSB
Overvoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage rising above this level will trigger an alarm and an
V
OUT
SMBALERT.
iin_oc_lvl (0x11) 1.983µV/R
Input Overcurrent Level: This is an alarm threshold for the input current. If enabled, the current rising above this level will trigger an alarm and an
SMBALERT.
ichg_uc_lvl (0x12) 1.983µV/R
Charge Undercurrent Level: This is an alarm threshold for the charge current. If enabled, the current falling below this level will trigger an alarm and an
SMBALERT.
dtemp_cold_lvl (0x13) Temperature = 0.028°C per LSB – 251.4°C
Die Temperature Cold Level: This is an alarm threshold for the die temperature. If enabled, the die temperature falling below this level will trigger an alarm
and an SMBALERT.
dtemp_hot_lvl (0x14) Temperature = 0.028°C per LSB – 251.4°C
Die Temperature Hot Level: This is an alarm threshold for the die temperature. If enabled, the die temperature rising above this level will trigger an alarm
and an SMBALERT.
esr_hi_lvl (0x15) R
ESR High Level: This is an alarm threshold for the measured stack ESR. If enabled, a measurement of stack ESR exceeding this level will trigger an alarm
and an SMBALERT.
SNSI
SNSC
/64 per LSB
SNSC
per LSB
per LSB
cap_lo_lvl (0x16) 336µF • R
Capacitance Low Level: This is an alarm threshold for the measured stack capacitance. If enabled, if the measured stack capacitance is less than this level
it will trigger an alarm and an SMBALERT. When ctl_cap_scale is set to one the constant is 3.36 • R
For more information www.linear.com/LTC3350
T/RTST
.
T/RTST
per LSB
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LTC3350
regisTer DescripTions
ctl_reg (0x17)
Control Register: Several Control Functions are grouped into this register.
BIT(S)BIT NAMEDESCRIPTION
0ctl_strt_capesrBegin a capacitance and ESR measurement when possible; this bit clears itself
1ctl_gpi_buffer_enA one in this bit location enables the input buffer on the GPI pin. With a zero in this
2ctl_stop_capesrStops an active capacitance/ESR measurement.
3ctl_cap_scaleIncreases capacitor measurement resolution by 100x, this is used when measuring
15:4–Reserved
num_caps (0x1A)
Number of Capacitors: This register shows the state of the CAP_SLCT1, CAP_SLCT0 pins. The value read in this register is the number of capacitors
programmed minus one.
VALUECAPACITORS
0b001 Capacitor Selected
0b012 Capacitors Selected
0b103 Capacitors Selected
0b114 Capacitors Selected
chrg_status (0x1B)
Charger Status Register: This register provides real time status information about the state of the charger system. Each bit is active high.
BIT(S)BIT NAMEDESCRIPTION
0chrg_stepdownThe synchronous controller is in step-down mode (charging)
1chrg_stepupThe synchronous controller is in step-up mode (backup)
2chrg_cvThe charger is
3chrg_uvloThe charger is in under
4chrg_input_ilimThe charger is in input current limit
5chrg_cappgThe capacitor voltage is above power good threshold
6chrg_shntThe capacitor manager is shunting
7chrg_balThe capacitor manager is balancing
8chrg_disThe charger is temporarily disabled for capacitance measurement
9chrg_ciThe charger is in constant current mode
10–Reserved
11chrg_pfoInput voltage is below PFI threshold
15:12–Reserved
once a cycle begins.
location the GPI pin is measured without the buffer.
smaller capacitors.
in constant voltage mode
voltage lockout
36
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Page 37
LTC3350
regisTer DescripTions
mon_status (0x1C)
Monitor Status: This register provides real time status information about the state of the monitoring system. Each bit is active high.
BIT(S)BIT NAMEDESCRIPTION
0mon_capesr_activeCapacitance/ESR measurement is in progress
1mon_capesr_scheduledWaiting programmed time to begin a capacitance/ESR measurement
2mon_capesr_pendingWaiting for satisfactory conditions to begin a capacitance/ESR measurement
3mon_cap_doneCapacitance measurement has completed
4mon_esr_doneESR Measurement has completed
5mon_cap_failedThe last attempted capacitance measurement was unable to complete
6mon_esr_failedThe last attempted ESR measurement was unable to complete
7–Reserved
8mon_power_failedThis bit is set when V
9mon_power_returnedThis bit is set when the input is above the PFI threshold and the charger is able to
15:10–Reserved
alarm_reg (0x1D)
Alarms Register: A one in any bit in the register indicates its respective alarm has triggered. All bits are active high.
BIT(S)BIT NAMEDESCRIPTION
0alarm_cap_
1alarm_cap_ovCapacitor overvoltage alarm
2alarm_gpi_uvGPI undervoltage alarm
3alarm_gpi_ovGPI overvoltage alarm
4alarm_vin_uvV
5alarm_vin_ovV
6alarm_vcap_uvV
7alarm_vcap_ovV
8alarm_vout_uvV
9alarm_vout_ovV
10alarm_iin_ocInput overcurrent alarm
11alarm_ichg_ucCharge undercurrent alarm
12alarm_dtemp_coldDie temperature cold alarm
13alarm_dtemp_hotDie temperature hot alarm
14alarm_esr_hiESR high alarm
15alarm_cap_loCapacitance low alarm
uvCapacitor under
charge. It is cleared only when power returns and the charger is able to charge.
charge. It is cleared only when mon_power_failed is set.
undervoltage alarm
IN
overvoltage alarm
IN
undervoltage alarm
CAP
overvoltage alarm
CAP
undervoltage alarm
OUT
overvoltage alarm
OUT
falls below the PFI threshold or the charger is unable to
IN
voltage alarm
For more information www.linear.com/LTC3350
3350fc
37
Page 38
LTC3350
regisTer DescripTions
meas_cap (0x1E) 336µF • RT/R
Measured capacitor stack capacitance value. When ctl_cap_scale is set to one the constant is 3.36µF • R
meas_esr (0x1F) R
Measured capacitor stack equivalent series resistance (ESR) value
meas_vcap1 (0x20) 183.5µV per LSB
Measured voltage between the CAP1 and CAPRTN pins.
meas_vcap2 (0x21) 183.5µV per LSB
Measured voltage between the CAP2 and CAP1 pins.
meas_vcap3 (0x22) 183.5µV per LSB
Measured voltage between the CAP3 and CAP2 pins.
meas_vcap4 (0x23) 183.5µV per LSB
Measured voltage between the CAP4 and CAP3 pins.
meas_gpi (0x24) 183.5µV per LSB
Measurement of GPI pin voltage.
T/RTST
.
TST
/64 per LSB
SNSC
per LSB
meas_vin (0x25) 2.21mV per LSB
Measured Input Voltage.
meas_vcap (0x26) 1.476mV per LSB
Measured Capacitor Stack Voltage.
meas_vout (0x27) 2.21mV per LSB
Measured Output Voltage.
Application Circuit 6. 11V to 15V, 2.3A Zeta-SEPIC High Voltage Capacitor Charger with 2A Input Current Limit and 10V, 25W Backup Mode
PFO
CAPGD
SMBALERT
SCL
SDA
11V TO 15V
V
DD
C5
1µF
C
C
22nF
R1
10k
C2
1µF
LTC3350
R
SNSI
0.016Ω
VOUTSN OUTFET
OUTFBPFI
DRV
INTV
BST
TGATE
BGATE
CFP
CFN
ICAP
VCAP
VCAPP5
CAP4
CAP3
CAP2
CAP1
CAPRTN
CAPFB
V
OUT
10V
25W IN BACKUP
C
OUT
R
FBO1
768k
R
Q1
Si1555DL
100k
FBO2
CC
CC
C
0.1µF
SW
C6
470pF
C4
0.1µF
B
C3
4.7µF
C
B2
4.7µF
22µF
×5
MP1
Si7415DN
4.7µH
1Ω
10µF
L1
10µF
L2
4.7µH
+
MN2
FDMC86520L
C7
10µF
R
SNSC
0.014Ω
CAP: NICHICON UHW1V222MHD
L1, L2: COILCRAFT XAL4030-472ME
SET ctl_cap_scale TO 1
R
R
CAP
2200µF
35V
×2
CAPTOP
255k
CAPBOT
24.3k
3350 TA07
R
C
820pF
R
FBC1
787k
R
FBC2
28k
FBC3
604k
FBC
MN1
0.1µF
R
158k
R
20k
FDMC7660S
C1
PF1
V
INFET
VOUTM5VOUTSP
IN
PF2
R3
10k
PFO
CAPGD
SMBALERT
SCL
SDA
VCC2P5
CAP_SLCT0
CAP_SLCT1
GPI
VC
RT
ITST
R6
10M
SGND
PGND
V
IN
R2
10k
R5
107k
In a Zeta-SEPIC application there are several differences
in the monitoring features due to differences in how the
LTC3350 is configured. The capacitor voltage is measured
differently, it is no longer measured in the meas_vcap
register, but in the meas_vcap1 register. The scale factor
for meas_vcap1 must be adjusted for the resistor divider
connected to the CAP1 pin. Also in this configuration
the precision current load (ITST) for the capacitance test
cannot be used. The load on the capacitors are the external
dividers only. A capacitance measurement may still be
done. The results in the meas_cap_register will have an
LSB in Farads of:
–7
⎞
⎛
R
CAPTOP
1+
⎟
⎜
R
⎠
⎝
CAPBOT
R
T
R
⎤
⎞
L
⎥
⎟
⎠
⎛
0.2
⎜
V
⎝
CAP
–5.6 •10
C
=
LSB
⎡
In 1–
⎢
where RL is the total resistance to ground in parallel with
the capacitor, R
CAPTOP
the capacitor to CAP1 and R
is the top divider resistor from
CAPBOT
is the bottom divider
resistor from CAP1 to ground. The above equation is for
when the ctl_cap_scale bit is set to one. ESR measurements
may be possible with large capacitors with larger ESR’s.
However, the accuracy of the ESR measurement in this
application is significantly reduced. The ESR measurement
in the meas_esr register must be scaled up by the resistor
divider ratio. The voltage at the CAP1 pin should be kept
below the V
SHUNT
setting.
The voltage at the CAP1 pin will be above the default shunt
value (2.7V) when V
is greater than 31V. In order to
CAP
continue charging to 35V, the shunts should be disabled
by setting vshunt to zero (0x0000).
3350fc
42
For more information www.linear.com/LTC3350
Page 43
LTC3350
Typical applicaTions
Application Circuit 7. 4.8V to 12V, 10A Supercapacitor Charger with 6.4A Input Current Limit and 5V, 30W Backup Mode
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.00 REF
5.00 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
5.15 ±0.05
3.15 ±0.05
0.25 ±0.05
0.50 BSC
5.5 REF
6.10 ±0.05
7.50 ±0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ±0.05
0.00 – 0.05
PACKAGE
OUTLINE
3.00 REF
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
37
38
0.40 ±0.10
1
2
44
7.00 ±0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5.50 REF
0.200 REF
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
5.15 ±0.10
3.15 ±0.10
BOTTOM VIEW—EXPOSED PAD
Formoreinformationwww.linear.com/LTC3350
R = 0.125
TYP
(UH) QFN REF C 1107
R = 0.10
TYP
3350fc
Page 45
LTC3350
revision hisTory
REVDATEDESCRIPTIONPAGE NUMBER
A09/14Modified I
Changed 5V to 6V in back-up mode under the Power MOSFET Selection section
Changed V
Modified Application Circuit
B01/15Remove V
Remove Conditions on I
Change Analog-to-Digital Converter section
Change range in the General Purpose Input section to 0V to 5V
Change MN1 to MP1 just below Figure 6
Change M1, M2 to MN1, MN2 in the PCB Layout Considerations section
Increase page numbers to all entries on the Register Map
For meas_vcap change µV to mV
Change name to Application Circuit 6
C08/15Modified Order Information Table for temperature grade identified by label on shipping container
Modified Input Overvoltage Protection Section
Add sentence at the end of the first paragraph
Add three sentences to the end of the Capacitance and ESR Measurements section
Replace sentence in the Limit Checking and Alarms section
Modified Figure 3
Add new supplier to Table 2, Supercapacitor Suppliers
Add Note 12 in the PCB Considerations Layout section
Change reference from R
Change reference from R
Change value of R
equations in C
RMS
voltage reference DAC setting
CAP
Common Mode Range from Electrical Characteristics
CMI
CAPBOT
and C
OUT
Falling and Rising
PFO
to RT/R
TST/RT
to RT/R
TST/RT
to 24.3k from 20k. Also add two sentences to the end of the text
: 2.7V to 5V, 1A Main Buck Regulator, 5A Boost Backup
OUT
Regulator Powered from Single Supercapacitor, Overvoltage Protection, 20Lead 4mm × 4mm QFN Package.
High Efficiency Step-Up/Step-Down Charging of Tw o Series Supercapacitors.
Automatic Cell Balancing. Programmable Charging Current to 500mA (Single
Inductor), 1A (Dual Inductor). 12-Lead 3mm × 4mm DFN Package
NiCd Batteries and Supercapacitors. Input Supply Range: 4.5V to 19V,
Programmable Charge Current Up to 3A, 38-Lead 5mm × 7mm QFN Package.
Constant-Current/Constant-V
Supercapacitor Stack. V
oltage Linear Charger for 2-Cell Series
: Li-Ion/Polymer Battery, a USB Port, or a 2.7V to