LINEAR TECHNOLOGY LTC2970, LTC2970-1 Technical data

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FEATURES

LTC2970/LTC2970-1

Dual I2C Power

Supply Monitor and

Margining Controller

DESCRIPTIO

■

Less Than ±0.5% Total Unadjusted Error 14-Bit ΔΣ

ADC with On-Chip Reference

■

Dual, 8-Bit IDACs with 1x Voltage Buffers

■

Linear, Voltage Servo Adjusts Supply Voltages by

Ramping IDAC Outputs Up/Down

■

I2C™ Bus Interface (SMBus Compatible)

■

Extensive, User Conﬁ gurable Fault Monitoring

■

On-Chip Temperature Sensor

■

Available in 24-Lead 4mm × 5mm QFN Package

APPLICATIO S

■

Dual Power Supply Voltage Servo

■

Monitoring Supply Voltage and Current

■

Programmable Power Supplies

■

Programmable Reference

The LTC®2970 is a dual power supply monitor and

margining controller with an SMBus compatible I

C bus

interface. A low-drift, on-chip reference and 14-bit ΔΣ A/D converter allow precise measurements of supply voltages, load currents or internal die temperature. Fault manage-

⎯A⎯L⎯E⎯R⎯

ment allows

T to be asserted for conﬁ gurable over and under voltage fault conditions. Two voltage buffered, 8-bit IDACs allow highly accurate programming of DC/DC converter output voltages. The IDACs can be conﬁ gured to automatically servo the power supplies to the desired voltages using the ADC. The LTC2970-1 adds a tracking feature that can be used to turn multiple power supplies on or off in a controlled manner.

The bus address is set to 1 of 9 possible combinations by pin strapping the ASEL0 and ASEL1 pins. The LTC2970/ LTC2970-1 are packaged in the 24-lead, 4mm × 5mm QFN package.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATIO

Dual Power Supply Monitor and Controller (One of Two Channels Shown)

8V TO 15V

12V

DC/DC

CONVERTER

RUN/SS

SGND

GND

OUT

1/2 LTC2970

I+

I–

LOAD

IN0_BM

IN0_BP

OUT0

IN0_AP

OUT0

IN0_AM

GND

ASEL0 ASEL1

GPIO_CFG

ALERT

SCL

SDA

GPIO_0

REF

ADC Total Unadjusted Error

vs Temperature

0.50

0.1μF

C BUS

SMBUS

()

COMPATIBLE

0.1μF

29701 TA01

15 PARTS MOUNTED ON PCB

0.25

ERROR (%)

–0.25

–0.50

–25 0 50

–50

TEMPERATURE (°C)

ADC VIN = 5V

29701 TA01b

100

29701fc

LTC2970/LTC2970-1

ABSOLUTE AXI U RATI GS

(Notes 1 and 2)

Supply Voltages:

......................................................... –0.3V to 6V

.................................................... –0.3V to 15V

12V

Digital Input/Output Voltages:

ASEL0, ASEL1 ............................ –0.3V to V

SDA, SCL, GPIO_CFG,

⎯A⎯L⎯E⎯R⎯

T, GPIO_0, GPIO_1 .......................... –0.3V to 6V

Analog Voltages:

IN0_AP

IN0_BM

IN1_BP

OUT0

, I

, V

OUT1

IN0_AM

IN1_AP

IN1_BM

, V , V , V

IN0_BP IN1_AM

, V

OUT0

.............. –0.3V to 6V

OUT1

, REF ......................... –0.3V to V

RGND .................................................... –0.3V to 0.3V

Operating Temperature Range:

LTC2970C ................................................ 0°C to 70°C

LTC2970I ............................................. –40°C to 85°C

Storage Temperature Range ...................–65°C to 125°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

+ 0.3V

PIN CONFIGURATION

TOP VIEW

RGND

REF

ASEL0

ASEL1

24 23 22 21 20

IN0_AP

IN0_AM

IN0_BP

IN0_BM

IN1_AP

IN1_AM

IN1_BP

24-LEAD (4mm × 5mm) PLASTIC QFN

EXPOSED PAD (PIN 25) IS GND MUST BE SOLDERED TO PCB

JMAX

8 9

10 11 12

OUT0VOUT1

12V

IN1_BM

UFD PACKAGE

= 125°C, θJA = 37°C/W

GPIO_CFG

SDA

SCL

ALERT

GPIO_0

GPIO_1

OUT0

OUT1

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2970CUFD#PBF LTC2970CUFD#TRPBF 2970 24-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C

LTC2970CUFD-1#PBF LTC2970CUFD-1#TRPBF 29701 24-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C

LTC2970IUFD#PBF LTC2970IUFD#TRPBF 2970 24-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C

LTC2970IUFD-1#PBF LTC2970IUFD-1#TRPBF 29701 24-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

29701fc

LTC2970/LTC2970-1

The ● denotes the speciﬁ cations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at T C

= 100nF and C

VDD

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power-Supply Characteristics

V12

LKO

12VIN Supply Current V

VDD Supply Current VDD = 5V, V

VDD Undervoltage Lockout VDD Ramping-Down, V

Supply Input Operating Range

Regulator Output Voltage 8V ≤ V

Regulator Output Voltage Temperature Coefﬁ cient

Regulator Output Voltage Load Regulation

Regulator Line Regulation 8V ≤ V

Regulator Output Short-Circuit Current V

12VIN

12VIN Supply Operating Range

Voltage Reference Characteristics

REF

Reference Output Voltage 1.229 V

Reference Voltage Temperature Coefﬁ cient

Reference Overdrive Voltage Input Range

ADC Characteristics

N_ADC Resolution N_ADC = 8.192V/16384 500 μV/LSB

TUE_ADC Total Unadjusted Error V

INL_ADC Integral Nonlinearity (Note 4)

DNL_ADC Differential Nonlinearity (Note 7)

IN_ADC

OS_ADC

Input Voltage Range

Offset Error

Offset Error Drift 0.19 μV/°C

GAIN_ADC Gain Error Full-Scale V

Gain Error Drift 3 ppm/°C

CONV_ADC

IN_ADC

LEAK_ADC

Conversion Time 33.3 ms

Input Sampling Capacitance 3pF

Input Sampling Frequency 61.4 kHz

Input Leakage Current 0V < VIN < 6V

IDAC Output Current Characteristics

N_I

OUT

INL_I

OUT

DNL_I

FS-IOUT

DRIFT-IOUT

OS-IOUT

Resolution (Guaranteed Monotonic) 8 Bits

Integral Nonlinearity V

Differential Nonlinearity V

OUT

Full-Scale Output Current V

Output Current Drift DAC Code = 'hff 32 ppm/°C

Offset Current DAC Code = 'h00

= 100nF.

REF

Undervoltage Lockout Hysteresis 118 mV

= 25°C. V

= 12V, VDD Floating

12VIN

–1mA ≤ I

12VIN

= 12V, VDD = 0V

12VIN

= 3V, VIN = V

< VDD – 1.5V

IOUTn

< VDD – 1.5V

IOUTn

< VDD – 1.5V, DAC Code = 'hff

IOUTn

12VIN

= V

12VIN

≤ 15V, –1mA ≤ I

≤ 0 160 ppm/mA

VDD

≤ 15V, I

VDD

INn_xP

= 6V

= 12V, VDD and REF pins ﬂ oating unless otherwise indicated,

●

12VIN

= V

VDD

≤ 0

●

3.7 4.14 4.4 V

●

4.5 5.75 V

●

4.75 4.95 5.25 V

= 0mA 80 ppm/V

●

–5 –34 –63 mA

●

815V

●

11.5V

– V

INn_xM

(Note 3)

●

–4.5 2 4.5 LSB

●

06V

●

–1000 –316 1000 μV

●

–236 –255 –276 μA

●

4.24 7.5 mA

3.7 5 mA

10 ppm/°C

2 ppm/°C

±0.5 %

±0.5 LSB

±0.4 %

±0.1 μA

±1 LSB

±0.1 μA

29701fc

LTC2970/LTC2970-1

The ● denotes the speciﬁ cations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at T

= 100nF and C

VDD

= 100nF.

REF

= 25°C. V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage Buffered IDAC Output Characteristics

INL_V

DNL_V

OS-VOUT

OUT

Integral Nonlinearity R

Differential Nonlinearity R

OUT

Offset Voltage VOS = V

Output Voltage Drift No Load on V

Load Regulation 0.1V < V

Leakage Current V

Short-Circuit Current Low V

Short-Circuit Current High V

= 10kΩ, No Load on V

IOUTn

= 10kΩ, No Load on V

IOUTn

– V

OUTn

< VDD – 1.5V, I

OUTn

0.1V < V

OUTn

< VDD – 1.5V, I

OUTn

High-Z, 0V ≤ V

Shorted to GND

Shorted to V

Soft Connect Comparator Characteristics (CMP0, CMP1)

Offset Voltage ±3 mV

Temperature Sensor Characteristics

TMP Gain 0.25 °C/LSB

Voltage Divider Characteristics

12V

GAIN_12V

Gain

Digital Inputs SCL, SDA, GPIO_CFG, GPIO_0, GPIO_1

Input High Threshold Voltage SDA, SCL

GPIO_CFG, GPIO_0, GIPO_1

Input Low Threshold Voltage SDA, SCL

GPIO_CFG, GPIO_0, GIPO_1

LEAK

HYST

Input Hysteresis 0.08 V

Input Leakage Current 0V ≤ VIN ≤ 6V

Input Capacitance 10 pF

Three State Inputs ASEL[1:0]

IH_ASEL

IL_ASEL

IN,HL

IN,Z

Open Drain Outputs SDA, GPIO_CFG, GPIO_0, GPIO_1,

Input High Threshold Voltage

Input Low Threshold Voltage

High, Low Input Current ASEL[1:0] = 0, V

High Z Input Current

⎯A⎯L⎯E⎯R⎯

Output Low Voltage I

SINK

= 3mA

Input Leakage Current 0V ≤ VIN ≤ 6V

= 12V, VDD and REF pins ﬂ oating unless otherwise indicated,

12VIN

●

1.6 ±10 mV

, No Load on V

IOUTn

OUTn

(Note 5)

OUTn

0.17 μV/°C

Source = 1mA –57 ppm/mA

VOUTn

Sink = 1mA 100 ppm/mA

VOUTn

●

0.329 0.333 0.335 V/V

●

1.5 V

●

1.0 V

●

0.5 V

●

±2 μA

●

1 ±100 nA

VDD – 0.5 V

OUTn

≤ V

±1 LSB

–50 mA

50 mA

2.1 V

1.6 V

±1 μA

±20 μA

0.4 V

±1 μA

29701fc

LTC2970/LTC2970-1

The ● denotes the speciﬁ cations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

C Interface Timing Characteristics

SCL

LOW

HIGH

BUF

HD,STA

SU,STA

SU,STO

HD,DAT

SU,DAT

SETUP_GPIO

HOLD_GPIO

OUT_GPIO

Internal Timers

TIMEOUT_SMB

SETUP_ADC

TIMEOUT_

SYNC

HOLD_TRACK

Serial Clock Frequency (Note 6)

Serial Clock Low Period (Note 6)

Serial Clock High Period (Note 6)

Bus Free Time Between Stop and Start (Note 6)

Start Condition Hold Time (Note 6)

Start Condition Setup Time (Note 6)

Stop Condition Setup Time (Note 6)

Data Hold Time (LTC2970 Receiving Data) Data Hold Time (LTC2970 Transmitting Data)

Data Setup Time (LTC2970 Receiving Data) (Note 6)

Pulse Width of Spike Suppressed (Note 6)

GPIO_0 and GPIO_1 Setup Time GPIO_0 and GPIO_1 input setup time

GPIO_0 and GPIO_1 Hold Time GPIO_0 and GPIO_1 input hold time

GPIO_0 and GPIO_1 Output Time GPIO_0 and GPIO_1 output delay after

Stuck BUS Timer The LTC2970 will release the I2C bus and

ADC Channel Setup Time After selecting a new ADC channel, the

Tracking SYNC Failure Timer LTC2970-1 Only: The LTC2970-1 will

Tracking IDAC Disconnect Delay LTC2970-1 Only: After the tracking

= 25°C.

(Note 6)

prior to the 26th rising SCL of an IO()

C read. These inputs must be valid and stable by this time to be returned in the IO() read result. (Note 6)

after the 26th rising SCL of an IO() I read. These inputs must be held until this amount of time has elapsed to be returned in the IO() read result. (Note 6)

the 35th rising SCL of an I

C write. These outputs will become high impedance or begin driving low by this time. (Note 6)

terminate the current command if the command is not completed before this amount of time has elapsed.

LTC2970 will wait this amount of time to allow the analog input to settle before beginning an ADC conversion.

abort a pending SYNC() command if a tracking command is not received before this amount of time has elapsed.

algorithm asserts CPIO_CFG low, the LTC2970-1 will delay disconnecting the IDACs from the power supply feedback nodes by this amount of time. Used while tracking power supplies on.

●

10 400 kHz

●

1.3 μs

●

0.6 μs

●

1.3 μs

●

600 ns

●

600 ns

●

600 ns

●

300 900

●

100 ns

●

2.5 μs

●

2.5 μs

●

98 ns

2.5 μs

ns ns

24 32 39 ms

304 μs

255 ms

32 ms

29701fc

LTC2970/LTC2970-1

The ● denotes the speciﬁ cations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁ cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SETUP_TRACK

DEC_TRACK

Tracking IDAC Disconnect Delay LTC2970-1 Only: After the tracking

Tracking IDAC Decrement Rate LTC2970-1 Only: The LTC2970-1 changes

= 25°C.

algorithm asserts CPIO_CFG high, the LTC2970-1 will wait this amount of time before starting to decrement Chn_a_ delay_track[9:0]. Used while tracking power supplies off.

Chn_a_delay_track[9:0] at this rate.

32 ms

88 μs/LSB

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise speciﬁ ed.

Note 3: TUE (%) is deﬁ ned as:

INL V LSB V

+500

•Gain Error

100

(• / )

TIMING DIAGRAM

The I2C Bus Speciﬁ cation

SDA

SU;DAT

SCL

LOW

Note 4: Integral nonlinearity (INL) is deﬁ ned as the deviation of a code from a straight line passing through the actual endpoints (0V and 6V) of the transfer curve. The deviation is measured from the center of the quantization band.

Note 5: Nonlinearity is deﬁ ned from the ﬁ rst code that is greater than or equal to the maximum offset speciﬁ cation to code 255 (full-scale).

Note 6: Maximum capacitive load, C clock risetime (t (20 + 0.1 • C

) and falltime (tf) are: (20 + 0.1 • CB)(ns) < tr < 300ns and

)(ns) < tf < 300ns. CB = capacitance of one bus line in pF.

SCL and SDA external pull-up voltage, V

, for SCL and SDA is 400pF. Data and

, is 3V < VIO < 5.5V.

Note 7: This speciﬁ cation is guaranteed by design.

HD;STA

BUF

START

CONDITION

HD;STA

HD;DAT

HIGH

SU;STA

REPEATED START

CONDITION

SU;STO

STOP

CONDITION

START

CONDITION

29701 TD

29701fc

TYPICAL PERFOR A CE CHARACTERISTICS

ADC Total Unadjusted Error vs Temperature ADC INL ADC DNL

0.050

0.025

–0.025

–0.050

–0.075

ERROR (%)

–0.100

–0.125

–0.150

–0.175

BASED ON AVERAGE OF 15 PARTS ASSEMBLED ON 1/8" THICK PCB

3.3V

ADC VIN = 5V

–50

–25

25 10

TEMPERATURE (oC)

1.8V

2.5V

29701 G01

2.5

2.0

1.5

1.0

0.5

ERROR (LSBs)

–0.5

–1.0

INPUT VOLTAGE (V)

LTC2970/LTC2970-1

1.00

0.75

0.50

0.25

–0.25

ERROR (LSBs)

–0.50

–0.75

–1.00

29701 G02

12 4

INPUT VOLTAGE (V)

29701 G03

ADC Zero Code Center Offset Voltage vs Temperature

–305

–310

–315

(MV)

–320

–325

–330

–335

–50

–25

ADC Noise Histogram

10,000,000

1,000,000

NUMBER OF READINGS

VIN = 0V

100000

10,000

1000

100

02550

TEMPERATURE (oC)

75 100

29701 G04

ADC Rejection vs Frequency at V

–10

–20

–30

–40

–50

–60

REJECTION (dB)

–70

–80

–90

–100

100

FREQUENCY AT VIN (Hz)

Voltage Buffered IDAC INL

0.50

CHANNELS 0 AND 1 SHOWN

= R

IOUT1

= 10k7

IOUT0

0.25

ERROR (LSBs)

–0.25

1000

10000

29701 G05

ADC Rejection vs Frequency at V

–10

–20

–30

–40

–50

–60

REJECTION (dB)

–70

–80

–90

–100

5000

15000 20000

10000

FREQUENCY AT VIN (Hz)

Voltage Buffered IDAC DNL

0.50

CHANNELS 0 AND 1 SHOWN

= R

IOUT0

0.25

ERROR (LSBs)

–0.25

IOUT1

= 10k7

25000

30000

29701 G06

–1 0 2

–2

OUTPUT CODE (LSBs)

29701 G07

–0.50

100

DAC CODE

150

200

29701 G08

250

–0.50

100

DAC CODE

150

200

250

29701 G09

29701fc

LTC2970/LTC2970-1

TYPICAL PERFOR A CE CHARACTERISTICS

IDAC Output Current vs Temperature

257.4

IDAC CODE = 'hff

= 13kΩ

IOUT

257.2

257.0

256.8

256.6

OUTPUT CURRENT (μA)

256.4

256.2

–50

02550

–25

TEMPERATURE (°C)

Voltage Buffered IDAC Load Regulation Sinking

0.35

= 0.1V

IOUT

0.30

0.25

0.20

0.15

0.10

OUTPUT VOLTAGE (V)

75 10

29701 G10

90oC

25oC

–45oC

Offset Voltage

OUTn

vs Temperature

1.620

IDAC CODE = 'h00

1.615

1.610

1.605

1.600

OFFSET VOLTAGE (mV)

1.595

1.590

–50

02550

–25

TEMPERATURE (oC)

Voltage Buffered IDAC Transient Response to 1LSB DAC Code Change

100k7 SERIES RESISTANCE ON V R

= 10k7

IOUT

CODE 'h7f

10mV PER DIVISION

75 100

29701 G11

OUTn

CODE 'h80

Voltage Buffered IDAC Load Regulation Sourcing

3.500

3.498

3.496

3.494

OUTPUT VOLTAGE (V)

3.492

= 3.5V

IOUTn

3.490 –2

–4

CURRENT (mA)

Voltage Buffered IDAC SoftConnect Transient Response

100k7 SERIES RESISTANCE ON V R

= 10k7

IOUT

CODE 'h80

HIGH-Z

10mV PER DIVISION

–6

CONNECTED

–8

OUTn

25oC

–45oC

90oC

–10

29701 G12

0.05

246 10

CURRENT (mA)

Voltage Buffered IDAC Transient Response During Transition from On State to High-Z State

100k7 SERIES RESISTANCE ON V R

= 10k7

IOUT

HIGH-Z

CONNECTED

10mV PER DIVISION

10Ms PER DIVISION

OUTn

5Ms PER DIVISION

Regulator Output Voltage

= 12V

= 0A

50 100

–25 0

25 75

TEMPERATURE (oC)

29701 G15

29701 G18

29701fc

29701 G13

29701 G16

1Ms PER DIVISION

Temperature Sensor Error vs Temperature

1.5

1.0

0.5

ERROR (oC)

–0.5

–1.0

–1.5

–50

02550

–25

TEMPERATURE (oC)

29701 G14

75 100

29701 G17

V vs Temperature

4.945

V I

VDD

4.944

4.943

4.942

(V)

4.941

4.940

4.939

4.938

–50

12VIN

TYPICAL PERFOR A CE CHARACTERISTICS

VDD Regulator Load Regulation

–100

–200

–300

(ppm)

–400

ΔV

–500

–600

–700

= 12V

12VIN

–800

–1 –2 –4

CURRENT (mA)

–45°C

25°C90°C

–3

29701 G19

(ppm)

–100

ΔV

–200

–300

–400

–500

–5

Regulator Line Regulation

400

NO LOAD ON V

300

200

100

25°C

–45°C

90°C

10 15

12VIN

(V)

13 14

UUU

PI FU CTIO S

LTC2970/LTC2970-1

VDD Regulator Short-Circuit Current vs Temperature

–25

= 12V

12VIN

= 0V

–30

–35

SHORT-CIRCUIT CURRENT (mA)

–40

–50

–25 0 25 50

TEMPERATURE (°C)

29701 G20

75 100

29701 G21

(Pin 1): Positive CH0_A ADC Multiplexer Input.

IN0_AP

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be conﬁ gured to servo IDAC0.

(Pin 2): Negative CH0_A ADC Multiplexer Input.

IN0_AM

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_A can be conﬁ gured to servo IDAC0.

(Pin 3): Positive CH0_B ADC Multiplexer Input. The

IN0_BP

output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only.

(Pin 4): Negative CH0_B ADC Multiplexer Input.

IN0_BM

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH0_B is a voltage monitor input only.

(Pin 5): Positive CH1_A ADC Multiplexer Input.

IN1_AP

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be conﬁ gured to servo IDAC1.

(Pin 6): Negative CH1_A ADC Multiplexer Input.

IN1_AM

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_A can be conﬁ gured to servo IDAC1.

(Pin 7): Positive CH1_B ADC Multiplexer Input. The

IN1_BP

output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only.

(Pin 8): Negative CH1_B ADC Multiplexer Input.

IN1_BM

The output of the differential, 7:1 multiplexer connects to the input of the ADC. CH1_B is a voltage monitor input only.

(Pin 9): VDD Power Supply, Voltage Monitor Input,

and Internal 5V Regulator Output. The supply input range is 4.5V to 5.75V. The V to the ADC through an internal mux. Bypass the V to device ground with a 100nF capacitor (C input voltage supply is available, ﬂ oat the V power the LTC2970 from the 12V

(Pin 10): 12V Power Supply and Voltage Monitor

12V

Input. An internal regulator generates 5V from 12V input range for 12V

pin voltage can be connected

). If no 5V

VDD

pin and

pin.

. The

is 8V to 15V. Bypass this pin with a

100nF capacitor. The regulator’s output is connected to the

pin. The 12VIN pin voltage can also be monitored by

the ADC through a 3:1 attenuator and the internal mux. If no 12V supply input is available, tie the 12V

to the VDD

pin and operate from 4.5V to 5.75V.

(Pin 11): CH0 Voltage Output. Buffered version of

OUT0

IDAC0 output voltage.

29701fc

LTC2970/LTC2970-1

UUU

PI FU CTIO S

(Pin 12): CH1 Voltage Output. Buffered version of

OUT1

IDAC1 output voltage.

(Pin 13): IDAC1 Current Output. Connect a resistor

OUT1

between this pin and the point-of-load ground for channel

1. The IDAC sources between 0 and 255μA.

(Pin 14): IDAC0 Current Output. Connect a resistor

OUT0

between this pin and the point-of-load ground for channel

0. The IDAC sources between 0 and 255μA.

GPIO_1 (Pin 15): General Purpose Input or Open Drain Digital Output. GPIO_1 can be conﬁ gured as the IDAC Fault or Faults output, a digital input, or an open-drain digital output.

GPIO_0 (Pin 16): General Purpose Input or Open Drain Digital Output. GPIO_0 can be conﬁ gured as the voltage monitor power-good or power-good bar output, a digital input, or a programmable open-drain output. Power good is the NOR of all instantaneous OV and UV faults; it does not include IDAC faults.

⎯A⎯L⎯E⎯R⎯

T (Pin 17): Open Drain Digital Output. Connect the

⎯A⎯L⎯E⎯R⎯

SMBALERT signal to this pin. either IDAC0 or IDAC1 rails out (optional), or when one of the monitored voltages ventures outside its UV and OV thresholds (also optional).

SCL (Pin 18): Serial Bus Clock Input.

T is asserted low when

SDA (Pin 19): Serial Bus Data Input and Output.

GPIO_CFG (Pin 20): GPIO Conﬁ guration Digital Input and

Open Drain Output. Pulling GPIO_CFG high will cause the GPIO_0 and GPIO_1 open-drain outputs to automatically assert low after a power-on reset. If GPIO_CFG is pulled low, then GPIO_0 and GPIO_1 do not assert low after power-up.

ASEL1 (Pin 21): Slave Address Select Bit 1. Tie this pin to the V location (see Table 2).

ASEL0 (Pin 22): Slave Address Select Bit 0. Tie this pin to the V location (see Table 2).

REF (Pin 23): Internal Reference Output or ADC Reference Overdrive Input. The voltage at this pin determines the full-scale input voltage of the delta-sigma ADC (V

SCALE

decouples the reference output from this pin. Bypass this pin to RGND with a 100nF capacitor (C

RGND (Pin 24): Reference Ground. Connect to device ground.

GND (Pin 25): Device Ground. Must be soldered to ground.

pin, ground, or ﬂ oat in order to select the address

= 6.65 • V

, typically). An internal 3.5k resistor

REF

FULL-

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BLOCK DIAGRA

LTC2970/LTC2970-1

IN0_AP

IN0_AM

IN0_BP

IN0_BM

IN1_AP

IN1_AM

IN1_BP

IN1_BM

1012V

25GND

12V

DDP

DDM

5V REGULATOR

OUT

IDAC0 8 BITS

VBUF0

0μA TO 255μA

CMP0

–

14 I

11 V

OUT0

–

TEMP

SENSOR

23REF

24RGND

18SCL

19SDA

(400kHz, SMBUS COMPATIBLE)

22ASEL0

21ASEL1

16GPIO_0

DAC SOFT CONNECT FUNCTION

15GPIO_1

17ALERT

20GPIO_CFG

MANAGE FAULT REPORTING

TRACKING CONTROL (LT2970-1)

TSNSP

TSNSM

CH0_AP

CH0_AM

CH0_BP

CH0_BM

CH1_AP

CH1_AM

CH1_BP

CH1_BM

7:1 MUX

I2C BUS INTERFACE

SERVO CONTROLLER

SERVO FUNCTION

MONITOR FUNCTION

WATCH DOG

POR

DELTA-SIGMA

–

6.65X (TYP)

OSCILLATOR

14-BIT

A/D

POR

ADC

CLOCKS

3.5k

UVLO

REFERENCE

1.229V (TYP)

20Ω

CLOCK

GENERATION

IDAC1 8 BITS

VBUF1

–

RAM

ADC_Results MONITOR LIMITS SERVO TARGETS

REGISTERS

I/O CONFIGURATION IDAC0 IDAC1 ADC MONITOR FAULT ENABLE INSTANTANEOUS FAULTS LATCHED FAULTS

0μA TO 255μA

CMP1

–

13 I

OUT1

12 V

OUT1

29701 BD

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LTC2970/LTC2970-1

TABLE OF CO TE TS

1. LTC2970 Operation Overview .............................................................................................................................13

C Serial Digital Interface .................................................................................................................................14

2. I

3. Register Command Set .......................................................................................................................................15

4. Detailed I

5. Soft Connecting the LTC2970 to the Power Supply Feedback Node ..................................................................20

6. Hard Connecting the LTC2970 to the Power Supply Trim Pin ............................................................................20

7. Programming a Previously Connected IDAC ......................................................................................................21

8. Disconnecting the LTC2970 from the Power Supply Trim Pin ...........................................................................21

9. Tracking Power Supplies Overview (LTC2970-1 Only) .......................................................................................21

10. Tracking Power Supplies On (LTC2970-1 Only) .................................................................................................21

11. Tracking Power Supplies Off (LTC2970-1 Only) .................................................................................................22

12. Continuous Power Supply Voltage Servo ...........................................................................................................23

C Command Register Descriptions ...................................................................................................16

(For Operations Sections)

13. One Time Power Supply Voltage Servo .............................................................................................................24

14. One Time Power Supply Voltage Servo with Repeat On Fault ..........................................................................24

15. Conﬁ guring ADC to Monitor Input Channels and Internal Temperature Sensor ................................................24

16. Generating and Monitoring Instantaneous Faults ..............................................................................................25

17. Generating and Monitoring Latched Faults ........................................................................................................26

18. General Purpose Input/Output Pins ....................................................................................................................27

19. Advanced Development Features .......................................................................................................................27

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OPERATIO

LTC2970/LTC2970-1

1. LTC2970 Operation Overview

The LTC2970 is designed to control and monitor two power supplies. The LTC2970’s superior accuracy allows it to precisely servo each supply’s output voltage over a wide range of operating conditions; increasing accuracy, reducing power requirements and component costs. Margining may be performed with equal ease and precision. The monitoring functions allow for increased reliability by alerting a system host about incipient failures before they occur. The seven channel ADC may also be used to monitor current, temperature, and the 5V or optional 12V supply.

The LTC2970’s unique architecture and control algorithm have been especially tailored for power supply management. The soft connect feature allows the LTC2970 to begin controlling a power supply without perturbing its initial value. The delta-sigma ADC architecture was speciﬁ cally chosen to average out power-supply noise and allow the LTC2970 to ignore fast transients. Unlike discrete time DACs, the LTC2970’s continuous time, voltage buffered IDAC is ideal for noise sensitive applications. The servo algorithm limits the IDAC step size to one LSB per iteration in order to minimize power supply transients. The point of load ground reference for the IDAC outputs minimize errors that would otherwise occur in a power system that experiences ground bounce. By selecting two resistor values, the user can choose the appropriate resolution while providing an important hardware range limit beyond which the supply may not be driven. The servo on fault option allows the LTC2970 to further reduce output voltage disturbances by only stepping the IDAC when the output voltage drifts outside of a user programmable window. The LTC2970 powers up in a high impedance state and will not interfere with default power supply operation. Similarly, powering down the LTC2970 will restore its high impedance state.

All communication with the LTC2970 is performed over an industry standard I also meets all SMBus setup times, hold times, and timeout requirements. The ALERT pin may be used to signal that one or more of the fourteen conﬁ gurable fault limits have been reached. Each fault may be individually masked. The

C interface supports word reads, word writes and the

I SMBus Alert Response Address protocol. Two general purpose IO pins may be used to provide additional fault information or user deﬁ ned system control. Powering down the LTC2970 will not interfere with I

The LTC2970-1 enables power supply tracking and sequencing with the addition of a few external components. A special global address and synchronization command allow multiple LTC2970-1’s to track and sequence multiple pairs of power supplies.

The LTC2970 can perform the following operations:

• Accept all programming commands and report status over the I

• Command each voltage buffered IDAC to connect to the corresponding power supply’s feedback node through an external resistor using the IDAC code that most closely approximates the feedback node’s regulation voltage (Soft Connect).

• Command each voltage buffered IDAC output to connect to the corresponding power supply’s feedback node through an external resistor with a user-selected IDAC code (Hard Connect).

• Change the code of a previously connected IDAC.

• Disconnect each voltage buffered IDAC output from the power supply’s feedback node.

• LTC2970-1 Only: Track two power supplies up or down. Multiple LTC2970-1’s can be conﬁ gured to track simultaneously or in a sequence.

C or SMBus bus.

C bus. The LTC2970 I2C interface

C operation.

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LTC2970/LTC2970-1

OPERATIO

• Continuously servo one or both supplies to a programmed voltage.

• Perform a one-time servo of one or both supplies to a programmed voltage and hold the servo codes in the controlling IDAC.

• Perform a one time servo of one or both supplies to a programmed voltage and hold the code(s) in the controlling IDAC(s) until over/under voltage monitoring detects a fault, at which point a control bit may be used to allow the LTC2970 to servo back to the initial voltage target.

• Select any combination of seven possible ADC channels to be monitored by the ADC.

• Generate instantaneous faults based on user programmable over-voltage and under-voltage limits and ﬁ xed IDAC limits. The status of OR’d voltage limit faults and IDAC faults may be output over GPIO_0 and GPIO_1, respectively.

• Enable instantaneous faults to set associated latched faults using the FAULT_EN register. The status of OR’d latched faults may be signalled using ALERT.

• Conﬁ gure the GPIO_0 and GPIO_1 pins to act as inputs or outputs.

C Serial Digital Interface

2. I

The LTC2970 communicates with a host (master) using the 2-wire, I shows the timing relationship of the signals on the bus.

C serial bus interface. The Timing Diagram

The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines.

The LTC2970 I all SMBus setup times, hold times and timeout requirements.

The LTC2970 is a receive-only (slave) device. The LTC2970 can signal the host through the SMBALERT protocol that it wants to talk by asserting ALERT low. The LTC2970 supports the three I

Slave Address

The LTC2970 can respond to one of nine 7-bit addresses. The two slave address select pins (ASEL1 and ASEL0) are programmed by the user and determine the slave address, as shown in Table 2.

The LTC2970 also supports the ARA address and a global address that allows multiple LTC2970s to be programmed with the same data simultaneously, as shown in Table 3.

Table 1. Supported I2C Command Types

READ DATA WORD:

S:ADR:W:A:CMD:A:Sr:ADR:R:A:DATA:A:DATA:NACK:P

WRITE DATA WORD:

S:ADR:W:A:CMD:A:DATA:A:DATA:A:P

ALERT RESPONSE

S:ARA:R:A:ADR:NACK:P:

C interface is SMBus compatible; it meets

C protocols summarized in Table 1.

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OPERATIO

LTC2970/LTC2970-1

Table 2. LTC2970 Address Table

ADDRESS[7:0]

(R/W = 0)

8’hB8 7’h5C L L

8’hBA 7’h5D L F

8’hBC 7’h5E L H

8’hBE 7’h5F F L

8’hD6 7’h6B F F

8’hD8 7’h6C F H

8’hDA 7’h6D H L

8’hDC 7’h6E H F

8’hDE 7’h6F H H

ASELn

< V

IL_ASEL

L: V

ADDRESS[7:1] ASEL1 ASEL0

F: ASELn Floating H: V

ASELn

> V

IH_ASEL

Table 3. Special LTC2970 Addresses

ADDRESS[7:0]

(R/W = 0)

ARA 8’h18 7’h0C This is the standard Alert

Global 8’hB6 7’h5B This a global address to which

ADDRESS[7:1] FUNCTION

Response Address for all SMBus devices. This address is independent of the value of the ASEL1 and ASEL0 pins.

all LTC2970s will respond. This address is independent of the value of the ASEL1 and ASEL0 pins.

3. Register Command Set

COMMAND FUNCTION DESCRIPTION R/W DATA

FAULT() Instantaneous Fault Status For All Channels Read Only 16 Bits ‘h00

FAULT_EN() Enable For All Latched Faults and Servo On Fault Read/Write 16 Bits ‘h08

FAULT_LA_INDEX() Index to All Latched Faults Read Only 16 Bits ‘h10

FAULT_LA() Latched Fault Status For All Channels Read Only 16 Bits ‘h11

IO() IO Control and Status Register Read/Write 16 Bits ‘h17

ADC_MON() Control Register For Selecting ADC Channels to Monitor Read/Write 16 Bits ‘h18

*SYNC() Control Register For Synchronizing Tracking Across Multiple Devices Read/Write 16 Bits ‘h1F

VDD_ADC() V

VDD_OV() V

VDD_UV() V

V12_ADC() 12V

V12_OV() 12V

V12_UV() 12V

CH0_A_ADC() CH0_A ADC Conversion Result Register Read Only 16 Bits ‘h40

CH0_A_OV() CH0_A Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h41

CH0_A_UV() CH0_A Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h42

CH0_A_SERVO() CH0_A Voltage Servo Control Register Read/Write 16 Bits ‘h43

CH0_A_IDAC() CH0_A IDAC Control Register Read/Write 16 Bits ‘h44

*CH0_A_IDAC_TRACK() CH0_A IDAC Track Final Value Register Read/Write 16 Bits ‘h45

*CH0_A_DELAY_TRACK() CH0_A IDAC Track Delay Register Read/Write 16 Bits ‘h46

CH0_B_ADC() CH0_B ADC Conversion Result Register Read Only 16 Bits ‘h48

CH0_B_OV() CH0_B Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h49

CH0_B_UV() CH0_B Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h4A

CH1_A_ADC() CH1_A ADC Conversion Result Register Read Only 16 Bits ‘h50

CH1_A_OV() CH1_A Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h51

CH1_A_UV() CH1_A Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h52

ADC Conversion Result Register Read Only 16 Bits ‘h28

DDIN

Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h29

DDIN

Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h2A

DDIN

ADC Conversion Result Register Read Only 16 Bits ‘h38

Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h39

Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h3A

LENGTH

COMMAND

BYTE VALUE

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LTC2970/LTC2970-1

OPERATIO

3. Register Command Set (Cont.)

COMMAND FUNCTION DESCRIPTION R/W DATA

CH1_A_SERVO() CH1_A Voltage Servo Control Register Read/Write 16 Bits ‘h53

CH1_A_IDAC() CH1_A IDAC Control Register Read/Write 16 Bits ‘h54

*CH1_A_IDAC_TRACK() CH1_A IDAC Track Control Register Read/Write 16 Bits ‘h55

*CH1_A_DELAY_TRACK() CH1_A IDAC Track Delay Register Read/Write 16 Bits ‘h56

CH1_B_ADC() CH1_B ADC Conversion Result Register Read Only 16 Bits ‘h58

CH1_B_OV() CH1_B Over-Voltage Monitor Control Register Read/Write 16 Bits ‘h59

CH1_B_UV() CH1_B Under-Voltage Monitor Control Register Read/Write 16 Bits ‘h5A

TEMP_ADC() Temperature ADC Conversion Result Register Read/Write 16 Bits ‘h68

RESERVED() All other commands are reserved for future expansion and should not be

written or read.

*LTC2970-1 Only. LTC2970 will not acknowledge these commands.

Read/Write 16 Bits ‘hXX

LENGTH

COMMAND

BYTE VALUE

4. Detailed I2C Command Register Descriptions

FAULT: Instantaneous Fault Register – Read

BIT(s) SYMBOL OPERATION

b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13]

b[15:14] Reserved Always Returns 0

Fault_ch0_a_ov Fault_ch0_a_uv Fault_ch0_a_idac Fault_ch0_b_ov Fault_ch0_b_uv Fault_ch1_a_ov Fault_ch1_a_uv Fault_ch1_a_idac Fault_ch1_b_ov Fault_ch1_b_uv Fault_vdd_ov Fault_vdd_uv Fault_v12_ov Fault_v12_uv

0 = The associated channel is clear of instantaneous faults.

1 = The associated channel has an instantaneous fault.

The reported faults are instantaneous and not latched. When used in conjunction with latched faults they may indicate faults that are transient in nature.

FAULT_EN: Fault Enabling Register – Read/Write

BIT(s) SYMBOL OPERATION

b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13] b[14] Fault_en_ch0_a_servo 0 = Do not re-servo CH0_A in

b[15] Fault_en_ch1_a_servo 0 = Do not re-servo CH1_A in

Fault_en_ch0_a_ov Fault_en_ch0_a_uv Fault_en_ch0_a_idac Fault_en_ch0_b_ov Fault_en_ch0_b_uv Fault_en_ch1_a_ov Fault_en_ch1_a_uv Fault_en_ch1_a_idac Fault_en_ch1_b_ov Fault_en_ch1_b_uv Fault_en_vdd_ov Fault_en_vdd_uv Fault_en_v12_ov Fault_en_v12_uv

0 = The associated bit in the FAULT_LA register will always be 0. (default)

1 = Instantaneous faults reported in the FAULT register will set associated bit in the FAULT_LA register.

response to instantaneous OV or UV fault.

1 = Repeat a one time servo of CH0_A in response to instantaneous OV or UV fault. CH0_A must have servo operation enabled with Ch0_a_idac_ servo_repeat set low, and Adc_mon_ ch0_a set high.

response to instantaneous OV or UV fault.

1 = Repeat a one time servo of CH1_A in response to instantaneous OV or UV fault. CH1_A must have servo operation enabled with Idac_ch1_a_ servo_repeat set low, and Adc_mon_ ch1_a set high.

29701fc

OPERATIO

LTC2970/LTC2970-1

4. Detailed I2C Command Register Descriptions

(Cont.)

FAULT_INDEX: Latched Fault Index Register – Read

BIT(s) SYMBOL OPERATION

b[0] Fault_la_index 0 = All faults indicated by FAULT_LA

b[15:1] Reserved Always Returns 0

FAULT_LA: Latched Fault Register – Read

BIT(s) SYMBOL OPERATION

b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11] b[12] b[13]

b[15:14] Reserved Always Returns 0

Fault_la_ch0_a_ov Fault_la_ch0_a_uv Fault_la_ch0_a_idac Fault_la_ch0_b_ov Fault_la_ch0_b_uv Fault_la_ch1_a_ov Fault_la_ch1_a_uv Fault_la_ch1_a_idac Fault_la_ch1_b_ov Fault_la_ch1_b_uv Fault_la_vdd_ov Fault_la_vdd_uv Fault_la_v12_ov Fault_la_v12_uv

are clear. 1 = One or more faults indicated by

FAULT_LA are set. This register allows a summary of all

latched faults to be viewed in a single read without resetting latched faults.

0 = The associated channel is clear of faults.

1 = The associated channel has faulted and is enabled.

The latched faults are set and held when the associated channel's instantaneous fault has occured with faults enabled. Clearing the enable bit for the associated channel in FAULT_EN will immediately clear its corresponding latched fault bit.

All latched channel faults are cleared when this register is read. They may be set again if the instantaneous fault condition and fault_en have not changed.

IO: Input/Output Data and General Purpose Control Register – Read/Write unless speciﬁ ed otherwise.

BIT(s) SYMBOL OPERATION

b[1:0] Io_cfg_0[1:0] Io_cfg_0[1:0] is used to conﬁ gure the function of

b[3:2] Io_cfg_1[1:0] Io_cfg_1[1:0] is used to conﬁ gure the function

b[4] Io_gpio_0 See Io_cfg_0.

b[5] Io_gpio_1 See Io_cfg_1.

b[6] Io_alertb Mirrors the value of the ALERT pin.

b[7] Io_alertb_enb 1 = ALERT pin never asserts (default).

b[8] Io_i2c_adc_

wen

b[9] Io_gpio_cfg Read only. GPIO_CFG digital input and open-

b[10] Io_track_start Writing a 1 to this bit will start tracking all

b[15:11] Reserved Always Returns 0

the GPIO_0 pin and IO(Io_gpio_0). 00: Io_gpio_0 = GPIO_0 = Power_good. Power_

good asserts high if there are no instantaneous over-voltage or under-voltage faults.

01: Io_gpio_0 = GPIO_0 = Power_good_bar. Power_good_bar is the complement of Power_good.

10: GPIO_0 is a general-purpose open-drain output and mirrors the value written to Io_gpio_0 (default).

11: GPIO_0 is a general-purpose digital input with Io_gpio_0 = GPIO_0

of the GPIO_1 pin and IO(Io_gpio_1). 00: Io_gpio_1 = GPIO_1 = Idac_fault.

Idac_fault asserts if either IDAC value is faulted (Chn_idac[7:0] = 8’h00 or 8’hff)

01: Io_gpio_1 = GPIO_1 = Idac_fault_bar. Idac_fault_bar is the complement of Idac_fault.

10 = GPIO_1 is a general-purpose opendrain output and mirrors the value written to Io_gpio_1 (default).

11 = GPIO_1 is a general-purpose digital input with Io_gpio_1 = GPIO_1

If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_0 is cleared and the GPIO_0 open-drain output will assert low.

If the GPIO_CFG pin is pulled-high during a power on reset, Io_gpio_1 is cleared and the GPIO_1 open-drain output will assert low.

Read only.

0 = ALERT pin asserts low when one or more FAULT_LA bits are set.

1 = Special test mode that inhibits ADC from writing to ADC result register and allows user to update registers over the I

0 = Normal operation (default).

drain output. Reading this bit returns the current state of the GPIO_CFG pin voltage.

enabled channels. Returns a 1 when tracking is pending (LTC2970-1). Reserved on LTC2970 and always returns 0.

C serial interface.

29701fc

LTC2970/LTC2970-1

OPERATIO

4. Detailed I2C Command Register Descriptions

(Cont.)

ADC_MON: ADC Monitoring Mux Control Register – Read/Write

BIT(s) SYMBOL OPERATION

b[0] b[1] b[2] b[3] b[4] b[5] b[6]

b[15:7] Reserved Always Returns 0

SYNC: Tracking Synchronization Control Register – Read/Write LTC2970-1 Only

BIT(s) SYMBOL OPERATION

b[0] Sync_track Write

b[15:1] Reserved Always Returns 0

Adc_mon_vdd Adc_mon_v12 Adc_mon_ch0_a Adc_mon_ch0_b Adc_mon_ch1_a Adc_mon_ch1_b Adc_mon_temp

0 = ADC will not convert associated channel. (Default)

1 = ADC will continuously convert associated channel.

0 = Do not synchronize. 1 = Synchronize all tracking enabled

registers to the same starting point. Read

0 = The LTC2970-1 is not synchronized for tracking (default).

1 = The LTC2970-1 is synchronized for tracking.

Use of the global address will allow the synchronization status of multiple LTC2970-1s to be veriﬁ ed in a single read; since a one can only be returned if all LTC2970-1s are synchronized. The IO_track_start command may then be issued with the same global address to begin synchronized tracking across multiple ICs.

VDD_ADC, V12_ADC, CH0_A_ADC, CH0_B_ADC, CH1_A_ADC, CH1_B_ADC, and TEMP_ADC: ADC Conversion Result Registers – Read Only Unless Speciﬁ ed Otherwise

BIT(s) SYMBOL OPERATION

b[14:0] Vdd_adc[14:0]

V12_adc[14:0] Ch0_a_adc[14:0] Ch0_b_adc[14:0] Ch1_a_adc[14:0] Ch1_b_adc[14:0] Temp_adc[14:0]

b[15] Vdd_adc_new

V12_adc_new Ch0_a_adc_new Ch0_b_adc_new Ch1_a_adc_new Ch1_b_adc_new Temp_adc_new

Measured data from ADC conversion. 'h4000 corresponds to negative full-

scale input voltage. 'h0000 corresponds to 0V. 'h3fff corresponds to full-scale input voltage.

2’s complement format, b[14] = sign. Read/Write when Io_i2c_adc_wen = 1. Default value is undeﬁ ned.

1 = The ADC has updated the associated result register since the last time the data was read.

0 = Previously read data. (Default)

VDD_OV, V12_OV, CH0_A_OV, CH0_B_OV, CH1_A_OV, CH1_B_ OV: Over Voltage Limit Registers – Read/Write

BIT(s) SYMBOL OPERATION

b[14:0] Vdd_ov[14:0]

V12_ov[14:0] Ch0_a_ov[14:0] Ch0_b_ov[14:0] Ch1_a_ov[14:0] Ch1_b_ov[14:0]

b[15] Reserved Always Returns 0

ADC over-voltage threshold limit. The associated instantaneous over

voltage fault is asserted if the channel’s ADC result is greater than this limit. Code 'h3fff disables OV threshold detect feature for that channel.

2’s complement format, b[14] = sign. Default value is undeﬁ ned.

VDD_UV, V12_UV, CH0_A_UV, CH0_B_UV, CH1_A_UV, CH1_B_ UV: Under Voltage Limit Registers – Read/Write

BIT(s) SYMBOL OPERATION

b[14:0] Vdd_uv[14:0]

V12_uv[14:0] Ch0_a_uv[14:0] Ch0_b_uv[14:0] Ch1_a_uv[14:0] Ch1_b_uv[14:0]

b[15] Reserved Always Returns 0

ADC under-voltage threshold limit. The associated instantaneous under

voltage fault is asserted if the channel’s ADC result is greater than this limit. Code 'h4000 disables UV threshold detect feature for that channel.

2’s complement format, b[14] = sign. Default value is undeﬁ ned.

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OPERATIO

LTC2970/LTC2970-1

4. Detailed I2C Command Register Descriptions (Cont.)

CH0_A_SERVO, CH1_A_SERVO: Voltage Servo Control Registers – Read/Write

BIT(s) SYMBOL OPERATION

b[14:0] Ch0_a_servo[14:0]

Ch1_a_servo[14:0]

b[15] Ch0_a_servo_en

Ch1_a_servo_en

CH0_A_IDAC, CH1_A_IDAC: IDAC Control/Data Registers – Read/Write

BIT(s) SYMBOL OPERATION

b[7:0] Ch0_a_idac[7:0]

Ch1_a_idac[7:0]

b[8] Ch0_a_idac_en

Ch1_a_idac_en

b[9] Ch0_a_idac_con

Ch1_a_idac_con

During servo operation Chn_a_idac[7:0] output current is

stepped to force Chn_a_adc[14:0] code to equal target code stored in Chn_a_servo[14:0].

2’s complement format, b[14] = sign Default value is undeﬁ ned.

0 = Chn_a servo disabled (default). 1 = Chn_a servo enabled.

Chn_a IDAC data value.

0 = V 1 = V There are two ways to enable

1) When Chn_a_idac_en is set high with Chn_a_idac_con low, the LTC2970 will perform a soft connect. During a soft connect, the V will not be connected to the V pin until the internal algorithm has servo’d the voltage at the IDACn pin to match the V pin voltage. Resolution is one Chn_a_idac LSB.

2) When Chn_a_idac_en is enabled with Chn_a_idac_con high, the LTC2970 will perform a hard connect. The V voltage buffer will be immediately connected to the V

0 = V has been enabled but is not yet connected to the output of the CHn voltage buffer. (Default)

1 = V connected to the output of the CHn voltage buffer.

See Chn_a_idac_en for additional information.

output tri-stated.

OUTn

output enabled.

OUTn

voltage buffer output

OUTn

is not enabled or

OUTn

is enabled and has been

OUTn

pin.

OUTn

b[10] Ch0_a_idac_pol

Ch1_a_idac_pol

b[11] Ch0_a_idac_servo_repeat

Ch1_a_idac_servo_repeat

b[15:12] Reserved Always Returns 0

0 = Use this setting when increasing V (VINn_AP-VINn_AM) to decrease. Inverting conﬁ guration common to DC/DC converters with external feedback networks.

1 = Use this setting when increasing V (VINn_AP-VINn_AM) to increase. Non-inverting conﬁ guration common to DC/DC converters with trim pins.

0 = During servo operation, servo Chn_a until the measured result is stable and matches the target code.

1 = During servo operation, continuously servo Chn_a to the target code.

OUTn

causes

CH0_A_IDAC_TRACK and CH1_A_IDAC_TRACK: IDAC Tracking data and control registers – Read/Write LTC2970-1 Only

BIT(s) SYMBOL OPERATION

b[7:0] Ch0_a_idac_

b[8] Ch0_a_idac_track_en

b[15:9] Reserved Always Returns 0

track[7:0] Ch1_a_idac_

track[7:0]

Ch1_a_idac_track_en

Final target value for of Chn_a_ idac[7:0]. During tracking, Chn_a_ idac[7:0] is incremented/decremented by 1 until it is equal to this value.

0 = inhibit tracking of Chn_a_idac[7:0]. 1 = enable tracking of Chn_a_idac[7:0]

CH0_A_DELAY_TRACK and CH1_A_DELAY_TRACK: IDAC Tracking delay register – Read/Write LTC2970-1 Only

BIT(s) SYMBOL OPERATION

b[9:0] Ch0_a_delay_track[9:0]

Ch1_a_delay_track[9:0]

b[1510] Reserved Always Returns 0

Delay used to synchronize or offset tracking events.

29701fc

LTC2970/LTC2970-1

OPERATIO

5. Soft Connecting the LTC2970 to the Power Supply Feedback Node

The soft connect feature allows the LTC2970 to connect to the power supply’s feedback node with minimal disturbance to the supply’s output voltage. This is accomplished by comparing the buffered voltage of I

and incrementing or decrementing Chn_a_idac[7:0]

OUT

until the comparator output (COMPn) changes. The value of Chn_a_idac[7:0] when the comparator transitions is the appropriate value for a soft connect. The voltage buffer output is only connected to V soft connect value without generating an instantaneous IDAC fault (Fault_chn_a_idac).

Soft-Connect Procedure:

Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing V differential voltage (VINn_AP – VINn_AM) to increase. When properly programmed, lowering the value in Chn_ a_idac[7:0] will always cause the output of the controlled power supply to decrease.

Ensure that the channel’s IDAC is not currently enabled for connection, i.e., the Chn_a_idac_en bit must be 0.

Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 0, Chn_a_idac_en = 1, and Chn_a_idac[7:0] = 0x80. The value programmed into Chn_a_idac[7:0] is ignored and Chn_a_idac[7:0] is initially set to 8’h80.

The LTC2970 will now ramp Chn_a_idac[7:0] while monitoring the output of the soft connect comparator. If the soft connect comparator trips, the LTC2970 will connect the output of V If the soft connect comparator does not trip before the IDAC value reaches ‘h00 or ‘hFF, then the soft connection will fail, an IDAC fault will be indicated (Fault_chn_a_idac), and Chn_a_idac_con will remain low.

Soft-Connect Rules:

When both channels are requesting a soft connect, channel 0 has priority.

Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect

BUFn

to V

and set Chn_a_idac_con high.

OUTn

if the IDAC reaches this

OUTn

to the voltage at

OUTn

causes

on that channel or the previously issued soft connect failed with an IDAC fault (Fault_chn_a_idac = 1). Recall that the Chn_a_idac_en bit must initially have been set to 0.

LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change Chn_a_idac_pol or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high.

LTC2970-1 Only: Soft connect requests will be ignored and the user will not be able to change the Chn_a_idac_pol bit if there is a pending tracking operation.

6. Hard Connecting the LTC2970 to the Power Supply Trim Pin

The hard connect feature allows the LTC2970 to bypass the soft connect algorithm and connect directly to the power supply’s feedback node using the value programmed into Chn_a_idac[7:0]. This feature is useful for systems that have calculated or measured an acceptable voltage at which to connect the IDAC’s buffered voltage V

Hard Connect Procedure:

Determine the appropriate polarity for Chn_a_idac_pol. Select Chn_a_idac_pol = 1 if incrementing V (VINn_AP – VINn_AP) to increase. When properly programmed, lowering the value in the IDAC will always cause the output of the controlled power supply to decrease.

Determine the value for Chn_a_idac[7:0]. The values ‘h00 or ‘hff are allowed, but they will trip the IDAC’s fault bit (Fault_chn_a_idac = 1).

When the IDAC is already connected, the value Chn_a_ idac[7:0] and Chn_a_idac_pol will be programmed into the IDAC provided all other conditions are met. See “Programming a Previously Connected Current DAC” for details

Update CHn_A_IDAC() with Chn_a_idac_pol, Chn_a_idac_ con = 1, Chn_a_idac_en = 1, and Chn_a_idac[7:0].

Hard Connect Rules:

Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if the LTC2970 is servicing a previously issued soft connect on that channel or the previously issued

BUFn

to V

OUTn

causes

29701fc

OPERATIO

LTC2970/LTC2970-1

soft connect failed with an IDAC fault (Fault_chn_a_idac =

1). Recall that a new hard connection requires the previous value of Chn_a_idac_en = 0.

LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_idac_con or Chn_a_idac[7:0] if GPIO_CFG is high and either GPIO_0 or GPIO_1 are high.

LTC2970-1 Only: Hard connect requests will be ignored and the user will not be able to change Chn_a_idac_pol, Chn_a_ idac_con or Chn_a_idac[7:0] if there is a pending tracking operation.

7. Programming a Previously Connected IDAC

The LTC2970 IDAC’s may be programmed after they have been connected with a soft connect or a hard connect provided a servo operation is not enabled on the associated channel.

Procedure:

Determine the value for Chn_a_idac[7:0]. The values ‘h00 or ‘hff are allowed, but will trip the IDAC’s fault bit (Fault_chn_a_idac = 1).

8. Disconnecting the LTC2970 from the Power Supply Trim Pin

can be placed in a high impedance state simply by

OUTn

clearing the Chn_a_idac_en bit. In order to minimize the resulting disturbance to the power supply voltage, the IDAC code should not be changed from its current value when clearing the Chn_a_idac_en bit. This is not an issue if the channel’s associated servo_en bit is high.

Disconnect Procedure:

Update CHn_IDAC() with Chn_a_idac_en set low.

The LTC2970 will immediately disconnect the buffered

from V

OUTn

Disconnect Rules:

Clearing Chn_a_idac_con with Chn_a_idac_en high will not disconnect the IDAC. Only setting Chn_a_idac_en low will clear Chn_a_idac_con.

LTC2970-1 Only: Chn_a_idac_en may not be changed if the feedback node connection is conﬁ gured for tracking. Tracking is enabled when GPIO_CFG is high and either GPIO_0 or GPIO_1 are high.

OUTn

Verify that the IDAC is already connected, and that Chn_a_idac_con is high.

Ensure that servo mode is not enabled for the channel being programmed. Chn_a_servo_en must be low. This requirement prevents the user from interfering with a previously requested servo operation.

Update the CHn_A_IDAC() register with Chn_a_idac_pol, Chn_a_idac_con = 1, Chn_a_idac_en = 1, and Chn_a_ idac[7:0].

Note: Care should be taken to preserve the current value of the Chn_a_idac_pol bit, since the LTC2970 does not prevent the user from changing this value when writing to the IDAC control registers.

Rules:

Setting Chn_a_idac_con to zero will not disconnect the DAC unless Chn_a_idac_en is also set low.

All Hard Connect rules apply.

9. Tracking Power Supplies Overview (LTC2970-1 Only)

The LTC2970-1 tracking feature allows the I to initiate a controlled power up or power down of two or more supplies (Figure 2 shows a typical LTC2970-1 application circuit). Multiple LTC2970-1’s with different addresses may be simultaneously programmed using the LTC2970 group address and the SYNC() command. Tracking is enabled when GPIO_CFG is pulled high and either GPIO_0 or GPIO_1 are high.

10. Tracking Power Supplies On (LTC2970-1 Only)

The LTC2970-1 tracking feature allows the I a controlled power up of two or more supplies.

Procedure: This procedure describes all the steps necessary to track up two or more power supplies. Steps that require I command function.

Power-up the LTC2970-1 with GPIO_CFG pulled high.

C interaction are preﬁ xed with the required I2C

C interface

C to initiate

29701fc

LTC2970/LTC2970-1

OPERATIO

This causes open-drain outputs GPIO_1 and GPIO_0 to automatically pull the power supplies’ run/soft-start pins to ground.

CHn_A_IDAC(): Hard connect Chn_a_idac[7:0] with a value that forces the power supplies off when GPIO_CFG = 1. Verify that Chn_a_idac_pol is at the appropriate value.

CHn_A_IDAC_TRACK(): Set Chn_a_idac_track_en = 1, and set the Chn_a_idac_track[7:0] target value to the code that causes V corresponding power supply’s feedback node voltage when it is in regulation.

CHn_A_DELAY_TRACK(): Set the value by which the incrementing of IDACn should be delayed with respect to the start of tracking event. This controls whether the power supplies track up coincidentally or sequentially.

IO(): Release the run/soft-start pins by programming io_gpio_n = 1. This will enable the power supplies without allowing their outputs to move since these are held low by Chn_a_idac[7:0]. Wait until power supplies have had sufﬁ cient time to start running before starting tracking.

SYNC(): Optional command that allows multiple LTC29701’s to be synchronized for tracking. Writing Sync_track = 1 will allow the LTC2970-1 to ﬁ nish its current ADC conversion before having it wait to receive io_track_start = 1. The LTC2970-1 will timeout this wait command after t

TIMEOUT_SYNC

global address will ensure all LTC2970-1’s are synchronized before proceeding with the tracking operation.

IO(): Set Io_track_start = 1 and keep the run/soft-start pins enabled. Use the global I up power supplies across multiple LTC2970-1’s.

LTC2970-1 response: For each tracking enabled channel, the LTC2970-1 will decrement the CHn_A_delay_track counter at a rate of t tracking counter reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the ﬁ nal value of Chn_a_idac_track[7:0] is reached, at which point Chn_a_idac_track_en is de-asserted. When the ﬁ nal value is reached for all channels, GPIO_CFG is asserted low. After a time delay of t de-asserted.

. Reading back Sync_track = 1 using the

to most closely approximate the

OUTn

C address to simultaneously track

DEC_TRACK

. As soon as a channel’s

HOLD_TRACK

, Chn_a_idac_en is

Power-Up Tracking Rules:

Tracking cannot begin if Chn_a_idac_con is not connected. This condition is met when the previous procedure is followed.

Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(Io_track_start) is asserted until tracking is complete or whenever tracking is pending, i.e., GPIO_CFG pulled high with either GPIO_0 or GPIO_1 asserted pulled high.

11. Tracking Power Supplies Off (LTC2970-1 Only)

The LTC2970-1 tracking feature allows the I a controlled power down of two or more supplies.

Procedure: This procedure describes all steps necessary to track down two or more power supplies. Steps that require I command function.

CHn_IDAC(): Disable the IDAC’s for each tracking enabled channel (Chn_a_idac_en = 0). Ensure Chn_a_idac_pol is at the appropriate value.

CHn_IDAC_TRACK(): Select the channels to be tracked by setting Chn_a_idac_track_en = 1, and set the target value for each Chn_a_idac_track[7:0] to that which forces the supply off.

CHn_A_DELAY_TRACK(): Set the value by which the decrementing of that channel’s DAC should be delayed with respect to the start of the tracking event. This controls whether the supplies track down coincidentally or sequentially.

TIMEOUT_SYNC

global address will ensure all LTC2970’s are synchronized before proceeding with the tracking operation.

IO(): Set Io_track_start = 1. Use the global I to simultaneously track down power supplies across multiple LTC2970’s.

C interaction are preﬁ xed with the required I2C

. Reading back Sync_track = 1 using the

C to initiate

C address

29701fc

OPERATIO

LTC2970/LTC2970-1

LTC2970-1 response: Each tracking enabled channel is soft connected. The GPIO_CFG pin is released allowing it to be pulled high. The LTC2970-1 waits t GPIO_CFG to settle. For each tracking enabled channel, the Chn_a_delay_track counter is decremented at a rate of t

DEC_TRACK

reaches zero, the LTC2970-1 will begin stepping the value of Chn_a_idac[7:0] by one count until the ﬁ nal value of Chn_a_idac_track[7:0] is reached. The tracking enable bit is then cleared for both channels (Chn_a_idac_track_en = 0).

IO(): The I and GPIO_0 low, disabling the power supplies.

Power Down Tracking Rules:

Power down tracking requests will be ignored until the user has disabled the IDAC’s by setting Chn_a_idac_en = 0 for each tracking enabled channel.

Chn_a_idac_track_pol, Chn_a_idac_track_en, and ch0_ idac[7:0] updates will be ignored after IO(IO_track_start) is asserted until tracking is complete and whenever tracking range is conﬁ gured; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high).

12. Continuous Power Supply Voltage Servo

The continuous voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value. The voltage of the external supply is monitored over Chn_A_ADC and compared to a target value stored in Chn_a_servo. After each conversion, Chn_A_IDAC is incremented by 1, decremented by 1, or held; whichever brings or keeps the measured voltage closer to the targeted servo value.

. As soon as a channel’s tracking counter

C interface may then be used to set GPIO_1

SETUP_TRACK

to allow

Determine the target servo voltage, Chn_a_servo[14:0].

Update CHn_A_SERVO() with Chn_a_servo_en = 1, and Chn_a_servo[14:0].

Update CHn_A_IDAC() with Chn_a_idac_servo_repeat =

1. This step may be skipped if Chn_a_idac_servo_repeat

was set high during the soft or hard connect procedure.

LTC2970 response: The LTC2970 will continuously increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0].

Whenever the CHn_A_SERVO() register is updated an internal ﬂ ag is cleared indicating that a successful servo has not been completed. This internal ﬂ ag, Chn_a_servo_done, initially causes the ADC to operate in an accelerated 12-bit mode. Once the channel reaches the servo target, the ADC switches back to 14-bit mode for two conversions before asserting Chn_a_servo_done high.

In continuous voltage servo mode the Chn_a_servo_done ﬂ ags allow the initial servo target to be reached quickly. During this time, ADC conversions for all non-servo channels are temporarily inhibited.

Rules:

The IDAC associated with the servo channel must be enabled. If Chn_a_idac_en is low the servo enable bit Chn_a_servo_en is always forced low.

The IDAC associated with the servo channel must be connected (Chn_a_idac_con = 1).

An IDAC fault may be generated during a continuous servo operation. The LTC2970 will report the fault and continue trying to servo that channel.

Procedure:

Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be asserted high. The servo channel’s IDAC must be enabled before Chn_A_servo_en can be set high.

LTC2970-1 Only: There must be no pending tracking commands. A pending tracking command will clear Chn_a_servo_en.

LTC2970-1 Only: The tracking range must not be enabled; (GPIO_CFG high with either GPIO_0 or GPIO_1 asserted high). An enabled tracking range will clear Chn low.

_a_servo_en

29701fc

LTC2970/LTC2970-1

OPERATIO

13. One Time Power Supply Voltage Servo

The one time voltage servo feature allows the LTC2970 to servo an external power supply to a programmed value and then stop updating the IDAC once the target value has been reached.

Procedure:

Follow procedure for hard connecting or soft connecting the LTC2970 to power supply trim pin; when updating CHn_A_IDAC(), Chn_a_idac_servo_repeat should be deasserted low. The servo channel’s IDAC must be enabled before Chn_a_servo_en may be set high.

Update CHn_A_IDAC() with Chn_a_idac_servo_repeat = 0. This step may be skipped if Chn_a_idac_servo_repeat was cleared low during the soft or hard connect procedure.

Update FAULT_EN() with Fault_en_chn_a_servo = 0. This prevents the LTC2970 from reinitiating a servo after an over-voltage or under-voltage fault.

Determine the target servo voltage, Chn_a_servo[14:0].

Procedure:

Follow procedure outlined for “One Time Power Supply Voltage Servo”.

Update FAULT_EN() with Fault_en_chn_a_servo = 1.

Enable detection of the appropriate instantaneous faults for all servo channels; see “Generating and Monitoring Instantaneous Faults”.

LTC2970 response: Any time an instantaneous undervoltage or over-voltage fault is detected on the servo channel (Fault_ov_a_chn or Fault_uv_a_chn), the internal Chn_a_servo_done ﬂ ag for that channel is cleared, and the LTC2970 will perform a complete one time servo. This allows the LTC2970 to precisely restore the power supply to the target servo value, after it has drifted beyond a user deﬁ ned operating window.

Rules:

All “Continuous Power Supply Voltage Servo” rules apply.

Update CHn_A_SERVO() register with Chn_a_servo_en = 1, and Chn_a_servo[14:0].

LTC2970 response: The LTC2970 will increment, decrement or hold Chn_a_idac[7:0] in order to match the measured value of (VINn_AP-VINn_AM) to Chn_a_servo[14:0]. The servo procedure will end when the internal Chn_a_servo_ done ﬂ ag is set (see “Continuous Power Supply Voltage Servo”). At this point the IDAC is either programmed to the appropriate servo value or faulted.

Rules:

All “Continuous Power Supply Voltage Servo” rules apply.

14. One Time Power Supply Voltage Servo with Repeat On Fault

The LTC2970 one time voltage servo feature may be modiﬁ ed to allow the LTC2970 to perform an additional power supply servo operation after an under-voltage or over-voltage fault is detected on the servo channel.

During a permanent under-voltage or over-voltage fault the LTC2970 will continuously try to correct the faulted channel, after each failed attempt all other channels that need monitoring by the ADC will be serviced.

15. Conﬁ guring ADC to Monitor Input Channels and Internal Temperature Sensor

The LTC2970 is able to perform ADC conversions on any combination of seven different input channels. A channel is converted if its associated ADC_MON() bit is set high. Refer to Table 7 for details.

Procedure:

Update ADC_MON() with the control bit of each channel that is to be monitored set high.

LTC2970 response: All enabled channels will be sequentially converted. The result of the most recent conversion may be read from the ADC result register. Each time a conversion is completed the new data bit associated with the result register is asserted high. The new data bit is

29701fc

LTC2970/LTC2970-1

OPERATIO

Table 7. LTC2970 ADC Conversion and Fault Limit Registers

INPUT CHANNEL ADC_MON()

CONTROL BIT

TEMPERATURE Adc_mon_temp Temp_adc[14:0] - -

VIN1_BP-VIN1_BM Adc_mon_b_ch1 Ch1_b_adc[14:0] Ch1_b_ov[14:0] Ch1_b_uv[14:0]

VIN1_AP-VIN1_AM Adc_mon_a_ch1 Ch1_a_adc[14:0] Ch1_a_ov[14:0] Ch1_a_uv[14:0]

VIN0_BP-VIN0_BM Adc_mon_b_ch0 Ch0_b_adc[14:0] Ch0_b_ov[14:0] Ch0_b_uv[14:0]

VIN0_AP-VIN0_AM Adc_mon_a_ch0 Ch0_a_adc[14:0] Ch0_a_ov[14:0] Ch0_a_uv[14:0]

12VIN Adc_mon_v12 V12_adc[14:0] V12_ov[14:0] V12_uv[14:0]

VDD Adc_mon_vdd Vdd_adc[14:0] Vdd_ov[14:0] Vdd_uv[14:0]

ADC RESULT REGISTER

(2s COMPLEMENT)

OV FAULT REGISTER

(2s COMPLEMENT)

UV FAULT REGISTER

(2s COMPLEMENT)

reset each time the result register is read. This provides a simple mechanism for supervisory software to determine if a new conversion has been completed since data was last read.

Rules:

The LTC2970 assigns priority to ADC conversions of CH1_A_ADC and CH0_A_ADC when these channels are in their initial fast servo mode.

16. Generating and Monitoring Instantaneous Faults

The LTC2970 supports fourteen different types of instantaneous faults. These faults together with the conditions that trigger them are deﬁ ned in Table 8. There are six under-voltage faults, six over-voltage faults and two IDAC limit faults. The FAULT() command may be used to read the status of all instantaneous fault bits. The IO() command may be used to conﬁ gure GPIO_0 and GPIO_1 to view voltage limit and IDAC faults respectively. The state

The IO() register control bit Io_i2c_adc_wen must be low

of GPIO_0 and GPIO_1 may be read using IO().

in order for ADC conversions to be performed.

LTC2970-1 Only: ADC conversions are suspended during any pending tracking requests.

Table 8. LTC2970 Fault Reporting Bits and Conditions

CONDITION THAT GENERATES AN INSTANTANEOUS FAULT

V12_adc[14:0] < V12_uv[14:0] Fault_v12_uv Fault_en_v12_uv Fault_la_v12_uv

V12_adc[14:0] > V12_ov[14:0] Fault_v12_ov Fault_en_v12_ov Fault_la_v12_ov

Vdd_adc[14:0] < Vdd_uv[14:0] Fault_vdd_uv Fault_en_vdd_uv Fault_la_vdd_uv

Vdd_adc[14:0] > Vdd_ov[14:0] Fault_vdd_ov Fault_en_vdd_ov Fault_la_vdd_ov

Ch1_b_adc[14:0] < Ch1_b_uv[14:0] Fault_ch1_b_uv Fault_en_ch1_b_uv Fault_la_ch1_b_uv

Ch1_b_adc[14:0] > Ch1_b_ov[14:0] Fault_ch1_b_ov Fault_en_ch1_b_ov Fault_la_ch1_b_ov

Idac_a_ch1[7:0] = 8’ff or 8’h00 Fault_ch1_a_idac Fault_en_ch1_a_idac Fault_la_ch1_a_idac

Ch1_a_adc[14:0] < Ch1_a_uv[14:0] Fault_ch1_a_uv Fault_en_ch1_a_uv Fault_la_ch1_a_uv

Ch1_a_adc[14:0] > Ch1_a_ov[14:0] Fault_ch1_a_ov Fault_en_ch1_a_ov Fault_la_ch1_a_ov

Ch0_b_adc[14:0] < Ch0_b_uv[14:0] Fault_ch0_b_uv Fault_en_ch0_b_uv Fault_la_ch0_b_uv

Ch0_b_adc[14:0] > Ch0_b_ov[14:0] Fault_ch0_b_ov Fault_en_ch0_b_ov Fault_la_ch0_b_ov

Idac_a_ch0[7:0] = 8’ff or 8’h00 Fault_ch0_a_idac Fault_en_ch0_a_idac Fault_la_ch0_a_idac

Ch0_a_adc[14:0] < Ch0_a_uv[14:0] Fault_ch0_a_uv Fault_en_ch0_a_uv Fault_la_ch0_a_uv

Ch0_a_adc[14:0] > Ch0_a_ov[14:0] Fault_ch0_a_ov Fault_en_ch0_a_ov Fault_la_ch0_a_ov

INSTANTANEOUS FAULT REPORTING

FAULT()

ENABLE FOR LATCHED FAULT REPORTING

FAULT_EN()

FAULT_LA()

LATCHED FAULT REPORTING

29701fc

LTC2970/LTC2970-1

OPERATIO

Procedure:

Update the over-voltage limit register with the value above which the ADC result should generate an over-voltage fault. Instantaneous over-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is greater than the over-voltage limit. They are cleared if the ADC result is less than or equal to the over-voltage limit. Setting the over-voltage limit to 14’h3fff inhibits instantaneous faults for the associated channel.

Update the under-voltage limit register with the value below which the ADC result should generate an under-voltage fault. Instantaneous under-voltage faults are updated after each ADC conversion. They are asserted high when the ADC result is less than the under-voltage limit. They are cleared if the ADC result is greater than or equal to the under-voltage limit. Setting the over-voltage limit to 14’h4000 inhibits instantaneous faults for the associated channel.

Update ADC_MON() control bits to allow ADC conversions on all channels that are to be monitored for over and under voltage limits. Instantaneous IDAC faults are polled after all ADC conversions are completed and set when the associated IDAC registers are at ‘h00 of ‘hff.

Read FAULT() to view the value of all instantaneous faults.

Instantaneous Ch0_a and Ch1_a faults may be used to trigger a servo on fault event.

Over-voltage and under-voltage faults require that the associated ADC_MON control bit be asserted high for instantaneous fault detection to be updated.

17. Generating and Monitoring Latched Faults

The LTC2970 is able to selectively latch instantaneous faults in the latched fault register FAULT_LA. Each instantaneous fault has an associated latched fault bit in FAULT_LA and a fault enable bit in FAULT_EN; (see Table 8) for details. When an instantaneous fault enable bit is high, any event that sets the instantaneous fault will simultaneously set the latched fault. The latched fault will remain set even if conditions permit the instantaneous fault to be cleared. The latched faults are immediately cleared whenever the associated fault enable bit is cleared. All latched faults are also cleared when the latched fault register is read over FAULT_LA().

The FAULT_INDEX() command may be read to determine if any latched faults are asserted. Reading FAULT_INDEX() does not clear latched faults. The ALERT output may also be conﬁ gured to view whether any latched faults are asserted.

Procedure:

The IO(Io_cfg_0) command may be used to conﬁ gure the GPIO_0 pin to output the internal Power_good ﬂ ag. Power_good is asserted high if there are no instantaneous over-voltage or under-voltage faults. IO() may be used to read the value of Power_good through io_gpio_0.

The IO(Io_cfg_1) command may be used to conﬁ gure the GPIO_1 pin to output the internal Idac_fault ﬂ ag. Idac_fault is asserted high if either IDAC value is faulted. IO() may be used to read the value of Idac_fault through io_gpio_1.

Rules:

The over-voltage and under-voltage limits must be initialized; they do not have a default value.

All over-voltage limits, under-voltage limits and ADC results use 2’s complement notation with bit position [14] of register [14:0] being used for the sign.

Follow procedure for generating instantaneous faults.

Write FAULT_EN() to enable any combination of latched faults.

Read FAULT_INDEX() to determine if any latched faults are asserted without clearing latched faults.

Read FAULT_LA() to monitor all latched faults. Reading FAULT_LA() will clear all latched faults. These will remain clear until the next time the LTC2970 polls and sets an associated instantaneous fault.

Setting IO(Io_alert_enb) low will cause ALERT to be asserted low whenever any one of the fourteen latched faults is asserted high. The value of the ALERT pin may also be read through IO(Alertb).

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OPERATIO

LTC2970/LTC2970-1

Rules:

See “Generating and Monitoring Instantaneous Faults”.

18. General Purpose Input/Output Pins

The GPIO_0 and GPIO_1 may be used to: (1) monitor instantaneous faults (see “Generating and Monitoring Instantaneous faults”); (2) control switcher run/start pins during tracking (see “Tracking Power Supplies Overview”); or (3) provide general purpose input/output pins.

Procedure:

To program GPIO_n as an open drain output set Io_cfg_n = 2’b10. The value written to lo_gpio_n will be output over GPIO_n.

To program GPIO_n as an input set Io_cfg_n = 2’b11. The value of GPIO_n may now be read through lo_gpio_n.

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APPLICATIO S I FOR ATIO

Rules:

The power on reset conﬁ gurations for GPIO_0 and GPIO_1 are output pins with a value equal to the complement of the GPIO_CFG level.

19. Advanced Development Features

The internal ADC may be disabled with the ADC result

registers accepting written I

C data. This feature allows faults to be generated for diagnostic purposes, without having to generate an actual overvoltage or undervoltage event.

Procedure:

Set IO(Io_i2c_adc_wen) high to enable ADC result register writes and disable internal ADC updates.

Rules:

Io_i2c_adc_wen must be clear for normal operation.

Margining DC/DC Converters with External Feedback Resistors

Figure 1 shows a typical application circuit for margining a power supply with an external feedback network. The

IN0_AP

and V

V age directly, and differential inputs V

differential inputs sense the load volt-

IN0_AM

and V

IN0_BP

IN0_BM

are connected across load current sense resistor R50. A correction voltage is developed at the I

pin by sourcing

OUT0

IDAC0’s current into resistor R40. R40 is Kelvin connected to the point-of-load GND in order to isolate V ground bounce due to load current changes. V replicated at V

is then connected to the feedback node of the power

OUT0

by an on-chip, unity-gain voltage buffer.

OUT0

IOUT0

from

supply through resistor R30. The feedback node can be isolated from the DAC’s correction voltage by placing the

pin in high-impedance mode. Since the GPIO_CFG

OUT0

pin is pulled-up to V

, the LTC2970’s GPIO_0 pin will

automatically hold the power supply’s RUN/SS pin low

after power-up until the I

C interface releases it.

8V TO 15V

OUT0

IN0_BM

IN0_BP

OUT0

IN0_AP

IN0_AM

GND

1/2 LTC2970

GPIO_CFG

ASEL0

DC/DC

CONVERTER

RUN/SS

SGND

GND

OUT

R50

–

R30

R20

LOAD

DC0

–

R40R10

Figure 1. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors

ALERT

SCL I

SDA

GPIO_0

REF

ASEL1

C BUS

0.1μF

29701 F01

0.1μF

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LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

4-Step Resistor Selection Procedure for DC/DC Converters with External Feedback Resistors

The following 4-step procedure should be used to quickly calculate the resistor values shown for the Typical Application Circuit shown in Figure 1.

1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage V

DC0,NOM

solve for R10.

DC0,NOM

verter when the LTC2970’s V state. V when the loop is in regulation, and I

is the desired output voltage of the DC/DC con-

pin is in a high impedance

OUT0

is the voltage at the converter’s feedback node

FB0

is the feedback

FB0

node’s input current.

•

VIRV

DC NOM FB FB

−•−

(1)

2. Solve for the maximum value of R30 that yields the maximum required DC/DC converter output voltage V

DC0,max

When V

is at 0V, the output of the DC/DC converter

OUT0

is at its maximum voltage. Note that the 10mV term corresponds to the maximum offset voltage of the IDAC 1X voltage buffer.

, and

DC NOM FB FB0

DC MIN DC NOM

40 236 10

RAVm

()

DC MAX DC NOM FB00 0

=•+

≤−•

•−−μ VV

≥+•−

⎛

⎜

⎝

R R

⎞

+•

⎟

⎠

(5)

(4)

R R

VmV

()

(6)

The margining resolution is bounded by:

••

40 276

RES

≤

256

volts/DAC LSB (7)

Margining DC/DC Converters with a TRIM Pin

Figure 2 illustrates a typical application circuit for margining the output voltage of a DC/DC converter with a TRIM Pin. The LTC2970’s V pin through resistor R30 and the I

pin connects directly to the TRIM

OUT0

pin is terminated

OUT0

at the converter's point-of-load ground throught R40. Resistors R30 and R40 give this application circuit two degrees of freedom so that the margin-up and margindown percentages can be speciﬁ ed independently.

RV mV

20 10

•−

()

≤

−

DC MAX DC NOM

(2)

3. Solve for the minimum value of R40 that’s needed to yield the minimum required DC/DC converter output voltage V

DC0,MIN

The DC/DC converter output voltage will be a minimum when IDAC0 is at its full-scale current. In order to guarantee that R40 is large enough, assume that IDAC0’s full-scale current is at the datasheet minimum of 236μA.

()

DC NOM DC MIN FB

≥

−

•++

236

VmV

(3)

4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution.

Following power-up, the LTC2970's V

pin defaults to a

OUT0

high-impedance state. If the soft-connect feature is used,

8V TO 15V

C BUS

0.1μF

29701 F02

29701fc

0.1μF

12V

VO+

TRIM

DC/DC

CONVERTER

SENSE+

ON/OFF

SENSE–

VO–

Figure 2. LTC2970 Application Circuit for DC/DC Converters with a TRIM Pin

LOAD

R30

DC0

–

R40

1/2 LTC2970

GPIO_CFG

OUT0

IN0_AP

OUT0

IN0_AM

GND ASEL0 ASEL1

ALERT

SCL I

SDA

GPIO_0

REF

LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

the LTC2970 will automatically ﬁ nd the IDAC code that most closely approximates the TRIM pin's open-circuit voltage before enabling V

and the converter's output is typically non-invert-

TRIM

ing, so be sure to set the LTC2970's CH0_a_idac_pol bit to 1 in order to allow the voltage servo feature to function properly.

DC/DC converters with a TRIM pin are usually margined high or low by connecting an external resistor between the TRIM pin and either the V relationships between these resistors and the Δ% change in the output voltage of the DC/DC converter are typically expressed as:

TRIM DOWN

TRIM UP

⎡

TRIM DC UP

⎢ ⎣

•• %

100

()

••%

REF UP

. Note: The relationship between

OUT0

or V

SENSE+

•

TRIM

DOWN

+Δ

−

TRIM_

RRIM

− Δ

•%50

SENSE–

−

pin. The

⎤ ⎥

TRIM

⎦

(8)

(9)

Tracking with the LTC2970-1

A typical LTC2970-1 tracking application circuit is shown in Figure 3 (the sequence of events for tracking are described in sections 9 and 10 of the Operation section). The GPIO_0 and GPIO_1 pins are tied directly to their respective DC/DC converter RUN/SS pins. Since GPIO_CFG is pulled-up to

, the LTC2970-1 will automatically hold off the DC/DC

converters after power-up by asserting open drain outputs GPIO_0 and GPIO_1 low. N-channel FETs Q10/11 and diodes D10/11 form unidirectional range switches around resistors R30A/31A while GPIO_CFG is high. These range switches allow the LTC2970-1’s V

OUT0

and V

OUT1

pins to drive the converter outputs all the way to/from ground through resistors R30B/31B. When GPIO_CFG pulls low, N-channel FETs Q10 and Q11 will turn off. R30A/31A and R30B/31B then combine in series for normal margin operation. The 100k/0.1μF low-pass ﬁ lter in series with the gates of Q10/11 minimizes charge injection into the feedback nodes of the DC/DC converters when GPIO_CFG pulls low.

8V TO 15V

where R

is the TRIM pin's opern-circuit output voltage and

REF

is the DC/DC converter's nominal output voltage.

% and Δ

is the resistance looking into the TRIM pin,

TRIM

% denote the percentage change in the

DOWN

converter's output voltage when margining up or down respectively.

2-Step Resistor Selection Procedure for DC/DC Converters with a TRIM Pin

The following two-step procedure should be used to calculate values for resistors R30 and R40 shown in Figure 2.

1. Solve for R30:

3050≤

TRIM

⎛

−Δ

DOWN

•

⎜

⎝

⎞

⎟

⎠

(10)

2. Solve for R40:

⎛

40 1

≥+

⎜

⎝

DOWN

⎞

REF

•

⎟

⎠

236

(11)

10k

100k

Q10

Q11

R30A

0.1μF

R31A

0.1μF

Q10, Q11: 2N7002

0.1μF

D10, D11: MMBD4448V *SOME DETAILS OMITTED FOR CLARITY

D10

R30B

R40

D11

R31B

R41

C BUS

ALERT

SCL

SDA

12V

GPIO_CFG

LTC2970-1

GND

GPIO_0

OUT0

GPIO_1

OUT1

Figure 3. LTC2970-1 Tracking Application Circuit

RUN/SS

DC/DC

CONVERTER

R10

RUN/SS

DC/DC

CONVERTER

R11

R20

R21

OUT

DC0

DC1

29701 F03

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LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

7-Step Procedure for Calculating Tracking Application Circuit Resistor Values, Counter Delay Values, and Terminal IDAC Codes

The following 7-step procedure should be used to calculate the resistor values, tracking counter delays, and terminal IDAC codes for the Tracking Application Circuit shown in Figure 3.

1. Assume a value for R20 and solve for R21.

DCn,NOM

the LTC2970’s V

2. Solve for R10 and R11.

3. Solve for R40 and R41.

For simplicity, this procedure assumes that R40 = R41. V

DCn,MAX

converter output margin voltages, respectively.

is the output voltage of the DC/DC converter when

pin is in a high impedance state.

OUTn

DC NOM

21 20

=•

⎛

DC NOM

⎜

⎝

and V

DC NOM

DCn,MIN

(12)

(13)

⎞

−

⎟

⎠

are the maximum and minimum

Due to the forward drop of diodes D10 and D11 (0.8V max), the minimum value for R40 = R41 from expression (14) may result in small or even negative values of R30 and R31 in Step 4. If this is the case, assume a minimum allowable value for R3nB, and use the following expression to calculate the minimum value R40 = R41:

40 41

=≥

•+ +

RBRRB

⎛

⎜

⎝

⎞

08 1

⎟

⎠

(15)

236mVAμ

Note: Use the channel whose parameters yield the maximum value for R40 = R41.

4. Solve for R30B and R31B.

Solve for the upper limits of R30B and R31B and then determine which resistor value constrains the maximum value of the other resistor using Equation 17.

RAVVmV

4 236 0 8 10

•−−−

≤

RBRRB

()

μ .

⎛

•+

⎜

⎝

1 1

⎞ ⎟

22n

⎠

(16)

(17)

The value of R40 = R41 is constrained by:

40 41=≥

⎛

()

DC NOM DC MIN

•

⎜ ⎜

()

⎝

DC MAX D

−

CC NOM

236μ

⎞

+110

⎟ ⎟

⎠

(14)

5. Solve for R30A and R31A.

R30A and R31A are constrained by:

≤

⎛

⎜

⎝

⎞

DC MAX DC NOM

•

⎟

⎜

⎠

⎝

−

nnn,NOM

− 3

⎞ ⎟

⎠

(18)

29701fc

LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

6. Solve for Channel 1’s tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK().

CH A DELAY TRACK

__ _ ()

()

DC NOM DC NOM

Note: V R1n. If the result for CH1_A_DELAY_TRACK() is less than 0, apply the unsigned result to the CH0_A_DELAY_TRACK() register.

7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0].

Ch a idac track

255

Note: This formula assumes that the Chn_a_idac_pol bit is set to 0.

Margining Application Circuit Design Example

Consider the LTC2970 application circuit shown in Figure

1. Channel 0 is a DC/DC converter whose output needs to be varied between 3.63V and 1.62V. V assume that I

1. Assume values for feedback resistor R20 and the nominal DC/DC converter output voltage V solve for R10.

Let V

DC0,NOM

and assume that R20 = 10kΩ. From Equation 1:

10 0 8

22 625 0 8

Let R10 = 4.37kΩ (the nearest E192 series resistor value).

′

−

141

A count R

μ /

DCn,NOM

__ _ [:]

−

ʹ is based on the ﬁ nal values of R2n and

ALSBR

FB0

= 2.625V (the average of 3.63V and 1.62V)

VIRV

DC NOM FB FB

.Ω

•

VV−

•

•μ

= 0A.

•

−•−

4 384

=Ω

′

(

331

•

counts

()

(20)

SSB s’)

(19)

= 0.8V and

FB0

DC0,NOM

, and

2. Solve for the value of R30 that yields the maximum required DC/DC converter output voltage V

From Equation 2:

RV mV

20 10

•−

()

≤

10 0 0

..Ω 8810

3 63 2 625

Let R30 = 7.68kΩ.

3. Solve for the value of R40 that’s needed to yield the minimum required DC/DC converter output voltage V

DC0,MIN

From Equation 3:

Let R40 = 6.81kΩ.

4. Re-calculate the minimum, nominal, and maximum DC/DC converter output voltages and the resulting margining resolution.

From Equations 4, 5, and 6:

()

≥

2 625

.μVVV

()

DC NOM FB FB0

⎛

08 1

•+

⎜

⎝

DC MIN DC NOM FB00 0

→<−•

DC MIN0

236 6 81 0

()

−

DC MAX DC NOM

•

VmV

−

()

−

DC NOM DC MIN FB

−

<−••−

•−

−

236

162

=•+

437

•+

236

⎛

⎜

⎝

110

⎞ ⎟

⎠

Ω.

2 631

Ωμ 8810 159VmV V−

796

2 631

R R

768

7 861

, Ω

•+

20 30

⎞

+• =

⎟

⎠

236 40

()

DC0,MAX

6 780

AR V

= .

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LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

660V

R R

VmV

()

768

DC MAX DC NOM FB00 0

>+•−

→>+•

DC MAX0

−

VmV

08 10 36

()

2 631

From Equation 7, the margining resolution will be less than:

••

RES

768

256

40 276

••

665

256

2276

μA

933

= . mV/LSB

Margining DC/DC Converter with TRIM Pin Design Example

Tracking Application Circuit Design Example

Consider the LTC2970-1 application circuit shown in Figure

3. Channel 0 is a 1.8V DC/DC converter while channel 1 is a 2.5V switching power supply. Both converters have a feedback node voltage of 0.8V and need to track on and off coincidentally. In addition, a margin range of +5% and –10% is required for each supply.

1. Assume a value for R20 and solve for R21.

Let R20 = 5,970Ω. From Equation 12:

DC NOM

21 20 5 970

=• = • =

DC NOM

,Ω 2292Ω

Let R21 = 8,250Ω (the nearest E192 Series resistor value).

2. Solve for R10 and R11.

From Equation 13:

The output voltage of the DC/DC converter in Figure 2 needs to be margined ±10% about its nominal value. Assume that R

= 10.22kΩ and V

TRIM

= 1.225V.

REF

1. Solve for R30 using Equation 10:

≤

.•

10 22

TRIM

⎛

•

⎜

⎝

⎛ ⎜

⎝

−

DOWN

110

DOWN

⎞ ⎟

⎠

= , Ω

⎞

⎟

⎠

40 880

Let R30 = 39.2kΩ.

2. Solve for R40 using Equations 11:

⎛

≥+

40 1

⎜

⎝

⎛

⎜

⎝

⎞ ⎟

⎠⎠

DOWN

236

.,1 225

Aμ

⎞

•

⎟

236

⎠

=•

10 381

REF

Let R40 = 10.5kΩ.

⎛ ⎜

⎝

⎛ ⎜

⎝

DC NOM

⎛

⎞

−

⎜

⎟

⎝

⎠

8 250

⎛

⎞

⎜

⎟

⎝

⎠

5 970

−

Let R10 = 4,750Ω and R11 = 3,880Ω.

3. Solve for R40 and R41.

Assume that R40 = R41.

40 41=≥

⎛

()

DC NOM DC MIN

•

⎜ ⎜

()

⎝

DC MAX D

⎛

−

109

(.)

•

⎜

(

1105 1

⎝

236

−

CC NOM

236

⎞

110

+=mV

−

⎟

⎠

Aμ

4 776

= , Ω

⎞

⎟

⎠

3 882

= , Ω

⎞

⎟

⎠

⎞

110

⎟ ⎟

⎠

10 212

Let R40 = R41 = 10.5kΩ

29701fc

LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

4. Solve for R30B and R31B.

RAVVmV

40 236 0 8 10

10 5 236 0 8 0 8 10

()

≤

• −−−(. . . )

k AVVmV

Ωμ

••+

RAVVmV

41 236 0 8 10

()

≤

10 5 236 0 8 0 8 10

• −−−(. . . )

k AVVmV

Ωμ

••+

For coincident tracking to occur Equation 17 also must be satisﬁ ed:

μ .

•−−−

⎛

•+

⎜

⎝

1 220

⎞ ⎟

⎠

⎛ ⎜

⎝

4 750

ΩΩ

•−−−

μ .

⎛

•+

⎜

⎝

⎞ ⎟

221

⎠

⎞ ⎟

⎠

5 970

⎛ ⎜

⎝

3 880

ΩΩ

8 250

⎞ ⎟

⎠

2 870

2 863

≤

⎛

⎜

⎝

8 250

⎛

⎜

⎝

3 880

⎞

⎞ ⎟⎟

⎠

•

⎟

⎠

105 1

⎛

•

⎜

⎝

⎛

DC MAX DC NOM

⎜ ⎝

−

NOM

2 890 49 888

,,ΩΩ

−=

⎞ ⎟

⎠

−=

⎞ ⎟

⎠

Let R30A = 49.9kΩ and R31A = 48.7kΩ.

6. Solve for Channel 1’s tracking counter delay relative to Channel 0, CH1_A_DELAY_TRACK().

First, recalculate the values of V

DCn,NOM

based on the ﬁ nal

values of R1n and R2n:

′

DC NOM FB FB0

08 1

=•+

5 970

⎛

• ++

⎜

⎝

4 750

, ,

Ω Ω

⎛

⎜

⎝

⎞ ⎟

⎠

⎞ ⎟

⎠

0 1 805

+• =

RBRRB

→=•= • =RB

→= •= • =RB

2 863

R30

R31

8 250

2 870

5 970

5 970 2 078

8 250 3 957

Let R30B = 2,100Ω and R31B = 2,890Ω.

5. Solve for R30A and R31A.

Referring to Equation 18:

≤

5 970

⎛

⎜

⎝

4 750

⎛

⎜

⎝

5 970

Ω Ω

⎞ ⎟⎟

⎠

⎞

•

⎟

⎠

105 1

⎛

•

⎜

⎝

⎛

DC MAX DC NOM

⎜ ⎝

−

NOM

2 100 50 806

,,ΩΩ

−=

⎞ ⎟

⎠

ΩΩΩ

−=

⎞ ⎟

⎠

8 250

3 880

Ω Ω

⎞

0 2 501

⎟

⎠

DC NOM1

′

08 1

=•+

⎛

⎜

⎝

Next, apply Equation 19:

CH A DELAY TRACK

__ _ ()

()

DC NOM DC NOM

2 501 1 805

()

′

−

141

A count R

μ /

−

•

2 890

•

88 250

1105

•

331

′

, ,

•

Ω Ω

counts

ΩμA count k

7. Solve for the IDAC0 and IDAC1 terminal tracking codes, Chn_a_idac_track[7:0].

Ch a idac Ch a idac

070170

__ [:] __ [:]

255

−

//.LSB k•=10 5

179

29701fc

LTC2970/LTC2970-1

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APPLICATIO S I FOR ATIO

2.7

2.4

2.1

1.8

1.5

VOLTS

1.2

0.9

0.6

0.3

Figure 4. Tracking Design Example DC/DC Converter Output Waveforms

Figure 4 shows the DC/DC converter output voltages for this design example tracking-up and tracking-down.

Temperature Sensor Conversion

The LTC2970's internal temperature sensor output is proportional to absolute temperature (PTAT). In order to convert the ADC reading to degress Celsius, apply the following formula:

ADC temp sensor reading

result C

()

(21)

__ _

Negative Power Supply Application Circuit

Figure 5 shows the LTC2970 controlling a negative power supply. The R30/R40 resistor divider translates the point of load voltage to the LTC2970’s V

inputs monitor the converter’s input current I • R

IN0_B

0.1μF

SENSE

GND

OUT

DC/DC

CONVERTER

Figure 5. Negative Power Supply Application Circuit

R20

R10

R20

LOAD

R10

DC1

DC0

5ms/DIV

29701 F04

.°= −4273 15

inputs while the

IN0_A

8V TO 15V

29701 F05

– V

IN0_AM

0.1μF

I2C BUS

0.1μF

)

12V

IN0_AP

IN0_AM

1/2 LTC2970

–

(

ALERT

SCL

SDA

REF

R30

•

1 +

(

IN0_AP

)

R40

IN0_BP

IN0_BM

TP0610K

OUT0

GND ASEL0 ASEL1

= V

OUT

drop across resistor R

. Since the VDD pin voltage

SENSE

is monitored by the LTC2970, its tolerance can be accounted for when calculating the point of load voltage. Transistor Q1 allows the I

pin to force current into

OUT0

the converter’s feedback node without forward biasing the LTC2970’s I

body diode. Note that I

OUT0

’s output

current defaults to 128μA after the LTC2970 comes out of power-on reset.

15-Bit Programmable Power Supply Application Circuit

Figure 6 illustrates how both servo channels of the LTC2970 can be conﬁ gured to adjust a single DC/DC converter over a 15-bit dynamic range. R30 and R31 are sized to force 1 bit of overlap between the coarse (channel 0) and ﬁ ne (channel 1) servo loops. One coarse servo iteration should be performed ﬁ rst on channel 0 with IDAC1 programmed to mid-scale, and then channel 1 can be programmed to servo to the desired voltage.

Programmable Reference Application Circuit

Figure 7 shows a LTC2970 conﬁ gured as a programmable reference that can span a 0V to 3.5V range with a resolution of 100μV and an absolute accuracy of less than ±0.5%. The two IDAC’s are paralleled by terminating IDAC1’s output resistor in the V output of the composite DAC from V

output and taking the

OUT0

. IDAC0 should

OUT1

servo once with IDAC1 set to mid-scale, and then IDAC1 can servo once, continuously, or trigger on drift to the desired target voltage.

8V TO 15V

12V

GND

OUT1

OUT0

OUT1

OUT0

IN0_AP

IN1_AP

IN0_AM

IN1_AM

LTC2970

GPIO_CFG

ALERT

GPIO_0

ASEL0 ASEL1

SCL

SDA

REF

OUT

DC/DC

CONVERTER

RUN/SS

SGND

GND

LOAD

R31

R30

R31 ≥ R30 • 128 R41 = R40

R20

LOAD

R41

R40R10

Figure 6. Programmable Power Supply Application Circuit

0.1μF

I2C BUS

0.1μF

29701 F06

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PACKAGE DESCRIPTIO

LTC2970/LTC2970-1

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1696)

4.50 ± 0.05

3.10 ± 0.05

2.65 ± 0.05

(2 SIDES)

0.25 ±0.05

0.50 BSC

3.65 ± 0.05

(2 SIDES)

4.10 ± 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

5.50 ± 0.05

TYPICAL APPLICATIO

0.70 ±0.05

PACKAGE OUTLINE

5.00 ± 0.10

(2 SIDES)

4.00 ± 0.10

(2 SIDES)

PIN 1 TOP MARK (NOTE 6)

2.65 ± 0.10

(2 SIDES)

0.75 ± 0.05

3.65 ± 0.10

(2 SIDES)

0.200 REF

0.00 – 0.05

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

R = 0.115 TYP

BOTTOM VIEW—EXPOSED PAD

23 24

PIN 1 NOTCH R = 0.30 TYP

0.25 ± 0.05

0.50 BSC

0.40 ± 0.05

(UFD24) QFN 0505

8V TO 15V

29701 F07

0.1μF

C BUS

0.1μF

12V

LTC2970

IN1_AP

IN1_AM

IN0_AP

IN0_AM

OUT1

22μF

OUT

–

10Ω

OUT1

100Ω

OUT0

12.7k

GND ASEL0 ASEL1

OUT0

ALERT

SCL

SDA

REF

Figure 7. Programmable Reference Application Circuit

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29701fc

LTC2970/LTC2970-1

TYPICAL APPLICATIO

OUT

DC/DC

CONVERTER 0

RUN/SS

SGND

PGND

I+

I–

R50

R30

R20

LOAD

R10 R40

8V TO 15V

12V

IN0_BM

IN0_BP

OUT0

IN0_AP

OUT0

IN0_AM

GPIO_0

GPIO_CFG

ALERT

SCL

SDA

10k

0.1μF

C BUS

SMBUS

()

COMPATIBLE

IN1_BM

IN1_BP

OUT1

IN1_AP

OUT1

IN1_AM

GPIO_1

GND

LTC2970

ASEL0 ASEL1

REF

RGND

212225

0.1μF

29701 TA01

OUT

DC/DC

CONVERTER 1

RUN/SS

SGND

PGND

R51

I+

I–

R31

R21

LOAD

R11 R41

Figure 8. Typical LTC2970 Application Circuit for DC/DC Converters with External Feedback Resistors

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC2920-1/LTC2920-2 Single/Dual Power Supply Margining Controllers Symmetric/Asymmetric High and Low Voltage Margining

LTC2921/LTC2922 Power Supply Trackers with Input Monitors 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches

LTC2923 Power Supply Tracking Controller Up to 3 Supplies

LTC2924 Quad Power Supply Sequencer Voltage Monitoring and Sequence Error Detection and Reporting

LTC2925 Multiple Power Supply Tracking Controller Power Good Timer, Remote Sense Switch

LTC2926 MOSFET Controller Power Supply Tracker Up to 3 Modules

LTC2927 Single Power Supply Tracker Point of Load Applications

29701fc

0308 REV C • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

LINEAR TECHNOLOGY LTC2970, LTC2970-1 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual