LINEAR TECHNOLOGY LTC2926 Technical data

FEATURES

LTC2926

MOSFET-Controlled

Power Supply Tracker

U

DESCRIPTIO

■

Flexible Power Supply Tracking and Sequencing

■

Adjustable Ramp Rates, Offsets and Time Delays

■

Controls Three Supplies with Series MOSFETs

■

Integrated Remote Sense Switching

■

FAULT Input/Output

■

STATUS Output/Power Good Input

■

Available in 20-Lead Narrow SSOP and 20-Lead QFN

(4mm × 5mm) Packages

U

APPLICATIO S

■

V

■

Microprocessor, DSP and FPGA Supplies

■

Servers

■

Communications Systems

All other trademarks are the property of their respective owners.
*Protected by U.S. Patents including 6897717.

and V

CORE

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Supply Tracking

I/O

U

TYPICAL APPLICATIO

1.8V MODULE

OUT

SENSE

3.3V MODULE

OUT

SENSE

15.0k

4.02k

FAULT

ON/OFF

100Ω

100Ω

15.0k

9.53k

10k

0.1µF

V

CC

D1

D2

RAMPBUF

TRACK1

TRACK2

V

CC

FAULT

ON

IRF7413Z

10Ω

SGATE2

LTC2926

GND

IRF7413Z

10Ω

PGTMR

SGATE1

STATUS/PGI

MGATE

RAMP

2926 TA01

1µF

FB1

FB2

1.8V
SLAVE1

3.3V
SLAVE2

S1

15.0k

9.53k

S2

15.0k

V

CC

4.02k

10k

STATUS

0.1µF

The LTC2926 provides a simple solution for tracking and
sequencing up to three power supply rails. An N-channel
MOSFET and a few resistors per channel confi gure the
load voltages to ramp up and down together, with voltage
offsets, with time delays or with different ramp rates.

Automatic remote sense switching compensates for voltage
drops across the MOSFETs. The LTC2926 provides two
integrated switches as well as a signal to control optional
additional external N-channel MOSFET sense switches.

The LTC2926 includes I/O signals for communication with
other devices. The status output asserts after tracking and
sequencing have completed. A low voltage on the power
good input after an adjustable timeout period causes load
disconnect. A low voltage on the fault I/O causes immedi­ate load disconnect. Until it is reset, a fault latch prevents
tracking and keeps the loads disconnected.

3.3V SLAVE2

500mV/DIV

5ms/DIV

3.3V SLAVE2

1.8V SLAVE1

5ms/DIV

1.8V SLAVE1

2926 TA01b

500mV/DIV

2926 TA01c

2926fa

1

LTC2926

WW

W

U

ABSOLUTE AXI U RATI GS

(Notes 1, 2)

Supply Voltage (VCC) ................................. –0.3V to 10V

Input Voltages

ON ......................................................... –0.3V to 10V

RAMP .............................................–0.3V to V

TRACK1, TRACK2 ........................–0.3V to V

PGTMR ........................................–0.3V to V

CC

+ 0.3V

CC

+ 0.3V

CC

+ 1V

Input/Output Voltages

FAULT .................................................... –0.3V to 10V

STATUS/PGI (Note 3) .......................... –0.3V to 11.5V

Output Voltages

RAMPBUF ....................................–0.3V to V

+ 0.3V

CC

FB1, FB2, D1, S1, D2, S2 ....................... –0.3V to 10V

MGATE, RSGATE (Note 3) ................... –0.3V to 11.5V

SGATE1, SGATE2 (Note 3) .................. –0.3V to 11.5V

UUW

PACKAGE/ORDER I FOR ATIO

RMS Currents

TRACK1, TRACK2 ................................................5mA

FB1, FB2 ..............................................................5mA

D1, S1, D2, S2 ...................................................30mA

Operating Temperature

LTC2926C ................................................ 0°C to 70°C

LTC2926I ............................................. –40°C to 85°C

Storage Temperature Range

GN Package .......................................–65°C to 150°C

UFD Package ...................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

GN Package ......................................................300°C

TOP VIEW

1

V

CC

TRACK1

SGATE1

2

3

FB1

4

S1

5

6

D1

7

ON

8

PGTMR

9

FAULT

10

GND

20-LEAD PLASTIC SSOP

T

JMAX

GN PACKAGE

= 125°C, θJA = 85°C/W

RAMPBUF

20

TRACK2

19

FB2

18

S2

17

SGATE2

16

D2

15

STATUS/PGI

14

RSGATE

13

MGATE

12

RAMP

11

ORDER PART NUMBER ORDER PART NUMBER UFD PART MARKING*

LTC2926CGN
LTC2926IGN

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

TOP VIEW

TRACK1

VCCRAMPBUF

TRACK2

20 19 18 17

9 10

RAMP

16

15

14

13

12

11

MGATE

FB2

S2

SGATE2

D2

STATUS/PGI

RSGATE

2926
2926

1

FB1

S1

2

SGATE1

3

4

D1

ON

5

6

PGTMR

20-LEAD (4mm × 5mm) PLASTIC QFN

EXPOSED PAD (PIN 21) IS GND

PCB CONNECTION OPTIONAL
T

JMAX

21

7 8

GND

FAULT

UFD PACKAGE

= 125°C, θJA = 43°C/W

LTC2926CUFD
LTC2926IUFD

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.*The temperature grade is identifi ed by a label on the shipping container.

2926fa

2

LTC2926

ELECTRICAL CHARACTERISTICS

The
temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage

V

CC

I

CC

V

CC(UVLO)

ΔV

CC(UVLO)

Control and I/O

V

ON(TH)

ΔV

ON(TH)

I

ON

V

ON(CLR)

t

CLR

V

ON(ARM)

t

ARM

V

FAULT(TH)

I

FAULT(UP)

V

FAULT(OL)

V

FAULT(OH)

V

PGI(TH)

ΔV

PGI(TH)

I

PGI(UP)

V

STATUS(OL)

V

STATUS(OH)

V

PGTMR(TH)

I

PGTMR(UP)

I

PGTMR(DN)

V

PGTMR(CLR)

Ramp Buffer

I

RAMP(IN)

V

RAMPBUF(OS)

V

RAMPBUF(OL)

Input Supply Voltage Operating Range

Input Supply Current I

Input Supply Undervoltage Lockout VCC Rising

Input Supply Undervoltage Lockout
Hysteresis

ON Pin Threshold Voltage VON Rising

ON Pin Threshold Voltage Hysteresis

ON Pin Input Current VON = 1.2V, VCC = 5.5V

ON Pin Fault Clear Threshold Voltage VON Falling

Fault Clear Delay VON Falling

ON Pin Fault Arm Threshold Voltage VON Rising

Fault Arm Delay VON Rising

FAULT Pin Input Threshold Voltage V

FAULT Pin Pull-up Current Fault Latch Clear, V

FAULT Pin Output Low Voltage Fault Latch Set, I

FAULT Pin Output High Voltage
(V

CC

– V

FAULT

)

STATUS/PGI Pin Input Threshold
Voltage

STATUS/PGI Pin Input Threshold
Voltage Hysteresis

STATUS/PGI Pin Pull-Up Current STATUS/PGI On, V

STATUS/PGI Pin Output Low Voltage VON Low, I

STATUS/PGI Pin Output High Voltage
(V

STATUS/PGI

– VCC)

PGTMR Pin Threshold Voltage V

PGTMR Pin Pull-Up Current ON High, V

PGTMR Pin Pull-Down Current ON Low, V

PGTMR Pin Clear Threshold Voltage V

RAMP Pin Input Current 0V < V

Ramp Buffer Offset Voltage V

RAMPBUF Pin Output Low Voltage I

= 25°C. VCC = 3.3V unless otherwise specifi ed.

A

TRACKn

I

RAMPBUF

I

TRACKn

I

RAMPBUF

Fault Latch Clear, I

V

I

STATUS/PGI

RAMPBUF

= 0mA, I

= –1mA, I

= –3mA

Falling

FAULT

STATUS/PGI

Rising

PGTMR

Falling

PGTMR

RAMP

= 1/2 VCC, I

RAMP

= 3mA

●

denotes the specifi cations which apply over the full operating

●

2.9 3.3 5.5 V

= 0mA,

FBn

●

1.5 2.5 3.5 mA

= 0mA

= –1mA,

FBn

= 1.5V

FAULT

= 5mA, VCC = 2.7V

FAULT

= –1µA

FAULT

Rising

STATUS/PGI

STATUS/PGI

= 5mA, VCC = 2.7V

= –1µA

= 1V

PGTMR

= 0.1V, VCC = 2.7V

PGTMR

< 5.5V, VCC = 5.5V

RAMPBUF

= 1.5V

= 0mA

●

8.5 9.5 10.5 mA

●

2.2 2.4 2.6 V

●

15 50 75 mV

●

1.20 1.23 1.26 V

●

40 75 110 mV

●

●

0.465 0.500 0.535 V

●

1 3 10 µs

●

0.565 0.600 0.635 V

●

1 4.5 10 µs

●

0.465 0.500 0.535 V

●

–3.0 –8.5 –13 µA

●

●

300 550 900 mV

●

1.10 1.23 1.36 V

●

30 75 150 mV

●

–7 –10 –13 µA

●

●

5.0 5.5 6.0 V

●

1.10 1.23 1.36 V

●

–8 –10 –12 µA

●

0.5 4 10 mA

●

50 100 150 mV

●

●

●

0 ±100 nA

100 400 mV

200 400 mV

0±1 µA

0 ±10 mV

32 60 mV

2926fa

3

LTC2926

ELECTRICAL CHARACTERISTICS

The
temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

RAMPBUF(OH)

Tracking Channels

I

ERROR(%)

V

TRACK

V

FB(REF)

I

FB(LEAK)

V

FB(CLAMP)

Master Ramp and Supply

ΔV

MGATE

I

MGATE(UP)

I

MGATE(DN)

I

MGATE(FAULT)

Slave Supplies

ΔV

SGATE

I

SGATE(UP)

I

SGATE(DN)

I

SGATE(UPFST)

I

SGATE(DNFST)

I

SGATE(FAULT)

Remote Sense Switches

ΔV

RSGATE

I

RSGATE(UP)

I

RSGATE(DN)

I

RSGATE(FAULT)

V

RSGATE(TH)

R

SW(ON)

RAMPBUF Pin Output High Voltage
(V

– V

CC

I

to I

FBn

TRACKn

(I

– I

FBn

TRACKn

)

RAMPBUF

Current Mismatch
)/I

TRACKn

• 100%

TRACK Pins Voltage I

FB Pins Internal Reference Voltage V

FB Pins Leakage Current V

FB Pins Clamp Voltage –1mA < I

MGATE Pin External N-Channel Gate
Drive (V

MGATE

– VCC)

MGATE Pin Pull-Up Current Fault Latch Clear, VON High, V

MGATE Pin Pull-Down Current Fault Latch Clear, VON Low, V

MGATE Pin Fault Pull-Down Current Fault Latch Set, VON High, V

SGATE Pins External N-Channel Gate
Drive (V

SGATEn

– VCC)

SGATE Pins Pull-Up Current Fault Latch Clear, V

SGATE Pins Pull-Down Current Fault Latch Clear, V

SGATE Pins Fast Pull-Up Current Fault Latch Clear, V

SGATE Pins Fast Pull-Down Current Fault Latch Clear, V

SGATE Pins Fault Pull-Down Current Fault Latch Set, VON High, V

RSGATE Pin External N-Channel Gate
Drive (V

RSGATE

– VCC)

RSGATE Pin Pull-Up Current Fault Latch Clear, Switches On, V

RSGATE Pin Pull-Down Current Fault Latch Clear, Switches Off,

RSGATE Pin Fault Pull-Down Current Fault Latch Set, Switches Off,

RSGATE Pin Threshold Voltage Ramping Completed on Pin Low, RSGATE

Remote Sense Switch On-Resistance Switches On, VDn = VCC + 0.3V, ISn = –10mA

= 25°C. VCC = 3.3V unless otherwise specifi ed.

A

I

RAMPBUF

I

TRACKn

I

TRACKn

TRACKn

I

TRACKn

I

MGATE

V

I

SGATEn

V

V

V

I

RSGATE

V

V

Falling

●

denotes the specifi cations which apply over the full operating

= –3mA

= –10µA
= –1mA

= –10µA
= –1mA

= VCC, I

TRACKn

= 0.8V, VCC = 5.5V

FBn

< –1µA

FBn

= –1µA

= 5.5V

CC

= –1µA, V

= 3.3V

SGATEn

= 3.3V

SGATEn

= 5.5V

CC

= –1µA

= 3.3V

RSGATE

= 5.5V, VCC = 5.5V

RSGATE

FBn

FBn

= 0mA

= 0.75V

= V

FBn

= V

FBn

= 0V, V

FBn

= 1V, V

FBn

MGATE

MGATE

MGATE

FB(REF)

FB(REF)

SGATEn

SGATEn

SGATEn

= 3.3V

= 3.3V

= 5.5V,

– 10mV,

+ 10mV,

= 3.3V

= 3.3V

= 5.5V,

= 0V

RSGATE

●

●

●

●

0.776

●

0.776

●

0.784 0.800 0.816 V

●

●

1.7 2.0 2.4 V

●

5.0 5.5 6.0 V

●

–7 –10 –13 µA

●

71013 µA

●

52050 mA

●

5.0 5.5 6.0 V

●

–6 –10 –13 µA

●

61013 µA

●

–21 –30 –39 µA

●

21 30 39 µA

●

52050 mA

●

5.0 5.5 6.0 V

●

–7 –10 –13 µA

●

71013 µA

●

52050 mA

●

1.10 1.23 1.36 V

●

60 80 mV

0
0

0.800

0.800

±3
±3

0.824

0.824

0 ±10 nA

210

%
%

V
V

Ω

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All currents into the device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to ground unless
otherwise specifi ed.

4

Note 3: The MGATE, SGATE1, SGATE2, RSGATE and STATUS/PGI pins are
internally limited to a minimum of 11.5V. Driving these pins to voltages
beyond the clamp level may damage the part.

2926fa

LTC2926

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Specifi cations are at TA = 25°C, VCC = 3.3V
unless otherwise specifi ed.

Supply Current vs Supply Voltage Supply Current vs Temperature Track Pin Voltage vs Temperature

12

12

0.812

10

8

6

(mA)

CC

I

I

= 0mA

RAMPBUF

= 0mA

I

TRACKn

4

2

0

= 0mA

I

FBn

3.0 3.5 4.5 5.5 6.0

2.5

Gate Drive Voltages vs
Supply Voltage

6.0
MGATE, RSGATE, SGATE1, SGATE2 PINS

5.8

5.6

5.4

GATE DRIVE (V)

5.2

GATE DRIVE = V

= –1µA

I

GATE

5.0

3.0 3.5 4.0 4.5 5.0 5.5

2.5

I

RAMPBUF

= –1mA

I

TRACKn

= –1mA

I

FBn

4.0 5.0
(V)

V

CC

– V

PIN

CC

VCC (V)

= –3mA

2926 G01

2926 G05

6.0

10

I

= –3mA

8

6

(mA)

CC

I

I

RAMPBUF

= 0mA

I

TRACKn

4

2

0

–50 25 75–25 0 50 100

I

FBn

= 0mA

RAMPBUF

I

TRACKn

= –1mA

I

FBn

= 0mA

TEMPERATURE (°C)

= –1mA

Gate Drive Voltages vs
Load Current

6

5

4

3

GATE DRIVE (V)

2

1

0

01525510 20 3530

GATE DRIVE = V

SGATE1,
SGATE2 PINS
FAST PULL-UP
MODE

MGATE, RSGATE,
SGATE1, SGATE2 PINS
PULL-UP MODE

I

(µA)

LOAD

PIN

2926 G02

– V

2926 G06

0.808

I

= –10µA

0.804

(V)

0.800

TRACK

V

0.796

0.792

0.788
–50 25 75–25 0 50 100

TEMPERATURE (°C)

TRACK

I

TRACK

= –1mA

2926 G03

Gate Fault Pull-Down Currents vs
Supply Voltage

30

CC

(mA)

GATE(PD)

I

MGATE, RSGATE, SGATE1, SGATE2 PINS

25

20

15

10

5

FAULT LATCH SET

0

3.0 3.5 4.0 4.5 5.0 5.5

2.5
(V)

V

CC

6.0

2926 G07

MGATE, RSGATE Fault Pull-Down
Currents vs Temperature

30

25

(mA)

20

15

RSGATE(PD)

, I

10

MGATE(PD)

I

5

FAULT LATCH SET

0

–50 25 75–25 0 50 100

MGATE, RSGATE PINS

VCC = 5.5V

VCC = 3.3V

VCC = 2.9V

TEMPERATURE (°C)

2926 G08

SGATE Fault Pull-Down Current vs
Temperature

30

25

20

(mA)

15

SGATE(PD)

I

10

5

FAULT LATCH SET

0

–50 25 75–25 0 50 100

SGATE1, SGATE2 PINS

VCC = 5.5V

VCC = 3.3V

VCC = 2.9V

TEMPERATURE (°C)

2926 G09

2926fa

5

LTC2926

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Specifi cations are at TA = 25°C, VCC = 3.3V
unless otherwise specifi ed.

RAMPBUF Output Low Voltage vs
Temperature

50

I

= 3mA

RAMPBUF

40

30

(mV)

OL

V

20

10

0

–50 25 75–25 0 50 100

VCC = 2.9V

VCC = 5.5V

TEMPERATURE (°C)

2926 G10

RAMPBUF Output High Voltage vs
Temperature

100

I

= –3mA

RAMPBUF

= VCC – V

V

OH

80

60

(mV)

OH

V

40

20

0

–50 25 75–25 0 50 100

RAMPBUF

VCC = 2.9V

VCC = 5.5V

TEMPERATURE (°C)

2926 G11

Logic Output Low Voltages vs
Supply Voltage

250

STATUS/PGI PIN

200

150

(mV)

OL

V

100

50

0

2.5

FAULT PIN

3.0 3.5 4.0 4.5 5.0 5.5
VCC (V)

I

STATUS/PGI

I

FAULT

= 5mA

= 5mA

6.0

2926 G12

6

2926fa

UUU

PI FU CTIO S

LTC2926

GN/UFD Packages

D1, S1, D2, S2 (Pins 6, 4, 15, 17/Pins 4, 2, 13, 15):

Remote Sense Switches #1 and #2. A 10Ω (max) switch
connects each pair of pins (D1/S1 and D2/S2) after MGATE,
SGATE1 and SGATE2 are all fully enhanced (MGATE >
RAMP + 4.9V or RAMP > V

+ 4.9V). The switch can be used to compensate for

V

CC

the voltage drop across the external MOSFET that controls
a slave or the master supply. Connect the switch between
the load and the supply’s sense node. Before the external
MOSFET is fully enhanced, a resistor between the supply’s
output and sense nodes provides local feedback. When
the ON pin voltage is low, the switch will open before the
MGATE, SGATE1 and SGATE2 pins will ramp down. Leave
unused switch terminal pairs unconnected.

Exposed Pad (Pin 21, UFD Package Only): Exposed pad
may be left open or connected to device GND.

FAULT (Pin 9/Pin 7): Negative-Logic Fault Input/Output.
Under normal conditions the internal fault latch is not set
and an 8.5µA current pulls up FAULT to a diode drop below

. When the voltage at FAULT is pulled below 0.5V, a

V

CC

fault condition is latched and an internal N-channel MOS­FET pulls FAULT to GND until the latch is reset. The fault
condition also pulls STATUS/PGI low, opens the remote
sense switches, and pulls MGATE, SGATE1 and SGATE2
to GND to disconnect the master and slave supplies from
their loads. Pulling STATUS/PGI below 1V after the power
good time-out delay also latches a fault. The fault latch is
reset when the ON pin voltage is below 0.5V, or when V
is undervoltage. The fault latch is armed when the ON pin
voltage exceeds 0.6V. To auto-retry after a fault, connect
FAULT to the ON pin. Leave the FAULT pin unconnected
if it is unused.

FB1, FB2 (Pins 3, 18/Pins 1, 16): Feedback Control In­put/Outputs. Each FB pin connects to the feedback node
of a slave supply. Connect an FB pin to the tap point of a
resistive voltage divider between the source (load side)
of the external MOSFET and GND. For a slave supply with
an accessible feedback path, no external MOSFET may
be necessary. In that case, connect an FB pin to the tap
point of a resistive voltage divider between the supply
generator’s feedback node and GND. To prevent damage

, and SGATE1, SGATE2 >

CC

CC

to the slave supply, the FB pins will not force the slave’s
feedback node above 2.4V. In addition, it will not actively
sink current even when the LTC2926 is not powered. Tie
unused FB pins to GND.

GND (Pin 10/Pin 8): Device Ground.

MGATE (Pin 12/Pin 10): Master Gate Drive for External

N-Channel MOSFET/Master Ramp. When the ON pin is
high, an internal 10µA current charges the gate of an
external N-channel MOSFET. A capacitor from MGATE
to GND sets the master ramp rate. Add a 10Ω resistor
between the capacitor and the MOSFET’s gate to prevent
high frequency oscillations. An internal charge pump
guarantees that the MGATE pin voltage will pull up to

5.5V above V
MOSFETs are fully enhanced. When the ON pin is pulled
low, the MGATE pin is pulled to GND by a 10µA current
source. Upon a fault condition, the MGATE pin is pulled
low immediately with 20mA. To create a master ramp
signal without an external MOSFET, tie the MGATE pin to
the RAMP pin. A weak internal clamp on the RAMP pin
limits MGATE to V
pin unconnected if it is unused.

ON (Pin 7/Pin 5): On Control Input. The ON pin has
a threshold of 1.23V with 75mV of hysteresis. A high
causes 10µA to fl ow out of the MGATE pin, ramping up
the supplies. A low causes 10µA to fl ow into the MGATE
pin, ramping down the supplies. Pull the ON pin below

0.5V to reset the fault latch. Pull the ON pin above 0.6V
after a fault latch reset to arm the fault latch.

PGTMR (Pin 8/Pin 6): Power Good Timer. Connect an
external capacitor between PGTMR and GND to set the
Power Good Time-Out Delay. When the ON pin is above

1.23V, a 10µA current pulls up PGTMR to V
an internal N-channel MOSFET pulls PGTMR to GND. If
the voltage on PGTMR exceeds 1.23V and the voltage
on STATUS/PGI is not above 1.23V, a fault condition is
latched, the remote sense switches are opened, and FAULT,
STATUS/PGI, MGATE, SGATE1, SGATE2 and RSGATE will
be immediately pulled to GND. To disable the Power Good
Timer tie PGTMR to GND.

, which ensures that logic-level N-channel

CC

+ 1V in this case. Leave the MGATE

CC

, otherwise

CC

2926fa

7

LTC2926

PI FU CTIO S

UUU

GN/UFD Packages

RAMP (Pin 11/ Pin 9): Ramp Buffer Input. Connect the

RAMP pin to the master ramp signal to force the slave
supplies to track it. When the RAMP pin is connected to
the source of an external N-channel MOSFET, the slave
supplies track the MOSFET’s source, the master supply
voltage, as it ramps up and down. When a master supply
is not required, the RAMP pin can be tied directly to the
MGATE pin to form a master ramp voltage. In this confi gura­tion, the supplies track the capacitor on the MGATE pin as
it is charged and discharged by the 10µA current source
that is controlled by the ON pin. The RAMP pin is weakly
clamped to V
a low impedance source to avoid sinking large currents
into the pin. Ground the RAMP pin if it is unused.

RAMPBUF (Pin 20/Pin 18): Ramp Buffer Output. The
RAMPBUF pin provides a low impedance buffered ver­sion of the signal on the RAMP pin. This buffered output
drives the resistive voltage dividers that connect to the
TRACK pins. Limit the capacitance at the RAMPBUF pin
to less than 100pF.

RSGATE (Pin 13/Pin 11): Gate Drive for Internal and
External N-Channel MOSFET Remote Sense Switches. A
remote sense path between a load and the sense input of
its supply generator automatically compensates for voltage
drops across the tracking MOSFET. After the series MOS­FETs are fully enhanced, a 10µA current pulls up RSGATE.
An internal charge pump guarantees that RSGATE will
pull up to 5.5V above V
N-channel MOSFETs are fully enhanced. When the voltage
at RSGATE exceeds V
is released. When the ON pin is low, a 10µA current source
pulls RSGATE to GND. Supplies will not track down until
the RSGATE pin voltage falls below 1.23V, which ensures
that the remote sense switches open before the loads are
disconnected. Connect RSGATE to the gates of additional
external N-channel MOSFETs to create more remote sense
switches. Upon a fault condition, the RSGATE pin is pulled
low immediately with 20mA. Optionally connect a capaci­tor between RSGATE and GND to set the switch-on rate
or to add delay between switch closure and STATUS/PGI
assertion. Leave RSGATE unconnected if it is unused.

+ 1V. Do not drive RAMP above VCC with

CC

, which ensures that logic-level

CC

+ 4.9V, the STATUS/PGI pull-down

CC

SGATE1, SGATE2 (Pins 5, 16/Pins 3, 14): Slave Gate Con­trollers for External N-Channel MOSFETs. Each SGATE pin
ramps a slave supply by controlling the gate of an external
N-channel MOSFET so that its source terminal follows the
tracking profi le set by external resistors and the master
ramp. It is a good practice to add a 10Ω resistor between
this pin and the MOSFET’s gate to prevent high frequency
oscillations. An internal charge pump guarantees that the
SGATE pin voltage will pull up to 5.5V above V
ensures that logic-level N-channel MOSFETs are fully
enhanced. Leave unused SGATE pins unconnected.

STATUS/PGI (Pin 14/Pin 12): Status Output/Power Good
Input. A 10µA current pulls up STATUS/PGI when MGATE,
SGATE1 and SGATE2 are fully enhanced, and the remote
sense switches are closed, otherwise an internal N-channel
MOSFET pulls down STATUS/PGI. If the STATUS/PGI pin
is pulled below 1V after the power-good time-out delay
(see PGTMR pin description), the fault latch is set, and
MGATE, SGATE1, SGATE2 and RSGATE are all pulled low
immediately. An internal charge pump guarantees that the
STATUS/PGI pin voltage will pull up to 5.5V above V
An external pull-up resistor may be added to limit the
STATUS/PGI voltage to logic levels. Leave the STATUS/PGI
pin unconnected if it is unused.

TRACK1, TRACK2 (Pins 2, 19/Pins 20, 17): Tracking Con­trol Inputs. A resistive voltage divider between RAMPBUF
and each TRACK pin determines the tracking profi le of
each supply channel. Each TRACK pin pulls up to 0.8V,
and the current supplied at TRACK is mirrored at FB. The
TRACK pins are capable of supplying at least 1mA when

= 2.9V. They may be capable of supplying up to 10mA

V

CC

when the supply is at 5.5V, so care should be taken not to
short this pin for extended periods. Limit the capacitance
at the TRACK pins to less than 25pF. Leave unused TRACK
pins unconnected.

(Pin 1/Pin 19): Positive Voltage Supply. Operating

V

CC

range is from 2.9V to 5.5V. An undervoltage lockout resets
the part when the supply is below 2.4V. V
bypassed to GND with a 0.1µF capacitor.

, which

CC

should be

CC

CC

.

8

2926fa

LTC2926

UU

W

FU CTIO AL BLOCK DIAGRA

+

ON

0.6V

0.5V

1.23V

RSGATE

+ 4.9V

V

CC

RSGATE

1.23V

MGATE

RAMP + 4.9V

2.4V

V

CC

+

–

+

–

+

–

+

–

+

–

+

–

UVLO

–

DELAY

DELAY

UVLO

CLEAR/ARM

SIGNAL LATCH

R

SQ

CLR/ARM

V

CC

FAST PULL-DOWN

V

CC

8.5µA

FAULT

+

0.5V

–

V

CC

PGTMR

CHARGE

10µA

FAST

PUMP

STATUS/PGI

MGATEGATE UP

UVLO

PGTMR HIGH

PGI LOW

CHARGE

PUMP

FAULT LATCH

R

SQ

+

–

+

–

+

–

10µA

10µA

FAULT

10µA

0.1V

1.23V

1.23V

PULL-DOWN

RAMP

SGATE1

VCC + 4.9V

SGATE2

VCC + 4.9V

D1

D2

TRACK2

TRACK1

RAMPBUF

+

–

V

CC

+

–

+

–

V

CC

V

CC

+

0.8V

–

1x

GND

CHARGE

PUMP

0.8V

+

–

10µA

10µA

CHARGE

PUMP

10µA/30µA

FAST

PULL-DOWN

10µA/30µA

FAST

PULL-DOWN

RSGATERSGATE UP

S1

S2

SGATE2

SGATE1UP/DOWN

FB2

FB1

RAMP

2926 BD

2926fa

9