LINEAR TECHNOLOGY LTC2753 Technical data

LTC2753

Dual Current Output

12-/14-/16-Bit SoftSpan

DACs with Parallel I/O

FEATURES

■

Six Programmable Output Ranges

Unipolar: 0V to 5V, 0V to 10V

Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V

■

Maximum 16-Bit INL Error: ±1 LSB over Temperature

■

Low 1μA (Maximum) Supply Current

■

Guaranteed Monotonic over Temperature

■

Low Glitch Impulse 1nV•s

■

2.7V to 5.5V Single Supply Operation

■

2µs Settling Time to ±1 LSB

■

Parallel Interface with Readback of All Registers

■

Asynchronous CLR Pin Clears DAC Outputs to 0V in

Any Output Range

■

Power-On Reset to 0V

■

48-Pin 7mm × 7mm QFN Package

APPLICATIONS

■

High Resolution Offset and Gain Adjustment

■

Process Control and Industrial Automation

■

Automatic Test Equipment

■

Data Acquisition Systems

DESCRIPTION

The LTC®2753 is a family of dual 12-, 14-, and 16-bit
multiplying parallel-input, current-output DACs. These
DACs operate from a single 2.7V to 5.5V supply and are all
guaranteed monotonic over temperature. The LTC2753A-16
provides 16-bit performance (±1LSB INL and DNL) over
temperature without any adjustments. These SoftSpan™
DACs offer six output ranges—two unipolar and four
bipolar—that can be programmed through the parallel
interface, or pinstrapped for operation in a single range.

The LTC2753 DACs use a bidirectional input/output parallel
interface that allows readback of any on-chip register. A
power-on reset circuit resets the DAC outputs to 0V when
power is initially applied. A logic low on the CLR pin asyn­chronously clears the DACs to 0V in any output range.

The parts are specifi ed over commercial and industrial
temperature ranges.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.

TYPICAL APPLICATION

Dual 16-Bit V

V

REF

5V

+

1/2 LT1469

–

150pF

DAC with Software-Selectable Ranges

OUT

47

R

OFSA

2

R

IN

R1

1

R

COM

R2

48

39

40

3

I/O PORT

16

I/O PORT

R

SPAN I/O

DATA I/O

REFA

REFB

OFSB

DAC A

DAC B

LTC2753-16

LTC2753-16 Integral Nonlinearity (INL)

1.0

R

46

FBA

15pF

I

45

OUT1A

I

4

OUT2A

44

R

VOSA

R

43

VOSB

32

I

OUT2B

I

42

OUT1B

15pF

41

R

FBB

–

1/2 LT1469

+

+

1/2 LT1469

–

2753 TA01

V

OUTA

V

OUTB

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

VDD= 5V

= 5V

V

REF

±10V RANGE

16384

32768
CODE

49152

25°C
90°C
–45°C

65535

2753 TA01b

2753f

1

LTC2753

ABSOLUTE MAXIMUM RATINGS

I

, I

OUT1X

, R

R

VOSX

to GND .................................................. –0.3V to 7V

V

DD

OUT2X

, R

FBX

, R

to GND .................................±0.3V

COM

, RIN, REFX to GND ...................±15V

OFSX

Digital Inputs and Digital I/O

to GND ..........................–0.3V to V

+0.3V (max 7V)

DD

PIN CONFIGURATION

OFSARFBA

VOSARVOSB

FBBROFSB

OUT1A

REFA

R

48 47 46 45 44 43 42 41 40 39 38 37

R

1

COM

R

2

IN

S2

3

I

4

OUT2A

GND

5

D11

6

D10

7

D9

8

D8

9

D7

10

D6

11

D5

12

13 14 15 16 17 18 19 20 21 22 23 24

D4

D3

V

LTC2753-12 UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

T

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

JMAX

OUT1B

I

R

I

R

REFBS1WR

49

DD

A1

A0

GND

CLR

D2D1D0

MSPAN

NC

= 125°C, θJA = 29°C/W

UPD

36

READ

35

D/S

34

S0

33

I

32

OUT2B

GND

31

NC

30

NC

29

NC

28

NC

27

NC

26

NC

25

R

COM

R

IN

S2

I

OUT2A

GND

D13
D12
D11
D10

D9
D8
D7

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

REFA

48 47 46 45 44 43 42 41 40 39 38 37

1
2
3
4
5
6
7
8

9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

D6

48-LEAD (7mm × 7mm) PLASTIC QFN

T

JMAX

(Notes 1, 2)

Operating Temperature Range

LTC2753C ..................................................... 0°C to 70°C

LTC2753I .................................................. –40°C to 85°C

Maximum Junction Temperature........................... 125°C

Storage Temperature Range ................... –65°C to 150°C

OFSARFBA

VOSARVOSB

OUT1A

R

I

DD

D5

NC

V

LTC2753-14 UK PACKAGE

= 125°C, θJA = 29°C/W

FBBROFSB

OUT1B

R

I

R

49

A1

A0

CLR

GND

REFBS1WR

D4D3D2

MSPAN

OFSARFBA

VOSARVOSB

FBBROFSB

OUT1A

OUT1B

I

R

I

R

REFA

R

48 47 46 45 44 43 42 41 40 39 38 37

UPD

36

READ

35

D/S

34

S0

33

I

32

OUT2B

GND

31

NC

30

NC

29

NC

28

NC

27

D0

26

D1

25

R

1

COM

R

2

IN

S2

3

I

4

OUT2A

GND

5

D15

6

D14

7

D13

8

D12

9

D11

10

D10

11

D9

12

13 14 15 16 17 18 19 20 21 22 23 24

D8

48-LEAD (7mm × 7mm) PLASTIC QFN

T

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

JMAX

49

DD

A1

D7

NC

V

LTC2753-16 UK PACKAGE

= 125°C, θJA = 29°C/W

REFBS1WR

UPD

36

READ

35

D/S

34

S0

33

I

32

OUT2B

GND

31

NC

30

NC

29

D0

28

D1

27

D2

26

D3

25

A0

D6D5D4

CLR

GND

MSPAN

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2753CUK-12#PBF LTC2753CUK-12#TRPBF LTC2753UK-12 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2753IUK-12#PBF LTC2753IUK-12#TRPBF LTC2753UK-12 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2753CUK-14#PBF LTC2753CUK-14#TRPBF LTC2753UK-14 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2753IUK-14#PBF LTC2753IUK-14#TRPBF LTC2753UK-14 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2753BCUK-16#PBF LTC2753BCUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2753BIUK-16#PBF LTC2753BIUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
LTC2753ACUK-16#PBF LTC2753ACUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2753AIUK-16#PBF LTC2753AIUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

2753f

2

LTC2753

ELECTRICAL CHARACTERISTICS

V
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T

LTC2753-12 LTC2753-14 LTC2753B-16 LTC2753A-16

SYMBOL PARAMETER CONDITIONS

Static Performance

●

Resolution
Monotonicity

DNL Differential

INL Integral

GE Gain Error All Output

GE

BZE Bipolar Zero Error All Bipolar

BZS

PSR Power Supply

I

LKG

C

IOUT1

Nonlinearity

Nonlinearity

Gain Error Temp-

TC

erature Coeffi cient

Bipolar Zero Temp-

TC

erature Coeffi cient

Rejection
I

Current
Output

Capacitance

OUT1

Leakage

Ranges
ΔGain/ΔTemp ±0.6 ±0.6 ±0.6 ±0.6 ppm/°C

Ranges

VDD = 5V, ±10%
V

= 3V, ±10%

DD

TA = 25°C
T

to T

MIN

Full-Scale
Zero Scale

MAX

12 14 16 16 Bits

●

12 14 16 16 Bits

●

●

●

●

●

●

●

±0.5 ±2 ±1.5 ±5 ±20 ±4 ±14 LSB

±0.2 ±1 ±0.6 ±3 ±12 ±2 ±8 LSB

±0.5 ±0.5 ±0.5 ±0.5 ppm/°C

±0.05 ±2

= 5V, V

DD

±1 ±1 ±1 ±0.2 ±1 LSB

±1 ±1 ±2 ±0.4 ±1 LSB

±0.025

±0.06

±5

75
45

= 5V unless otherwise specifi ed. The ● denotes the

REF

±0.1

±0.25

±0.05 ±2

±5

75
45

±0.05 ±2

75
45

= 25°C.

A

±0.4

±1

±5

±0.03

±0.1

±0.05 ±2

75
45

±0.2
±0.5

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

LSB/V

nA

±5

pF
pF

VDD = 5V, V

= 5V unless otherwise specifi ed. The ● denotes specifi cations that apply over the full operating temperature range,

REF

otherwise specifi cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resistances (Note 3)

●

R1, R2 Reference Inverting Resistors (Note 4)
R

REF

R

FB

R

OFS

R

VOS

Dynamic Performance

THD Total Harmonic Distortion (Note 8) Multiplying –110 dB

DAC Input Resistance
Feedback Resistor (Note 3)
Bipolar Offset Resistor (Note 3)
Offset Adjust Resistor

Output Settling Time 0V to 10V Range, 10V Step. To ±0.0015% FS

Glitch Impulse (Note 6) 1 nV•s
Digital-to-Analog Glitch Impulse (Note 7) 1 nV•s
Multiplying Feedthrough Error 0V to 10V Range, V

Output Noise Voltage Density (Note 9) at I

(Note 5)

Sine Wave

OUT1

= ±10V, 10kHz

REF

16 20 k

●

810 k

●

810 k

●

16 20 k

●

800 1000 k

2s

0.5 mV

13 nV/√⎯H⎯z

2753f

3

LTC2753

ELECTRICAL CHARACTERISTICS

V
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

V

DD

I

DD

Digital Inputs

V

IH

V

IL

I

IN

C

IN

Digital Outputs

V

OH

V

OL

Supply Voltage
Supply Current, VDD Digital Inputs = 0V or V

Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V

2.7V ≤ V

Digital Input Low Voltage 4.5V < VDD ≤ 5.5V

2.7V ≤ V
Digital Input Current VIN = GND to V
Digital Input Capacitance VIN = 0V (Note 10)

IOH = 200µA
IOL = 200µA

= 5V, V

DD

< 3.3V

DD

≤ 4.5V

DD

= 5V unless otherwise specifi ed. The ● denotes the

DD

REF

DD

●

●

●

●

●

●

●

●

●

●

= 25°C.

A

2.7 5.5 V

2.4
2

VDD – 0.4 V

0.5 1 A

0.8

0.6
±1 µA

6pF

0.4 V

V
V

V
V

TIMING CHARACTERISTICS

The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

= 4.5V to 5.5V

V

DD

Write and Update Timing

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

I/O Valid to WR Rising Edge Set-Up
I/O Valid to WR Rising Edge Hold
WR Pulse Width Low
UPD Pulse Width High
UPD Falling Edge to WR Falling Edge No Data Shoot-Through

WR Rising Edge to UPD Rising Edge (Note 10)
D/S Valid to WR Falling Edge Set-Up Time
WR Rising Edge to D/S Valid Hold Time
A1-A0 Valid to WR Falling Edge Setup Time
WR Rising Edge to A1-A0 Valid Hold Time

A1-A0 Valid to UPD Rising Edge Setup Time
UPD Falling Edge to A1-A0 Valid Hold Time

Readback Timing

t

13

t

14

t

15

t

26

t

27

WR Rising Edge to READ Rising Edge
READ Falling Edge to WR Falling Edge (Note 10)
READ Rising Edge to I/O Propagation Delay CL = 10pF
A1-A0 Valid to READ Rising Edge Setup Time
READ Falling to A1-A0 Valid Hold Time (Note 10)

●

7ns

●

7ns

●

15 ns

●

15 ns

●

0ns

●

0ns

●

7ns

●

7ns

●

5ns

●

0ns

●

9ns

●

7ns

●

7ns

●

20 ns

●

●

20 ns

●

0ns

40 ns

4

2753f

LTC2753

TIMING CHARACTERISTICS

The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t

17

t

18

t

19

t

20

t

22

t

23

t

24

CLR Timing

t

25

= 2.7V to 3.3V

V

DD

Write and Update Timing

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

Readback Timing

t

13

t

14

t

15

t

26

t

27

t

17

t

18

t

19

t

20

UPD Valid to I/O Propagation Delay CL = 10pF
D/S Valid to READ Rising Edge (Note 10)
READ Rising Edge to UPD Rising Edge No Update
UPD Falling Edge to READ Falling Edge No Update
READ Falling Edge to UPD Rising Edge (Note 10)
I/O Bus Hi-Z to READ Rising Edge (Note 10)
READ Falling Edge to I/O Bus Active (Note 10)

CLR Pulse Width Low

I/O Valid to WR Rising Edge Set-Up
I/O Valid to WR Rising Edge Hold
WR Pulse Width Low
UPD Pulse Width High
UPD Falling Edge to WR Falling Edge No Data Shoot-Through

WR Rising Edge to UPD Rising Edge (Note 10)
D/S Valid to WR Falling Edge Set-Up Time
WR Rising Edge to D/S Valid Hold Time
A1-A0 Valid to WR Falling Edge Setup Time
WR Rising Edge to A1-A0 Valid Hold Time

A1-A0 Valid to UPD Rising Edge Setup Time
UPD Falling Edge to A1-A0 Valid Hold Time

WR Rising Edge to Read Rising Edge
Read Falling Edge to WR Falling Edge (Note 10)
Read Rising Edge to I/O Propagation Delay CL = 10pF
A1-A0 Valid to READ Rising Edge Setup Time
READ Falling to A1-A0 Valid Hold Time (Note 10)
UPD Valid to I/O Propagation Delay CL = 10pF
D/S Valid to Read Rising Edge (Note 10)
Read Rising Edge to UPD Rising Edge No Update
UPD Falling Edge to Read Falling Edge No Update

= 25°C.

A

●

●

7ns

●

0ns

●

0ns

●

7ns

●

0ns

●

20 ns

●

15 ns

●

15 ns

●

15 ns

●

30 ns

●

30 ns

●

0ns

●

0ns

●

7ns

●

7ns

●

7ns

●

0ns

●

15 ns

●

15 ns

●

10 ns

●

35 ns

●

●

35 ns

●

0ns

●

●

12 ns

●

0ns

●

0ns

26 ns

53 ns

43 ns

2753f

5

LTC2753

The ● denotes specifi cations that apply over the full operating temperature range,

TIMING CHARACTERISTICS

otherwise specifi cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

= 2.7V to 3.3V

V

DD

t

22

t

23

t

24

CLR Timing
t

25

READ Falling Edge to UPD Rising Edge (Note 10)
I/O Bus Hi-Z to Read Rising Edge (Note 10)
Read Falling Edge to I/O Bus Active (Note 10)

CLR Pulse Width Low

●

10 ns

●

0ns

●

35 ns

●

20 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.

Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specifi ed pins is constant for
all output ranges if the I

Note 4: R1 is measured from R
R

.

COM

Note 5: Using LT1469 with C
of 1.7s can be achieved by optimizing the time constant on an individual

OUT1X

and I

IN

FEEDBACK

pins are held at ground.

OUT2X

to R

; R2 is measured from REFA to

COM

= 15pF. A ±0.0015% settling time

basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.

Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifi er: LT1469; C

Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6V

amplifi er = LT1469.
Note 9. Calculation from V

(Boltzmann constant), R = resistance (), T = temperature (°K), and B =
bandwidth (Hz).

Note 10. Guaranteed by design. Not production tested.

= 27pF.

FB

at 1kHz. 0V to 5V range. DAC code = FS. Output

RMS

= √⎯4⎯k⎯T⎯R

n

⎯⎯⎯

B, where k = 1.38E-23 J/°K

6

2753f

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2753-16

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

1.0

VDD= 5V

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

V

REF

±10V RANGE

0

16384

32768
CODE

49152

65535

2753 G01

DNL vs Temperature Bipolar Zero vs Temperature

1.0
VDD= 5V

0.8

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

V

REF

±10V RANGE

–40

= 5V

–20200

TEMPERATURE (°C)

+DNL

–DNL

40

80

60

2753 G05

1.0

VDD= 5V

0.8

V
±10V RANGE

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

8

VDD= 5V
V

6

±10V RANGE

4

2

0

BZE (LSB)

2

4

6

8

–40

= 5V

REF

REF

–20200

16384

= 5V

0.5ppm/°C (TYP)

TEMPERATURE (°C)

32768
CODE

49152

40

= 25°C, unless otherwise noted.

T

A

INL vs Temperature

1.0
VDD= 5V

65535

2753 G02

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

V

REF

±10V RANGE

–40

= 5V

–20200

Gain Error vs Temperature

16

VDD= 5V

= 5V

V

REF

12

±10V RANGE

8

4

0

GE (LSB)

–4

–8

–12

–16

–40

80

60

2753 G06

–20200

+INL

–INL

TEMPERATURE (°C)

0.6ppm/°C (TYP)

TEMPERATURE (°C)

40

40

80

60

2753 G04

80

60

2753 G07

INL vs V

1.0

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–10 –8

VDD= 5V
±5V RANGE

+INL

–INL

REF

DNL vs V

1.0
VDD= 5V

0.8

±5V RANGE

0.6

+INL

–INL

0

44–6

2

2

V

(V)

REF

10

6

8

2753 G08

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–10 –8

+DNL

–DNL

REF

44–6

+DNL

–DNL

0

2

2

V

(V)

REF

10

6

8

2751 G09

2753f

7

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2753-16

INL vs V

1.0

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

2.5

LTC2753-14

LTC2753-12

DD

343.5

+INL

–INL

VDD (V)

4.5

5

WAVEFORM

250µV/DIV

5.5

2751 G09b

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

1.0

VDD= 5V

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

V

REF

±10V RANGE

0

4096

8192

CODE

Settling 0V to 10V

UPD

5V/DIV

GATED

SETTLING

USING LT1469 AMP
C

FEEDBACK

0V TO 10V STEP

12288

16383

2753 G11

= 12pF

500ns/DIV

1.0

VDD= 5V

0.8

V
±10V RANGE

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

TA = 25°C, unless otherwise noted.

Multiplying Frequency Response
vs Digital Code

ALL BITS ON

0

D15
D14

D13

–20

D12
D11
D10

–40

D9
D8
D7

–60

D6
D5
D4
D3

–80

ATTENUATION (dB)

D2
D1

–100

–120

8192

CODE

D0

ALL BITS OFF

1k 10k 100k 1M

100

12288

2753 G12

REF

2753 G10

= 5V

4096

UNIPOLAR 5V OUTPUT RANGE
LT1469 OUTPUT AMPLIFIER
C

= 15pF

FEEDBACK

FREQUENCY (Hz)

16383

10M

2753 G10a

8

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

1.0

0.8

0.6

0.4

0.2

0.0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

VDD= 5V

= 5V

V

REF

±10V RANGE

1024

2048

CODE

3072

4095

2753 G13

1.0

0.8

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0

VDD= 5V

= 5V

V

REF

±10V RANGE

1024

2048

CODE

3072

4095

2753 G14

2753f

LTC2753

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2753-12, LTC2753-14, LTC2753-16

Midscale Glitch

20

SUPPLY CURRENT (mA)

15

10

5

0

10

UPD

5V/DIV

V

OUT

2mV/DIV

V

DD

V

REF

0V TO 5V RANGE

Logic Threshold
vs Supply Voltage

2

= 5V

= 5V

1nV•S (TYP)

500ns/DIV

USING AN LT1469
C

FEEDBACK

= 27pF

2753 G15

T

= 25°C, unless otherwise noted.

A

Supply Current vs
Logic Input Voltage

VDD = 5V

VDD = 3V

01

2345

DIGITAL INPUT VOLTAGE (V)

Supply Current
vs Update Frequency

2753 G16

1.75

1.5

1.25

1

LOGIC THRESHOLD (V)

0.75

0.5

2.5

3

RISING

FALLING

3.5 4 4.5
VDD (V)

5 5.5

2753 G17

1

0.1

0.01

SUPPLY CURRENT (mA)

0.001

0.0001

VDD = 5V

100

10

UPDATE FREQUENCY (Hz)

VDD = 3V

10k

100k

1k

1M

2753 G18

2753f

9

LTC2753

PIN FUNCTIONS

R

(Pin 1): Center Tap Point for the Reference Inverting

COM

Resistors. The 20k reference inverting resistors R1 and R2
are connected internally from R

IN

to R

and from R

COM

COM

to REFA, respectively (see Block Diagram). For normal
operation tie R

to the negative input of the external

COM

reference inverting amplifi er (see Typical Applications).

(Pin 2): Input Resistor R1 of the Reference Inverting

R

IN

Resistors. The 20k resistor R1 is connected internally from

to R

R

IN

reference voltage V

. For normal operation tie RIN to the external

COM

. Typically 5V; accepts up to ±15V.

REF

S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used
to program and to read back the output ranges of the
DACs.

(Pin 4): DAC A Current Output Complement. Tie

I

OUT2A

to ground.

I

OUT2A

GND (Pin 5): Shield Ground, provides necessary shielding
for I

. Tie to ground.

OUT2A

D3-D11 (Pins 6-14): LTC2753-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D11 is the MSB.

D5-D13 (Pins 6-14): LTC2753-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D13 is the MSB.

D7-D15 (Pins 6-14): LTC2753-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D15 is the MSB.

output range. When confi gured for single-span operation,
the output range is set via hardware pin strapping. The
input and DAC registers of the span I/O port are transparent
and do not respond to write or update commands.

To confi gure the part for single-span use, tie MSPAN directly
to V

. If MSPAN is instead connected to GND (SoftSpan

DD

confi guration), the output ranges are set and verifi ed by
using write, update and read operations. See Manual Span
Confi guration in the Operation section. MSPAN must be
connected either directly to GND (SoftSpan confi guration)
or V

(single-span confi guration).

DD

D0-D2 (Pins 22-24): LTC2753-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.

D0-D4 (Pins 22-26): LTC2753-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.

D0-D6 (Pins 22-28): LTC2753-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.

NC (Pins 25-30): LTC2753-12 Only. No Internal Connection.
NC (Pins 27-30): LTC2753-14 Only. No Internal Connection.
NC (Pins 29, 30): LTC2753-16 Only. No Internal Con-

nection.
GND (Pin 31): Shield Ground, provides necessary shielding

for I

. Tie to ground.

OUT2B

(Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.

V

DD

Requires a 0.1µF bypass capacitor to GND.

NC (Pin 16): No Internal Connection.
A1 (Pin 17): DAC Address Bit 1. See Table 3.
A0 (Pin 18): DAC Address Bit 0. See Table 3.
GND (Pin 19): Ground. Tie to ground.

CLR (Pin 20): Asynchronous Clear. When CLR is taken
to a logic low, the data registers are reset to the zero-volt
code for the present output range (V

OUT

= 0V).

MSPAN (Pin 21): Manual Span Control Pin. MSPAN is used
to confi gure the LTC2753 for operation in a single, fi xed

10

I

(Pin 32): DAC B Current Output Complement. Tie

OUT2B

I

OUT2B

to ground.

S0 (Pin 33): Span I/O Bit 0. Pins S0, S1 and S2 are used to
program and to read back the output range of the DACs.

D/S (Pin 34): Data/Span Select. This pin is used to select
the data I/O pins or the span I/O pins (D0 to D15 or S0
to S2, respectively), along with their respective dedicated
registers, for write or read operations. Update operations
ignore D/S, since all updates affect both data and span
registers. For single-span operation, tie D/S to ground.

READ (Pin 35): Read Pin. When READ is asserted high,
the data I/O pins (D0-D15) or span I/O pins (S0-S2)

2753f

PIN FUNCTIONS

LTC2753

output the contents of the selected register (see Table

1). For single-span operation, readback of the span I/O
pins is disabled.

UPD (Pin 36): Update and Buffer Select Pin. When READ
is held low and UPD is asserted high, the contents of the
addressed DAC’s input registers (both data and span) are
copied into their respective DAC registers. The output of the
DAC is updated, refl ecting the new DAC register values.

When READ is held high, the update function is disabled
and the UPD pin functions as a buffer selector—logic low
to select the input register, high to select the DAC register.
See Readback in the Operation section.

WR (Pin 37): Active Low Write Pin. A Write operation cop-
ies the data present on the data or span I/O pins (D0-D15
or S0-S2, respectively) into the associated input register.
When READ is high, the Write function is disabled.

S1 (Pin 38): Span I/O Bit 1. Pins S0, S1 and S2 are used
to program and to read back the output ranges of the
DACs.

REFB (Pin 39): Reference Input for DAC B. The impedance
looking into this pin is 10k to ground. For normal opera­tion tie to the output of the reference inverting amplifi er.
Typically –5V; accepts up to ±15V.

R

(Pin 40): Bipolar Offset Network for DAC B. This

OFSB

pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RIN (Pin 2). The
impedance looking into this pin is 20k to ground.

R

(Pin 41): DAC B Feedback Resistor. For normal

FBB

operation tie to the output of the I/V converter amplifi er
for DAC B (see Typical Applications). The DAC output
current from I
to the R

pin. The impedance looking into this pin is

FBB

fl ows through the feedback resistor

OUT1B

10k to ground.

0V. For normal operation tie to the negative input of the I/V
converter amplifi er for DAC B (see Typical Applications).

(Pin 43): DAC B Offset Adjust. Nominal input range

R

VOSB

is ±5V. The impedance looking into this pin is 1M to ground.
If not used, tie R

R

(Pin 44): DAC A Offset Adjust. Nominal input range

VOSA

to ground.

VOSB

is ±5V. The impedance looking into this pin is 1M to ground.
If not used, tie R

I

(Pin 45): DAC A Current Output. This pin is a virtual

OUT1A

to ground.

VOSA

ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifi er for DAC A (see Typical Applications).

R

(Pin 46): DAC A Feedback Resistor. For normal

FBA

operation tie to the output of the I/V converter amplifi er
for DAC A (see Typical Applications). The DAC output
current from I

fl ows through the feedback resistor

OUT1A

to the RFBA pin. The impedance looking into this pin is
10k to ground.

R

(Pin 47): Bipolar Offset Network for DAC A. This

OFSA

pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at R

(Pin 2). The

IN

impedance looking into this pin is 20k to ground.
REFA (Pin 48): Reference Input for DAC A, and connec-

tion for internal reference inverting resistor R2. The 20k
resistor R2 is connected internally from R

to REFA. For

COM

normal operation tie this pin to the output of the reference
inverting amplifi er (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (R

and R

IN

fl oating).

COM

Exposed Pad (Pin 49): Ground. The Exposed Pad must
be soldered to the PCB.

I

(Pin 42): DAC B Current Output. This pin is a virtual

OUT1B

ground when the DAC is operating and should reside at

2753f

11

LTC2753

BLOCK DIAGRAM

DATA I /O

6-14, 22-28

SPAN I /O

DAC

ADDRESS

3, 38, 33

R

IN

2 1 48 47 46

16

I/O

PORT

I/O

3

PORT

17

A1

18

A0

DATA INPUT

REGISTER

SPAN INPUT

REGISTER

DATA INPUT

REGISTER

SPAN INPUT

REGISTER

CONTROL LOGIC

16

3

16

3

R

COM

R1 R2

DATA DAC
REGISTER

SPAN DAC
REGISTER

DATA DAC
REGISTER

SPAN DAC
REGISTER

REFA R

16

16-BIT WITH

SPAN SELECT

3

16

16-BIT WITH

SPAN SELECT

3

3935 37 36 34 20 21 40 41

REFBMSPANREAD WR UPD D/S CLR

OFSARFBA

DAC A

DAC B

R

OFSB

45

I

OUT1A

4

I

OUT2A

44

R

VOSA

R

VOSB

43
42

I

OUT1B

32

I

OUT2B

2753 BD

R

FBB

12

2753f

TIMING DIAGRAMS

WR

Write, Update and Clear Timing

t

3

t

1

t

2

LTC2753

DATA/SPAN I/O

INPUT

UPD

D/S

ADDRESS

A1 - A0

CLR

READ

WR

VALID

t

t

5

t

7

VALID

t

9

VALID

t

6

t

4

t

8

10

t

11

VALID

t

25

t

12

2753 TD01

Readback Timing

t

13

t

14

DATA/SPAN I/O

INPUT

DATA/SPAN I/O

OUTPUT

ADDRESS

A1-A0

UPD

D/S

t

23

t

15

VALID

t

26

VALID

t

19

t

18

VALID

t

17

VALID

t

20

t

24

t

27

t

22

2753 TD02

2753f

13

LTC2753

OPERATION

Output Ranges

The LTC2753 is a dual current-output, parallel-input preci­sion multiplying DAC with software-programmable output
ranges. SoftSpan provides two unipolar output ranges
(0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V,
±5V, ±10V and –2.5V to 7.5V). These ranges are obtained
when an external precision 5V reference is used. When
a reference voltage of 2V is used, the SoftSpan ranges
become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to 3V.
The output ranges are linearly scaled for references other
than 2V and 5V.

Digital Section

The LTC2753 has 4 internal registers for each DAC, a total
of 8 registers (see Block Diagram). Each DAC channel has
two sets of double-buffered registers—one set for the data,
and one set for the span (output range) of the DAC. The
double-buffered feature provides the capability to simulta­neously update the span and code, which allows smooth
voltage transitions when changing output ranges. It also
permits the simultaneous updating of multiple DACs.

Each set of double-buffered registers comprises an input
register and a DAC register. The input registers are holding
buffers—when data is loaded into an input register via a
write operation, the DAC outputs are not affected.

The contents of a DAC register, on the other hand, di­rectly control the DAC output voltage or output range.
The contents of the DAC registers are changed by copying
the contents of an input register into its associated DAC
register via an update operation.

Write and Update Operations

The data input register of the addressed DAC is loaded
directly from a 16-bit microprocessor bus by holding the
D/S pin low and pulsing the WR pin low (write operation).
The DAC register is loaded by pulsing the UPD pin high
(update operation), which copies the data held in the input
register into the DAC register. Note that updates always
include both data and span; but the DAC register values
will not change unless the input register values have previ­ously been changed via a write operation.

Loading the span input register is accomplished similarly,
holding the D/S pin high and bringing the WR pin low. The
span and data register structures are the same except for
the number of parallel bits—the span registers have 3 bits,
while the data registers have 12, 14, or 16.

To make both registers transparent for fl owthrough
mode, tie WR low and UPD high. However, this defeats
the deglitcher operation and output glitch impulse may
increase. The deglitcher is activated on the rising edge
of the UPD pin.

The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, confi gura­tion. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.

It is possible to control both data and span on one 16-bit
wide data bus by allowing span pins S2 to S0 to share
bus lines with the data LSBs (D2 to D0). No write or read
operation includes both span and data, so there cannot
be a confl ict.

The asynchronous clear pin resets both DACs to 0V in any
output range. CLR resets all data registers, while leaving
the span registers undisturbed.

V

DD

V

DD

MSPAN
S2
S1
S0

D/S

WR UPD READ A1 A0

Figure 1. Using MSPAN to Confi gure the LTC2753 for Single-Span

Operation (±10V Range).

LTC2753-16

DAC A

DAC B

2753 F01

16

DATA I/O

14

2753f

OPERATION

LTC2753

These devices also have a power-on reset that initializes
both DACs to V

= 0V in any output range. The DACs

OUT

power up in the 0V-5V range if the part is in SoftSpan
confi guration; for manual span (see Manual Span Confi gu­ration below), both DACs power up in the manually-chosen
range at the appropriate code.

Manual Span Confi guration

Multiple output ranges are not needed in some applications.
To confi gure the LTC2753 for single-span operation, tie the
MSPAN pin to V

and the D/S pin to GND. The desired

DD

output range is then specifi ed by the span I/O pins (S0,
S1 and S2) as usual, but the pins are programmed by ty­ing directly to GND or V

(see Figure 1 and Table 2). In

DD

this confi guration, both DAC channels will initialize to the
chosen output range at power-up, with V

OUT

= 0V.

When confi gured for manual span operation, span pin
readback is disabled.

Readback

The contents of any one of the 8 interface registers can
be read back from the I/O ports.

The I/O pins are grouped into two ports: data and span. The
data I/O port comprises pins D0-D11, D0-D13 or D0-D15
(LTC2753-12, LTC2753-14 or LTC2753-16, respectively).
The span I/O port comprises pins S0, S1 and S2 for all
parts.

the D/S pin. The selected I/O port’s pins become logic
outputs during readback, while the unselected I/O port’s
pins remain high-impedance inputs.

With the DAC channel and I/O port selected, assert READ
high and select the desired input or DAC register using the
UPD pin. Note that UPD is a two function pin—the update
function is only available when READ is low. When READ
is high, the update function is disabled and the UPD pin
instead selects the input or DAC register for readback.
Table 1 shows the readback functions for the LTC2753.

Table 1. Write, Update and Read Functions

READ D/S WR UPD SPAN I/O DATA I/O

0 0 0 0 - Write to Input Register
0 0 0 1 - Write/Update

00 10 - ­0 0 1 1 Update DAC Register Update DAC Register
0 1 0 0 Write to Input Register ­0 1 0 1 Write/Update

(Transparent)
01 10 - ­0 1 1 1 Update DAC register Update DAC Register
1 0 X 0 - Read Input Register
1 0 X 1 - Read DAC Register
1 1 X 0 Read Input Register ­1 1 X 1 Read DAC Register -

X = Don’t Care

(Transparent)

-

Each DAC channel has a set of data registers that are
controlled and read back from the data I/O port; and a set
of span registers that are controlled and read back from
the span I/O port. The register structure is shown in the
Block Diagram.

A readback operation is initiated by asserting READ to
logic high after selecting the desired DAC channel and I/O
port. The I/O pins, which are high-impedance digital inputs
when READ is low, selectively change to low-impedance
logic outputs during readback.

Select the DAC channel with address pins A1 and A0, and
select the I/O port (data or span) to be read back with

The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, hold UPD low
and assert READ high. The contents of the selected port’s
input register are output to its I/O pins.

To read back the contents of a DAC register, hold UPD low
and assert READ high, then bring UPD high to select the
DAC register. The contents of the selected DAC register are
output by the selected port’s I/O pins. Note: if no update is
desired after the readback operation, UPD must be returned
low before bringing READ low; otherwise the UPD pin will
revert to its primary function and update the DAC.

2753f

15

LTC2753

OPERATION

System Offset Adjustment

Many systems require compensation for overall system
offset. The R

VOSA

and R

offset adjustment pins are

VOSB

provided for this purpose. For noise immunity and ease
of adjustment, the control voltage is attenuated to the
DAC output:

= –0.01 • V(R

V

OS

= –0.02 • V(R

V

OS

) [0V to 5V, ±2.5V spans]

VOSX

) [0V to 10V, ±5V, –2.5V to 7.5V

VOSX

spans]

= –0.04 • V(R

V

OS

) [±10V span]

VOSX

The nominal input range of this pin is ±5V; other reference
voltages of up to 15V may be used if needed. The R

VOSX

pins have an input impedance of 1M. To preserve the
settling performance of the LTC2753, drive this pin with a
Thevenin-equivalent impedance of 10k or less. Short any
unused system offset adjustment pins to I

OUT2

.

Table 2. Span Codes

S2 S1 S0 SPAN

0 0 0 Unipolar 0V to 5V
0 0 1 Unipolar 0V to 10V
0 1 0 Bipolar –5V to 5V
0 1 1 Bipolar –10V to 10V
1 0 0 Bipolar –2.5V to 2.5V
1 0 1 Bipolar –2.5V to 7.5V

Codes not shown are reserved and should not be used.

Table 3. Address Codes

DAC CHANNEL A1 A0

A00
B01

ALL* 1 1

Codes not shown are reserved and should not be used.
*If readback is taken using the All DACs address, the LTC2753 defaults to

DAC A.

16

2753f

LTC2753

OPERATION— EXAMPLES

1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at
0V, will stay there. The 16-Bit DAC code is shown in hex for compactness.

WR

SPAN I/O

INPUT

DATA I/O

INPUT

UPD

D/S

READ = LOW

010

2. Load ±10V range with the output at 5V, changing to –5V.

WR

SPAN I/O

INPUT

DATA I/O

INPUT

UPD

C000

H

011

8000

H

UPDATE (5V)

UPDATE
(±5V RANGE, V

4000

UPDATE (–5V)

H

OUT

= 0V)

2753 TD03

D/S

READ = LOW

3. Write and update midscale code in 0V to 5V range (V

OUT

and DAC registers before updating.

WR

DATA I/O

INPUT

DATA I/O

OUTPUT

UPD

READ

8000

HI-Z

D/S

HI-Z

H

8000

H

INPUT REGISTER DAC REGISTER

2753 TD04

= 2.5V) using readback to check the contents of the input

0000

H

UPDATE (2.5V)

2753 TD05

2753f

17

LTC2753

APPLICATIONS INFORMATION

Op Amp Selection

Because of the extremely high accuracy of the 16-bit
LTC2753-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.

Tables 4 and 5 contain equations for evaluating the effects
of op amp parameters on the LTC2753’s accuracy when

Table 4. Variables for Each Output Range That Adjust the
Equations in Table 5

OUTPUT RANGE A1 A2 A3 A4 A5

5V 1.1 2 1 1
10V 2.2 3 0.5 1.5
±5V 22111.5

±10V 4 4 0.83 1 2.5

±2.5V 1 1 1.4 1 1

–2.5V to 7.5V 1.9 3 0.7 0.5 1.5

programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipolar
gain error. Tables 4 and 5 can also be used to determine
the effects of op amp parameters on the LTC2753-14
and the LTC2753-12. However, the results obtained from
Tables 4 and 5 are in 16-bit LSBs. Divide these results
by 4 (LTC2753-14) and 16 (LTC2753-12) to obtain the
correct LSB sizing.

Table 6 contains a partial list of LTC precision op amps
recommended for use with the LTC2753. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specifi ed error budget. Select the amplifi er
from Table 6 and insert the specifi ed op amp parameters
in Table 5. Add up all the errors for each category to de­termine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.

Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.

OP AMP

V

OS1

I

B1

A

VOL1

V

OS2

I

B2

A

VOL2

(mV)

(nA)

(V/V)

(mV)

(mV)

(V/V)

INL (LSB)

V

OS1

I

• 0.0003 •

B1

A1 •

0

0

DNL (LSB)

• 3.2 •

5V

V

()

V

REF

5V

()

V

REF

16.5k
0

()

A

VOL1

0

• 0.82 •

OS1

I

• 0.00008 •

B1

A2 •

0

0

0

5V

()

V

REF

5V

()

V

REF

1.5k
0

()

A

VOL1

UNIPOLAR

OFFSET (LSB)

A3 • V

OS1

I

• 0.13 •

B1

0

0

0

• 13.2 •

5V

()

V

REF

5V

()

V

REF

BIPOLAR ZERO

ERROR (LSB)

A3 • V

A4 • V

A4 • I

• 19.8 •

OS1

I

• 0.13 •

B1

()

()

()

V

• 13.1 •

OS2

• 0.13 •

B2

66k

A4 •

()

A

VOL2

UNIPOLAR GAIN

ERROR (LSB)

5V

V

I

• 13.2 •

OS1

• 0.0018 •

B1

A5 •

V

• 26.2 •

OS2

I

• 0.26 •

B2

()

V

REF

5V

REF

5V

()

V

REF

5V

()

V

REF

()

5V

()

V

REF

5V

()

V

REF

131k

()

A

VOL1

5V

()

V

REF

5V

()

V

REF

131k

A

VOL2

I

V

OS1

B1

V

OS2

I

B2

BIPOLAR GAIN

ERROR (LSB)

• 13.2 •

• 0.0018 •

A5 •

• 26.2 •

• 0.26 •

()

5V

()

V

REF

5V

()

V

REF

131k

()

A

VOL1

5V

()

V

REF

5V

()

V

REF

131k

A

VOL2

Table 6. Partial List of LTC Precision Amplifi ers Recommended for Use with the LTC2753 with Relevant Specifi cations

AMPLIFIER SPECIFICATIONS

V

AMPLIFIER

LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp

OS

μV

nA

I

B

A

VOL

V/mV

VOLTAGE

NOISE

nV/√⎯H⎯z

CURRENT

NOISE

pA/√⎯H⎯z

SLEW

RATE
V/μs

GAIN BANDWIDTH

PRODUCT

MHz

t

SETTLING

with LTC2753

μs

POWER

DISSIPATION

mW

2753f

18

APPLICATIONS INFORMATION

LTC2753

Op amp offset will contribute mostly to output offset and
gain error, and has minimal effect on INL and DNL. For
example, for the LTC2753-16 with a 5V reference in 5V
unipolar mode, a 250µV op amp offset will cause a 3.3LSB
zero-scale error and a 3.3LSB gain error; but only 0.8LSB
of INL degradation and 0.2LSB of DNL degradation.

While not directly addressed by the simple equations in
Tables 4 and 5, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to fi nd the worst-case V
over temperature. Then, plug these numbers in the V
and I

equations from Table 5 and calculate the tempera-

B

OS

and IB

OS

ture-induced effects.
For applications where fast settling time is important, Ap-

plication Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time, offers a thorough discus­sion of 16-bit DAC settling time and op amp selection.

Precision Voltage Reference Considerations

Much in the same way selecting an operational amplifi er
for use with the LTC2753 is critical to the performance of
the system, selecting a precision voltage reference also
requires due diligence. The output voltage of the LTC2753
is directly affected by the voltage reference; thus, any
voltage reference error will appear as a DAC output volt­age error.

There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit appli­cations: output voltage initial tolerance, output voltage
temperature coeffi cient and output voltage noise.

Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.

A reference’s output voltage temperature coeffi cient af­fects not only the full-scale error, but can also affect the
circuit’s apparent INL and DNL performance. If a refer­ence is chosen with a loose output voltage temperature
coeffi cient, then the DAC output voltage along its transfer
characteristic will be very dependent on ambient conditions.
Minimizing the error due to reference temperature coef­fi cient can be achieved by choosing a precision reference
with a low output voltage temperature coeffi cient and/or
tightly controlling the ambient temperature of the circuit
to minimize temperature gradients.

As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may con­tribute a dominant share of the system’s noise fl oor. This
in turn can degrade system dynamic range and signal-to­noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practi­cal for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, fi ltering the output of the reference
may be required to minimize output noise.

Table 7. Partial List of LTC Precision References Recommended
for Use with the LTC2753 with Relevant Specifi cations

REFERENCE

LT1019A-5,
LT1019A-10

LT1236A-5,
LT1236A-10

LT1460A-5,
LT1460A-10

LT1790A-2.5 ±0.05% 10ppm/°C 12µV

INITIAL

TOLERANCE

±0.05% 5ppm/°C 12µV

±0.05% 5ppm/°C 3µV

±0.075% 10ppm/°C 20µV

TEMPERATURE

DRIFT

0.1Hz to 10Hz
NOISE

P-P

P-P

P-P

P-P

2753f

19

LTC2753

APPLICATIONS INFORMATION

Grounding

As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. I
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to

, a low resistance trace should be used to route this

I

OUT2

must be tied

OUT2

pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code dependent current
fl owing to ground. When the resistance of this circuit
board trace becomes greater than 1, a force/sense am­plifi er confi guration should be used to drive this pin (see
Figure 2). This preserves the excellent accuracy (1LSB
INL and DNL) of the LTC2753-16.

20

2753f

APPLICATIONS INFORMATION

ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE

4,32

I

OUT2

ZETEX

BAT54S

1

23

6

LT1468

200

–

2

3

+

200Ω

1000pF

I

OUT2

6

1

23

LT1001

ZETEX*
BAT54S

LTC2753

–

2

3

+

V

REF

5V

1

1/2 LT1469

3

+

–

2

150pF

R

R

OFSA

R

COM

REFA

47

2

IN

1

48

Figure 2. Optional Circuits for Driving I

*SCHOTTKY BARRIER DIODE

LTC2753-16

DAC A

from GND with a Force/Sense Amplifi er.

OUT2

R

46

FBA

15pF

45

I

OUT1A

I

4

OUT2A

R

44

VOSA

2753 F02

2

3

–

1/2 LT1469

+

1

V

OUTA

2753f

21

LTC2753

TYPICAL APPLICATIONS

Dual 16-Bit V

V

REF

5V

+

1

1/2 LT1469

–

3

2

150pF

C1*

DATA I/O
D15 - D0

SPAN I/O

S2 - S0

R

R

R

OFSA

R

COM

REFA

REFB

OFSB

DAC with Software-Selectable Ranges

OUT

DAC A

DAC B

MSPAN

LTC2753-16

A1, A0

ADDRESS

47

2

IN

R1

1

R2

48

39

40

16

3

WR UPD READ D/S CLR

37 36 35 34 20 21 17, 18

WR UPD READ D/S CLR

I/O PORT

I/O PORT

R

46

FBA

15pF

C2

45

I

OUT1A

I

4

OUT2A

R

44

VOSA

R

43

VOSB

I

32

OUT2B

42

I

OUT1B

C3

R

41

FBB

15pF

–

2

1/2 LT1469

+

3

+

5

1/2 LT1469

–

6

1

7

2753 F03

V

V

OUTA

OUTB

*FOR MULTIPLYING APPLICATIONS C1 = 15pF

22

2753f

PACKAGE DESCRIPTION

LTC2753

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

0.70 ±0.05

5.15 ± 0.05

5.15 ± 0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

7.00 ± 0.10
(4 SIDES)

PIN 1 TOP MARK
(SEE NOTE 6)

5.50 REF

(4 SIDES)

6.10 ±0.05 7.50 ± 0.05

PACKAGE OUTLINE

0.75 ± 0.05
R = 0.10

TYP

5.50 REF

(4-SIDES)

R = 0.115

TYP

5.15 ± 0.10

PIN 1

CHAMFER

C = 0.35

4847

0.40 ± 0.10

1

2

0.200 REF

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa­tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.00 – 0.05

5.15 ± 0.10

(UK48) QFN 0406 REV C

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

2753f

23

LTC2753

TYPICAL APPLICATION

Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply

+

C20

10µF

V

IN OUT

U3

22

LT1027

GND

4

TRIM

6

R2

5

10k

1

GAIN
TRIM

DATA I/O

SPAN I/O

C13
10µF

C23

0.1µF

15 47 40 2 1 48 39

6

D15

7

D14

8

D13

9

D12

10

D11

11

D10

12

D9

13

D8

14

D7

22

D6

23

D5

24

D4

25

D3

26

D2

27

D1

28

D0

3

S2

38

S1

33

S0

R

V

OFSA

DD

34 35 36 37 20 21

R

R

OFSB

WRUPDREADD/S CLR MSPAN

WRUPDREADD/S CLR

IN

2

–

U2A

®

1469

LT

3

C22

µF

0.001

R

REFA REFB R

COM

U1

LTC2753-16

+

51931 49 41

OFFSET
TRIM A

+

V

8

4

–

V

GNDGNDGNDGND

2

33

R1

1

10k

1

46

FBA

45

I

OUT1A

4

I

OUT2A

44

R

VOSA

43

R

VOSB

32

I

OUT2B

42

I

OUT1B

R

FBB

OFFSET
TRIM B

2

R3
10k

1

C1

30pF

–

6

5

3

2

U4B

LT1469

+

8

+

U4A

LT1469

–

4

V

V

+

–

C2

30pF

7

1

2753 TA03

V

V

OUTA

OUTB

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LT1027 Precision Reference 1ppm/°C Maximum Drift
LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise
LT1468 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate
LT1469 Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate
LTC1588/LTC1589/

Serial 12-/14-/16-Bit I

LTC1592
LTC1591/LTC1597 Parallel 14-/16-Bit I
LTC1821 Parallel 16-Bit V
LTC2601/LTC2611/

Serial 12-/14-/16-Bit V

OUT

LTC2621
LTC2606/LTC2616/

Serial 12-/14-/16-Bit V

LTC2626
LTC2641/LTC2642 Serial 12-/14-/16-Bit Unbuffered V

DACs
LTC2704 Serial 12-/14-/16-Bit V
LTC2751 Parallel 12-/14-/16-Bit I

Single DACs

Linear Technology Corporation

24

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

Single DAC Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package

OUT

Single DAC Integrated 4-Quadrant Resistors

OUT

Single DAC ±1LSB INL, DNL, 0V to 10V, 0V to –10V, ±10V Output Ranges

Single DACs Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

OUT

DFN-10 Package

Single DACs Single DACs, I2C-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

OUT

DFN-10 Package

OUT

Single

±2LSB INL, ±1LSB DNL, 1µs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10
Packages

Quad DACs Software-Selectable (SoftSpan) Ranges, Integrated Amplifi ers, ±2LSB INL

OUT

SoftSpan

OUT

±1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 5mm × 7mm
QFN-38 Package

●

www.linear.com

© LINEAR TECHNOLOGY CORPORATION 2007

2753f

LT 1007 • PRINTED IN USA