FEATURES
www.BDTIC.com/LINEAR
■
Smallest Pin-Compatible Quad DACs:
LTC2609: 16 Bits
LTC2619: 14 Bits
LTC2629: 12 Bits
■
Guaranteed Monotonic Over Temperature
■
Separate Reference Inputs
■
27 Selectable Addresses
■
400kHz I2C™ Interface
■
Wide 2.7V to 5.5V Supply Range
■
Low Power Operation: 250µA per DAC at 3V
■
Individual Channel Power Down to 1µA (Max)
■
High Rail-to-Rail Output Drive (±15mA, Min)
■
Ultralow Crosstalk Between DACs (5µV)
■
LTC2609/LTC2619/LTC2629: Power-On Reset to
Zero Scale
■
LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset
to Midscale
■
Tiny 16-Lead Narrow SSOP Package
U
APPLICATIO S
■
Mobile Communications
■
Process Control and Industrial Automation
■
Automatic Test Equipment and Instrumentation
LTC2609/LTC2619/LTC2629
Quad 16-/14-/12-Bit
Rail-to-Rail DACs with
2
C Interface
U
I
DESCRIPTIO
The LTC®2609/LTC2619/LTC2629 are quad 16-, 14- and
12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs in a
16-lead SSOP package. They have built-in high performance output buffers and are guaranteed monotonic.
These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.
The parts use a 2-wire, I2C compatible serial interface. The
LTC2609/LTC2619/LTC2629 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz).
The LTC2609/LTC2619/LTC2629 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2609-1/LTC2619-1/
LTC2629-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5396245. Patent pending.
W
BLOCK DIAGRA
V
V
V
REFA
OUTA
OUTB
REFB
SCL
SDA
INPUT
REGISTER
INPUT
REGISTER
I2C
INTERFACE
GND
1
REFLO
3
DAC A
4
DAC B
5
6
8
9
2
DAC
REGISTER
DAC
REGISTER
32-BIT SHIFT REGISTER
INPUT
INPUT
CONTROL
LOGIC
CC
16
REGISTER
REGISTER
DAC
REGISTER
DAC
REGISTER
ADDRESS
DECODE
LOGIC
DAC D
DAC C
15
14
13
12
11
10
7
2609 BD
REFD
V
OUTD
V
OUTC
REFC
CA0
CA1
CA2
Differential Nonlinearity
(LTC2609)
1.0
VCC = 5V
0.8
= 4.096V
V
REF
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 16384 32768 49152 65535
CODE
2609 G02
26091929f
1
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
A
W
O
LUTEXI TIS
S
A
WUW
U
(Note 1)
ARB
G
Any Pin to GND........................................... –0.3V to 6V
Any Pin to VCC.............................................– 6V to 0.3V
Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ – 65°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C
WU
/
PACKAGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
O
RDER I FOR ATIO
TOP VIEW
1
GND
2
REFLO
3
REFA
4
V
OUTA
5
V
OUTB
6
REFB
7
CA2
8
SCL
16-LEAD PLASTIC SSOP
T
JMAX
GN PACKAGE
= 135°C, θJA = 150°C
V
16
CC
REFD
15
V
14
OUTD
V
13
OUTC
REFC
12
CA0
11
CA1
10
SDA
9
U
Operating Temperature Range:
LTC2609C/LTC2619C/LTC2629C
LTC2609C-1/LTC2619C-1/LTC2629C-1 ... 0°C to 70°C
LTC2609I/LTC2619I/LTC2629I
LTC2609I-1/LTC2619I-1/LTC2629I-1 .. –40°C to 85°C
ORDER PART NUMBER
LTC2609CGN
LTC2609CGN-1
LTC2609IGN
LTC2609IGN-1
LTC2619CGN
LTC2619CGN-1
LTC2619IGN
LTC2619IGN-1
LTC2629CGN
LTC2629CGN-1
LTC2629IGN
LTC2629IGN-1
GN PART MARKING
2609
26091
2609I
2609I1
2619
26191
2619I
2619I1
2629
26291
2629I
2629I1
LECTRICAL C CHARA TERIST
E
temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution ● 12 14 16 Bits
Monotonicity (Note 2) ● 12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1LSB
INL Integral Nonlinearity (Note 2) ● ±1 ± 4 ±4 ±16 ± 16 ± 64 LSB
Load Regulation V
ZSE Zero-Scale Error Code = 0 ● 1.5 9 1.5 9 1.5 9 mV
V
OS
GE Gain Error ● ±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR
Offset Error (Note 4) ● ±1 ± 9 ±1 ± 9 ±1 ± 9mV
VOS Temperature ±6 ±6 ±6 µV/°C
Coefficient
Gain Temperature ±3 ± 3 ±3 ppm/°C
Coefficient
= VCC = 5V, Midscale
REF
= 0mA to 15mA Sourcing ● 0.02 0.125 0.1 0.5 0.3 2 LSB/mA
I
OUT
= 0mA to 15mA Sinking ● 0.02 0.125 0.1 0.5 0.4 2 LSB/mA
I
OUT
V
= VCC = 2.7V, Midscale
REF
= 0mA to 7.5mA Sourcing ● 0.04 0.25 0.2 1 0.7 4 LSB/mA
I
OUT
= 0mA to 7.5mA Sinking ● 0.05 0.25 0.2 1 0.8 4 LSB/mA
I
OUT
ICS
The ● denotes specifications which apply over the full operating
unloaded, unless otherwise noted.
OUT
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
26091929f
2
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
LECTRICAL C CHARA TERIST
E
ICS
temperature range, otherwise specifications are at T
REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSR Power Supply Rejection VCC ±10% –80 dB
R
OUT
I
SC
Reference Input
I
REF
Power Supply
V
CC
I
CC
Digital I/O (Note 9)
V
IL
V
IH
V
IL(CAn)
V
IH(CAn)
R
INH
R
INL
R
INF
V
OL
t
OF
t
SP
I
IN
C
IN
C
B
C
CAX
DC Output Impedance V
DC Crosstalk (Note 10) Due to Full-Scale Output Change (Note 11) ±5 µV
Short-Circuit Output Current VCC = 5.5V, V
Input Voltage Range ● 0V
Resistance Normal Mode ● 88 125 160 kΩ
Capacitance 14 pF
Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA
Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 5V (Note 3) ● 1.25 2 mA
Low Level Input Voltage ● 0.3V
(SDA and SCL)
High Level Input Voltage ● 0.7V
(SDA and SCL)
Low Level Input Voltage on CA
(n = 0, 1, 2)
High Level Input Voltage on CA
(n = 0, 1, 2)
Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ
to Set CAn = V
to V
CC
Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ
to GND to Set CA
Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 2MΩ
to VCC or GND to Set CAn = Float
Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V
Output Fall Time VO = V
Pulse Width of Spikes Suppressed ● 050ns
by Input Filter
Input Leakage 0.1VCC ≤ VIN ≤ 0.9V
I/O Pin Capacitance (Note 12) ● 10 pF
Capacitive Load for Each Bus Line ● 400 pF
External Capacitive Load on Address ● 10 pF
Pins CAn (n = 0, 1, 2)
n
= GND
CC
n
n
= VCC = 5V, Midscale; –15mA ≤ I
REF
V
= VCC = 2.7V, Midscale; –7.5mA ≤ I
REF
Due to Load Current Change ±4 µV/mA
Due to Powering Down (Per Channel) ±4 µV
Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND ● 15 36 60 mA
VCC = 2.7V, V
Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND
= 3V (Note 3) ● 1 1.6 mA
V
CC
DAC Powered Down (Note 3) VCC = 5V ● 0.35 1 µA
DAC Powered Down (Note 3) V
See Test Circuit 1 ● 0.15V
See Test Circuit 1 ● 0.85V
= 10pF to 400pF (Note 7)
C
B
The ● denotes specifications which apply over the full operating
= 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
A
unloaded, unless otherwise noted. (Note 9)
OUT
≤ 15mA ● 0.030 0.15 Ω
OUT
≤ 7.5mA ● 0.035 0.15 Ω
OUT
= 5.5V
IH(MIN)
REF
= 2.7V
REF
to VO = V
CC
CC
CC
= 3V ● 0.15 1 µA
CC
, ● 20 + 0.1C
IL(MAX)
● 15 36 60 mA
● 7.5 22 50 mA
● 7.5 30 50 mA
CC
CC
CC
B
● 1 µA
250 ns
CC
CC
26091929f
V
V
V
V
V
3
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
LECTRICAL C CHARA TERIST
E
ICS
temperature range, otherwise specifications are at T
REFC = REFD = 2.048V (VCC = 2.7V), REFLO = 0V, V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
t
S
e
n
Settling Time (Note 5) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs
±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 6) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs
±0.0015% (±1LSB at 16 Bits) 5.2 µs
Voltage Output Slew Rate 0.7 0.7 0.7 V/µs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Midscale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz
At f = 10kHz 100 100 100 nV/√Hz
Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV
The ● denotes specifications which apply over the full operating
= 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB =
A
unloaded, unless otherwise noted.
OUT
LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1
P-P
UW
TI I G CHARACTERISTICS
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V
f
SCL
t
HD(STA)
t
LOW
t
HIGH
t
SU(STA)
t
HD(DAT)
t
SU(DAT)
t
r
t
f
t
SU(STO)
t
BUF
t
1
t
2
SCL Clock Frequency ● 0 400 kHz
Hold Time (Repeated) Start Condition ● 0.6 µs
Low Period of the SCL Clock Pin ● 1.3 µs
High Period of the SCL Clock Pin ● 0.6 µs
Set-Up Time for a Repeated Start Condition ● 0.6 µs
Data Hold Time ● 0 0.9 µs
Data Set-Up Time ● 100 ns
Rise Time of Both SDA and SCL Signals (Note 7) ● 20 + 0.1C
Fall Time of Both SDA and SCL Signals (Note 7) ● 20 + 0.1C
Set-Up Time for Stop Condition ● 0.6 µs
Bus Free Time Between a Stop and Start Condition ● 1.3 µs
Falling Edge of 9th Clock of the 3rd Input Byte ● 400 ns
to LDAC High or Low Transition
LDAC Low Pulse Width ● 20 ns
The ● denotes specifications which apply over the full operating temperature
B
B
300 ns
300 ns
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Linearity and monotonicity are defined from code k
N
– 1, where N is the resolution and kL is given by kL = 0.016(2N/V
2
rounded to the nearest whole code. For V
256 and linearity is defined from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or V
Note 4: Inferred from measurement at code k
scale.
Note 5: VCC = 5V, V
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
REF
, CA0, CA1 and CA2 floating.
CC
= 4.096V. DAC is stepped 1/4 scale to 3/4 scale
= 4.096V and N = 16, kL =
REF
(see Note 2) and at full
L
to code
L
REF
),
4
Note 6: VCC = 5V, V
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 7: C
Note 8: All values refer to V
Note 9: These specifications apply to LTC2609/LTC2609-1,
LTC2619/LTC2619-1, LTC2629/LTC2629-1.
Note 10: DC crosstalk is measured with V
REFD = 4.096V, with the measured DAC at midscale, unless otherwise
noted.
Note 11: R
Note 12: Guaranteed by design and not production tested.
= capacitance of one bus line in pF.
B
= 2kΩ to GND or VCC.
L
= 4.096V. DAC is stepped ±1LSB between half
REF
IH(MIN)
and V
levels.
IL(MAX)
= 5V, REFA = REFB = REFC =
CC
26091929f
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2609
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature
32
VCC = 5V
= 4.096V
V
REF
24
16
8
0
INL (LSB)
–8
–16
–24
–32
0 16384 32768 49152 65535
CODE
2609 G01
1.0
VCC = 5V
0.8
0.6
0.4
0.2
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
= 4.096V
V
REF
0
0 16384 32768 49152 65535
CODE
2609 G02
32
24
16
8
0
INL (LSB)
–8
–16
–24
–32
–50
VCC = 5V
= 4.096V
V
REF
–30 –10 10 30 50 70 90
INL (POS)
INL (NEG)
TEMPERATURE (°C)
2609 G03
DNL vs Temperature
1.0
VCC = 5V
= 4.096V
V
0.8
REF
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
–30 –10 10 30 50 70 90
–50
TEMPERATURE (°C)
100µV/DIV
DNL (POS)
DNL (NEG)
2609 G04
INL vs V
32
24
16
8
0
INL (LSB)
–8
–16
–24
–32
0
REF
VCC = 5.5V
INL (POS)
INL (NEG)
1 2 3 4 5
V
(V)
REF
2609 G05
Settling to ±1LSB Settling of Full-Scale Step
V
OUT
SCL
2V/DIV
9TH CLOCK
OF 3RD DATA
BYTE
9.7µs
V
OUT
100µV/DIV
SCR
2V/DIV
DNL vs V
1.5
VCC = 5.5V
1.0
0.5
0
DNL (LSB)
–0.5
–1.0
–1.5
0
12.3µs
9TH CLOCK OF
3RD DATA BYTE
REF
DNL (POS)
DNL (NEG)
1 2 3 4 5
V
(V)
REF
2609 G06
2µs/DIV
= 5V, V
V
CC
1/4 SCALE TO 3/4 SCALE STEP
= 2k, CL = 200pF
R
L
AVERAGE OF 2048 EVENTS
= 4.096V
REF
2609 G07
5µs/DIV
SETTLING TO ±1LSB
= 5V, V
V
CC
CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS
REF
= 4.096V
2609 G08
26091929f
5
LTC2609/LTC2619/LTC2629
2µs/DIV
2609 G14
V
OUT
1mV/DIV
SCL
2V/DIV
V
CC
= 5V, V
REF
= 4.096V
1/4 SCALE TO 3/4 SCALE STEP
R
L
= 2k, CL = 200pF
AVERAGE OF 2048 EVENTS
6.8µs
9TH CLOCK
OF 3RD DATA
BYTE
www.BDTIC.com/LINEAR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2619
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
8
VCC = 5V
= 4.096V
V
REF
6
4
2
0
INL (LSB)
–2
–4
–6
–8
0 4096 8192 12288 16383
CODE
2609 G09
1.0
VCC = 5V
0.8
0.6
0.4
0.2
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
= 4.096V
V
REF
0
0 4096 8192 12288 16383
CODE
LTC2629
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
2.0
1.5
1.0
0.5
0
INL (LSB)
–0.5
–1.0
–1.5
–2.0
0 1024 2048 3072 4095
CODE
VCC = 5V
V
REF
= 4.096V
2609 G12
1.0
VCC = 5V
0.8
= 4.096V
V
REF
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 1024 2048 3072 4095
CODE
2609 G10
2609 G13
V
OUT
100µV/DIV
SCL
2V/DIV
Settling to ±1LSB
9TH CLOCK
OF 3RD DATA
BYTE
2µs/DIV
= 5V, V
V
CC
1/4 SCALE TO 3/4 SCALE STEP
= 2k, CL = 200pF
R
L
AVERAGE OF 2048 EVENTS
REF
= 4.096V
Settling to ±1LSB
8.9µs
2609 G11
6
26091929f
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2609/LTC2619/LTC2629
Current Limiting
0.10
CODE = MIDSCALE
(V)
OUT
∆V
–0.02
–0.04
–0.06
–0.08
–0.10
0.08
0.06
0.04
0.02
0
V
REF
–30 –20 –10 0 10 20 30 40
–40
V
= VCC = 3V
V
= VCC = 5V
REF
V
REF
= VCC = 3V
REF
I
(mA)
OUT
= VCC = 5V
Zero-Scale Error vs Temperature
3
2.5
2.0
1.5
1.0
ZERO-SCALE ERROR (mV)
0.5
0
–30 –10 10 30 50 70 90
–50
TEMPERATURE (°C)
2609 G15
2609 G18
Load Regulation Offset Error vs Temperature
1.0
CODE = MIDSCALE
0.8
0.6
0.4
0.2
(mV)
0
V
OUT
∆V
–0.2
–0.4
–0.6
–0.8
–1.0
= VCC = 5V
REF
V
= VCC = 3V
REF
–35 –25 – 15 – 5 5 15 25 35
I
OUT
(mA)
2609 G16
3
2
1
0
–1
OFFSET ERROR (mV)
–2
–3
–30 –10 10 30 50 70 90
–50
TEMPERATURE (°C)
Gain Error vs Temperature Offset Error vs V
0.4
0.3
0.2
0.1
0
–0.1
GAIN ERROR (%FSR)
–0.2
–0.3
–0.4
–30 –10 10 30 50 70 90
–50
TEMPERATURE (°C)
2609 G19
3
2
1
0
–1
OFFSET ERROR (mV)
–2
–3
2.5 3
3.5 4 4.5 5 5.5
VCC (V)
2609 G17
CC
2609 G20
Gain Error vs V
0.4
0.3
0.2
0.1
0
–0.1
GAIN ERROR (%FSR)
–0.2
–0.3
–0.4
2.5 3
CC
3.5 4 4.5 5 5.5
VCC (V)
2609 G21
ICC Shutdown vs V
450
400
350
300
250
(nA)
CC
200
I
150
100
50
0
2.5 3
CC
3.5 4 4.5 5 5.5
VCC (V)
2609 G22
26091929f
7
LTC2609/LTC2619/LTC2629
LOGIC VOLTAGE (V)
0
1.0
I
CC
(mA)
1.1
1.3
1.4
1.5
3 3.5 4 4.5
1.9
2609 G28
1.2
0.5 1 1.5 2 2.5 5
1.6
1.7
1.8
VCC = 5V
SWEEP SCL
AND SDA
0V TO V
CC
AND V
CC
TO 0V
www.BDTIC.com/LINEAR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2609/LTC2619/LTC2629
Large-Signal Response
V
OUT
0.5V/DIV
V
REF
1/4 SCALE TO 3/4 SCALE
Headroom at Rails
vs Output Current
5.0
4.5
4.0
3.5
3.0
(V)
2.5
OUT
V
2.0
1.5
1.0
0.5
0
1 2 3 4 5 6 7 8 910
0
= VCC = 5V
5V SOURCING
3V SOURCING
3V SINKING
2.5µs/DIV
I
(mA)
OUT
5V SINKING
2609 G23
2609 G26
V
OUT
10mV/DIV
SCL
2V/DIV
1V/DIV
V
V
OUT
Midscale Glitch Impulse
TRANSITION FROM
MS-1 TO MS
TRANSITION FROM
9TH CLOCK
OF 3RD DATA
BYTE
MS TO MS-1
2.5µs/DIV
Power-On Reset to Midscale
V
= V
REF
CC
CC
500µs/DIV
2609 G24
2606 G27
V
1V/DIV
V
OUT
10mV/DIV
Power-On Reset Glitch
CC
4mV PEAK
250µs/DIV
Supply Current vs Logic Voltage
2609 G25
8
26091929f
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2609/LTC2619/LTC2629
Output Voltage Noise,
Multiplying Bandwidth
0
–3
–6
–9
–12
–15
–18
dB
–21
–24
–27
VCC = 5V
(DC) = 2V
V
REF
–30
–33
–36
(AC) = 0.2V
V
REF
CODE = FULL SCALE
1k
10k 100k
FREQUENCY (Hz)
P-P
1M
2609 G29
0.1Hz to 10Hz
V
OUT
10µV/DIV
012345678910
SECONDS
2609 G30
Short-Circuit Output Current vs
V
(Sinking)
OUT
50
VCC = 5.5V
= 5.6V
V
REF
CODE = 0
40
SWEPT 0V TO V
V
30
10mA/DIV
20
10
0
0
OUT
1
CC
234
1V/DIV
56
2609 G31
Short-Circuit Output Current vs
V
(Sourcing)
OUT
0
VCC = 5.5V
= 5.6V
V
REF
CODE = FULL SCALE
–10
–20
10mA/DIV
–30
–40
–50
SWEPT VCC TO 0V
V
OUT
0
1
234
1V/DIV
56
2609 G32
26091929f
9
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
UUU
PIN FUNCTIONS
GND (Pin 1): Analog Ground.
REFLO (Pin 2): Reference Low. The voltage at this pin sets
the zero scale (ZS) voltage of all DACs. This pin can be
raised up to 1V above ground at VCC = 5V or 100mV above
ground at VCC = 3V.
REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage
Inputs for each DAC. REFx sets the full-scale voltage of the
DACs. REFLO ≤ REFx ≤ VCC.
V
to V
OUTA
Outputs. The output range is from REFLO to REFx.
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 1).
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source
to VCC.
(Pins 4, 5, 13, 14): DAC Analog Voltage
OUTD
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance pin while data is shifted in and is an
open-drain N-channel output during acknowledgment.
SDA requires a pull-up resistor or current source to VCC.
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V
or leave it floating to select an I
(Table 1).
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V
or leave it floating to select an I
(Table 1).
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
2
C slave address for the part
2
C slave address for the part
CC
CC
, GND
, GND
10
26091929f
BLOCK DIAGRA
www.BDTIC.com/LINEAR
REFA
3
W
REFLO
2
GND
LTC2609/LTC2619/LTC2629
V
CC
1
16
REFD
15
V
V
REFB
OUTA
OUTB
SCL
SDA
REGISTER
REGISTER
ADDRESS
DECODE
LOGIC
DAC D
DAC C
14
13
12
11
10
7
2609 BD
V
OUTD
V
OUTC
REFC
CA0
CA1
CA2
DAC A
4
DAC B
5
6
8
9
DAC
REGISTER
DAC
REGISTER
INPUT
INPUT
32-BIT SHIFT REGISTER
INTERFACE
REGISTER
REGISTER
I2C
INPUT
INPUT
CONTROL
LOGIC
REGISTER
DAC
DAC
REGISTER
26091929f
11
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
TEST CIRCUITS
Test Circuit 2Test Circuit 1
V
DD
100Ω
V
IH(CAn)/VIL(CAn)
WUW
TI I G DIAGRA S
SDA
t
f
SCL
ALL VOLTAGE LEVELS REFER TO V
t
LOW
t
HD(STA)
S
t
r
t
HD(DAT)
CA
IH(MIN)
n
t
SU(DAT)
t
HIGH
AND V
IL(MAX)
t
f
LEVELS
t
SU(STA)
Figure 1
R
INH/RINL/RINF
t
HD(STA)
S P S
t
SP
t
SU(STO)
CA
n
GND
2609 TC
t
t
BUF
r
2609 F01
12
26091929f
OPERATIO
www.BDTIC.com/LINEAR
LTC2609/LTC2619/LTC2629
U
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619-1/LTC2629-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2609/
LTC2619/LTC2629 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range – 0.3V ≤ REFx ≤ VCC + 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at VCC (Pin 16) is in
transition. The REFx pins can be clamped to stay below the
maximum voltage by using Schottky diodes as shown in
Figure 2, thereby easing sequencing constraints.
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
2
using the standard 2-wire I
C interface. The Timing Diagram (Figure 1) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be
high when the bus is not in use. External pull-up resistors
or current sources are required on these lines. The value
of these pull-up resistors is dependent on the power supply and can be obtained from the I2C specifications. For an
2
I
C bus operating in the fast mode, an active pull-up will
be necessary if the bus capacitance is greater than 200pF.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629. The LTC2609/LTC2619/LTC2629 do not respond to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communication to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
V
16
V
REFA
REFB
REFC
REFD
CC
3
6
12
15
2609 F02
LTC2609/
LTC2619/
LTC2629
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
CC
REFA
REFB
REFC
REFD
Transfer Function
The digital-to-analog transfer function is:
V
OUT IDEAL
()
k
REFx REFLO REFLO
[– ]=
⎜
⎟
N
⎝
⎠
2
+
⎛
⎞
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
26091929f
13
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
U
OPERATIO
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2609/LTC2619/LTC2629 respond to a
write by a master in this manner. The LTC2609/LTC2619/
LTC2629 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or float. This results in
27 selectable addresses for the part. The slave address
assignments are shown in Table 1.
Table 1. Slave Address Map
CA2 CA1 CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0
GND GND GND 0 0 1 0 0 0 0
GND GND FLOAT 0 0 1 0 0 0 1
GND GND V
GND FLOAT GND 0 0 1 0 0 1 1
GND FLOAT FLOAT 0 1 0 0 0 0 0
GND FLOAT V
GND V
GND V
GND V
FLOAT GND GND 0 1 1 0 0 0 1
FLOAT GND FLOAT 0 1 1 0 0 1 0
FLOAT GND V
FLOAT FLOAT GND 1 0 0 0 0 0 0
FLOAT FLOAT FLOAT 1 0 0 0 0 0 1
FLOAT FLOAT V
FLOAT V
FLOAT V
FLOAT V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GND GND 1 0 1 0 0 1 0
GND FLOAT 1 0 1 0 0 1 1
GND V
FLOAT GND 1 1 0 0 0 0 1
FLOAT FLOAT 1 1 0 0 0 1 0
FLOAT V
V
V
V
GLOBAL ADDRESS 1 1 1 0 0 1 1
GND 0100010
CC
FLOAT 0 1 0 0 0 1 1
CC
CC
CC
CC
CC
CC
CC
CC
V
GND 1000011
FLOAT 1 0 1 0 0 0 0
V
GND 1110000
FLOAT 1 1 1 0 0 0 1
V
0010010
CC
0100001
CC
0110000
CC
0110011
CC
1000010
CC
1010001
CC
1100000
CC
1100011
CC
1110010
CC
In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2609, LTC2619 and
LTC2629 parts to be accomplished with one 3-byte write
transaction on the I
2
C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.
Write Word Protocol
The master initiates communication with the LTC2609/
LTC2619/LTC2629 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2609/
LTC2619/LTC2629 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2609/LTC2619/LTC2629 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2609/LTC2619/LTC2629 executes the command specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2609/LTC2619/LTC2629 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
and 4-bit DAC address. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don’t care bits (LTC2609, LTC2619 and LTC2629
respectively).
A typical LTC2609 write transaction is shown
in Figure 4.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
14
26091929f
OPERATIO
www.BDTIC.com/LINEAR
U
Write Word Protocol for LTC2609/LTC2619/LTC1629
WA
S
SLAVE ADDRESS
1ST DATA BYTE
A 2ND DATA BYTE A 3RD DATA BYTE A P
LTC2609/LTC2619/LTC2629
Input Word (LTC2609)
A3
A2
A1
C3
Input Word (LTC2619)
C3
Input Word (LTC2629)
C3
C1
C2
1ST DATA BYTE
C1
C2
1ST DATA BYTE
C1
C2
1ST DATA BYTE
C0
C0
C0
A3
A3
A0
A2
A1
A0
A2
A1
A0
D12
D13D14D15
2ND DATA BYTE
D10
D11D12D13
2ND DATA BYTE 3RD DATA BYTE
D8
D9D10D11
2ND DATA BYTE 3RD DATA BYTE
Figure 3
Table 2
COMMAND*
C3 C2 C1 C0
0000 Write to Input Register n
0001 Update (Power Up) DAC Register n
0010 Write to Input Register n, Update (Power Up) All n
0011 Write to and Update (Power Up) n
0100 Power Down n
1111 No Operation
ADDRESS (n)*
A3 A2 A1 A0
0000 DAC A
0001 DAC B
0010 DAC C
0011 DAC D
1111 All DACs
*Command and address codes not shown are reserved and should not be used.
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the Block Diagram.
INPUT WORD
D11 D10 D 9 D8
D9 D8 D 7 D 6
D7 D6 D 5 D 4
D6
D5 D4 D3 D2 D1
D7
D4
D3 D2 D1 D0 X
D5
D2
D1 D0 X X X
D3
3RD DATA BYTE
D0
X
X
2609 F03
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high impedance state, and the
output pins are passively pulled to REFLO through
individual 90k resistors. Input- and DAC-register contents
are not disturbed during power down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in
combination with the appropriate DAC address, (n). The
16-bit data word is ignored. The supply current is reduced
by approximately 1/4 for each DAC powered down.
The effective resistance at REFx (Pins 3, 6, 12 and 15)
are at high impedance (typically > 1GΩ) when the corresponding DACs are powered down. Normal operation can
be resumed by executing any command which includes a
DAC update, as shown in Table 2.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than four DACs are in a powered-down state prior to
the update command, the power-up delay time is 5µs.
If on the other hand, all four DACs are powered down,
26091929f
15
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
U
OPERATIO
then the main bias generation circuit block has been
automatically shut down in addition to the individual DAC
amplifiers and reference inputs. In this case, the power-up
delay time is 12µs (for VCC = 5V) or 30µs (for VCC = 3V).
Voltage Output
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
2.7V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω • 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics section.
The amplifier is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping
“signal” and “power” grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a
continuous and uninterrupted plane, except for necessary
lead pads and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. When a zero scale
DAC output voltage of zero is desired, REFLO (Pin 2)
should be connected to system star ground.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full scale
when the REF pins are tied to VCC. If REFx = VCC and the
DAC full-scale error (FSE) is positive, the output for the
highest codes limits at VCC as shown in Figure 4c. No fullscale limiting can occur if REFx is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
16
26091929f
ACK
ACK
123456789123456789123456789123456789
2609 F04
ACK
START
X = DON’T CARE
STOP
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
SDA
SA6 SA5 SA4 SA3 SA2 SA1 SA0
SCL
V
OUT
C2C3
C3 C2 C1 C0 A3 A2 A1 A0
C1 C0 A3 A2 A1 A0
ACK
COMMAND
D15 D14 D13 D12 D11 D10 D9 D8
MS DATA
D7 D6 D5 D4 D3 D2 D1 D0
LS DATA
SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR
SLAVE ADDRESS
www.BDTIC.com/LINEAR
OPERATIO
LTC2609/LTC2619/LTC2629
U
Figure 4. Typical LTC2609 Input Waveform—Programming DAC Output for Full Scale
26091929f
17
LTC2609/LTC2619/LTC2629
2609 F05
INPUT CODE
(5b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
32, 7680 65, 535
INPUT CODE
OUTPUT
VOLTAGE
(5a)
REFx = V
CC
REFx = V
CC
(5c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
www.BDTIC.com/LINEAR
U
OPERATIO
18
Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect
of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale
26091929f
TYPICAL APPLICATIO
www.BDTIC.com/LINEAR
Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters
C1
V
0.1µF
CC
V
CC
16
V
CC
LTC2609CGN
11
0.1µF
0.1µF
CA0
10
CA1
7
CA2
9
I2C
EXT REFLO
V
IN
C6
V
IN
LT1790ACS6-4.096
C8
8
REFLO
LT1790ACS6-5
4
V
V
IN
3
NC
GND GND
12
4
V
V
IN
3
NC
GND GND
12
SDA
SCL
REFLO GND
OUT
NC
OUT
NC
2
JP1 REFLO
5V
6
5
4.096V
6
5
V
REFA
V
OUTB
REFB
V
OUTC
REFC
V
OUTD
REFD
REF
OUTA
1
REF
EXT
GND
C7
1µF
6.3V
C9
1µF
6.3V
LTC2609/LTC2619/LTC2629
U
V
JP7
A
B
C5
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
DISABLE
ADC
CS
SCK
MOSI
MISO
REF
2
4
6
5V
4.096V
2.048V
V
OUTA
REFA
V
OUTB
REFB
V
OUTC
REFC
V
OUTD
REFD
GND
GND
SPI
BUS
REF
REF
REF
REFA
JP3
A
1
3
4
3
5
6
13
12
14
15
2
B
4
C5
6
1
3
9
10
11
12
13
14
15
17
5
REFB
JP4
A
B
C5
LTC2428CG
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
ZSSET
REFC
JP5
2
4
6
MUXOUT ADCIN FSSET
8-CHANNEL
MUX
GND GND GND GND GND GND
GND
1
A
1
B
3
C5
C3
R5
100pF
7.5k
743
61618222728
REFD
JP6
C4
R8
22Ω
20-BIT
ADC
A
1
3
V
2
B
4
C5
6
V
CC
C5
0.1µF
2
8
V
CC
CC
CSADC
CSMUX
SCK
CLK
DIN
SD0
F0
2
4
6
V
REF
0.1µF
+
–
ADC REF
1
3
JP2
V
ON/OFF
CC
R6
23
7.5k
20
25
19
21
24
26
R7
7.5k
2609 TA02
C10
0.1µF
V
IN
LT1790ACS6-2.048
4
3
V
IN
NC
GND GND
12
2.048V
REF
6
V
OUT
NC
C11
5
1µF
6.3V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
26091929f
19
LTC2609/LTC2619/LTC2629
www.BDTIC.com/LINEAR
U
PACKAGE DESCRIPTIO
(Reference LTC DWG # 05-08-1641)
GN Package
16-Lead Plastic SSOP
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.007 – .0098
(0.178 – 0.249)
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
(MILLIMETERS)
INCHES
16
15
12
.189 – .196*
(4.801 – 4.978)
14
3
.045 ±.005
.150 – .165
.229 – .244
(5.817 – 6.198)
.0250 BSC.0165 ± .0015
.015
± .004
(0.38 ± 0.10)
0° – 8° TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
× 45°
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
13
4
12 11 10
5
678
.0250
(0.635)
9
.004 – .0098
(0.102 – 0.249)
BSC
.009
(0.229)
REF
.150 – .157**
(3.810 – 3.988)
GN16 (SSOP) 0204
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V
= 2.7V to 5.5V, V
CC
LTC1654 Dual 14-Bit Rail-to-Rail V
LTC1655/LTC1655L Single 16-Bit V
LTC1657/LTC1657L Parallel 5V/3V 16-Bit V
LTC1660/LTC1665 Octal 10/8-Bit V
DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched
OUT
OUT
DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output
OUT
LTC1458L: V
DAC Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA
OUT
DACs Low Power, Deglitched, Rail-to-Rail V
LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610 Octal 16-/14-/12-Bit V
DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2620 Output, SPI Serial Interface
LTC2601/LTC2611 Single 16-/14-/12-Bit V
DACs in 10-Lead DFN 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2621 Output, SPI Serial Interface
LTC2602/LTC2612 Dual 16-/14-/12-Bit V
DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2622 Output, SPI Serial Interface
LTC2604/LTC2614 Quad 16-/14-/12-Bit V
DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2624 Output, SPI Serial Interface
LTC2605/LTC2615 Octal 16-/14-/12-Bit V
DACs with I2C Interface in 16-Lead SSOP 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2625 Output
LTC2606/LTC2616 Single 16-/14-/12-Bit V
DACs in 10-Lead DFN with I2C Interface 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail
OUT
LTC2626 Output
= 0V to 4.096V
OUT
= 0V to 2.5V
OUT
OUT
Linear Technology Corporation
20
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
26091929f
LT/LW/TP 0505 500 • PRINTED IN THE USA
© LINEAR TECHNOLOGY CORPORATION 2005
Loading...