LINEAR TECHNOLOGY LTC2607, LTC2617, LTC2627 Technical data

FEATURES

■

Smallest Pin-Compatible Dual DACs:
LTC2607: 16 Bits
LTC2617: 14 Bits
LTC2627: 12 Bits

■

Guaranteed Monotonic Over Temperature

■

27 Selectable Addresses

■

400kHz I2CTM Interface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 260µA per DAC at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Ultralow Crosstalk (30µV)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2607/LTC2617/LTC2627: Power-On Reset to
Zero Scale

■

LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset
to Midscale

■

Tiny (3mm × 4mm) 12-Lead DFN Package

U

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2607/LTC2617/LTC2627

16-/14-/12-Bit Dual Rail-to-Rail

DACs with I

2

C Interface

U

DESCRIPTIO

The LTC®2607/LTC2617/LTC2627 are dual 16-, 14- and
12-bit,
12-lead DFN package. They have built-in high perfor­mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.

The parts use a 2-wire, I
LTC2607/LTC2617/LTC2627 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.

The LTC2607/LTC2617/LTC2627 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2607-1/LTC2617-1/
LTC2627-1 to midscale. The voltage outputs stay at
midscale until a valid write and update takes place.

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5396245 and 6891433. Patent Pending

2.7V to 5.5V rail-to-rail voltage output DACs in a

2

C compatible serial interface. The

BLOCK DIAGRA

REFLO GND REF V

11

V

OUTA

12

12-/14-/16-BIT DAC

1

CA0 CA1

2

3

LDAC

W

10

DAC REGISTER

INPUT REGISTER

32-BIT SHIFT REGISTER

4

SCL

2-WIRE INTERFACE

9

DAC REGISTER

INPUT REGISTER

5

SDA

CC

8

12-/14-/16-BIT DAC

CA2

Differential Nonlinearity

(LTC2607)

V

OUTB

7

6

2607 BD

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 16384 32768 49152 65535

CODE

2607 G02

26071727f

1

LTC2607/LTC2617/LTC2627

W

O

A

LUTEXI TIS

S

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V

CC

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

PACKAGE

TOP VIEW

CA0

1

CA1

2

3

LDAC

4

SCL

5

SDA

6

CA2

12-LEAD (4mm × 3mm) PLASTIC DFN

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.

DE12 PACKAGE

= 125°C, θJA = 43°C/W

T

JMAX

EXPOSED PAD (PIN 13) IS GND

MUST BE SOLDERED TO PCB

A

........................................................

/

O

RDER I FOR ATIO

12

11

13

10

9

8

7

V

OUTA

REFLO

GND

REF

V

CC

V

OUTB

WUW

ARB

U
G

–6V to 0.3V

WU

ORDER PART

NUMBER

LTC2607CDE
LTC2607IDE

LTC2607CDE-1
LTC2607IDE-1

DE12 PART MARKING*

2607 2617 2626

26071 26171 26271

(Note 1)

Operating Temperature Range:

LTC2607C/LTC2617C/LTC2627C
LTC2607C-1/LTC2617C-1/LTC2627C-1 ... 0°C to 70°C
LTC2607I/LTC2617I/LTC2627I
LTC2607I-1/LTC2617I-1/LTC2627I-1 .. – 40°C to 85°C

U

ORDER PART

NUMBER

LTC2617CDE
LTC2617IDE

LTC2617CDE-1
LTC2617IDE-1

DE12 PART MARKING*

ORDER PART

NUMBER

LTC2627CDE
LTC2627IDE

LTC2627CDE-1
LTC2627IDE-1

DE12 PART MARKING*

LECTRICAL C CHARA TERIST

E

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance

Resolution

Monotonicity (Note 2)
DNL Differential Nonlinearity (Note 2)
INL Integral Nonlinearity (Note 2)

Load Regulation V

ZSE Zero-Scale Error Code = 0
V

OS

GE Gain Error

Offset Error (Note 6)

VOS Temperature ±7 ±7 ±7 µV/°C

Coefficient

Gain Temperature ±4 ± 4 ±4 ppm/°C

Coefficient

= VCC = 5V, Midscale

REF

= 0mA to 15mA Sourcing

I

OUT

= 0mA to 15mA Sinking

I

OUT

V

= VCC = 2.7V, Midscale

REF

= 0mA to 7.5mA Sourcing

I

OUT

= 0mA to 7.5mA Sinking

I

OUT

ICS

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

●

12 14 16 Bits

●

12 14 16 Bits

●

●

●

●

●

●

●

●

●

±0.5 ±1 ±1 LSB

± 1.5 ± 4 ±5 ± 16 ± 19 ±64 LSB

0.02 0.125 0.1 0.5 0.35 2 LSB/mA

0.03 0.125 0.1 0.5 0.42 2 LSB/mA

0.04 0.25 0.2 1 0.7 4 LSB/mA

0.05 0.25 0.2 1 0.8 4 LSB/mA
19 19 19 mV

±1 ± 9 ± 1 ±9 ±1 ± 9mV

±0.15 ±0.7 ±0.15 ±0.7 ±0.15 ±0.7 %FSR

26071727f

2

LTC2607/LTC2617/LTC2627

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V
R

OUT

DC Output Impedance V

±10% –80dB

CC

= VCC = 5V, Midscale;

REF

–15mA ≤ I

= VCC = 2.7V, Midscale;

V

REF

–7.5mA ≤ I

≤ 15mA ● 0.032 0.15 Ω

OUT

≤ 7.5mA ● 0.035 0.15 Ω

OUT

DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±4 µV

Due to Load Current Change ±3 µV/mA
Due to Powering Down (per channel) ±30 µV

I

SC

Short-Circuit Output Current VCC = 5.5V, V

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

VCC = 2.7V, V

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

REF

REF

= 5.5V

= 2.7V

● 15 36 60 mA

CC

● 15 37 60 mA

● 7.5 22 50 mA

CC

● 7.5 30 50 mA

Reference Input

Input Voltage Range ● 0V

CC

Resistance Normal Mode ● 44 64 80kΩ
Capacitance 30 pF

I

REF

Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Power Supply

V

CC

I

CC

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 5V (Note 3) ● 0.66 1.3 mA

= 3V (Note 3) ● 0.52 1 mA

V

CC

DAC Powered Down (Note 3) V
DAC Powered Down (Note 3) V

= 5V ● 0.4 1 µA

CC

= 3V ● 0.10 1 µA

CC

Digital I/O (Note 11)

V

IL

V

IH

V

IL(LDAC)

V

IH(LDAC)

V

IL(CAn)

V

IH(CAn)

R

INH

R

INL

R

INF

V

OL

t

OF

t

SP

I

IN

C

IN

C

B

C

CAX

Low Level Input Voltage (SDA and SCL) ● 0.3V
High Level Input Voltage (SDA and SCL) ● 0.7V

CC

CC

Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V ● 0.8 V

V

= 2.7V to 5.5V ● 0.6 V

CC

High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V ● 2.4 V

= 2.7V to 3.6V ● 2.0 V

V

CC

Low Level Input Voltage on CA
(

n

= 0, 1, 2)

High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 ● 0.85V

n

See Test Circuit 1 ● 0.15V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to Set CAn = V

to V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ
to GND to Set CA

n

= GND

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 2MΩ

or GND to Set CAn = Float

to V

CC

Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V
Output Fall Time VO = V

C

= 10pF to 400pF (Note 9)

B

IH(MIN)

to VO = V

, ● 20 + 0.1C

IL(MAX)

B

250 ns

Pulse Width of Spikes Suppressed by Input Filter ● 050ns
Input Leakage 0.1VCC ≤ VIN ≤ 0.9V

CC

● 1 µA

I/O Pin Capacitance Note 12 ● 10 pF
Capacitive Load for Each Bus Line ● 400 pF
External Capacitive Load on Address ● 10 pF

n (n

Pins CA

= 0, 1, 2)

26071727f

V

V
V

V

V

3

LTC2607/LTC2617/LTC2627

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

AC Performance

t

S

e

n

Settling Time (Note 7) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 8) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.8 0.8 0.8 V/µs

Capacitive Load Driving 1000 1000 1000 pF

Glitch Impulse At Midscale Transition 12 12 12 nV • s

Multiplying Bandwidth 180180180kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

P-P

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V

f

SCL

t

HD(STA)

t

LOW

t

HIGH

t

SU(STA)

t

HD(DAT)

t

SU(DAT)

t

r

t

f

t

SU(STO)

t

BUF

t

1

t

2

SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
Data Set-Up Time
Rise Time of Both SDA and SCL Signals (Note 9)
Fall Time of Both SDA and SCL Signals (Note 9)
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Falling Edge of 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition
LDAC Low Pulse Width

= 25°C. (See Figure 1) (Notes 10, 11)

A

The ● denotes specifications which apply over the full operating temperature

●

●

●

●

●

●

●

●

●

●

●

●

●

0 400 kHz

0.6 µs

1.3 µs

0.6 µs

0.6 µs
0 0.9 µs

100 ns
20 + 0.1C
20 + 0.1C

B

B

0.6 µs

1.3 µs

400 ns

20 ns

300 ns
300 ns

Note 1: Absolute maximum ratings are those values beyond which the life of
a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/V
rounded to the nearest whole code. For V
and linearity is defined from code 256 to code 65,535.

Note 3: SDA, SCL and LDAC at 0V or V
Note 4: DC crosstalk is measured with V

measured DAC at midscale, unless otherwise noted.
Note 5: R

= 2kΩ to GND or VCC.

L

= 4.096V and N = 16, kL = 256

REF

, CA0, CA1 and CA2 Floating.

CC

= 5V and V

CC

to code

L

REF

= 4.096V, with the

REF

),

4

Note 6: Inferred from measurement at code k
Note 7: V

3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: V

and half scale – 1. Load is 2k in parallel with 200pF to GND.

Note 9: C
Note 10: All values refer to V
Note 11: These specifications apply to LTC2607/LTC2607-1,

LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.

= 5V, V

CC

= 5V, V

CC

= capacitance of one bus line in pF.

B

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale and

REF

= 4.096V. DAC is stepped ±1LSB between half scale

REF

and V

IH(MIN)

(Note 2) and at full scale.

L

levels.

IL(MAX)

26071727f

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32

VCC = 5V

= 4.096V

V

REF

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0 16384 32768 49152 65535

CODE

2607 G01

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 16384 32768 49152 65535

CODE

2607 G02

32

VCC = 5V

= 4.096V

V

REF

24

16

8

0

INL (LSB)

–8

–16

–24

–32

–50 –30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2607 G03

DNL vs Temperature

1.0
VCC = 5V

= 4.096V

V

0.8

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–50 –30 –10 10 30 50 70 90

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

Settling to ±1LSB Settling of Full-Scale Step

V

OUT

100µV/DIV

9TH CLOCK

SCL

2V/DIV

OF 3RD DATA
BYTE

2607 G04

INL vs V

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0 1 2 3 45

9.7µs

VCC = 5.5V

REF

INL (POS)

INL (NEG)

V

(V)

REF

V

OUT

100µV/DIV

SCL

2V/DIV

2607 G05

DNL vs V

1.5
VCC = 5.5V

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

0 1 2 3 45

12.3µs

9TH CLOCK OF
3RD DATA BYTE

REF

DNL (POS)

DNL (NEG)

V

(V)

REF

2607 G06

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

= 4.096V

REF

2607 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

V

CC

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

REF

= 4.096V

2607 G08

26071727f

5

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2617

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

8

VCC = 5V

= 4.096V

V

REF

6

4

2

0

INL (LSB)

–2

–4

–6

–8

0 4096 8192 12288 16383

CODE

2607 G09

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4096 8192 12288 16383

CODE

LTC2627

Integral Nonlinearity (INL)

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 1024 2048 3072 4095

CODE

VCC = 5V
V

REF

= 4.096V

2607 G12

Differential Nonlinearity (DNL)

1.0

VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4095

CODE

2607 G10

2607 G13

V

OUT

100µV/DIV

SCL

2V/DIV

V

OUT

1mV/DIV

SCL

2V/DIV

Settling to ±1LSB

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

Settling to ±1LSB

6.8µs

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

V

= 5V, V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

8.9µs

2607 G11

2607 G14

6

26071727f