LINEAR TECHNOLOGY LTC2607, LTC2617, LTC2627 Technical data

FEATURES

■

Smallest Pin-Compatible Dual DACs:
LTC2607: 16 Bits
LTC2617: 14 Bits
LTC2627: 12 Bits

■

Guaranteed Monotonic Over Temperature

■

27 Selectable Addresses

■

400kHz I2CTM Interface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 260µA per DAC at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Ultralow Crosstalk (30µV)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2607/LTC2617/LTC2627: Power-On Reset to
Zero Scale

■

LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset
to Midscale

■

Tiny (3mm × 4mm) 12-Lead DFN Package

U

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2607/LTC2617/LTC2627

16-/14-/12-Bit Dual Rail-to-Rail

DACs with I

2

C Interface

U

DESCRIPTIO

The LTC®2607/LTC2617/LTC2627 are dual 16-, 14- and
12-bit,
12-lead DFN package. They have built-in high perfor­mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.

The parts use a 2-wire, I
LTC2607/LTC2617/LTC2627 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.

The LTC2607/LTC2617/LTC2627 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2607-1/LTC2617-1/
LTC2627-1 to midscale. The voltage outputs stay at
midscale until a valid write and update takes place.

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5396245 and 6891433. Patent Pending

2.7V to 5.5V rail-to-rail voltage output DACs in a

2

C compatible serial interface. The

BLOCK DIAGRA

REFLO GND REF V

11

V

OUTA

12

12-/14-/16-BIT DAC

1

CA0 CA1

2

3

LDAC

W

10

DAC REGISTER

INPUT REGISTER

32-BIT SHIFT REGISTER

4

SCL

2-WIRE INTERFACE

9

DAC REGISTER

INPUT REGISTER

5

SDA

CC

8

12-/14-/16-BIT DAC

CA2

Differential Nonlinearity

(LTC2607)

V

OUTB

7

6

2607 BD

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 16384 32768 49152 65535

CODE

2607 G02

26071727f

1

LTC2607/LTC2617/LTC2627

W

O

A

LUTEXI TIS

S

Any Pin to GND........................................... –0.3V to 6V

Any Pin to V

CC

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

PACKAGE

TOP VIEW

CA0

1

CA1

2

3

LDAC

4

SCL

5

SDA

6

CA2

12-LEAD (4mm × 3mm) PLASTIC DFN

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.

DE12 PACKAGE

= 125°C, θJA = 43°C/W

T

JMAX

EXPOSED PAD (PIN 13) IS GND

MUST BE SOLDERED TO PCB

A

........................................................

/

O

RDER I FOR ATIO

12

11

13

10

9

8

7

V

OUTA

REFLO

GND

REF

V

CC

V

OUTB

WUW

ARB

U
G

–6V to 0.3V

WU

ORDER PART

NUMBER

LTC2607CDE
LTC2607IDE

LTC2607CDE-1
LTC2607IDE-1

DE12 PART MARKING*

2607 2617 2626

26071 26171 26271

(Note 1)

Operating Temperature Range:

LTC2607C/LTC2617C/LTC2627C
LTC2607C-1/LTC2617C-1/LTC2627C-1 ... 0°C to 70°C
LTC2607I/LTC2617I/LTC2627I
LTC2607I-1/LTC2617I-1/LTC2627I-1 .. – 40°C to 85°C

U

ORDER PART

NUMBER

LTC2617CDE
LTC2617IDE

LTC2617CDE-1
LTC2617IDE-1

DE12 PART MARKING*

ORDER PART

NUMBER

LTC2627CDE
LTC2627IDE

LTC2627CDE-1
LTC2627IDE-1

DE12 PART MARKING*

LECTRICAL C CHARA TERIST

E

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance

Resolution

Monotonicity (Note 2)
DNL Differential Nonlinearity (Note 2)
INL Integral Nonlinearity (Note 2)

Load Regulation V

ZSE Zero-Scale Error Code = 0
V

OS

GE Gain Error

Offset Error (Note 6)

VOS Temperature ±7 ±7 ±7 µV/°C

Coefficient

Gain Temperature ±4 ± 4 ±4 ppm/°C

Coefficient

= VCC = 5V, Midscale

REF

= 0mA to 15mA Sourcing

I

OUT

= 0mA to 15mA Sinking

I

OUT

V

= VCC = 2.7V, Midscale

REF

= 0mA to 7.5mA Sourcing

I

OUT

= 0mA to 7.5mA Sinking

I

OUT

ICS

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

●

12 14 16 Bits

●

12 14 16 Bits

●

●

●

●

●

●

●

●

●

±0.5 ±1 ±1 LSB

± 1.5 ± 4 ±5 ± 16 ± 19 ±64 LSB

0.02 0.125 0.1 0.5 0.35 2 LSB/mA

0.03 0.125 0.1 0.5 0.42 2 LSB/mA

0.04 0.25 0.2 1 0.7 4 LSB/mA

0.05 0.25 0.2 1 0.8 4 LSB/mA
19 19 19 mV

±1 ± 9 ± 1 ±9 ±1 ± 9mV

±0.15 ±0.7 ±0.15 ±0.7 ±0.15 ±0.7 %FSR

26071727f

2

LTC2607/LTC2617/LTC2627

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V
R

OUT

DC Output Impedance V

±10% –80dB

CC

= VCC = 5V, Midscale;

REF

–15mA ≤ I

= VCC = 2.7V, Midscale;

V

REF

–7.5mA ≤ I

≤ 15mA ● 0.032 0.15 Ω

OUT

≤ 7.5mA ● 0.035 0.15 Ω

OUT

DC Crosstalk (Note 4) Due to Full Scale Output Change (Note 5) ±4 µV

Due to Load Current Change ±3 µV/mA
Due to Powering Down (per channel) ±30 µV

I

SC

Short-Circuit Output Current VCC = 5.5V, V

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

VCC = 2.7V, V

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

REF

REF

= 5.5V

= 2.7V

● 15 36 60 mA

CC

● 15 37 60 mA

● 7.5 22 50 mA

CC

● 7.5 30 50 mA

Reference Input

Input Voltage Range ● 0V

CC

Resistance Normal Mode ● 44 64 80kΩ
Capacitance 30 pF

I

REF

Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Power Supply

V

CC

I

CC

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V
Supply Current VCC = 5V (Note 3) ● 0.66 1.3 mA

= 3V (Note 3) ● 0.52 1 mA

V

CC

DAC Powered Down (Note 3) V
DAC Powered Down (Note 3) V

= 5V ● 0.4 1 µA

CC

= 3V ● 0.10 1 µA

CC

Digital I/O (Note 11)

V

IL

V

IH

V

IL(LDAC)

V

IH(LDAC)

V

IL(CAn)

V

IH(CAn)

R

INH

R

INL

R

INF

V

OL

t

OF

t

SP

I

IN

C

IN

C

B

C

CAX

Low Level Input Voltage (SDA and SCL) ● 0.3V
High Level Input Voltage (SDA and SCL) ● 0.7V

CC

CC

Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V ● 0.8 V

V

= 2.7V to 5.5V ● 0.6 V

CC

High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V ● 2.4 V

= 2.7V to 3.6V ● 2.0 V

V

CC

Low Level Input Voltage on CA
(

n

= 0, 1, 2)

High Level Input Voltage on CAn (n = 0, 1, 2) See Test Circuit 1 ● 0.85V

n

See Test Circuit 1 ● 0.15V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to Set CAn = V

to V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ
to GND to Set CA

n

= GND

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 2MΩ

or GND to Set CAn = Float

to V

CC

Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V
Output Fall Time VO = V

C

= 10pF to 400pF (Note 9)

B

IH(MIN)

to VO = V

, ● 20 + 0.1C

IL(MAX)

B

250 ns

Pulse Width of Spikes Suppressed by Input Filter ● 050ns
Input Leakage 0.1VCC ≤ VIN ≤ 0.9V

CC

● 1 µA

I/O Pin Capacitance Note 12 ● 10 pF
Capacitive Load for Each Bus Line ● 400 pF
External Capacitive Load on Address ● 10 pF

n (n

Pins CA

= 0, 1, 2)

26071727f

V

V
V

V

V

3

LTC2607/LTC2617/LTC2627

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

unloaded, unless otherwise noted.

V

OUT

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

AC Performance

t

S

e

n

Settling Time (Note 7) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 8) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.8 0.8 0.8 V/µs

Capacitive Load Driving 1000 1000 1000 pF

Glitch Impulse At Midscale Transition 12 12 12 nV • s

Multiplying Bandwidth 180180180kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), REFLO = 0V,

A

LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1

P-P

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V

f

SCL

t

HD(STA)

t

LOW

t

HIGH

t

SU(STA)

t

HD(DAT)

t

SU(DAT)

t

r

t

f

t

SU(STO)

t

BUF

t

1

t

2

SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
Data Set-Up Time
Rise Time of Both SDA and SCL Signals (Note 9)
Fall Time of Both SDA and SCL Signals (Note 9)
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Falling Edge of 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition
LDAC Low Pulse Width

= 25°C. (See Figure 1) (Notes 10, 11)

A

The ● denotes specifications which apply over the full operating temperature

●

●

●

●

●

●

●

●

●

●

●

●

●

0 400 kHz

0.6 µs

1.3 µs

0.6 µs

0.6 µs
0 0.9 µs

100 ns
20 + 0.1C
20 + 0.1C

B

B

0.6 µs

1.3 µs

400 ns

20 ns

300 ns
300 ns

Note 1: Absolute maximum ratings are those values beyond which the life of
a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/V
rounded to the nearest whole code. For V
and linearity is defined from code 256 to code 65,535.

Note 3: SDA, SCL and LDAC at 0V or V
Note 4: DC crosstalk is measured with V

measured DAC at midscale, unless otherwise noted.
Note 5: R

= 2kΩ to GND or VCC.

L

= 4.096V and N = 16, kL = 256

REF

, CA0, CA1 and CA2 Floating.

CC

= 5V and V

CC

to code

L

REF

= 4.096V, with the

REF

),

4

Note 6: Inferred from measurement at code k
Note 7: V

3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.
Note 8: V

and half scale – 1. Load is 2k in parallel with 200pF to GND.

Note 9: C
Note 10: All values refer to V
Note 11: These specifications apply to LTC2607/LTC2607-1,

LTC2617/LTC2617-1, LTC2627/LTC2627-1.
Note 12: Guaranteed by design and not production tested.

= 5V, V

CC

= 5V, V

CC

= capacitance of one bus line in pF.

B

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale and

REF

= 4.096V. DAC is stepped ±1LSB between half scale

REF

and V

IH(MIN)

(Note 2) and at full scale.

L

levels.

IL(MAX)

26071727f

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32

VCC = 5V

= 4.096V

V

REF

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0 16384 32768 49152 65535

CODE

2607 G01

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 16384 32768 49152 65535

CODE

2607 G02

32

VCC = 5V

= 4.096V

V

REF

24

16

8

0

INL (LSB)

–8

–16

–24

–32

–50 –30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2607 G03

DNL vs Temperature

1.0
VCC = 5V

= 4.096V

V

0.8

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–50 –30 –10 10 30 50 70 90

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

Settling to ±1LSB Settling of Full-Scale Step

V

OUT

100µV/DIV

9TH CLOCK

SCL

2V/DIV

OF 3RD DATA
BYTE

2607 G04

INL vs V

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0 1 2 3 45

9.7µs

VCC = 5.5V

REF

INL (POS)

INL (NEG)

V

(V)

REF

V

OUT

100µV/DIV

SCL

2V/DIV

2607 G05

DNL vs V

1.5
VCC = 5.5V

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

0 1 2 3 45

12.3µs

9TH CLOCK OF
3RD DATA BYTE

REF

DNL (POS)

DNL (NEG)

V

(V)

REF

2607 G06

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

= 4.096V

REF

2607 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

V

CC

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

REF

= 4.096V

2607 G08

26071727f

5

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2617

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

8

VCC = 5V

= 4.096V

V

REF

6

4

2

0

INL (LSB)

–2

–4

–6

–8

0 4096 8192 12288 16383

CODE

2607 G09

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4096 8192 12288 16383

CODE

LTC2627

Integral Nonlinearity (INL)

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0 1024 2048 3072 4095

CODE

VCC = 5V
V

REF

= 4.096V

2607 G12

Differential Nonlinearity (DNL)

1.0

VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4095

CODE

2607 G10

2607 G13

V

OUT

100µV/DIV

SCL

2V/DIV

V

OUT

1mV/DIV

SCL

2V/DIV

Settling to ±1LSB

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

Settling to ±1LSB

6.8µs

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

V

= 5V, V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

8.9µs

2607 G11

2607 G14

6

26071727f

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Current Limiting

0.10
CODE = MIDSCALE

0.08

0.06

0.04

0.02

(V)

0

OUT

∆V

–0.02

–0.04

–0.06

–0.08

–0.10

–40 –30 –20 –10 0 10 20 30 40

V

REF

V

REF

V

REF

V

REF

= VCC = 5V

= VCC = 3V

= VCC = 3V

= VCC = 5V

I

(mA)

OUT

Zero-Scale Error vs Temperature

3

2.5

2.0

1.5

1.0

ZERO-SCALE ERROR (mV)

0.5

0

–50 –30 –10 10 30 50 70 90

TEMPERATURE (°C)

2607 G15

2607 G18

Load Regulation Offset Error vs Temperature

1.0
CODE = MIDSCALE

0.8

0.6

0.4

0.2

(mV)

0

V

∆V

OUT

–0.2

–0.4

–0.6

–0.8

–1.0

= VCC = 5V

REF

V

= VCC = 3V

REF

–35 –25 –15 – 5 5 15 25 35

I

(mA)

OUT

Gain Error vs Temperature

0.4

0.3

0.2

0.1

0

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

–50 –30 –10 10 30 50 70 90

TEMPERATURE (°C)

2607 G16

2607 G19

3

2

1

0

–1

OFFSET ERROR (mV)

–2

–3

–50 –30 –10 10 30 50 70 90

TEMPERATURE (°C)

Offset Error vs V

3

2

1

0

–1

OFFSET ERROR (mV)

–2

–3

3 3.5 4 4.5 5 5.5

2.5

2607 G17

CC

VCC (V)

2607 G20

Gain Error vs V

0.4

0.3

0.2

0.1

0

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

3 3.5 4 4.5 5 5.5

2.5

CC

VCC (V)

2607 G21

450

400

350

300

250

(nA)

CC

200

I

150

100

Shutdown vs V

I

CC

50

0

2.5

CC

3 3.5 4 4.5 5 5.5

VCC (V)

2607 G22

26071727f

7

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Large-Signal Response

V

OUT

0.5V/DIV

V

= VCC = 5V

REF

1/4-SCALE TO 3/4-SCALE

V

10mV/DIV

2V/DIV

2.5µs/DIV

2607 G23

Headroom at Rails
vs Output Current

5.0

4.5

4.0

3.5

3.0

(V)

2.5

OUT

V

2.0

1.5

1.0

0.5

0

0 1 2 3 4 5 6 7 8910

5V SOURCING

3V SOURCING

3V SINKING

I

(mA)

OUT

5V SINKING

Midscale Glitch Impulse

OUT

9TH CLOCK

SCL

2607 G26

OF 3RD DATA
BYTE

2.5µs/DIV

TRANSITION FROM

MS-1 TO MS

TRANSITION FROM

MS TO MS-1

2606 G26

Power-On Reset to Midscale

V

REF

1V/DIV

V

CC

V

OUT

= V

10mV/DIV

CC

Power-On Reset to Zeroscale

V

CC

1V/DIV

V

OUT

250µs/DIV

500µs/DIV

2607 G27

4mV PEAK

2607 G25

8

Supply Current vs Logic Voltage

950

900

850

800

750

(µA)

700

CC

I

650

600

550

500

0.5 1 1.5 2 2.5 5

0

LOGIC VOLTAGE (V)

3 3.5 4 4.5

VCC = 5V
SWEEP LDAC
OV TO V

CC

2607 G28

Supply Current vs Logic Voltage

1300

1200

1100

1000

(µA)

CC

I

900

800

700

600

500

HYSTERSIS

370mV

12 4

0

LOGIC VOLTAGE (V)

VCC = 5V
SWEEP SCL AND
SDA OV TO V
AND VCC TO OV

3

CC

5

2607 G029

26071727f

LTC2607/LTC2617/LTC2627

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2607/LTC2617/LTC2627

Output Voltage Noise,

Multiplying Bandwidth

0

–3

–6

–9

–12

–15

–18

dB

–21

–24

–27

VCC = 5V

(DC) = 2V

V

REF

–30

–33

–36

(AC) = 0.2V

V

REF

CODE = FULL SCALE

1k

10k 100k

FREQUENCY (Hz)

P-P

1M

2607 G30

0.1Hz to 10Hz

V

OUT

10µV/DIV

012345678910

SECONDS

2607 G31

Short-Circuit Output Current vs
V

(Sinking)

OUT

50

VCC = 5.5V

= 5.6V

V

REF

CODE = 0

40

SWEPT 0V TO V

V

30

10mA/DIV

20

10

0

0

OUT

1

CC

234

1V/DIV

56

2607 G32

Short-Circuit Output Current vs

(Sourcing)

V

OUT

0

VCC = 5.5V

= 5.6V

V

REF

CODE = FULL SCALE

–10

–20

10mA/DIV

–30

–40

–50

SWEPT VCC TO 0V

V

OUT

0

1

234

1V/DIV

56

2607 G33

26071727f

9

LTC2607/LTC2617/LTC2627

UUU

PIN FUNCTIONS

CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I

2

C slave address for the

part (Table 1).

CA1 (Pin 2): Chip Address Bit 1. Tie this pin to V
or leave it floating to select an I

2

C slave address for the

, GND

CC

part (Table 1).

LDAC (Pin 3): Asynchronous DAC Update. A falling edge
of this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part wakes up sleeping DACs without
updating the DAC output. Software power-down is dis­abled when LDAC is low. LDAC is disabled when tied high.

SCL (Pin 4): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source

.

to V

CC

SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in and an open­drain N-channel output during acknowledgment. Requires
a pull-up resistor or current source to V

CC.

CA2 (Pin 6): Chip Address Bit 2. Tie this pin to VCC, GND

2

or leave it floating to select an I

C slave address for the

part (Table 1).

V

(Pin 7): DAC Analog Voltage Output. The output

OUTB

range is V

V

(Pin 8): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

CC

REFLO

to V

REF

.

REF (Pin 9): Reference Voltage Input. The input range
is V

REFLO

≤ V

REF

≤ VCC.

GND (Pin 10): Analog Ground.

REFLO (Pin 11): Reference Low. The voltage at this pin

sets the zero scale (ZS) voltage of all DACs. The V
can be used at voltages up to 1V for V

= 5V, or 100mV

CC

REFLO

pin

for VCC = 3V.

(Pin 12): DAC Analog Voltage Output. The output

V

OUTA

range is V

REFLO

to V

REF

.

Exposed Pad (Pin 13): Ground. Must be soldered to
PCB ground.

10

26071727f

BLOCK DIAGRA

LTC2607/LTC2617/LTC2627

W

V

12

OUTA

1

CA0 CA1

TEST CIRCUITS

REFLO GND REF V

11

12-/14-/16-BIT DAC

2

LDAC

DAC REGISTER

INPUT REGISTER

3

10

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

4

SCL

9

12-/14-/16-BIT DAC

DAC REGISTER

INPUT REGISTER

5

SDA

CC

8

V

OUTB

7

6

CA2

2607 BD

100Ω

V

IH(CAn)/VIL(CAn)

CAn

R

INH/RINL/RINF

Test Circuit 2Test Circuit 1

V

DD

CAn

GND

2607 TC

26071727f

11

9TH CLOCK

OF 3RD

DATA BYTE

t

1

SCL

2607 F02b

SDA

t

f

S

t

r

t

LOW

t

HD(STA)

ALL VOLTAGE LEVELS REFER TO V

IH(MIN)

AND V

IL(MAX)

LEVELS

t

HD(DAT)

t

SU(DAT)

t

SU(STA)

t

HD(STA)

t

SU(STO)

t

SP

t

BUF

t

r

t

f

t

HIGH

SCL

S

PS

2607 F01

ACK

ACK

123456789123456789123456789123456789

2607 F02A

ACK

t

1

START

SDA

SA6 SA5 SA4 SA3

SLAVE ADDRESS

SA2 SA1 SA0

SCL

LDAC

C2C3 C1 C0 A3 A2 A1 A0

ACK

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

t

2

LTC2607/LTC2617/LTC2627

WUW

TI I G DIAGRA S

12

Figure 1

Figure 2a

Figure 2b

26071727f

OPERATIO

LTC2607/LTC2617/LTC2627

U

Power-On Reset

The LTC2607/LTC2617/LTC2627 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2607-1/
LTC2617-1/LTC2627-1 set the voltage outputs to midscale
when power is first applied.

For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2607/
LTC2617/LTC2627 contain circuitry to reduce the power­on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 9) should be kept within the range
–0.3V ≤ V
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 8) is in transition.

≤ VCC + 0.3V (see Absolute Maximum

REF

The value of these pull-up resistors is dependent on the
power supply and can be obtained from the I
tions. For an I
pull-up will be necessary if the bus capacitance is greater
than 200pF.

The LTC2607/LTC2617/LTC2627 are receive-only (slave)
devices. The master can write to the LTC2607/LTC2617/
LTC2627. The LTC2607/LTC2617/LTC2627 do not re­spond to a read from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica­tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.

When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I

Acknowledge

2

C bus operating in the fast mode, an active

2

C device.

2

C specifica-

Transfer Function

The digital-to-analog transfer function is:

k

⎛

V

OUT IDEAL

where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
REF (Pin 6).

Serial Digital Interface

The LTC2607/LTC2617/LTC2627 communicate with a host
using the standard 2-wire I
grams (Figures 1 and 2) show the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.

⎞

=

⎜

⎝

VV V

−

()

REF REFLO REFLO()

⎟

N

⎠

2

2

C interface. The Timing Dia-

+

is the voltage at

REF

The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re­lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2607/LTC2617/LTC2627 respond to a
write by a master in this manner. The LTC2607/LTC2617/
LTC2627 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or float. This results in

26071727f

13

LTC2607/LTC2617/LTC2627

U

OPERATIO

Table 1. Slave Address Map

CA2 CA1 CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0

GND GND GND 0 0 1 0 0 0 0

GND GND FLOAT 0 0 1 0 0 0 1

GND GND V

GND FLOAT GND 0 0 1 0 0 1 1

GND FLOAT FLOAT 0 1 0 0 0 0 0

GND FLOAT V

GND V

GND V

GND V

FLOAT GND GND 0 1 1 0 0 0 1

FLOAT GND FLOAT 0 1 1 0 0 1 0

FLOAT GND V

FLOAT FLOAT GND 1 0 0 0 0 0 0

FLOAT FLOAT FLOAT 1 0 0 0 0 0 1

FLOAT FLOAT V

FLOAT V

FLOAT V

FLOAT V

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND GND 1 0 1 0 0 1 0

GND FLOAT 1 0 1 0 0 1 1

GND V

FLOAT GND 1 1 0 0 0 0 1

FLOAT FLOAT 1 1 0 0 0 1 0

FLOAT V

V

V

V

GLOBAL ADDRESS 1 1 1 0 0 1 1

GND 0100010

CC

FLOAT 0 1 0 0 0 1 1

CC

CC

CC

CC

CC

CC

CC

CC

V

GND 1000011

FLOAT 1 0 1 0 0 0 0

V

GND 1110000

FLOAT 1 1 1 0 0 0 1

V

0010010

CC

0100001

CC

0110000

CC

0110011

CC

1000010

CC

1010001

CC

1100000

CC

1100011

CC

1110010

CC

27 selectable addresses for the part. The slave address
assignments are shown in Table 1.

In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2607, LTC2617 and
LTC2627 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.

The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.

Write Word Protocol

The master initiates communication with the LTC2607/
LTC2617/LTC2627 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2607/
LTC2617/LTC2627 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2607/LTC2617/LTC2627 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2607/LTC2617/LTC2627 executes the com­mand specified in the 24-bit input word.

If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2607/LTC2617/LTC2627 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).

The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
word C3-C0, and 4-bit DAC address A3-A0. The next two
bytes consist of the 16-bit data word. The 16-bit data word
consists of the 16-, 14- or 12-bit input code, MSB to LSB,
followed by 0, 2 or 4 don’t care bits (LTC2607, LTC2617
and LTC2627 respectively). A typical LTC2607 write trans­action is shown in Figure 4.

The command (C3-C0) and address (A3-A0) assignments
are shown in Table 2. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the Block Diagram.

26071727f

14

OPERATIO

U

Write Word Protocol for LTC2607/LTC2617/LTC1627

WA

S

SLAVE ADDRESS

1ST DATA BYTE

A 2ND DATA BYTE A 3RD DATA BYTE A

LTC2607/LTC2617/LTC2627

P

Input Word (LTC2607)

C3

Input Word (LTC2617)

C3

Input Word (LTC2627)

C3

C1

C2

C1

C2

C1

C2

A3

C0

1ST DATA BYTE

A3

C0

1ST DATA BYTE

A3

C0

1ST DATA BYTE

A2

A1

A0

A2

A1

A0

A2

A1

A0

D12

D13D14D15

2ND DATA BYTE

D10

D11D12D13

2ND DATA BYTE 3RD DATA BYTE

D8

D9D10D11

2ND DATA BYTE 3RD DATA BYTE

Figure 3

Table 2

COMMAND*

C3 C2 C1 C0

0000 Write to Input Register

0001 Update (Power Up) DAC Register

0011 Write to and Update (Power Up)

0100 Power Down

1111 No Operation

ADDRESS*

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

1 1 1 1 All DACs

*Command and address codes not shown are reserved and should not be used.

Power-Down Mode

For power-constrained applications, the power-down mode
can be used to reduce the supply current whenever one or
both of the DAC outputs are not needed. When in power­down, the buffer amplifiers, bias circuits and reference input
are disabled and draw essentially zero current. The DAC out­puts are put into a high impedance state, and the output pins
are passively pulled to V

through 90k resistors.

REFLO

Input-register and DAC-register contents are not disturbed
during power-down.

Either or both DAC channels can be put into power-down
mode by using command 0100

in combination with the

b

appropriate DAC address. The 16-bit data word is

INPUT WORD

D11 D10 D9 D 8

D9 D8 D7 D6

D7 D6 D5 D4

D6

D5 D4 D3 D2 D1

D7

D4

D3 D2 D1 D0 X

D5

D2

D1 D0 X X X

D3

3RD DATA BYTE

D0

X

X

2607 F03

ignored. The supply and reference currents are reduced
by approximately 50% for each DAC powered down; the
effective resistance at REF (Pin 9) rises accordingly,
becoming a high-impedance input (typically > 1GΩ)
when both DACs are powered down.

Normal operation can be resumed by executing any com­mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as
described in the next section. The selected DAC is powered
up as its voltage output is updated. When a DAC in
powered-down state is powered up and updated, normal
settling is delayed. If one of the two DACs is in a powered­down state prior to the update command, the power up
delay is 5µs. If on the other hand, both DACs are powered
down, the main bias generation circuit has been automati­cally shut down in addition to the DAC amplifiers and
reference input and so the power up delay time is

12µs (for VCC = 5V) or 30µs (for V

CC

= 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC registers with
the contents of the input registers. Asynchronous update
is disabled when the input word is being clocked into
the part.

26071727f

15

LTC2607/LTC2617/LTC2627

U

OPERATIO

If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC registers to be updated
with the contents of the input registers.

If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DACs but does not cause the outputs
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog­nized, the command specified in the 24-bit word just
transferred is executed and the DAC outputs updated.

The DACs are powered up when LDAC is taken low,
independent of any activity on the I

If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down
command that was specified in the input word. LDAC is
disabled when tied high.

Voltage Output

Both of the two rail-to-rail amplifiers have guaranteed load
regulation when sourcing or sinking up to 15mA at 5V
(7.5mA at 3V).

Load regulation is a measure of the amplifiers’ ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.035Ω when driving a load well away from
the rails.

When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output
devices; e.g., when sinking 1mA, the minimum output
voltage = 30Ω • 1mA = 30mV. See the graph Headroom
at Rails vs Output Current in the Typical Performance
Characteristics section.

The amplifiers are stable driving capacitive loads of up to
1000pF.

2

C bus.

Board Layout

The excellent load regulation performance is achieved in
part by separating the signal and power grounds as REFLO
and GND pins, respectively.

The PC Board should have separate areas for the analog
and digital sections of the circuit. This keeps the digital
signals away from the sensitive analog signals and facili­tates the use of separate digital and analog ground planes
that have minimal interaction with each other.

Digital and analog ground planes should be joined at only
one point, establishing a system star ground. Ideally, the
analog ground plane should be located on the component
side of the board, and should be allowed to run under the
part to shield it from noise. Analog ground should be a
continuous and uninterrupted plane, except for necessary
lead pads and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground. Resistance from the GND pin to the analog power
supply return should be as low as possible. Resistance
here will add directly to the channel resistance of the
output device when sinking load current. When a zero
scale DAC output voltage of zero is required, the REFLO pin
should be connected to system star ground. Any shared
trace resistance between REFLO and GND pins is undesir­able since it adds to the effective DC output impedance
(typically 0.035Ω) of the part.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.

Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full scale
when the REF pin is tied to V
full-scale error (FSE) is positive, the output for the highest
codes limits at V
limiting will occur if V

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.

as shown in Figure 5c. No full-scale

CC

REF

. If V

CC

is less than VCC – FSE.

= VCC and the DAC

REF

16

26071727f

ACK

ACK

123456789123456789123456789123456789

2607 F04

ACK

START

X = DON’T CARE

STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

SDA

SA6 SA5 SA4 SA3 SA2 SA1 SA0

SCL

V

OUT

C2C3

C3 C2 C1 C0 A3 A2 A1 A0

C1 C0 A3 A2 A1 A0

ACK

COMMAND

D15 D14 D13 D12 D11 D10 D9

D8

MS DATA

D7 D6 D5 D4 D3 D2 D1

D0

LS DATA

SA6 SA5 SA4 SA3 SA2 SA1 SA0

WR

SLAVE ADDRESS

OPERATIO

LTC2607/LTC2617/LTC2627

U

Figure 4. Typical LTC2607 Input Waveform—Programming DAC Output for Full Scale

26071727f

17

LTC2607/LTC2617/LTC2627

2607 F05

INPUT CODE

(b)

OUTPUT

VOLTAGE

OFFSET

0V

32, 7680 65, 535

INPUT CODE

OUTPUT

VOLTAGE

(a)

V

REF

= V

CC

V

REF

= V

CC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

U

OPERATIO

18

Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect

of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

26071727f

PACKAGE DESCRIPTIO

LTC2607/LTC2617/LTC2627

U

DE/UE Package

12-Lead Plastic DFN (4mm × 3mm)

(Reference LTC DWG # 05-08-1695)

0.65 ±0.05

3.50 ±0.05

1.70 ±0.05
(2 SIDES)2.20 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

3.30 ±0.05
(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

4.00 ±0.10
(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

NOTE:

1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

0.50
BSC

3.00 ±0.10
(2 SIDES)

0.75 ±0.05

R = 0.20

TYP

1.70 ± 0.10
(2 SIDES)

0.00 – 0.05

R = 0.115

TYP

0.25 ± 0.05

3.30 ±0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

127

16

0.50
BSC

0.38 ± 0.10

PIN 1
NOTCH

(UE12) DFN 0603

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

26071727f

19

LTC2607/LTC2617/LTC2627

U

TYPICAL APPLICATIO

Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

I2C BUS

3
1

2
6

4
5

VCCREF

LDAC
CA0
CA1
CA2

LTC2607

SCL
SDA

GND REFLO

10, 13

73

V

OUTB

OUTPUT B

12 4

V

OUTA

OUTPUT A

RELATED PARTS

DAC

DAC

100Ω

100Ω

V

REF

1V TO 5V

7.5k

7.5k

CH 1

CH 0

28 6

FS

SET

LTC2422

ZS

SET

5

5V5V

V

GND

CC

1

6

2607 TA01

SCK
SDO

CS

F

0.1µF

O

9

8

SPI BUS

7

10

PART NUMBER DESCRIPTION COMMENTS

LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, V

= 2.7V to 5.5V, V

CC

LTC1654 Dual 14-Bit Rail-to-Rail V
LTC1655/LTC1655L Single 16-Bit V
LTC1657/LTC1657L Parallel 5V/3V 16-Bit V
LTC1660/LTC1665 Octal 10/8-Bit V
LTC1664 Quad 10-Bit V

DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched

OUT

OUT

DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

LTC1458L: V

DAC Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

OUT

DACs Low Power, Deglitched, Rail-to-Rail V

= 0V to 4.096V

OUT

= 0V to 2.5V

OUT

OUT

LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step
LTC2600/LTC2610/ Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2620 Output, SPI Serial Interface
LTC2601/LTC2611/ Single 16-/14-/12-Bit V

DACs in 10-Lead DFN 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2621 Output, SPI Serial Interface
LTC2602/LTC2612/ Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2622 Output, SPI Serial Interface
LTC2604/LTC2614/ Quad 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2624 Output, SPI Serial Interface
LTC2605/LTC2615/ Octal 16-/14-/12-Bit V

LTC2625 Output, I
LTC2606/LTC2616/ 16-/14-/12-Bit V

LTC2626 Output, I
LTC2609/LTC2619/ Quad 16-/14-/12-Bit V

LTC2629 Rail-to-Rail Output with Separate V

DACs with I2C Interface 250µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

DACs with I2C Interface 270µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail

OUT

DACs with I2C Interface 250µA Range per DAC, 2.7V to 5.5V Supply Range,

OUT

2

C Interface

2

C Interface

Pins for Each DAC

REF

20

Linear Technology Corporation

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