LINEAR TECHNOLOGY LTC2606, LTC2616, LTC2626 Technical data

CODE

0 16384 32768 49152 65535

DNL (LSB)

2606 G02

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

VCC = 5V
V

REF

= 4.096V

查询LTC2606供应商

FEATURES

■

Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits

■

Guaranteed 16-Bit Monotonic Over Temperature

■

27 Selectable Addresses

■

400kHz I2CTM Interface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 270µA at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale

■

LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset
to Midscale

■

Tiny (3mm × 3mm) 10-Lead DFN Package

U

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2606/LTC2616/LTC2626

16-/14-/12-Bit Rail-to-Rail DACs

with I

2

C Interface

U

DESCRIPTIO

The LTC®2606/LTC2616/LTC2626 are single 16-, 14­and 12-bit,
in a 10-lead DFN package. They have built-in high perfor­mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.

The parts use a 2-wire, I
LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.

The LTC2606/LTC2616/LTC2626 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

2.7V-to-5.5V rail-to-rail voltage output DACs

2

C compatible serial interface. The

BLOCK DIAGRA

SCL

3

INTERFACE

ADDRESS

DECODE

SDA

2

CA0

4

CA1

5

CA2

1

W

9 6

V

CC

INPUT

REGISTER

I2C

CONTROL

LOGIC

I2C

LDAC

10

REF

DAC

REGISTER

GND

8

16-BIT DAC

V

OUT

7

2606 BD

Differential Nonlinearity

(LTC2606)

26061626f

1

LTC2606/LTC2616/LTC2626

A

W

O

LUTEXI TIS

S

A

WUW

U

(Note 1)

ARB

G

Any Pin to GND........................................... –0.3V to 6V

Any Pin to VCC.............................................– 6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

WU

/

PACKAGE

CA2

1

SDA

2

3

SCL

4

CA0

5

CA1

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

O

RDER I FOR ATIO

TOP VIEW

10

9

11

DD PACKAGE

= 125°C, θJA = 43°C/W

8

7

6

LDAC

V

CC

GND

V

OUT

REF

ORDER PART

NUMBER

LTC2606CDD
LTC2606IDD

LTC2606CDD-1
LTC2606IDD-1

DD PART MARKING

LAJX

LAJW

Operating Temperature Range:

LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I .. – 40°C to 85°C

U

ORDER PART

NUMBER

LTC2616CDD
LTC2616IDD

LTC2616CDD-1
LTC2616IDD-1

DD PART MARKING

LBPQ

LBPR

ORDER PART

NUMBER

LTC2626CDD
LTC2626IDD

LTC2626CDD-1
LTC2626IDD-1

DD PART MARKING

LBPS

LBPT

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LECTRICAL C CHARA TERIST

E

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V
unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance

Resolution ● 12 14 16 Bits

Monotonicity (Note 2) ● 12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) ● ±1 ± 4 ±4 ± 16 ±14 ±64 LSB

Load Regulation V

ZSE Zero-Scale Error Code = 0 ● 19 19 19 mV
V

OS

GE Gain Error ● ±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR

Offset Error (Note 5) ● ±1 ±9 ±1 ±9 ±1 ±9mV

VOS Temperature ±5 ±5 ±5 µV/°C

Coefficient

Gain Temperature ±8.5 ±8.5 ±8.5 ppm/°C

Coefficient

= VCC = 5V, Midscale

REF

= 0mA to 15mA Sourcing ● 0.025 0.125 0.1 0.5 0.5 2 LSB/mA

I

OUT

= 0mA to 15mA Sinking ● 0.05 0.125 0.2 0.5 0.7 2 LSB/mA

I

OUT

V

= VCC = 2.7V, Midscale

REF

= 0mA to 7.5mA Sourcing ● 0.05 0.25 0.2 1 0.9 4 LSB/mA

I

OUT

= 0mA to 7.5mA Sinking ● 0.1 0.25 0.4 1 1.5 4 LSB/mA

I

OUT

ICS

The ● denotes specifications which apply over the full operating

unloaded,

OUT

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

2

26061626f

LTC2606/LTC2616/LTC2626

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V

A

unloaded,

OUT

unless otherwise noted. (Note 11)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V
R

OUT

I

SC

DC Output Impedance V

Short-Circuit Output Current VCC = 5.5V, V

Reference Input

Input Voltage Range ● 0V

Resistance Normal Mode ● 88 124 160 kΩ

Capacitance 15 pF
I

REF

Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Power Supply

V

CC

I

CC

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V

Supply Current VCC = 5V (Note 3) ● 0.340 0.5 mA

Digital I/O (Note 11)

V

IL

Low Level Input Voltage ● –0.5 0.3V

(SDA and SCL)
V

IH

High Level Input Voltage (Note 8) ● 0.7V

(SDA and SCL)
V

IL(LDAC)

V

IH(LDAC)

V

IL(CAn)

V

IH(CAn)

R

INH

R

INL

Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V ● 0.8 V

High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V ● 2.4 V

Low Level Input Voltage on CA

n

= 0, 1, 2)

(

High Level Input Voltage on CA

n

= 0, 1, 2)

(

n

n

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to Set CAn = V

to V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to GND to Set CAn = GND
R

INF

V

OL

t

OF

t

SP

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 2MΩ

or GND to Set CAn = Float

to V

CC

Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V

Output Fall Time VO = V

Pulse Width of Spikes Suppressed ● 050ns

by Input Filter
I

IN

C

IN

C

B

C

CAX

Input Leakage 0.1VCC ≤ VIN ≤ 0.9V

I/O Pin Capacitance ● 10 pF

Capacitive Load for Each Bus Line ● 400 pF

External Capacitive Load on Address ● 10 pF

n (n

Pins CA

= 0, 1, 2)

= ±10% –81 dB

CC

= VCC = 5V, Midscale; –15mA ≤ I

REF

= VCC = 2.7V, Midscale; –7.5mA ≤ I

V

REF

= 5.5V

REF

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

VCC = 2.7V, V

REF

= 2.7V

Code: Zero Scale; Forcing Output to V

≤ 15mA ● 0.05 0.15 Ω

OUT

≤ 7.5mA ● 0.06 0.15 Ω

OUT

CC

CC

● 15 34 60 mA

● 15 36 60 mA

● 7.5 22 50 mA

Code: Full Scale; Forcing Output to GND ● 7.5 29 50 mA

CC

= 3V (Note 3) ● 0.27 0.4 mA

V

CC

DAC Powered Down (Note 3) V

= 5V ● 0.35 1 µA

CC

DAC Powered Down (Note 3) VCC = 3V ● 0.10 1 µA

CC

CC

VCC = 2.7V to 5.5V ● 0.6 V

= 2.7V to 3.6V ● 2.0 V

V

CC

See Test Circuit 1 ● 0.15V

See Test Circuit 1 ● 0.85V

to VO = V

IH(MIN)

= 10pF to 400pF (Note 9)

C

B

CC

, ● 20 + 0.1C

IL(MAX)

● 1 µA

CC

B

CC

250 ns

26061626f

V

V

V

V

V

3

LTC2606/LTC2616/LTC2626

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V

A

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

AC Performance

t

S

e

n

Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 7) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.75 0.75 0.75 V/µs

Capacitive Load Driving 1000 1000 1000 pF

Glitch Impulse At Midscale Transition 12 12 12 nV • s

Multiplying Bandwidth 180 180 180 kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

P-P

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V

f

SCL

t

HD(STA)

t

LOW

t

HIGH

t

SU(STA)

t

HD(DAT)

t

SU(DAT)

t

r

t

f

t

SU(STO)

t

BUF

t

1

t

2

SCL Clock Frequency ● 0 400 kHz

Hold Time (Repeated) Start Condition ● 0.6 µs

Low Period of the SCL Clock Pin ● 1.3 µs

High Period of the SCL Clock Pin ● 0.6 µs

Set-Up Time for a Repeated Start Condition ● 0.6 µs

Data Hold Time ● 0 0.9 µs

Data Set-Up Time ● 100 ns

Rise Time of Both SDA and SCL Signals (Note 9) ● 20 + 0.1C

Fall Time of Both SDA and SCL Signals (Note 9) ● 20 + 0.1C

Set-Up Time for Stop Condition ● 0.6 µs

Bus Free Time Between a Stop and Start Condition ● 1.3 µs

Falling Edge of 9th Clock of the 3rd Input Byte ● 400 ns

to LDAC High or Low Transition

LDAC Low Pulse Width ● 20 ns

The ● denotes specifications which apply over the full operating temperature

B

B

300 ns
300 ns

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

N

– 1, where N is the resolution and kL is given by kL = 0.016(2N/V

2
rounded to the nearest whole code. For V
256 and linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),

code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full scale.

CC

.

= 4.096V and N = 16, kL =

REF

to code

L

REF

),

4

Note 6: VCC = 5V, V
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 7: V
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

Note 8: Maximum V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to V
Note 11: These specifications apply to LTC2606/LTC2606-1,

LTC2616/LTC2616-1, LTC2626/LTC2626-1.

= 5V, V

CC

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

REF

= 4.096V. DAC is stepped ±1LSB between half

REF

= V

IH

CC(MAX)

IH(MIN)

+ 0.5V

and V

IL(MAX)

levels.

26061626f

LTC2606/LTC2616/LTC2626

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

VCC = 5V

= 4.096V

V

REF

16384 32768 49152 65535

CODE

2606 G01

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 16384 32768 49152 65535

CODE

2606 G02

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

–50

VCC = 5V

= 4.096V

V

REF

–30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2606 G03

DNL vs Temperature

1.0
VCC = 5V

= 4.096V

V

0.8

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–50

–30 –10 10 30 50 70 90

TEMPERATURE (°C)

100µV/DIV

DNL (POS)

DNL (NEG)

2606 G04

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

INL vs V

REF

VCC = 5.5V

INL (POS)

INL (NEG)

1 2 3 4 5

V

(V)

REF

2606 G05

Settling to ±1LSB Settling of Full-Scale Step

V

OUT

SCL

2V/DIV

9TH CLOCK
OF 3RD DATA
BYTE

9.7µs

V

OUT

100µV/DIV

SCR

2V/DIV

DNL vs V

1.5
VCC = 5.5V

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

0

12.3µs

9TH CLOCK OF
3RD DATA BYTE

REF

DNL (POS)

DNL (NEG)

1 2 3 4 5

V

(V)

REF

2606 G06

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

2606 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

V

CC

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

REF

= 4.096V

2606 G08

26061626f

5

LTC2606/LTC2616/LTC2626

2µs/DIV

2606 G14

V

OUT

1mV/DIV

SCL

2V/DIV

V

CC

= 5V, V

REF

= 4.096V
1/4-SCALE TO 3/4-SCALE STEP
R

L

= 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

6.8µs

9TH CLOCK
OF 3RD DATA
BYTE

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2616

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

8

6

4

2

0

INL (LSB)

–2

–4

–6

–8

0

VCC = 5V

= 4.096V

V

REF

4096 8192 12288 16383

CODE

2606 G09

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 4096 8192 12288 16383

CODE

LTC2626

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0

VCC = 5V

= 4.096V

V

REF

1024 2048 3072 4095

CODE

2606 G12

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4095

CODE

2606 G10

2606 G13

V

OUT

100µV/DIV

SCL

2V/DIV

Settling to ±1LSB

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

= 4.096V

REF

Settling to ±1LSB

8.9µs

2606 G11

6

26061626f