LINEAR TECHNOLOGY LTC2606, LTC2616, LTC2626 Technical data

CODE

0 16384 32768 49152 65535

DNL (LSB)

2606 G02

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

VCC = 5V
V

REF

= 4.096V

查询LTC2606供应商

FEATURES

■

Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits

■

Guaranteed 16-Bit Monotonic Over Temperature

■

27 Selectable Addresses

■

400kHz I2CTM Interface

■

Wide 2.7V to 5.5V Supply Range

■

Low Power Operation: 270µA at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale

■

LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset
to Midscale

■

Tiny (3mm × 3mm) 10-Lead DFN Package

U

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2606/LTC2616/LTC2626

16-/14-/12-Bit Rail-to-Rail DACs

with I

2

C Interface

U

DESCRIPTIO

The LTC®2606/LTC2616/LTC2626 are single 16-, 14­and 12-bit,
in a 10-lead DFN package. They have built-in high perfor­mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.

The parts use a 2-wire, I
LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.

The LTC2606/LTC2616/LTC2626 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

2.7V-to-5.5V rail-to-rail voltage output DACs

2

C compatible serial interface. The

BLOCK DIAGRA

SCL

3

INTERFACE

ADDRESS

DECODE

SDA

2

CA0

4

CA1

5

CA2

1

W

9 6

V

CC

INPUT

REGISTER

I2C

CONTROL

LOGIC

I2C

LDAC

10

REF

DAC

REGISTER

GND

8

16-BIT DAC

V

OUT

7

2606 BD

Differential Nonlinearity

(LTC2606)

26061626f

1

LTC2606/LTC2616/LTC2626

A

W

O

LUTEXI TIS

S

A

WUW

U

(Note 1)

ARB

G

Any Pin to GND........................................... –0.3V to 6V

Any Pin to VCC.............................................– 6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Storage Temperature Range ................ – 65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

WU

/

PACKAGE

CA2

1

SDA

2

3

SCL

4

CA0

5

CA1

10-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

O

RDER I FOR ATIO

TOP VIEW

10

9

11

DD PACKAGE

= 125°C, θJA = 43°C/W

8

7

6

LDAC

V

CC

GND

V

OUT

REF

ORDER PART

NUMBER

LTC2606CDD
LTC2606IDD

LTC2606CDD-1
LTC2606IDD-1

DD PART MARKING

LAJX

LAJW

Operating Temperature Range:

LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I .. – 40°C to 85°C

U

ORDER PART

NUMBER

LTC2616CDD
LTC2616IDD

LTC2616CDD-1
LTC2616IDD-1

DD PART MARKING

LBPQ

LBPR

ORDER PART

NUMBER

LTC2626CDD
LTC2626IDD

LTC2626CDD-1
LTC2626IDD-1

DD PART MARKING

LBPS

LBPT

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LECTRICAL C CHARA TERIST

E

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V
unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance

Resolution ● 12 14 16 Bits

Monotonicity (Note 2) ● 12 14 16 Bits
DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) ● ±1 ± 4 ±4 ± 16 ±14 ±64 LSB

Load Regulation V

ZSE Zero-Scale Error Code = 0 ● 19 19 19 mV
V

OS

GE Gain Error ● ±0.1 ±0.7 ±0.1 ±0.7 ±0.1 ±0.7 %FSR

Offset Error (Note 5) ● ±1 ±9 ±1 ±9 ±1 ±9mV

VOS Temperature ±5 ±5 ±5 µV/°C

Coefficient

Gain Temperature ±8.5 ±8.5 ±8.5 ppm/°C

Coefficient

= VCC = 5V, Midscale

REF

= 0mA to 15mA Sourcing ● 0.025 0.125 0.1 0.5 0.5 2 LSB/mA

I

OUT

= 0mA to 15mA Sinking ● 0.05 0.125 0.2 0.5 0.7 2 LSB/mA

I

OUT

V

= VCC = 2.7V, Midscale

REF

= 0mA to 7.5mA Sourcing ● 0.05 0.25 0.2 1 0.9 4 LSB/mA

I

OUT

= 0mA to 7.5mA Sinking ● 0.1 0.25 0.4 1 1.5 4 LSB/mA

I

OUT

ICS

The ● denotes specifications which apply over the full operating

unloaded,

OUT

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

2

26061626f

LTC2606/LTC2616/LTC2626

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V

A

unloaded,

OUT

unless otherwise noted. (Note 11)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V
R

OUT

I

SC

DC Output Impedance V

Short-Circuit Output Current VCC = 5.5V, V

Reference Input

Input Voltage Range ● 0V

Resistance Normal Mode ● 88 124 160 kΩ

Capacitance 15 pF
I

REF

Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Power Supply

V

CC

I

CC

Positive Supply Voltage For Specified Performance ● 2.7 5.5 V

Supply Current VCC = 5V (Note 3) ● 0.340 0.5 mA

Digital I/O (Note 11)

V

IL

Low Level Input Voltage ● –0.5 0.3V

(SDA and SCL)
V

IH

High Level Input Voltage (Note 8) ● 0.7V

(SDA and SCL)
V

IL(LDAC)

V

IH(LDAC)

V

IL(CAn)

V

IH(CAn)

R

INH

R

INL

Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V ● 0.8 V

High Level Input Voltage (LDAC) VCC = 2.7V to 5.5V ● 2.4 V

Low Level Input Voltage on CA

n

= 0, 1, 2)

(

High Level Input Voltage on CA

n

= 0, 1, 2)

(

n

n

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to Set CAn = V

to V

CC

CC

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 10 kΩ

to GND to Set CAn = GND
R

INF

V

OL

t

OF

t

SP

Resistance from CAn (n = 0, 1, 2) See Test Circuit 2 ● 2MΩ

or GND to Set CAn = Float

to V

CC

Low Level Output Voltage Sink Current = 3mA ● 0 0.4 V

Output Fall Time VO = V

Pulse Width of Spikes Suppressed ● 050ns

by Input Filter
I

IN

C

IN

C

B

C

CAX

Input Leakage 0.1VCC ≤ VIN ≤ 0.9V

I/O Pin Capacitance ● 10 pF

Capacitive Load for Each Bus Line ● 400 pF

External Capacitive Load on Address ● 10 pF

n (n

Pins CA

= 0, 1, 2)

= ±10% –81 dB

CC

= VCC = 5V, Midscale; –15mA ≤ I

REF

= VCC = 2.7V, Midscale; –7.5mA ≤ I

V

REF

= 5.5V

REF

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

VCC = 2.7V, V

REF

= 2.7V

Code: Zero Scale; Forcing Output to V

≤ 15mA ● 0.05 0.15 Ω

OUT

≤ 7.5mA ● 0.06 0.15 Ω

OUT

CC

CC

● 15 34 60 mA

● 15 36 60 mA

● 7.5 22 50 mA

Code: Full Scale; Forcing Output to GND ● 7.5 29 50 mA

CC

= 3V (Note 3) ● 0.27 0.4 mA

V

CC

DAC Powered Down (Note 3) V

= 5V ● 0.35 1 µA

CC

DAC Powered Down (Note 3) VCC = 3V ● 0.10 1 µA

CC

CC

VCC = 2.7V to 5.5V ● 0.6 V

= 2.7V to 3.6V ● 2.0 V

V

CC

See Test Circuit 1 ● 0.15V

See Test Circuit 1 ● 0.85V

to VO = V

IH(MIN)

= 10pF to 400pF (Note 9)

C

B

CC

, ● 20 + 0.1C

IL(MAX)

● 1 µA

CC

B

CC

250 ns

26061626f

V

V

V

V

V

3

LTC2606/LTC2616/LTC2626

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at T

The ● denotes specifications which apply over the full operating

= 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), V

A

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS

AC Performance

t

S

e

n

Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 7) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.75 0.75 0.75 V/µs

Capacitive Load Driving 1000 1000 1000 pF

Glitch Impulse At Midscale Transition 12 12 12 nV • s

Multiplying Bandwidth 180 180 180 kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

P-P

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.7V to 5.5V

f

SCL

t

HD(STA)

t

LOW

t

HIGH

t

SU(STA)

t

HD(DAT)

t

SU(DAT)

t

r

t

f

t

SU(STO)

t

BUF

t

1

t

2

SCL Clock Frequency ● 0 400 kHz

Hold Time (Repeated) Start Condition ● 0.6 µs

Low Period of the SCL Clock Pin ● 1.3 µs

High Period of the SCL Clock Pin ● 0.6 µs

Set-Up Time for a Repeated Start Condition ● 0.6 µs

Data Hold Time ● 0 0.9 µs

Data Set-Up Time ● 100 ns

Rise Time of Both SDA and SCL Signals (Note 9) ● 20 + 0.1C

Fall Time of Both SDA and SCL Signals (Note 9) ● 20 + 0.1C

Set-Up Time for Stop Condition ● 0.6 µs

Bus Free Time Between a Stop and Start Condition ● 1.3 µs

Falling Edge of 9th Clock of the 3rd Input Byte ● 400 ns

to LDAC High or Low Transition

LDAC Low Pulse Width ● 20 ns

The ● denotes specifications which apply over the full operating temperature

B

B

300 ns
300 ns

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

N

– 1, where N is the resolution and kL is given by kL = 0.016(2N/V

2
rounded to the nearest whole code. For V
256 and linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),

code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full scale.

CC

.

= 4.096V and N = 16, kL =

REF

to code

L

REF

),

4

Note 6: VCC = 5V, V
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 7: V
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

Note 8: Maximum V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to V
Note 11: These specifications apply to LTC2606/LTC2606-1,

LTC2616/LTC2616-1, LTC2626/LTC2626-1.

= 5V, V

CC

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

REF

= 4.096V. DAC is stepped ±1LSB between half

REF

= V

IH

CC(MAX)

IH(MIN)

+ 0.5V

and V

IL(MAX)

levels.

26061626f

LTC2606/LTC2616/LTC2626

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

VCC = 5V

= 4.096V

V

REF

16384 32768 49152 65535

CODE

2606 G01

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 16384 32768 49152 65535

CODE

2606 G02

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

–50

VCC = 5V

= 4.096V

V

REF

–30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2606 G03

DNL vs Temperature

1.0
VCC = 5V

= 4.096V

V

0.8

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

–50

–30 –10 10 30 50 70 90

TEMPERATURE (°C)

100µV/DIV

DNL (POS)

DNL (NEG)

2606 G04

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

INL vs V

REF

VCC = 5.5V

INL (POS)

INL (NEG)

1 2 3 4 5

V

(V)

REF

2606 G05

Settling to ±1LSB Settling of Full-Scale Step

V

OUT

SCL

2V/DIV

9TH CLOCK
OF 3RD DATA
BYTE

9.7µs

V

OUT

100µV/DIV

SCR

2V/DIV

DNL vs V

1.5
VCC = 5.5V

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

0

12.3µs

9TH CLOCK OF
3RD DATA BYTE

REF

DNL (POS)

DNL (NEG)

1 2 3 4 5

V

(V)

REF

2606 G06

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

2606 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

V

CC

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

REF

= 4.096V

2606 G08

26061626f

5

LTC2606/LTC2616/LTC2626

2µs/DIV

2606 G14

V

OUT

1mV/DIV

SCL

2V/DIV

V

CC

= 5V, V

REF

= 4.096V
1/4-SCALE TO 3/4-SCALE STEP
R

L

= 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

6.8µs

9TH CLOCK
OF 3RD DATA
BYTE

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2616

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

8

6

4

2

0

INL (LSB)

–2

–4

–6

–8

0

VCC = 5V

= 4.096V

V

REF

4096 8192 12288 16383

CODE

2606 G09

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 4.096V

V

REF

0

0 4096 8192 12288 16383

CODE

LTC2626

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

2.0

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

–2.0

0

VCC = 5V

= 4.096V

V

REF

1024 2048 3072 4095

CODE

2606 G12

1.0
VCC = 5V

0.8

= 4.096V

V

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 1024 2048 3072 4095

CODE

2606 G10

2606 G13

V

OUT

100µV/DIV

SCL

2V/DIV

Settling to ±1LSB

9TH CLOCK
OF 3RD DATA
BYTE

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

= 4.096V

REF

Settling to ±1LSB

8.9µs

2606 G11

6

26061626f

LTC2606/LTC2616/LTC2626

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606/LTC2616/LTC2626

Current Limiting

0.10
CODE = MIDSCALE

(V)

OUT

∆V

–0.02

–0.04

–0.06

–0.08

–0.10

0.08

0.06

0.04

0.02

0

–40

V

= VCC = 5V

REF

V

= VCC = 3V

REF

V

= VCC = 3V

REF

V

= VCC = 5V

REF

–30 –20 –10 0 10 20 30 40

I

OUT

(mA)

Zero-Scale Error vs Temperature

3

2.5

2.0

1.5

1.0

ZERO-SCALE ERROR (mV)

0.5

0

–50

–30 –10 10 30 50 70 90

TEMPERATURE (°C)

2606 G17

2606 G20

Load Regulation Offset Error vs Temperature

1.0
CODE = MIDSCALE

0.8

0.6

0.4

0.2

(mV)

0

V

∆V

OUT

–0.2

–0.4

–0.6

–0.8

–1.0

= VCC = 5V

REF

V

= VCC = 3V

REF

–35 –25 –15 –5 5 15 25 35

I

OUT

(mA)

2606 G18

3

2

1

0

–1

OFFSET ERROR (mV)

–2

–3

–50

–30 –10 10 30 50 70 90

TEMPERATURE (°C)

Gain Error vs Temperature Offset Error vs V

0.4

0.3

0.2

0.1

0

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

–50

–30 –10 10 30 50 70 90

TEMPERATURE (°C)

2606 G21

3

2

1

0

–1

OFFSET ERROR (mV)

–2

–3

2.5 3

3.5 4 4.5 5 5.5
VCC (V)

2606 G19

CC

2606 G22

Gain Error vs V

0.4

0.3

0.2

0.1

0

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

2.5 3

CC

3.5 4 4.5 5 5.5
VCC (V)

2606 G23

ICC Shutdown vs V

450

400

350

300

250

(nA)

CC

200

I

150

100

50

0

2.5 3

CC

3.5 4 4.5 5 5.5
VCC (V)

2606 G24

26061626f

7

LTC2606/LTC2616/LTC2626

1V/DIV

500µs/DIV

2606 G29

V

CC

V

OUT

V

REF

= V

CC

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606/LTC2616/LTC2626

V

OUT

0.5V/DIV

Large-Signal Response

V

= VCC = 5V

REF

1/4-SCALE TO 3/4-SCALE

2.5µs/DIV

Headroom at Rails
vs Output Current

5.0

4.5

4.0

3.5

3.0

(V)

2.5

OUT

V

2.0

1.5

1.0

0.5

0

0

1 2 3 4 5 6 7 8 910

2606 G25

5V SOURCING

3V SOURCING

3V SINKING

I

(mA)

OUT

V

OUT

10mV/DIV

SCL

2V/DIV

5V SINKING

Midscale Glitch Impulse

TRANSITION FROM

MS-1 TO MS

TRANSITION FROM

9TH CLOCK
OF 3RD DATA
BYTE

2606 G28

MS TO MS-1

2.5µs/DIV

Power-On Reset Glitch

V

CC

1V/DIV

V

OUT

10mV/DIV

2606 G26

Power-On Reset to Midscale

250µs/DIV

4mV PEAK

2606 G27

Supply Current vs Logic Voltage

650

600

550

500

450

(µA)

CC

I

400

350

300

– 250

0

123 53.50.5 1.5 2.5 4.5

LOGIC VOLTAGE (V)

VCC = 5V
SWEEP LDAC
0V TO V

CC

4

2606 G30

Supply Current vs Logic Voltage

(µA)

CC

I

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

HYSTERESIS

0

370mV

10.5

21.5

LOGIC VOLTAGE (V)

VCC = 5V
SWEEP SCL AND
SDA 0V TO V
AND VCC TO 0V

3 3.5 4.5

2.5

CC

4

5

2606 G31

26061626f

8

LTC2606/LTC2616/LTC2626

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606/LTC2616/LTC2626

Output Voltage Noise,

Multiplying Bandwidth

0

–3

–6

–9

–12

–15

–18

dB

–21

–24

–27

VCC = 5V

(DC) = 2V

V

REF

–30

–33

–36

(AC) = 0.2V

V

REF

CODE = FULL SCALE

1k

10k 100k

FREQUENCY (Hz)

P-P

1M

2606 G32

0.1Hz to 10Hz

V

OUT

10µV/DIV

012345678910

SECONDS

2606 G33

Short-Circuit Output Current vs
V

(Sinking)

OUT

0mA

10mA/DIV

VCC = 5.5V

= 5.6V

V

REF

CODE = 0

SWEPT 0V TO V

V

OUT

1V/DIV

Short-Circuit Output Current vs
V

(Sourcing)

OUT

0mA

10mA/DIV

VCC = 5.5V

= 5.6V

V

REF

CODE = FULL SCALE

SWEPT VCC TO 0V

CC

2606 G18

V

OUT

1V/DIV

2606 G19

26061626f

9

LTC2606/LTC2616/LTC2626

UUU

PIN FUNCTIONS

CA2 (Pin 1): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it floating to select an I
(Table 1).

SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to V

SCL (Pin 3): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source
to VCC.

CA0 (Pin 4): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 1).

CA1 (Pin 5): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it floating to select an I2C slave address for the part
(Table 1).

2

C slave address for the part

.

CC

REF (Pin 6): Reference Voltage Input. 0V ≤ V

(Pin 7): DAC Analog Voltage Output. The output

V

OUT

range is 0V to V

GND (Pin 8): Analog Ground.

VCC (Pin 9): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

LDAC (Pin 10): Asynchronous DAC Update. A falling edge

on this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part does not update the DAC output.
Software power-down is disabled when LDAC is low.

Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.

REF

.

REF

≤ VCC.

10

26061626f

BLOCK DIAGRA

W

9 6

V

CC

LTC2606/LTC2616/LTC2626

REF

SCL

3

SDA

2

CA0

4

CA1

5

CA2

1

TEST CIRCUITS

I2C

INTERFACE

I2C

ADDRESS

DECODE

CONTROL

LOGIC

LDAC

10

INPUT

REGISTER

DAC

REGISTER

GND

8

16-BIT DAC

Test Circuit 2Test Circuit 1

V

OUT

7

2606 BD

V

DD

100Ω

V

IH(CAn)/VIL(CAn)

R

CA

n

INH/RINL/RINF

CA

n

GND

2606 TC

26061626f

11

ACK

ACK

123456789123456789123456789123456789

2606 F02A

ACK

t

1

START

SDA

A6 A5 A4 A3

SLAVE ADDRESS

A2 A1 A0

SCL

LDAC

C2C3 C1 C0 X X X X

ACK

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

t

2

9TH CLOCK

OF 3RD

DATA BYTE

t

1

SCL

LDAC

2606 F02b

SDA

t

f

S

t

r

t

LOW

t

HD(STA)

ALL VOLTAGE LEVELS REFER TO V

IH(MIN)

AND V

IL(MAX)

LEVELS

t

HD(DAT)

t

SU(DAT)

t

SU(STA)

t

HD(STA)

t

SU(STO)

t

SP

t

BUF

t

r

t

f

t

HIGH

SCL

S

P

S

2606 F01

LTC2606/LTC2616/LTC2626

WUW

TI I G DIAGRA S

12

Figure 1

Figure 2a

Figure 2b

26061626f

OPERATIO

LTC2606/LTC2616/LTC2626

U

Power-On Reset

The LTC2606/LTC2616/LTC2626 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2606-1/
LTC2616-1/LTC2626-1 set the voltage outputs to midscale
when power is first applied.

For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2606/
LTC2616/LTC2626 contain circuitry to reduce the power­on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range
–0.3V ≤ V
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at VCC (Pin 9) is in transition.

Transfer Function

The digital-to-analog transfer function is:

V

OUT IDEAL

where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
(Pin 6).

Serial Digital Interface

The LTC2606/LTC2616/LTC2626 communicate with a host
using the standard 2-wire I2C interface. The Timing Dia­grams (Figures 1 and 2) show the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the

≤ VCC + 0.3V (see Absolute Maximum

REF

k

⎛

⎞

=

V

⎜

⎟

REF()

N

⎝

⎠

2

is the voltage at REF

REF

power supply and can be obtained from the I2C specifica­tions. For an I2C bus operating in the fast mode, an active
pull-up will be necessary if the bus capacitance is greater
than 200pF.

The LTC2606/LTC2616/LTC2626 are receive-only (slave)
devices. The master can write to the LTC2606/LTC2616/
LTC2626. The LTC2606/LTC2616/LTC2626 do not re­spond to a read from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica­tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.

When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I2C device.

Acknowledge

The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re­lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2606/LTC2616/LTC2626 respond to a
write by a master in this manner. The LTC2606/LTC2616/
LTC2626 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: VCC, GND or float. This results in
27 selectable addresses for the part. The slave address
assignments are shown in Table 1.

26061626f

13

LTC2606/LTC2616/LTC2626

U

OPERATIO

Table 1. Slave Address Map

CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0

GND GND GND 0 0 1 0 0 0 0

GND GND FLOAT 0 0 1 0 0 0 1

GND GND V

GND FLOAT GND 0 0 1 0 0 1 1

GND FLOAT FLOAT 0 1 0 0 0 0 0

GND FLOAT V

GND V

GND V

GND V

FLOAT GND GND 0 1 1 0 0 0 1

FLOAT GND FLOAT 0 1 1 0 0 1 0

FLOAT GND V

FLOAT FLOAT GND 1 0 0 0 0 0 0

FLOAT FLOAT FLOAT 1 0 0 0 0 0 1

FLOAT FLOAT V

FLOAT V

FLOAT V

FLOAT V

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND GND 1 0 1 0 0 1 0

GND FLOAT 1 0 1 0 0 1 1

GND V

FLOAT GND 1 1 0 0 0 0 1

FLOAT FLOAT 1 1 0 0 0 1 0

FLOAT V

V

V

V

GLOBAL ADDRESS 1 1 1 0 0 1 1

GND 0100010

CC

FLOAT 0 1 0 0 0 1 1

CC

CC

CC

CC

CC

CC

CC

CC

V

GND 1000011

FLOAT 1 0 1 0 0 0 0

V

GND 1110000

FLOAT 1 1 1 0 0 0 1

V

0010010

CC

0100001

CC

0110000

CC

0110011

CC

1000010

CC

1010001

CC

1100000

CC

1100011

CC

1110010

CC

In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I2C bus. The global address is a 7-bit
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.

Write Word Protocol

The master initiates communication with the LTC2606/
LTC2616/LTC2626 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2606/LTC2616/LTC2626 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2606/LTC2616/LTC2626 executes the com­mand specified in the 24-bit input word.

If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).

The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
and four don’t care bits. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626
respectively).

A typical LTC2606 write transaction is shown

in Figure 4.

The command assignments (C3-C0) are shown in Table 2.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an ana­log voltage at the DAC output. The update operation also
powers up the DAC if it had been in power-down mode. The
data path and registers are shown in the Block Diagram.

Power-Down Mode

The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.

14

For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the DAC
output is not needed. When in power-down, the buffer
amplifier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into

26061626f

OPERATIO

U

Write Word Protocol for LTC2606/LTC2616/LTC1626

S

SLAVE ADDRESS

WA

1ST DATA BYTE

A 2ND DATA BYTE A 3RD DATA BYTE A P

LTC2606/LTC2616/LTC2626

Input Word (LTC2606)

C3

Input Word (LTC2616)

C3

Input Word (LTC2626)

C3

C1

C2

C1

C2

C1

C2

X

C0

1ST DATA BYTE

X

C0

1ST DATA BYTE

X

C0

1ST DATA BYTE

X

X

X

X

X

X

X

X

X

D12

D13D14D15

2ND DATA BYTE

D10

D11D12D13

2ND DATA BYTE 3RD DATA BYTE

D8

D9D10D11

2ND DATA BYTE 3RD DATA BYTE

Figure 3

Table 2

COMMAND*

C3 C2 C1 C0

0000 Write to Input Register

0001 Update (Power Up) DAC Register

0011 Write to and Update (Power Up)

0100 Power Down

1111 No Operation

*Command codes not shown are reserved and should not be used.

a high impedance state, and the output pin is passively
pulled to ground through 90k resistors. Input- and DAC­register contents are not disturbed during power-down.

The DAC channel can be put into power-down mode by
using command 0100b. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective
resistance at REF becomes a high impedance input
(typically > 1GΩ).

Normal operation can be resumed by executing any com­mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as de­scribed in the next section. The DAC is powered up as its
voltage output is updated. When the DAC in powered­down state is powered up and updated, normal settling is
delayed. The main bias generation circuit block has been

INPUT WORD

D11 D10 D9 D8

D9 D8 D 7 D6

D7 D6 D 5 D4

D6

D5 D4 D3 D2 D1

D7

D4

D3 D2 D1 D0 X

D5

D2

D1 D0 X X X

D3

3RD DATA BYTE

D0

X

X

2606 F03

automatically shut down in addition to the DAC amplifier
and reference input and so the power up delay time is

12µs (for VCC = 5V) or 30µs (for V

CC

= 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC register with
the contents of the input register. Asynchronous update is
disabled when the input word is being clocked into the part.

If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.

If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog­nized, the command specified in the 24-bit word just
transferred is executed and the DAC output is updated.

The DAC is powered up when LDAC is taken low, indepen­dent of any activity on the I2C bus.

If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down com­mand that was specified in the input word.

26061626f

15

LTC2606/LTC2616/LTC2626

U

OPERATIO

Voltage Output

The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex­pressed in LSB/mA.

DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers’ DC output
impedance is 0.050Ω when driving a load well away from
the rails.

When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω • 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteris­tics section.

The amplifier is stable driving capacitive loads of up to
1000pF.

Board Layout

The excellent load regulation performance is achieved in
part by keeping “signal” and “power” grounds separated
internally and by reducing shared internal resistance.

The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.

The PC board should have separate areas for the analog and
digital sections of the circuit. This keeps digital signals away

from sensitive analog signals and facilitates the use of
separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each other.

Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu­ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.

The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star ground
should be as low as possible. Resistance here will add
directly to the effective DC output impedance of the device
(typically 0.050Ω). Note that the LTC2606/LTC2616/
LTC2626 are no more susceptible to these effects than other
parts of their type; on the contrary, they allow layout-based
performance improvements to shine rather than limiting
attainable performance with excessive internal resistance.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.

Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full scale
when the REF pin is tied to VCC. If V
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 5c. No full-scale
limiting can occur if V

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

is less than VCC – FSE.

REF

= VCC and the DAC

REF

16

26061626f

ACK

ACK

123456789123456789123456789123456789

2606 F05

ACK

START

X = DON’T CARE

STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

SDA

A6 A5 A4 A3 A2 A1 A0

SCL

V

OUT

C2C3

C3C2C1C0XXXX

C1 C0 X X X X

ACK

COMMAND

D15 D14 D13 D12 D11 D10 D9 D8

MS DATA

D7 D6 D5 D4 D3 D2 D1 D0

LS DATA

A6 A5 A4 A3 A2 A1 A0 WR

SLAVE ADDRESS

OPERATIO

LTC2606/LTC2616/LTC2626

U

Figure 4. Typical LTC2606 Input Waveform—Programming DAC Output for Full Scale

26061626f

17

LTC2606/LTC2616/LTC2626

2606 F05

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V

32, 7680 65, 535

INPUT CODE

OUTPUT

VOLTAGE

(a)

V

REF

= V

CC

V

REF

= V

CC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

U

OPERATIO

18

Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect

of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

26061626f

PACKAGE DESCRIPTIO

LTC2606/LTC2616/LTC2626

U

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

0.675 ±0.05

3.50 ±0.05

1.65 ±0.05
(2 SIDES)2.15 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE

0.50
BSC

2.38 ±0.05
(2 SIDES)

3.00 ±0.10
(4 SIDES)

0.75 ±0.05

1.65 ± 0.10
(2 SIDES)

0.00 – 0.05

R = 0.115

TYP

2.38 ±0.10
(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

106

15

0.25 ± 0.05

0.50 BSC

0.38 ± 0.10

(DD10) DFN 0403

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen­tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

26061626f

19

LTC2606/LTC2616/LTC2626

U

TYPICAL APPLICATIO

Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

2

I

C BUS

CA0

CA1
CA2

5V

V

REF

DAC

100Ω

1V TO 5V

7.5k

100pF

3

V

IN

0.1µF

10

LDAC

4

CA0

2

SDA

3

SCL

5

CA1

1

CA2

V

CC

LTC2606

GND

8

V

REF

7

V

OUT

OUTPUT

296 1

FS

SET

LTC2421

ZS

GND

SET

56

5V

0.1µF

V

CC

SCK
SDO

2606 TA01

9
8

SPI BUS

7

CS

10

F

O

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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= 2.7V to 5.5V, V

CC

LTC1654 Dual 14-Bit Rail-to-Rail V
LTC1655/LTC1655L Single 16-Bit V
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DACs with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched

OUT

OUT

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OUT

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OUT

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DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2620 Output, SPI Serial Interface
LTC2601/LTC2611 Single 16-/14-/12-Bit V

DACs in 10-Lead DFN 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2621 Output, SPI Serial Interface
LTC2602/LTC2612 Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2622 Output, SPI Serial Interface
LTC2604/LTC2614 Quad 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2624 Output, SPI Serial Interface

= 0V to 4.096V

OUT

= 0V to 2.5V

OUT

OUT

20

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

[phone] ● FAX: [phone]

●

www.linear.com

26061626f

LT/TP 1204 1K • PRINTED IN THE USA

© LINEAR TECHNOLOGY CORPORATION 2004