Datasheet LTC2601, LTC2611, LTC2621 Datasheet (LINEAR TECHNOLOGY)

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FEATURES

■

Smallest Pin-Compatible Single DACs: LTC2601: 16 Bits LTC2611: 14 Bits LTC2621: 12 Bits

■

Guaranteed Monotonic Over Temperature

■

Wide 2.5V to 5.5V Supply Range

■

Low Power Operation: 300µA at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

Tiny (3mm × 3mm) 10-Lead DFN Package

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2601/LTC2611/LTC2621

16-/14-/12-Bit Rail-to-Rail

DACs in 10-Lead DFN

DESCRIPTIO

The LTC®2601/LTC2611/LTC2621 are single 16-, 14and 12-bit, in a 10-lead DFN package. They have built-in high performance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, and load regulation in single-supply, voltage-output multiples.

The parts use a simple SPI/MICROWIRETM compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisy-chain capability, hardware CLR and asynchronous DAC update (LDAC) pins are included.

The LTC2601/LTC2611/LTC2621 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale; and after power-up, they stay at zero scale until a valid write and update take place.

, LTC and LT are registered trademarks of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation. U.S. patent number 5396245.

2.5V-to-5.5V rail-to-rail voltage output DACs

BLOCK DIAGRA

SDI

SCK

32-BIT

SHIFT

CS/LD

SDO

CONTROL

DECODE

LOGIC

LDAC

INPUT

REF

DAC

CLR

12-/14-/16-BIT DAC

GND

Differential Nonlinearity (LTC2601)

1.0 VCC = 5V

0.8

= 4.096V

REF

0.6

0.4

OUT

2601 BD

0.2

DNL (LSB)

–0.2 –0.4 –0.6 –0.8 –1.0

0 16384 32768 49152 65535

CODE

2600 G02

2601f

LTC2601/LTC2611/LTC2621

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

8 4 5

LDAC V

GND V

OUT

REF

SDO

SDI SCK CLR

CS/LD

(Note 1)

LUTEXI TIS

WUW

ARB

Any Pin to GND........................................... – 0.3V to 6V

Any Pin to VCC.............................................–6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LTC2601C/LTC2611C/LTC2621C .......... 0°C to 70°C

LTC2601I/LTC2611I/LTC2621I.......... –40°C to 85°C

Storage Temperature Range ................ –65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

PACKAGE

RDER I FOR ATIO

ORDER PART

NUMBER

LTC2601CDD LTC2601IDD LTC2611CDD LTC2611IDD LTC2621CDD LTC2621IDD

DD PART MARKING

= 125°C, θJA = 43°C/W

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

LAGT LBFQ LBFS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LECTRICAL C CHARA TERIST

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance

Resolution ● 12 14 16 Bits Monotonicity (Note 2) ● 12 14 16 Bits

DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1 LSB INL Integral Nonlinearity (Note 2) ● ±0.8 ±4 ±3 ±16 ±13 ±64 LSB

Load Regulation V

ZSE Zero-Scale Error Code = 0 ● 19 19 19 mV V

GE Gain Error ● ±0.03 ±0.7 ±0.1 ±0.7 ±0.05 ±0.7 %FSR

Offset Error (Note 5) ● ±1.5 ±9 ±1.5 ±9 ±1.5 ±9mV VOS Temperature ±5 ±5 ±5 µV/°C

Coefficient

Gain Temperature ±2 ±2 ±2 ppm/°C Coefficient

= VCC = 5V, Midscale

REF

= 0mA to 15mA Sourcing ● 0.03 0.125 0.10 0.5 0.45 2 LSB/mA

OUT

= 0mA to 15mA Sinking ● 0.04 0.125 0.15 0.5 0.60 2 LSB/mA

OUT

= VCC = 2.5V, Midscale

REF

= 0mA to 7.5mA Sourcing ● 0.06 0.25 0.2 1 0.9 4 LSB/mA

OUT

= 0mA to 7.5mA Sinking ● 0.08 0.25 0.3 1 1.2 4 LSB/mA

OUT

ICS

The ● denotes specifications which apply over the full operating

unloaded,

OUT

LTC2621 LTC2611 LTC2601

2601f

LTC2601/LTC2611/LTC2621

LECTRICAL C CHARA TERIST

ICS

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V

The ● denotes specifications which apply over the full operating

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V

OUT

Reference Input

REF

Power Supply

Digital I/O

DC Output Impedance V

Short-Circuit Output Current VCC = 5.5V, V

Input Voltage Range ● 0V Resistance Normal Mode ● 88 124 160 kΩ Capacitance 15 pF Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Positive Supply Voltage For Specified Performance ● 2.5 5.5 V Supply Current VCC = 5V (Note 3) ● 0.375 0.55 mA

Digital Input High Voltage VCC = 2.5V to 5.5V ● 2.4 V

Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V

Digital Output High Voltage Load Current = –100µA ● VCC – 0.4 V Digital Output Low Voltage Load Current = +100µA ● 0.4 V Digital Input Leakage VIN = GND to V Digital Input Capacitance (Note 4) ● 8pF

= 5V ±10% –80 dB

= 3V ±10% ● –80 dB

= VCC = 5V, Midscale; –15mA ≤ I

REF

= VCC = 2.5V, Midscale; –7.5mA ≤ I

REF

= 5.5V Code: Zero Scale; Forcing Output to V Code: Full Scale; Forcing Output to GND

VCC = 2.5V, V

Code: Zero Scale; Forcing Output to V Code: Full Scale; Forcing Output to GND

= 3V (Note 3) ● 0.30 0.45 mA

DAC Powered Down (Note 3) V DAC Powered Down (Note 3) V

= 2.5V to 3.6V ● 2.0 V

= 2.5V to 5.5V ● 0.6 V

REF

= 2.5V

CC CC

≤ 15mA ● 0.04 0.15 Ω

OUT

≤ 7.5mA ● 0.05 0.15 Ω

OUT

= 5V ● 0.40 1 µA = 3V ● 0.10 1 µA

LTC2601/LTC2611/LTC2621

● 15 35 60 mA

● 15 39 60 mA

● 7.5 20 50 mA

● 7.5 27 50 mA

● ±1 µA

2601f

LTC2601/LTC2611/LTC2621

LECTRICAL C CHARA TERIST

ICS

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V

The ● denotes specifications which apply over the full operating

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS AC Performance

Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs ±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs (Note 7) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.80 0.80 0.80 V/µs Capacitive Load Driving 1000 1000 1000 pF Glitch Impulse At Midscale Transition 12 12 12 nV • s Multiplying Bandwidth 180 180 180 kHz Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

LTC2621 LTC2611 LTC2601

P-P

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 2.5V to 5.5V

SDI Valid to SCK Setup ● 4ns SDI Valid to SCK Hold ● 4ns SCK High Time ● 9ns SCK Low Time ● 9ns CS/LD Pulse Width ● 10 ns LSB SCK High to CS/LD High ● 7ns CS/LD Low to SCK High ● 7ns SDO Propagation Delay from SCK Falling Edge C

CLR Pulse Width ● 20 ns CS/LD High to SCK Positive Edge ● 7ns LDAC Pulse Width ● 15 ns CS/LD High to LDAC High or Low Transition ● 200 ns SCK Frequency 50% Duty Cycle ● 50 MHz

The ● denotes specifications which apply over the full operating temperature

LTC2601/LTC2611/LTC2621

= 10pF

LOAD

VCC = 4.5V to 5.5V ● 20 ns

= 2.5V to 5.5V ● 45 ns

Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

– 1, where N is the resolution and kL is given by kL = 0.016(2N/V

2 rounded to the nearest whole code. For V 256 and linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V Note 4: Guaranteed by design and not production tested.

= 4.096V and N = 16, kL =

REF

to code

REF

Note 5: Inferred from measurement at code K full scale.

Note 6: V and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 7: V scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

= 5V, V

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

REF

= 4.096V. DAC is stepped ±1LSB between half

REF

= 0.016(2N/V

REF

) and at

2601f

LTC2601/LTC2611/LTC2621

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2601

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

INL (LSB)

–8

–16

–24

–32

VCC = 5V

= 4.096V

REF

16384 32768 49152 65535

CODE

2601 G01

1.0 VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2 –0.4 –0.6 –0.8 –1.0

= 4.096V

REF

0 16384 32768 49152 65535

CODE

2600 G02

INL (LSB)

–8

–16

–24

–32

–50

VCC = 5V

= 4.096V

REF

–30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2601 G03

DNL vs Temperature

1.0 VCC = 5V

= 4.096V

0.8

REF

0.6

0.4

0.2

DNL (LSB)

–0.2 –0.4 –0.6 –0.8 –1.0

–30 –10 10 30 50 70 90

–50

TEMPERATURE (°C)

DNL (POS)

DNL (NEG)

OUT

100µV/DIV

CS/LD

2V/DIV

2601 G04

INL vs V

INL (LSB)

–8

–16

–24

–32

REF

VCC = 5.5V

INL (POS)

INL (NEG)

1 2 3 4 5

(V)

REF

2601 G05

DNL vs V

1.5

1.0

0.5

DNL (LSB)

–0.5

–1.0

–1.5

REF

VCC = 5.5V

1 2 3 4 5

Settling to ±1LSB Settling of Full-Scale Step

OUT

9.7µs

100µV/DIV

CS/LD

2V/DIV

12.3µs

DNL (POS)

DNL (NEG)

(V)

REF

2601 G06

2µs/DIV

= 5V, V

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

REF

= 4.096V

2601 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

CODE 512 TO 65535 STEP AVERAGE OF 2048 EVENTS

REF

= 4.096V

2601 G08

2601f

LTC2601/LTC2611/LTC2621

2µs/DIV

2601 G14

OUT

1mV/DIV

CS/LD

2V/DIV

= 5V, V

REF

= 4.096V 1/4-SCALE TO 3/4-SCALE STEP R

= 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

6.8µs

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2611

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

INL (LSB)

–2

–4

–6

–8

VCC = 5V

= 4.096V

REF

4096 8192 12288 16383

CODE

2601 G09

1.0 VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2 –0.4 –0.6 –0.8 –1.0

= 4.096V

REF

0 4096 8192 12288 16383

CODE

LTC2621

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

2.0

1.5

1.0

0.5

INL (LSB)

–0.5

–1.0

–1.5

–2.0

VCC = 5V

= 4.096V

REF

1024 2048 3072 4095

CODE

2601 G12

1.0 VCC = 5V

0.8

= 4.096V

REF

0.6

0.4

0.2

DNL (LSB)

–0.2 –0.4 –0.6 –0.8 –1.0

0 1024 2048 3072 4095

CODE

LTC2601/LTC2611/LTC2621

2601 G10

2601 G13

OUT

100µV/DIV

CS/LD

2V/DIV

Settling to ±1LSB

2µs/DIV

= 5V, V

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

REF

= 4.096V

Settling to ±1LSB

8.9µs

2601 G11

(V)

∆V

Current Limiting

0.10 CODE = MIDSCALE

0.08

0.06

0.04

0.02

OUT

–0.02 –0.04 –0.06 –0.08 –0.10

–30 –20 –10 0 10 20 30 40

–40

REF

= VCC = 5V = VCC = 3V

= VCC = 3V = VCC = 5V

(mA)

OUT

2601 G17

Load Regulation Offset Error vs Temperature

1.0 CODE = MIDSCALE

0.8

0.6

0.4

0.2

(mV)

∆V

OUT

–0.2 –0.4 –0.6 –0.8 –1.0

= VCC = 5V

REF

= VCC = 3V

REF

–35 –25 –15 –5 5 15 25 35

(mA)

OUT

2601 G18

–1

OFFSET ERROR (mV)

–2

–3

–30 –10 10 30 50 70 90

–50

TEMPERATURE (°C)

2601 G19

2601f

LTC2601/LTC2611/LTC2621

2.5µs/DIV

OUT

0.5V/DIV

2601 G25

REF

= VCC = 5V

1/4-SCALE TO 3/4-SCALE

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2601/LTC2611/LTC2621

Zero-Scale Error vs Temperature

2.5

2.0

1.5

1.0

ZERO-SCALE ERROR (mV)

0.5

–30 –10 10 30 50 70 90

–50

0.4

0.3

0.2

0.1

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

2.5 3

TEMPERATURE (°C)

3.5 4 4.5 5 5.5 VCC (V)

2601 G20

2601 G23

Gain Error vs Temperature Offset Error vs V

0.4

0.3

0.2

0.1

–0.1

GAIN ERROR (%FSR)

–0.2

–0.3

–0.4

–30 –10 10 30 50 70 90

–50

ICC Shutdown vs V

450

400

350

300

250

(nA)

200

150

100

2.5 3

TEMPERATURE (°C)

2601 G21

3.5 4 4.5 5 5.5 VCC (V)

2601 G24

–1

OFFSET ERROR (mV)

–2

–3

2.5 3

Large-Signal ResponseGain Error vs V

3.5 4 4.5 5 5.5 VCC (V)

2601 G22

Midscale Glitch Impulse

OUT

10mV/DIV

CS/LD

5V/DIV

12nV-s TYP

2.5µs/DIV

2601 G26

1V/DIV

OUT

10mV/DIV

Power-On Reset Glitch

250µs/DIV

4mV PEAK

2601 G27

Headroom at Rails vs Output Current

5.0

4.5

4.0

3.5

3.0

(V)

2.5

OUT

2.0

1.5

1.0

0.5 0

1 2 3 4 5 6 7 8 910

5V SOURCING

3V SOURCING

3V SINKING

(mA)

OUT

5V SINKING

2601 G28

2601f

LTC2601/LTC2611/LTC2621

1V/DIV

10mA/DIV

0mA

2600 G19

VCC = 5.5V V

REF

= 5.6V CODE = FULL SCALE V

OUT

SWEPT VCC TO 0V

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2601/LTC2611/LTC2621

Supply Current vs Logic Voltage

2.4

2.3

2.2

2.1

2.0

(mA)

1.9

1.8

1.7

1.6

1.5

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

LOGIC VOLTAGE (V)

VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO V

Multiplying Bandwidth

0 –3 –6 –9

–12 –15 –18

–21 –24 –27

VCC = 5V

(DC) = 2V

REF

–30 –33 –36

(AC) = 0.2V

REF

CODE = FULL SCALE

10k 100k

P-P

FREQUENCY (Hz)

Hardware CLR

2601 G29

OUT

1V/DIV

CLR

5V/DIV

1µs/DIV

2601 G31

Output Voltage Noise,

0.1Hz to 10Hz

OUT

10µV/DIV

012345678910

2601 G32

SECONDS

2601 G33

Short-Circuit Output Current vs V

(Sinking)

OUT

0mA

10mA/DIV

VCC = 5.5V

= 5.6V

REF

CODE = 0

SWEPT 0V TO V

OUT

1V/DIV

Short-Circuit Output Current vs V

(Sourcing)

OUT

2601 G18

2601f

UUU

PIN FUNCTIONS

LTC2601/LTC2611/LTC2621

SDO (Pin 1): Serial Interface Data Output. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. This pin is used for daisy-chain operation.

SDI (Pin 2): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK (Pin␣ 3). The LTC2601 accepts input word lengths of either 24 or 32 bits.

SCK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible.

CLR (Pin 4): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible.

CS/LD (Pin 5): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI

into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed.

REF (Pin 6): Reference Voltage Input. 0V ≤ V V

(Pin 7): DAC Analog Voltage Output. The output

OUT

range is 0V to V

GND (Pin 8): Analog Ground. VCC (Pin 9): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V. LDAC (Pin 10): Asynchronous DAC Update Pin. If CS/LD

is high, a falling edge on LDAC immediately updates the DAC register with the contents of the input register (similar to a software update). If CS/LD is low when LDAC goes low, the DAC register is updated after CS/LD returns high. A low on the LDAC pin powers up the DAC. A software power down command is ignored if LDAC is low.

Exposed Pad (Pin 11): Ground. Must be soldered to PCB ground.

REF

≤ VCC.

2601f

LTC2601/LTC2611/LTC2621

BLOCK DIAGRA

SDI

SCK

CS/LD

SDO

WUW

TI I G DIAGRA S

SCK

32-BIT

SHIFT

REF

INPUT

CONTROL

DECODE

LOGIC

LDAC

1232324

DAC

CLR

12-/14-/16-BIT DAC

GND

OUT

2601 BD

SDI

CS/LD

SDO

LDAC

2601 F01a

Figure 1a

CS/LD

LDAC

2601 F01b

Figure 1b

2601f

OPERATIO

LTC2601/LTC2611/LTC2621

Power-On Reset

The LTC2601/LTC2611/LTC2621 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable.

For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2601/ LTC2611/LTC2621 contain circuitry to reduce the poweron glitch; furthermore, the glitch amplitude can be made arbitrarily small by reducing the ramp rate of the power supply. For example, if the power supply is ramped to 5V in 1ms, the analog outputs rise less than 10mV above ground (typ) during power-on. See Power-On Reset Glitch in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range –0.3V ≤ V

≤ VCC + 0.3V (see Absolute Maximum

REF

Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition.

device to execute the command specified in the 24-bit input word. The complete sequence is shown in Figure 2a.

The command (C3-C0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the DAC. In an update operation, the data word is copied from the input register to the DAC register and converted to an analog voltage at the DAC output. The update operation also powers up the DAC if it had been in powerdown mode. The data path and registers are shown in the Block Diagram.

While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the 32-bit sequence. The 32-bit word is required for daisy-chain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes).

Daisy-Chain Operation

Transfer Function

The digital-to-analog transfer function is:



OUT IDEAL







REF()





where k is the decimal equivalent of the binary DAC input code, N is the resolution and V

is the voltage at REF

REF

(Pin 6).

Serial Interface

The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering-on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then 4 don’t care bits; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSBto-LSB, followed by 0, 2 or 4 don’t care bits (LTC2601, LTC2611 and LTC2621 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the

The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge.

The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a “daisy chain” series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain.

Table 1.

COMMAND*

C3 C2 C1 C0

0000 Write to Input Register 0001 Update (Power Up) DAC Register 0011 Write to and Update (Power Up) 0100 Power Down 1111 No Operation

*Command codes not shown are reserved and should not be used.

2601f

LTC2601/LTC2611/LTC2621

OPERATIO

INPUT WORD (LTC2601)

COMMAND DON’T CARE BITS DATA (16 BITS)

INPUT WORD (LTC2611)

INPUT WORD (LTC2621)

COMMAND DON’T CARE BITS DATA (14 BITS + 2 DON’T CARE BITS)

COMMAND DON’T CARE BITS DATA (12 BITS + 4 DON’T CARE BITS)

MSB

D12

D13

MSB

D11 D10 D9 D8

MSB

D12

D13D14D15

D11 D10 D9 D8

Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series.

In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, which executes the commands specified for each of the devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain.

D11 D10 D9 D8

D5 D4 D3 D2 D1

D0 X XXX

LSB

D0 X X

LSB

2601 TBL01

2601 TBL02

2601 TBL03

REF rises accordingly becoming a high impedance input (typically > 1GΩ).

Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1 or performing an asynchronous update (LDAC) as described in the next section. The DAC is powered up as its voltage output is updated. When the DAC in powereddown state is powered up and updated, normal settling is delayed. The main bias generation circuit block has been automatically shut down in addition to the DAC amplifier and reference input and so the power up delay time is 12µs (for VCC = 5V) or 30µs (for V

= 3V).

Power-Down Mode

For power-constrained applications, power-down mode can be used to reduce the supply current whenever the DAC output is not needed. When in power-down, the buffer amplifier, bias circuit and reference input is disabled and draws essentially zero current. The DAC output is put into a high impedance state, and the output pin is passively pulled to ground through 90k resistors. Inputand DAC-register contents are not disturbed during powerdown.

The DAC can be put into power-down mode by using command 0100b. The 16-bit data word is ignored. The supply and reference currents are reduced to almost zero when the DAC is powered down; the effective resistance at

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 1, the LDAC pin asynchronously updates the DAC register with the contents of the input register.

If CS/LD is high, a low on the LDAC pin causes the DAC register to be updated with the contents of the input register.

If CS/LD is low, a low going pulse on the LDAC pin before the rising edge of CS/LD powers up the DAC but does not cause the output to be updated. If LDAC remains low after the rising edge of CS/LD, then LDAC is recognized, the command specified in the 24-bit word just transferred is executed and the DAC output is updated.

2601f

OPERATIO

LTC2601/LTC2611/LTC2621

The DAC is powered up when LDAC is taken low, independent of the state of CS/LD.

If LDAC is low at the time CS/LD goes high, it inhibits any software power-down command that was specified in the input word.

Voltage Outputs

The rail-to-rail amplifier contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifier’s DC output impedance is 0.05Ω when driving a load well away from the rails.

When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25Ω • 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section.

The amplifier is stable driving capacitive loads of up to 1000pF.

Board Layout

The excellent load regulation of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance.

The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this,

careful thought should be given to the grounding scheme and board layout in order to ensure rated performance.

The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other.

Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer.

The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.05Ω). Note that the LTC2601/LTC2611/ LTC2621 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited to voltages within the supply range.

Since the analog output of the device cannot go below ground, it may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If V full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if V

Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.

is less than VCC – FSE.

REF

= VCC and the DAC

REF

2601f

LTC2601/LTC2611/LTC2621

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3

CS/LD

SCK

SDI

COMMAND WORD 4 DON’T CARE BITS DATA WORD

24-BIT INPUT WORD

2601 F02a

24 25 26 27 28 29 30 31 32

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

CS/LD

SCK

SDI

COMMAND WORD DATA WORD

DON’T CARE 4 DON’T CARE BITS

C2 C1 C0 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3XXXXXXXX

SDO

CURRENT

32-BIT

INPUT WORD

2601 F02b

PREVIOUS 32-BIT INPUT WORD

D15

SCK

SDI

SDO

PREVIOUS D14PREVIOUS D15

D14

OPERATIO

Figure 2a. LTC2601 24-Bit Load Sequence (Minimum Input Word).

LTC2611 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;

LTC2621 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits

Figure 2b. LTC2601 32-Bit Load Sequence (Required for Daisy-Chain Operation).

LTC2611 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits;

LTC2621 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits

2601f

OPERATIO

LTC2601/LTC2611/LTC2621

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

INPUT CODE

(b)

Figure 3. Effects of Rail-to-Rail Operation On the DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

PACKAGE DESCRIPTIO

= V

REF

OUTPUT

VOLTAGE

32, 7680 65, 535

INPUT CODE

(a)

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

= V

REF

INPUT CODE

POSITIVE

(c)

FSE

OUTPUT VOLTAGE

2601 F03

0.675 ±0.05

3.50 ±0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

1.65 ±0.05 (2 SIDES)2.15 ±0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

3.00 ±0.10

(4 SIDES)

0.75 ±0.05

1.65 ± 0.10

(2 SIDES)

0.00 – 0.05

R = 0.115

TYP

2.38 ±0.10

(2 SIDES)

BOTTOM VIEW—EXPOSED PAD

106

0.25 ± 0.05

0.50 BSC

0.38 ± 0.10

(DD10) DFN 1103

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2601f

LTC2601/LTC2611/LTC2621

TYPICAL APPLICATIO

Demo Circuit DC777 Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

SPI

BUS

100Ω

REF

1V TO 5V

7.5k

100pF

0.1µF

4 2 3 5 1

LDAC CLR SDI SCK CS/LD SDO

LTC2601

GND

REF

OUT

DAC

OUTPUT

296 1

SET

LTC2421

GND

SET

0.1µF

SCK

SDO

9 8 7

2601 TA01

RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

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LTC1654 Dual 14-Bit Rail-to-Rail V LTC1655/LTC1655L Single 16-Bit V LTC1657/LTC1657L Parrallel 5V/3V 16-Bit V LTC1660/LTC1665 Octal 10/8-Bit V LTC1661 Dual 10-Bit V LTC1662 Dual 10-Bit V LTC1663 Single 10-Bit V LTC1664 Quad 10-Bit V

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OUT

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OUT

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OUT

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OUT

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OUT

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OUT

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OUT

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= 2.7V to 5.5V, V

LTC1669 Single 10-Bit VOUT DAC 5-Lead SOT-23 Pin-for-Pin Compatible with LTC1663 LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step LTC2600/LTC2610 Octal 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2620 Output LTC2602/LTC2612 Dual 16-/14-/12-Bit V

DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2622 Output LTC2604/LTC2614 Quad 16-/14-/12-Bit V

DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

OUT

LTC2624 Output

= 0V to 4.096V

OUT

= 0V to 2.5V

OUT

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

2601f

LT/TP 0404 1K • PRINTED IN THE USA

 LINEAR TECHNOLOGY CORPORATION 2004

Datasheet LTC2601, LTC2611, LTC2621 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual