LINEAR TECHNOLOGY LTC2601, LTC2611, LTC2621 Technical data

查询LTC2601CDD供应商

FEATURES

■

Smallest Pin-Compatible Single DACs:
LTC2601: 16 Bits
LTC2611: 14 Bits
LTC2621: 12 Bits

■

Guaranteed Monotonic Over Temperature

■

Wide 2.5V to 5.5V Supply Range

■

Low Power Operation: 300µA at 3V

■

Power Down to 1µA, Max

■

High Rail-to-Rail Output Drive (±15mA, Min)

■

Double-Buffered Data Latches

■

Asynchronous DAC Update Pin

■

Tiny (3mm × 3mm) 10-Lead DFN Package

U

APPLICATIO S

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

LTC2601/LTC2611/LTC2621

16-/14-/12-Bit Rail-to-Rail

DACs in 10-Lead DFN

U

DESCRIPTIO

The LTC®2601/LTC2611/LTC2621 are single 16-, 14­and 12-bit,
in a 10-lead DFN package. They have built-in high perfor­mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive, and load regulation in single-supply,
voltage-output multiples.

The parts use a simple SPI/MICROWIRETM compatible
3-wire serial interface which can be operated at clock rates
up to 50MHz. Daisy-chain capability, hardware CLR and
asynchronous DAC update (LDAC) pins are included.

The LTC2601/LTC2611/LTC2621 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.

, LTC and LT are registered trademarks of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.
U.S. patent number 5396245.

2.5V-to-5.5V rail-to-rail voltage output DACs

BLOCK DIAGRA

SDI

2

SCK

3

32-BIT

SHIFT

REGISTER

CS/LD

5

SDO

1

CONTROL

DECODE

LOGIC

LDAC

10

W

INPUT

REGISTER

6

REF

DAC

REGISTER

CLR

4

9

V

CC

12-/14-/16-BIT DAC

GND

8

Differential Nonlinearity (LTC2601)

1.0
VCC = 5V

0.8

V

= 4.096V

REF

0.6

0.4

V

OUT

7

2601 BD

0.2

0

DNL (LSB)

–0.2
–0.4
–0.6
–0.8
–1.0

0 16384 32768 49152 65535

CODE

2600 G02

2601f

1

LTC2601/LTC2611/LTC2621

TOP VIEW

11

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

10

9

6

7

8
4
5

3

2

1

LDAC
V

CC

GND
V

OUT

REF

SDO

SDI
SCK
CLR

CS/LD

A

S

(Note 1)

W

O

LUTEXI TIS

A

WUW

U

ARB

G

Any Pin to GND........................................... – 0.3V to 6V

Any Pin to VCC.............................................–6V to 0.3V

Maximum Junction Temperature ......................... 125°C

Operating Temperature Range

LTC2601C/LTC2611C/LTC2621C .......... 0°C to 70°C

LTC2601I/LTC2611I/LTC2621I.......... –40°C to 85°C

Storage Temperature Range ................ –65°C to 125°C

Lead Temperature (Soldering, 10 sec)................ 300°C

PACKAGE

/

O

RDER I FOR ATIO

ORDER PART

NUMBER

LTC2601CDD
LTC2601IDD
LTC2611CDD
LTC2611IDD
LTC2621CDD
LTC2621IDD

WU

U

DD PART MARKING

T

= 125°C, θJA = 43°C/W

JMAX

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

LAGT
LBFQ
LBFS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LECTRICAL C CHARA TERIST

E

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V
unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
DC Performance

Resolution ● 12 14 16 Bits
Monotonicity (Note 2) ● 12 14 16 Bits

DNL Differential Nonlinearity (Note 2) ● ±0.5 ±1 ±1 LSB
INL Integral Nonlinearity (Note 2) ● ±0.8 ±4 ±3 ±16 ±13 ±64 LSB

Load Regulation V

ZSE Zero-Scale Error Code = 0 ● 19 19 19 mV
V

OS

GE Gain Error ● ±0.03 ±0.7 ±0.1 ±0.7 ±0.05 ±0.7 %FSR

Offset Error (Note 5) ● ±1.5 ±9 ±1.5 ±9 ±1.5 ±9mV
VOS Temperature ±5 ±5 ±5 µV/°C

Coefficient

Gain Temperature ±2 ±2 ±2 ppm/°C
Coefficient

= VCC = 5V, Midscale

REF

I

= 0mA to 15mA Sourcing ● 0.03 0.125 0.10 0.5 0.45 2 LSB/mA

OUT

= 0mA to 15mA Sinking ● 0.04 0.125 0.15 0.5 0.60 2 LSB/mA

I

OUT

V

= VCC = 2.5V, Midscale

REF

= 0mA to 7.5mA Sourcing ● 0.06 0.25 0.2 1 0.9 4 LSB/mA

I

OUT

I

= 0mA to 7.5mA Sinking ● 0.08 0.25 0.3 1 1.2 4 LSB/mA

OUT

ICS

The ● denotes specifications which apply over the full operating

unloaded,

OUT

LTC2621 LTC2611 LTC2601

2

2601f

LTC2601/LTC2611/LTC2621

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V

The ● denotes specifications which apply over the full operating

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PSR Power Supply Rejection V

R

OUT

I

SC

Reference Input

I

REF

Power Supply

V

CC

I

CC

Digital I/O

V

IH

V

IL

V

OH

V

OL

I

LK

C

IN

DC Output Impedance V

Short-Circuit Output Current VCC = 5.5V, V

Input Voltage Range ● 0V
Resistance Normal Mode ● 88 124 160 kΩ
Capacitance 15 pF
Reference Current, Power Down Mode DAC Powered Down ● 0.001 1 µA

Positive Supply Voltage For Specified Performance ● 2.5 5.5 V
Supply Current VCC = 5V (Note 3) ● 0.375 0.55 mA

Digital Input High Voltage VCC = 2.5V to 5.5V ● 2.4 V

Digital Input Low Voltage VCC = 4.5V to 5.5V ● 0.8 V

Digital Output High Voltage Load Current = –100µA ● VCC – 0.4 V
Digital Output Low Voltage Load Current = +100µA ● 0.4 V
Digital Input Leakage VIN = GND to V
Digital Input Capacitance (Note 4) ● 8pF

= 5V ±10% –80 dB

CC

V

= 3V ±10% ● –80 dB

CC

= VCC = 5V, Midscale; –15mA ≤ I

REF

= VCC = 2.5V, Midscale; –7.5mA ≤ I

V

REF

= 5.5V
Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

VCC = 2.5V, V

Code: Zero Scale; Forcing Output to V
Code: Full Scale; Forcing Output to GND

V

= 3V (Note 3) ● 0.30 0.45 mA

CC

DAC Powered Down (Note 3) V
DAC Powered Down (Note 3) V

V

= 2.5V to 3.6V ● 2.0 V

CC

= 2.5V to 5.5V ● 0.6 V

V

CC

REF

REF

= 2.5V

CC
CC

CC

≤ 15mA ● 0.04 0.15 Ω

OUT

≤ 7.5mA ● 0.05 0.15 Ω

OUT

CC

CC

= 5V ● 0.40 1 µA
= 3V ● 0.10 1 µA

LTC2601/LTC2611/LTC2621

● 15 35 60 mA

● 15 39 60 mA

● 7.5 20 50 mA

● 7.5 27 50 mA

CC

● ±1 µA

V

2601f

3

LTC2601/LTC2611/LTC2621

LECTRICAL C CHARA TERIST

E

ICS

temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), V

The ● denotes specifications which apply over the full operating

unloaded,

OUT

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance

t

S

e

n

Settling Time (Note 6) ±0.024% (±1LSB at 12 Bits) 7 7 7 µs

±0.006% (±1LSB at 14 Bits) 9 9 µs
±0.0015% (±1LSB at 16 Bits) 10 µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 µs
(Note 7) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 µs

±0.0015% (±1LSB at 16 Bits) 5.2 µs

Voltage Output Slew Rate 0.80 0.80 0.80 V/µs
Capacitive Load Driving 1000 1000 1000 pF
Glitch Impulse At Midscale Transition 12 12 12 nV • s
Multiplying Bandwidth 180 180 180 kHz
Output Voltage Noise Density At f = 1kHz 120 120 120 nV/√Hz

At f = 10kHz 100 100 100 nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz 15 15 15 µV

LTC2621 LTC2611 LTC2601

P-P

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC = 2.5V to 5.5V

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

12

t

13

SDI Valid to SCK Setup ● 4ns
SDI Valid to SCK Hold ● 4ns
SCK High Time ● 9ns
SCK Low Time ● 9ns
CS/LD Pulse Width ● 10 ns
LSB SCK High to CS/LD High ● 7ns
CS/LD Low to SCK High ● 7ns
SDO Propagation Delay from SCK Falling Edge C

CLR Pulse Width ● 20 ns
CS/LD High to SCK Positive Edge ● 7ns
LDAC Pulse Width ● 15 ns
CS/LD High to LDAC High or Low Transition ● 200 ns
SCK Frequency 50% Duty Cycle ● 50 MHz

The ● denotes specifications which apply over the full operating temperature

LTC2601/LTC2611/LTC2621

= 10pF

LOAD

VCC = 4.5V to 5.5V ● 20 ns

= 2.5V to 5.5V ● 45 ns

V

CC

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

N

– 1, where N is the resolution and kL is given by kL = 0.016(2N/V

2
rounded to the nearest whole code. For V
256 and linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V
Note 4: Guaranteed by design and not production tested.

CC

.

= 4.096V and N = 16, kL =

REF

to code

L

REF

),

4

Note 5: Inferred from measurement at code K
full scale.

Note 6: V
and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 7: V
scale and half scale – 1. Load is 2k in parallel with 200pF to GND.

= 5V, V

CC

= 5V, V

CC

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

REF

= 4.096V. DAC is stepped ±1LSB between half

REF

= 0.016(2N/V

L

REF

) and at

2601f

LTC2601/LTC2611/LTC2621

UW

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2601

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

VCC = 5V

= 4.096V

V

REF

16384 32768 49152 65535

CODE

2601 G01

1.0
VCC = 5V

0.8

0.6

0.4

0.2

DNL (LSB)

–0.2
–0.4
–0.6
–0.8
–1.0

= 4.096V

V

REF

0

0 16384 32768 49152 65535

CODE

2600 G02

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

–50

VCC = 5V

= 4.096V

V

REF

–30 –10 10 30 50 70 90

INL (POS)

INL (NEG)

TEMPERATURE (°C)

2601 G03

DNL vs Temperature

1.0
VCC = 5V

= 4.096V

V

0.8

REF

0.6

0.4

0.2

0

DNL (LSB)

–0.2
–0.4
–0.6
–0.8
–1.0

–30 –10 10 30 50 70 90

–50

TEMPERATURE (°C)

DNL (POS)

DNL (NEG)

V

OUT

100µV/DIV

CS/LD

2V/DIV

2601 G04

INL vs V

32

24

16

8

0

INL (LSB)

–8

–16

–24

–32

0

REF

VCC = 5.5V

INL (POS)

INL (NEG)

1 2 3 4 5

V

(V)

REF

2601 G05

DNL vs V

1.5

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

–1.5

0

REF

VCC = 5.5V

1 2 3 4 5

Settling to ±1LSB Settling of Full-Scale Step

V

OUT

9.7µs

100µV/DIV

CS/LD

2V/DIV

12.3µs

DNL (POS)

DNL (NEG)

V

(V)

REF

2601 G06

2µs/DIV

= 5V, V

V

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, CL = 200pF

R

L

AVERAGE OF 2048 EVENTS

REF

= 4.096V

2601 G07

5µs/DIV

SETTLING TO ±1LSB

= 5V, V

V

CC

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

REF

= 4.096V

2601 G08

2601f

5