Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
■
Directly Digitizes High Impedance Sensors with
Full Accuracy
■
600nV RMS Noise, Independent of V
■
GND to VCC Input/Reference Common Mode Range
■
2-Wire I2C Interface
■
Simultaneous 50Hz/60Hz Rejection
■
2ppm (0.25LSB) INL, No Missing Codes
■
1ppm Offset and 15ppm Full-Scale Error
■
No Latency: Digital Filter Settles in a Single Cycle
■
Single Supply 2.7V to 5.5V Operation
■
Internal Oscillator
■
Six Addresses Available
■
Available in a Tiny (3mm × 3mm) 10-Lead
REF
DFN Package
U
APPLICATIO S
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
■
Strain Gauge Transducers
■
Instrumentation
■
Industrial Process Control
■
DVMs and Meters
LTC2483
16-Bit ∆Σ ADC with Easy Drive
2
C Interface
U
DESCRIPTIO
The LTC®2483 combines a 16-bit plus sign No Latency ∆Σ
analog-to-digital converter with patented Easy DriveTM technology and I
scheme eliminates dynamic input current errors and the
shortcomings of on-chip buffering through automatic
cancellation of differential input current. This allows large
external source impedances and input signals, with rail-torail input range to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2483 allows a wide common mode input range
(0V to V
reference can be as low as 100mV or can be tied directly
. The noise level is 600nV RMS independent of V
to V
CC
This allows direct digitization of low level signals with 16bit accuracy. The LTC2483 includes an on-chip trimmed
oscillator, eliminating the need for external crystals or
oscillators and provides 87dB rejection of 50Hz and 60Hz
line frequency noise. Absolute accuracy and low drift are
automatically maintained through continuous, transparent, offset and full-scale calibration.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Patent Pending.
2
C digital interface. The patented sampling
) independent of the reference voltage. The
CC
REF
TM
.
TYPICAL APPLICATIO
V
CC
SENSE
10k
10k
= 0
I
DIFF
1µF
V
IN
V
IN
REF+V
+
LTC2483
–
GND
REF
U
+FS Error vs R
80
VCC = 5V
= 5V
V
REF
60
+
= 3.75V
V
IN
–
= 1.25V
V
IN
40
= GND
F
1µF
SCL
SDA
CA0/F
CA1
2483 TA01
2-WIRE
2
I
C INTERFACE
0
6 ADDRESSES
CC
–
O
= 25°C
T
A
20
0
–20
+FS ERROR (ppm)
–40
–60
–80
1
1010010k
SOURCE
R
SOURCE
at IN+ and IN
CIN = 1µF
1k
(Ω)
–
100k
2483 TA02
2483fa
1
LTC2483
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1
CA0/F
0
CA1
GND
SDA
SCL
REF
+
V
CC
REF
–
IN
+
IN
–
WWWU
ABSOLUTE AXI U RATI GS
(Notes 1, 2)
Supply Voltage (VCC) to GND...................... –0.3V to 6V
Analog Input Voltage to GND ....... –0.3V to (V
Reference Input Voltage to GND .. – 0.3V to (V
Digital Input Voltage to GND ........ – 0.3V to (V
Digital Output Voltage to GND ..... – 0.3V to (V
Operating Temperature Range
LTC2483C ................................................... 0°C to 70°C
LTC2483I ................................................ – 40°C to 85°C
Storage Temperature Range ................ –65°C to 125°C
+ 0.3V)
CC
+ 0.3V)
CC
+ 0.3V)
CC
+ 0.3V)
CC
UU
W
PACKAGE/ORDER I FOR ATIO
T
= 125°C, θJA = 43°C/ W
JMAX
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC2483CDD
LTC2483IDD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
DD PART MARKING*
LBSR
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
The ● denotes the specifications which apply over the full operating
= 25°C. (Notes 3, 4)
A
PARAMETERCONDITIONSMINTYPMAXUNITS
Resolution (No Missing Codes)0.1 ≤ V
Integral Nonlinearity5V ≤ VCC ≤ 5.5V, V
2.7V ≤ VCC ≤ 5.5V, V
Offset Error2.5V ≤ V
Offset Error Drift2.5V ≤ V
Positive Full-Scale Error2.5V ≤ V
Positive Full-Scale Error Drift2.5V ≤ V
≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
REF
= 5V, V
REF
= 2.5V, V
REF
≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
REF
≤ VCC, GND ≤ IN+ = IN– ≤ V
REF
≤ VCC, IN+ = 0.75V
REF
≤ VCC, IN+ = 0.75V
REF
= 2.5V (Note 6)
IN(CM)
IN(CM)
, IN– = 0.25V
REF
, IN– = 0.25V
REF
= 1.25V (Note 6)1ppm of V
CC
REF
REF
●
16Bits
●
●
210ppm of V
0.52.5µV
10nV/°C
●
25ppm of V
0.1ppm of
V
Negative Full-Scale Error2.5V ≤ V
Negative Full-Scale Error Drift2.5V ≤ V
≤ VCC, IN– = 0.75V
REF
≤ VCC, IN– = 0.75V
REF
, IN+ = 0.25V
REF
, IN+ = 0.25V
REF
REF
REF
●
25ppm of V
0.1ppm of
V
Total Unadjusted Error5V ≤ VCC ≤ 5.5V, V
5V ≤ VCC ≤ 5.5V, V
2.7V ≤ VCC ≤ 5.5V, V
Output Noise5V ≤ VCC ≤ 5.5V, V
= 2.5V, V
REF
= 5V, V
REF
= 2.5V, V
REF
= 5V, GND ≤ IN– = IN+ ≤ VCC (Note 12)0.6µV
REF
= 1.25V (Note 6)15ppm of V
IN(CM)
= 2.5V (Note 6)15ppm of V
IN(CM)
= 1.25V (Note 6)15ppm of V
IN(CM)
REF
REF
REF
REF
REF
/°C
REF
/°C
REF
REF
REF
RMS
2
2483fa
LTC2483
U
COVERTER CHARACTERISTICS
temperature range, otherwise specifications are at T
PARAMETERCONDITIONSMINTYPMAXUNITS
Input Common Mode Rejection DC2.5V ≤ V
Input Common Mode Rejection2.5V ≤ V
50Hz ±2%
Input Common Mode Rejection2.5V ≤ V
60Hz ±2%
Input Normal Mode Rejection2.5V ≤ V
50Hz ±2%
Input Normal Mode Rejection2.5V ≤ V
60Hz ±2%
Input Normal Mode Rejection2.5V ≤ V
50Hz/60Hz ±2%
Reference Common Mode2.5V ≤ V
Rejection DC
Power Supply Rejection DCV
Power Supply Rejection, 50Hz ±2%V
Power Supply Rejection, 60Hz ±2%V
REF
REF
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
≤ VCC, GND ≤ IN– = IN+ ≤ V
REF
= 2.5V, IN– = IN+ = GND120dB
= 2.5V, IN– = IN+ = GND (Notes 7, 9)120dB
= 2.5V, IN– = IN+ = GND (Notes 8, 9)120dB
The ● denotes the specifications which apply over the full operating
= 25°C. (Notes 3, 4)
A
(Note 5)
CC
(Note 5)
CC
(Note 5)
CC
(Notes 5, 7)
CC
(Notes 5, 8)
CC
(Notes 5, 9)
CC
(Note 5)
CC
●
140dB
●
140dB
●
140dB
●
110120dB
●
110120dB
●
87dB
●
120140dB
UUU
AALOG IPUT AUD REFERECE
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
+
IN
–
IN
FSFull Scale of the Differential Input (IN+ – IN–)
The ● denotes the specifications which apply over the full operating
●
0.5V
REF
16
FS/2
–FS+FSV
0.1V
CC
–10110nA
–10110nA
–1001100nA
REF
= V
CC
●
●
●
●
●
●
V
V
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3
LTC2483
UU
I2C DIGITAL I PUTS A D DIGITAL OUTPUTS
the full operating temperature range, otherwise specifications are at T
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
IH
V
IL
V
IL(CA1)
V
IH(CA0/F0,CA1)
R
INH
R
INL
R
INF
I
I
V
HYS
V
OL
t
OF
t
SP
I
IN
C
I
C
B
C
CAX
V
IH(EXT,OSC)
V
IL(EXT,OSC)
High Level Input Voltage
Low Level Input Voltage
Low Level Input Voltage for Address Pin
High Level Input Voltage for Address Pins
Resistance from CA0/F0,CA1 to VCC to Set
Chip Address Bit to 1
Resistance from CA1 to GND to Set
Chip Address Bit to 0
Resistance from CA0/F0, CA1 to VCC or
GND to Set Chip Address Bit to Float
Digital Input Current
Hysteresis of Schmitt Trigger Inputs(Note 5)0.05V
Low Level Output Voltage SDAI = 3mA
Output Fall Time from V
IHMIN
to V
ILMAX
Bus Load CB 10pF to 400pF (Note 14)
Input Spike Suppression
Input Leakage0.1V
CC
≤ V
IN
Capacitance for Each I/O Pin
Capacitance Load for Each Bus Line
External Capacitive Load on Chip
Address Pins (CA0/F
High Level CA0/F0 External Oscillator2.7V ≤ V
Low Level CA0/F0 External Oscillator2.7V ≤ V
,CA1) for Valid Float
0
CC
CC
= 25°C. (Note 3)
A
≤ V
CC
< 5.5V
< 5.5V
The ● denotes the specifications which apply over
●
0.7V
CC
●
●
●
0.95V
CC
●
●
●
●
●
●
●
●
●
●
●
●
●
2MΩ
–1010µA
CC
20+0.1C
B
10pF
V
– 0.5VV
CC
0.3V
CC
0.05V
CC
10kΩ
10kΩ
0.4V
250ns
50ns
1µA
400pF
10pF
0.5V
V
V
V
V
V
WU
POWER REQUIRE E TS
range, otherwise specifications are at T
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
V
CC
I
CC
Supply Voltage
Supply CurrentConversion Mode (Note 11)
A
The ● denotes the specifications which apply over the full operating temperature
= 25°C. (Note 3)
Sleep Mode (Note 11)
●
●
●
2.75.5V
160250µA
12 µA
2483fa
4
LTC2483
WU
TIIG CHARACTERISTICS
range, otherwise specifications are at T
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
f
EOSC
t
HEO
t
LEO
t
CONV_1
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion TimeSimultaneous 50Hz/60Hz
= 25°C. (Note 3)
A
The ● denotes the specifications which apply over the full operating temperature
External Oscillator (Note 10)
●
●
●
●
●
104000kHz
0.125100µs
0.125100µs
144.1146.9149.9ms
41036/f
EOSC
ms
UW
I2C TI I G CHARACTERISTICS
temperature range, otherwise specifications are at T
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
f
SCL
t
HD(SDA)
t
LOW
t
HIGH
t
SU(STA)
t
HD(DAT)
t
SU(DAT)
t
r
t
f
t
SU(STO)
SCL Clock Frequency
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock Pin
HIGH Period of the SCL Clock Pin
Set-Up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time for Both SDA and SCL Signals(Note 14)
Fall Time for Both SDA and SCL Signals(Note 14)
Set-Up Time for STOP Condition
The ● denotes the specifications which apply over the full operating
= 25°C. (Notes 3, 15)
A
●
●
●
●
●
●
●
●
●
●
0400kHz
0.6µs
1.3µs
0.6µs
0.6µs
0 0.9µs
100ns
20+0.1C
B
20+0.1C
B
0.6µs
300ns
300ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: V
= 2.7V to 5.5V unless otherwise specified.
CC
= REF+ – REF–, V
V
REF
= IN+ – IN–, V
V
IN
INCM
= (REF+ + REF–)/2, FS = 0.5V
REFCM
= (IN+ + IN–)/2.
REF
;
Note 4: Use internal conversion clock or external conversion clock source
with f
= 307.2kHz unless otherwise specified.
EOSC
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz f
Note 8: 60Hz f
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or f
= 256kHz ±2% (external oscillator).
EOSC
= 307.2kHz ±2% (external oscillator).
EOSC
EOSC
= 280kHz
±2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/F
external oscillator frequency, f
, is expressed in kHz.
EOSC
pin. The
0
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: C
Note 15: All values refer to V
RMS Noise
vs Input Differential VoltageRMS Noise vs V
1.0
VCC = 5V
V
= 5V
REF
0.9
)
REF
0.8
V
IN(CM)
T
A
= 2.5V
= 25°C
1.0
0.9
0.8
VCC = 5V
= 5V
V
REF
= 0V
V
IN
V
IN(CM)
= 25°C
T
A
= GND
IN(CM)
LTC2483
RMS Noise vs Temperature (TA)
1.0
VCC = 5V
= 5V
V
REF
0.9
= 0V
V
IN
= GND
V
IN(CM)
0.8
0.7
0.6
RMS NOISE (ppm OF V
0.5
0.4
–1.5–0.50.51.5
INPUT DIFFERENTIAL VOLTAGE (V)
RMS Noise vs V
1.0
V
= 2.5V
REF
= 0V
V
IN
= GND
V
0.9
IN(CM)
= 25°C
T
A
0.8
0.7
RMS NOISE (µV)
0.6
0.5
0.4
2.7
3.13.5
CC
4.35.1 5.5
3.94.7
VCC (V)
2483 G10
2483 G13
0.7
RMS NOISE (µV)
0.6
0.5
0.4
–1
2.5–2–2.5–1012
01
RMS Noise vs V
1.0
VCC = 5V
= 0V
V
IN
0.9
0.8
0.7
RMS NOISE (µV)
0.6
0.5
0.4
= GND
V
IN(CM)
= 25°C
T
A
0
1234
356
24
V
(V)
IN(CM)
REF
V
(V)
REF
2483 G11
5
2483 G14
0.7
RMS NOISE (µV)
0.6
0.5
0.4
–45
–30 –1515
Offset Error vs V
0304560
TEMPERATURE (°C)
IN(CM)
75 90
2483 G12
Offset Error vs TemperatureOffset Error vs V
0.3
VCC = 5V
V
REF
0.2
V
)
IN
V
REF
IN(CM)
0.1
0
–0.1
OFFSET ERROR (ppm OF V
–0.2
–0.3
–300
–45
= 5V
= 0V
= GND
–15
TEMPERATURE (°C)
3090
15
CC
0.3
REF+ = 2.5V
–
= GND
REF
)
REF
OFFSET ERROR (ppm OF V
60
45
75
2483 G16
–0.1
–0.2
–0.3
0.2
0.1
0
2.7
= 0V
V
IN
V
IN(CM)
= 25°C
T
A
3.13.5
= GND
4.35.15.5
3.94.7
VCC (V)
2483 G17
Offset Error vs V
0.3
0.2
)
REF
0.1
0
–0.1
OFFSET ERROR (ppm OF V
–0.2
–0.3
0
1234
REF
VCC = 5V
–
= GND
REF
= 0V
V
IN
= GND
V
IN(CM)
= 25°C
T
A
V
(V)
REF
5
2483.G18
2483fa
7
LTC2483
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140
1k100k
2483 G23
10100
10k1M
REJECTION (dB)
VCC = 4.1V DC
V
REF
= 2.5V
IN
+
= GND
IN
–
= GND
T
A
= 25°C
UW
TYPICAL PERFOR A CE CHARACTERISTICS
On-Chip Oscillator Frequency
vs Temperature
310
308
306
304
FREQUENCY (kHz)
VCC = 4.1V
= 2.5V
V
302
REF
= 0V
V
IN
= GND
V
IN(CM)
300
–45 –30
–15
TEMPERATURE (°C)
30
150
PSRR vs Frequency at V
0
VCC = 4.1V DC ±1.4V
= 2.5V
V
REF
–20
+
= GND
IN
–
= GND
IN
–40
= 25°C
T
A
–60
–80
REJECTION (dB)
–100
–120
On-Chip Oscillator Frequency
vs V
CC
310
308
306
304
FREQUENCY (kHz)
302
300
60 75
90
2483 G21
45
2.5
3.54.04.5
3.0
VCC (V)
V
REF
V
IN
V
IN(CM)
= 2.5V
= 0V
= GND
5.05.5
2483 G22
PSRR vs Frequency at V
CC
Conversion Current
CC
PSRR vs Frequency at V
0
VCC = 4.1V DC ±0.7V
= 2.5V
V
REF
–20
+
= GND
IN
–
= GND
IN
–40
= 25°C
T
A
–60
–80
REJECTION (dB)
–100
–120
CC
vs Temperature
200
180
160
140
CONVERSION CURRENT (µA)
120
VCC = 5V
VCC = 2.7V
–140
8
0
60
80
40
20
FREQUENCY AT VCC (Hz)
100
SLEEP MODE CURRENT (µA)
140
120160
180
2483 G24
Sleep Mode Current
vs Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–300
–15
–45
TEMPERATURE (°C)
220200
VCC = 5V
VCC = 2.7V
3090
45
15
–140
30600
60
306503070030800
FREQUENCY AT VCC (Hz)
75
2483 G27
30750
500
450
400
350
300
250
SUPPLY CURRENT (µA)
200
150
100
100
–300
–45
2483 G25
Conversion Current
vs Output Data Rate
V
= V
REF
CC
IN+ = GND
–
= GND
IN
= EXT OSC
CA0/F
0
= 25°C
T
A
0
2040601007010305090
OUTPUT DATA RATE (READINGS/SEC)
VCC = 5V
–15
TEMPERATURE (°C)
VCC = 3V
80
3090
15
2483 G28
60
75
45
2483 G26
2483fa
LTC2483
U
UU
PI FU CTIO S
REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
more positive than the reference negative input, REF
at least 0.1V.
V
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
converter bipolar input range (V
from –0.5 • V
the converter produces unique overrange and underrange
output codes.
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2483 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted out the SDA
pin on the falling edges of the SCL clock.
as long as the reference positive input, REF+, is
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
CC
+ 0.3V. Within these limits the
CC
= IN+ – IN–) extends
IN
to 0.5 • V
REF
. Outside this input range
REF
–
, by
SDA (Pin 7): Serial Data Output Line of the I2C Interface.
In the transmitter mode (Read), the conversion result is
output through the SDA pin. It is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to V
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating)
address control bit for the device I
CA0/F
0
Input Pin. When no transition is detected on the CA0/F
pin, it is a two state (HIGH or Floating) address control bit
for the device I
external clock signal with a frequency f
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located at
a frequency f
internally to a HIGH.
is needed.
CC
2
C address.
(Pin 10): Chip Address Control Pin/External Clock
0
2
C address. When the pin is driven by an
of at least
EOSC
/5120 and sets the Chip Address CA0
EOSC
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9
LTC2483
UU
W
FU CTIO AL BLOCK DIAGRA
+
REF
1
+
IN
4
–
IN
5
+
IN
–
IN
AUTOCALIBRATION
–
REF
3
REF
3RD ORDER
∆Σ ADC
–
REF
AND CONTROL
+
V
GND
2
CC
SCL
6
CA0/F
SDA
CA1
0
2483 FB
7
9
10
I2C
SERIAL
INTERFACE
INTERNAL
OSCILLATOR
8
10
2483fa
WUUU
APPLICATIO S I FOR ATIO
LTC2483
CONVERTER OPERATION
Converter Operation Cycle
The LTC2483 is a low power, ∆Σ analog-to-digital con-
2
verter with an I
C interface. After power on reset, its
operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1).
POWER ON RESET
CONVERSION
SLEEP
NO
ACKNOWLEDGE
YES
DATA OUTPUT
STOP
NO
OR READ
24-BITS
YES
2483 F01
Figure 1. LTC2483 State Transition Diagram
Initially, the LTC2483 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read operation.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
LTC2483 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conversion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. This result is shifted
out on the SDA pin under the control of the SCL. Data is
updated on the falling edges of SCL allowing the user to
reliably latch data on the rising edge of SCL. A new
conversion is initiated at the conclusion of a data read
operation (read out all 24 bits).
2
I
C INTERFACE
The LTC2483 communicates through an I2C interface.
2
The I
C interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
they never drive the bus HIGH. The bus wires are externally connected to a positive supply voltage via a currentsource or pull-up resistor. When the bus is free, both
lines are HIGH. Data on the I2C-bus can be transferred at
rates of up to 100kbit/s in the Standard-mode and up to
400kbit/s in the Fast-mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit that transfer. At the same time any device
addressed is considered a slave.
The LTC2483 can only be addressed as a slave. Once
addressed, it can transmit the last conversion result.
Therefore the serial clock line SCL is an input only and the
data line SDA is bidirectional (data out/address in). The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
2
on the I
C-bus.
The device will not acknowledge an external request
during the conversion state. After a conversion is finished,
the device is ready to accept a read request. Once the
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APPLICATIO S I FOR ATIO
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The
repeated START (Sr) conditions are functionally identical
to the START (S).
SDA
t
SU;DAT
t
r
SCL
t
f
t
LOW
t
r
Data Transferring
2
After the START condition, the I
C bus is busy and data
transfer is set between a master and a slave. Data is
2
transferred over I
C in groups of nine bits (one byte)
followed by an acknowledge bit, therefore each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an Acknowledge (ACK) by pulling SDA LOW or
leaves SDA HIGH to indicate a Not Acknowledge (NAK)
condition. Change of data state can only happen while SCL
is LOW.
t
HD;STA
t
SP
t
t
r
BUF
t
HD;STA
SSrPS
t
HD;DAT
Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus
t
HIGH
t
SU;STA
t
SU;STO
2483 F02
12
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LTC2483
LTC2483 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2483’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. A write operation will also generate an NAK
signal. If the conversion is complete, it issues an acknowledge (ACK) by pulling SDA LOW.
The output register contains the last conversion result.
After each conversion is completed, the device automatically enters the sleep state where the supply current is
reduced to 1µA. When the LTC2483 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can read
up to three bytes from the LTC2483. After a complete Read
operation (3 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same output phase will be NAKed. The LTC2483 output
data stream is 24 bits long, shifted out on the falling edges
of SCL. The first bit is the conversion result sign bit (SIG),
see Tables 1 and 2. This bit is HIGH if V
<0. The second bit is the most significant bit (MSB) of
V
IN
≥ 0. It is LOW if
IN
the result. The first two bits (SIG and MSB) can be used to
indicate over range conditions. If both bits are HIGH, the
differential input voltage is above +FS and the following 16
bits are set to LOW to indicate an overrange condition. If
both bits are LOW, the input voltage is below –FS and the
following 16 bits are set to HIGH to indicate an underrange
condition. The function of these two bits is summarized in
Table 1. The next 16 bits contain the conversion results in
binary two’s complement format. The remaining six bits
are LOW.
Table 1. LTC2483 Status Bits
BIT 23BIT 22
INPUT RANGESIGMSB
VIN ≥ 0.5 • V
0V ≤ VIN < 0.5 • V
–0.5 • V
VIN < –0.5 • V
REF
≤ VIN < 0V01
REF
REF
REF
11
10
00
As long as the voltage on the IN+ and IN– pins is maintained within the – 0.3V to (V
+ 0.3V) absolute maximum
CC
operating range, a conversion result is generated for any
differential input voltage
= 0.5 • V
. For differential input voltages greater than
REF
from –FS = –0.5 • V
VIN
REF
to +FS
+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • V
REF
.
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APPLICATIO S I FOR ATIO
Initiating a New Conversion
When the LTC2483 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device
is ready for a Read operation. After the device acknowledges a Read request, the device exits the sleep state and
enters the data output state. The data output state concludes and the LTC2483 starts a new conversion once a
STOP condition is issued by the master or all 24-bits of
data are read out of the device.
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the 9th clock cycle of a byte read when the
bus is free (the ACK/NAK cycle).
LTC2483 Address
The LTC2483 has two address pins, enabling one in 6
possible addresses, as shown in Table 3.
Table 3. LTC2483 Address Assignment
CA1CA0/F0 *Address
LOWHIGH001 01 00
LOWFloating001 01 01
FloatingHIGH001 01 11
FloatingFloating010 01 00
HIGHHIGH010 01 10
HIGHFloating010 01 11
* CA0/F0 is treated as HIGH when driven by a valid external clock.
Data Read
The data read operation sequence is shown in Figure 5.
When the conversion is finished, the device may be
addressed for a read operation. At the end of a read
operation, a new conversion begins. At the conclusion
of the conversion cycle, the next result may be read
using the method described above. If the conversion
cycle is not concluded and a valid address selects the
device, the LTC2483 generates a NAK signal indicating
the conversion cycle is in progress.
Easy Drive Input Current Cancellation
The LTC2483 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input current. This enables external RC networks and high impedance sensors to directly interface to the LTC2483 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architecture does not require on-chip buffers enabling input
signals to swing all the way to ground and up to V
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale auto-calibration and the
absolute accuracy (full scale + offset + linearity) is maintained even with external RC networks.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz and 60Hz plus
their harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock. The
LTC2483 incorporates a highly accurate on-chip oscillator.
This eliminates the need for external frequency setting components such as crystals or oscillators.
CC
.
14
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APPLICATIO S I FOR ATIO
LTC2483
Frequency Rejection Selection (CA0/F0)
The LTC2483 internal oscillator provides better than 87dB
normal mode rejection at line frequencies of 50Hz and
60Hz and all of their harmonics (up to the 255th) from
48Hz to 62.4Hz.
When a fundamental rejection frequency different from
50Hz/60Hz is required or when the converter must be
synchronized with an outside source, the LTC2483 can
operate with an external conversion clock. The converter
7 … …89 1 29
1
7-BIT
ADDRESS
START BY
MASTER
ACK BY
LTC2483
SLEEPDATA OUTPUT
ACK BY
MASTER
automatically detects the presence of an external clock
signal at the CA0/F
pin and turns off the internal oscilla-
0
tor. The chip address for CA0 is internally set HIGH. The
frequency f
of the external signal must be at least
EOSC
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
1 23456 789
LSBRMSBSGND15
, the LTC2483 provides better than 110dB
EOSC
NAK BY
MASTER
2483 F03
Figure 3. Timing Diagram for Reading from the LTC2483
SACKDATASrDATA TRANSFERRINGP
CONVERSIONCONVERSION
7-BIT ADDRESS
SLEEPDATA INPUT/OUTPUTCONVERSION
7-BIT ADDRESS
SLEEPSLEEPDATA OUTPUTDATA OUTPUT
R/W
2483 F04
Figure 4. The LTC2483 Conversion Sequence
7-BIT ADDRESSSSRRACKACKREADREADPP
CONVERSION
2483 F05
Figure 5. Consecutive Reading at the Same Configuration
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APPLICATIO S I FOR ATIO
normal mode rejection in a frequency range of f
EOSC
/5120
± 4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/5120
is shown in Figure 6.
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
NORMAL MODE REJECTION (dB)
–130
–135
–140
–12–8–404812
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
Figure 6. LTC2483 Normal Mode Rejection When
Using an External Oscillator
Whenever an external clock is not present at the CA0/F
EOSC
/5120(%)
2483 F06
0
pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode.
CA0/F
may be tied HIGH or left floating in order to set the
0
chip address. The LTC2483 operation will not be disturbed if the change of conversion clock source occurs
during the sleep state or during the data output state while
the converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected.
Table 4 summarizes the duration of the conversion state of
each state and the achievable output data rate as a function
of f
EOSC
.
Ease of Use
The
LTC2483
data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2483 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to the
user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2483 automatically enters an internal reset state
when the power supply voltage V
drops below approxi-
CC
mately 2V. This feature guarantees the integrity of the conversion result.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2483 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2483 external reference voltage range is 0.1V to
VCC. The converter output noise is determined by the
Table 4. LTC2483 State Duration
STATEOPERATING MODEDURATION
CONVERSIONInternal Oscillator50Hz/60Hz Rejection147ms, Output Data Rate ≤ 6.8 Readings/s
External OscillatorCA0/F0 = External Oscillator with Frequency 41036/f
f
EOSC
Hz (f
/5120 Rejection)
EOSC
s, Output Data Rate ≤ f
EOSC
/41036 Readings/s
EOSC
16
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IINIIN
VV
R
I REF
VV V
R
V
VR
VD
R
VV V
R
V
VR
where
AVGAVG
IN CMREF CM
EQ
AVG
REF INCM REFCM
EQ
IN
REF EQ
REF T
EQ
REFREF CMIN CM
EQ
IN
REF EQ
+
+
REF+REF
–
()=()
=
−
•
()
=
•−+
•
−
•
−≅
+
()
–
()()
() ()
.
.
.
.• •
.–
.•
–
•
05
15
05
05
15
05
2
2
:
V
VININ
V
IN IN
REFCM
IN
INCM
=
=−
=
+
−
⎛
⎝
⎜
⎞
⎠
⎟
=Ω
=•
()
+−
+−
V,
REF
=
REF
+
REF–+
⎛
⎝
⎜
⎞
⎠
⎟
2
2
R2.98M INTERNAL OSCILLATOR
R0.833 10 / fEXTERNAL OSCILLATOR
D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
EQ
EQ
12
EOSC
T
WHERE REF– IS INTERNALLY TIED TO GND
APPLICATIO S I FOR ATIO
LTC2483
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference voltage. Since the transition noise (600nV) is much less than
the quantization noise (V
/217), a decrease in the refer-
REF
ence voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external F
signal) at substantially higher output
O
data rates (see the Output Data Rate section).
The reference input is differential. The differential reference input range (V
the common mode reference input range is 0V to V
= REF+ – REF–) is 100mV to VCC and
REF
CC
.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN
extending from GND – 0.3V to V
+
and IN– input pins
+ 0.3V. Outside
CC
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly.
Within these limits, the LTC2483 converts the bipolar
differential input signal, V
where FS = 0.5 • V
REF
= IN+ – IN–, from –FS to +FS
IN
. Beyond this range, the converter
indicates the overrange or the underrange condition using
distinct output codes. Since the differential input current
cancellation does not rely on an on-chip buffer, current
cancellation and DC performance is maintained rail-to-rail.
nput signals applied to IN+ and IN– pins may extend by
I
300mV below ground and above V
. In order to limit any
CC
fault current, resistors of up to 5k may be added in series
+
with the IN
and IN– pins without affecting the performance of the devices. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if V
= 5V. This error has a
REF
very strong temperature dependency.
Driving the Input and Reference
The input and reference pins of the LTC2483 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these capacitors are switching between these four pins transferring
small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 7.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with R
and CEQ (see
SW
Figure 7), a first order passive network with a time constant
τ = (R
+ RSW) • CEQ. The converter is able to sample the
S
V
CC
+
I
REF
V
REF
+
I
IN
+
V
IN
–
I
IN
–
V
IN
SWITCHING FREQUENCY
f
SW
f
SW
I
REF
V
REF
= 123kHz INTERNAL OSCILLATOR
= 0.4 • f
+
V
CC
–
–
EXTERNAL OSCILLATOR
EOSC
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
RSW (TYP)
10k
RSW (TYP)
I
LEAK
10k
I
LEAK
RSW (TYP)
10k
RSW (TYP)
I
LEAK
10k
I
LEAK
C
EQ
12pF
(TYP)
2483 F07
Figure 7. LTC2483 Equivalent Analog Input Circuit
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APPLICATIO S I FOR ATIO
input signal with better than 1ppm accuracy if the sampling
period is at least 14 times greater than the input circuit time
constant τ. The sampling process on the four input analog
pins is quasi-independent so each time constant should be
considered by itself and, under worst-case circumstances,
the errors may add.
When using the internal oscillator, the LTC2483’s frontend switched-capacitor network is clocked at 123kHz
corresponding to an 8.1µs sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that τ ≤ 8.1µs/14 =
580ns. When an external oscillator of frequency f
used, the sampling period is 2.5/f
error of less than 1ppm, τ ≤ 0.178/f
and, for a settling
EOSC
.
EOSC
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is low
(up to 10kΩ with no external bypass capacitor or up to
500Ω with 0.001µF bypass), complete settling of the input
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
For many applications, the sensor output impedance combined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10kΩ bridge driving a 0.1µF
bypass capacitor has a time constant an order of magnitude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or V
), added system cost and increased
CC
power. The LTC2483 uses a proprietary switching algorithm that forces the average differential input current to
zero independent of external settling errors. This allows
accurate direct digitization of high impedance sensors
without the need of buffers (see Figures 8 to 10). Additional errors resulting from mismatched leakage currents
must also be taken into account.
The switching algorithm forces the average input current
on the positive input (I
current on the negative input (I
+
) to be equal to the average input
IN
–
). Over the complete
IN
conversion cycle, the average differential input current
(I
IN+
–
– I
) is zero. While the differential input current is
IN
EOSC
is
R
SOURCE
V
V
INCM
INCM
+ 0.5V
– 0.5V
IN
R
SOURCE
IN
C
EXT
C
EXT
Figure 8. An RC Network at IN+ and IN
80
VCC = 5V
= 5V
V
REF
60
+
= 3.75V
V
IN
–
= 1.25V
V
IN
40
= 25°C
T
A
20
0
–20
+FS ERROR (ppm)
–40
–60
–80
1
C
= 1nF, 0.1µF, 1µF
EXT
1010010k
R
SOURCE
Figure 9. +FS Error vs R
80
VCC = 5V
= 5V
V
REF
60
+
= 1.25V
V
IN
–
= 3.75V
V
IN
40
= 25°C
T
A
20
0
–20
–FS ERROR (ppm)
–40
–60
–80
1
C
= 1nF, 0.1µF, 1µF
EXT
1010010k
R
SOURCE
Figure 10. –FS Error vs R
C
C
EXT
1k
(Ω)
SOURCE
= 100pF
C
EXT
1k
(Ω)
SOURCE
IN
C
PAR
≅20pF
LTC2483
IN
C
PAR
≅20pF
= 0pF
EXT
= 100pF
2483 F09
at IN+ and IN
C
= 0pF
EXT
100k
2483 F10
at IN+ and IN
+
–
2483 F08
–
100k
–
–
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APPLICATIO S I FOR ATIO
+
zero, the common mode input current (I
IN
proportional to the difference between the common mode
input voltage (V
voltage (V
REFCM
) and the common mode reference
INCM
).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN
also do not affect the accuracy.
+ I
IN
+
and IN
–
)/2 is
–
LTC2483
Table 5. Suggested Input Configuration for LTC2483
IN+ and IN–. Can Takeand IN–. Can Take Large
Large Source Resistance Source Resistance.
with Negligible ErrorUnbalanced Resistance
> 1nF at Both IN+Minimize IN+ and IN
EXT
and IN–. Can Take LargeCapacitors and Avoid
Source Resistance withLarge Source Impedance
Negligible Error(<5k Recommended)
> 1nF at Both IN
EXT
Results in an Offset
Which Can be Calibrated
+
–
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
INCM
and V
. For a reference
REFCM
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74µA. This common mode input current has no effect on
the accuracy if the external source impedances tied to IN
+
and IN– are matched. Mismatches in these source impedances lead to a fixed offset error but do not affect the
linearity or full-scale reading. A 1% mismatch in 1kΩ
source resistances leads to a 15ppm shift (74µV) in offset
voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2483 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1kΩ source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input common mode voltages.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN
–
IN
, the expected drift of the dynamic current and offset
+
and
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and 10µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2483 samples the differential
reference pins REF
+
and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.
For relatively small values of the external reference capacitors (C
< 1nF), the voltage on the sampling capacitor
REF
settles almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
will deteriorate the converter offset and gain
REF
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LTC2483
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APPLICATIO S I FOR ATIO
performance without significant benefits of reference filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
> 1nF) may be
REF
required as reference filters in certain configurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. For the internal
oscillator, the related difference resistance is 1.1MΩ and
90
VCC = 5V
80
= 5V
V
REF
+
= 3.75V
V
IN
70
–
= 1.25V
V
IN
= 25°C
T
A
60
50
40
30
+FS ERROR (ppm)
20
10
0
–10
C
= 0.01µF
REF
= 0.001µF
C
REF
= 100pF
C
REF
= 0pF
C
REF
10
0
100
R
SOURCE
(Ω)
1k
10k
100k
2483 F11
the resulting full-scale error is 0.46ppm for each ohm of
source resistance driving the REF
CA0/F
f
is driven by an external oscillator with a frequency
0
(external conversion clock operation), the typical
EOSC
differential reference resistance is 0.30 • 10
each ohm of source resistance driving the REF
–6
will result in 1.67 • 10
• f
EOSC
+
and REF– pins. When
12
/f
Ω and
EOSC
+
or REF– pins
ppm gain error. The typical
+FS and –FS errors for various combinations of source
resistance seen by the REF
+
or REF– pins and external
capacitance connected to that pin are shown in Figures
11-14.
10
0
C
C
REF
VCC = 5V
= 5V
V
REF
+
= 1.25V
V
IN
–
= 3.75V
V
IN
= 25°C
T
A
= 0.01µF
REF
= 0.001µF
= 100pF
C
REF
C
REF
10
= 0pF
100
R
SOURCE
1k
(Ω)
10k
100k
2483 F12
–10
–20
–30
–40
–50
–FS ERROR (ppm)
–60
–70
–80
–90
0
Figure 11. +FS Error vs R
500
VCC = 5V
= 5V
V
REF
+
= 3.75V
V
IN
400
–
= 1.25V
V
IN
= 25°C
T
A
300
200
+FS ERROR (ppm)
100
0
200
0
Figure 13. +FS Error vs R
20
at REF+ or REF– (Small C
SOURCE
C
= 1µF, 10µF
REF
C
REF
C
= 0.01µF
REF
600
400
R
SOURCE
at REF+ or REF– (Large C
SOURCE
800
(Ω)
= 0.1µF
2483 F13
1000
REF
REF
)
)
Figure 12. –FS Error vs R
0
–100
–200
C
= 1µF, 10µF
REF
–300
–FS ERROR (ppm)
VCC = 5V
= 5V
V
REF
+
–400
–500
0
V
IN
V
IN
T
A
= 1.25V
–
= 3.75V
= 25°C
200
Figure 14. –FS Error vs R
at REF+ or REF– (Small C
SOURCE
C
= 0.01µF
REF
C
= 0.1µF
REF
600
400
R
SOURCE
at REF+ or REF– (Large C
SOURCE
800
(Ω)
1000
2483 F14
REF
REF
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APPLICATIO S I FOR ATIO
LTC2483
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
2
–V
/(V
IN
• REQ) – (0.5 • V
REF
• DT)/REQ in the reference
REF
pin current as expressed in Figure 7. When using internal
oscillator, every 100Ω of reference source resistance
translates into about 0.61ppm additional INL error. When
CA0/F
f
REF
is driven by an external oscillator with a frequency
0
, every 100Ω of source resistance driving REF+ or
EOSC
–
translates into about 2.18 • 10–6 • f
EOSC
ppm additional INL error. Figure 15 shows the typical INL error due
to the source resistance driving the REF
when large C
values are used. The user is advised to
REF
minimize the source impedance driving the REF
–
REF
pins.
+
or REF– pins
+
and
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
– V
) and a 5V reference,
INCM
each Ohm of reference source resistance introduces an
extra (V
REFCM
– V
INCM
)/(V
• REQ) full-scale gain error,
REF
which is 0.067ppm when using internal oscillator. If an
external clock is used, the corresponding extra gain error
is 0.24 • 10
–6
• f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF
+
and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maxi-
mum full-scale error.
10
VCC = 5V
8
= 5V
V
REF
= 2.5V
V
IN(CM)
6
= 25°C
T
A
= 10µF
C
)
REF
4
REF
2
0
–2
INL (ppm OF V
–4
–6
–8
–10
Figure 15. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for C
–0.5
–0.3
–0.1
VIN/V
REF
0.1
(V)
R = 1k
R = 500Ω
R = 100Ω
0.3
REF
0.5
2483 F15
> 1µF
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LTC2483
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APPLICATIO S I FOR ATIO
Output Data Rate
When using its internal oscillator, the LTC2483 produces
up to 6.82sps with simultaneous 50Hz/60Hz rejection. The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (CA0/F
con-
0
nected to an external oscillator), the LTC2483 output data
rate can be increased as desired. The duration of the
conversion phase is 41036/f
EOSC
. If f
= 307.2kHz, the
EOSC
converter notch is set at 60Hz.
An increase in f
over the nominal 307.2kHz will
EOSC
translate into a proportional increase in the maximum
50
V
= V
IN(CM)
VCC = V
40
V
)
CA0/F
REF
30
20
10
OFFSET ERROR (ppm OF V
0
–10
REF(CM)
= 5V
REF
= 0V
IN
= EXT CLOCK
0
TA = 85°C
TA = 25°C
20406080
OUTPUT DATA RATE (READINGS/SEC)
10010030507090
2483 F16
output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in f
will result in a proportional change
EOSC
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying
upon the LTC2483’s exceptional common mode rejection
and by carefully eliminating common mode to differential
mode conversion sources in the input circuit. The user
should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the
circuits driving the IN
3500
V
VCC = V
3000
CA0/F
)
REF
2500
2000
1500
1000
+FS ERROR (ppm OF V
500
0
0
+
and IN– pins.
= V
IN(CM)
REF(CM)
= 5V
REF
= EXT CLOCK
0
TA = 85°C
T
= 25°C
A
50
6080
70
30
40
20
10
OUTPUT DATA RATE (READINGS/SEC)
90
2483 F17
100
Figure 16. Offset Error vs Output Data Rate and TemperatureFigure 17. +FS Error vs Output Data Rate and Temperature
0
–500
)
REF
–1000
–1500
–2000
–2500
–FS ERROR (ppm OF V
V
= V
IN(CM)
–3000
VCC = V
REF
= EXT CLOCK
CA0/F
–3500
0
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
TA = 85°C
REF(CM)
= 5V
30
40
6080
50
T
A
= 25°C
70
90
2483 F18
100
Figure 18. –FS Error vs Output Data Rate and Temperature
22
24
22
TA = 85°C
20
18
16
V
RESOLUTION (BITS)
14
12
10
= V
IN(CM)
VCC = V
V
CA0/F
RES = LOG 2 (V
0
REF(CM)
= 5V
REF
= 0V
IN
= EXT CLOCK
0
30
20
10
OUTPUT DATA RATE (READINGS/SEC)
Figure 19. Resolution (Noise
REF
40
/NOISE
50
= 25°C
T
A
)
RMS
70
6080
RMS
90
2483 F19
≤ 1LSB)
vs Output Data Rate and Temperature
100
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LTC2483
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred through the input and the reference pins. If large
external input and/or reference capacitors (CIN, C
REF
) are
used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter
performance for any value of f
and/or reference capacitors (C
. If small external input
EOSC
, C
IN
) are used, the
REF
effect of the external source resistance upon the LTC2483
typical performance can be inferred from Figures 9, 10,
11 and 12 in which the horizontal axis is scaled by
307200/f
EOSC
22
20
.
18
T
TA = 85°C
16
= 25°C
A
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3
+
increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity.
Typical measured performance curves for output data
rates up to 100 readings per second are shown in Figures 16 to 23. In order to obtain the highest possible level
of accuracy from this converter at output data rates above
20 readings per second, the user is advised to maximize
the power supply voltage used and to limit the maximum
ambient operating temperature. In certain circumstances,
a reduction of the
differential reference voltage may
be beneficial.
20
V
= V
IN(CM)
= 25°C
A
0
REF(CM)
= EXT CLOCK
VCC = V
REF
= 5V
VIN = 0V
CA0/F
)
15
T
REF
10
5
14
RESOLUTION (BITS)
V
= V
IN(CM)
VCC = V
12
CA0/F
RES = LOG 2 (V
10
0
Figure 20. Resolution (INL
REF(CM)
= 5V
REF
= EXT CLOCK
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
/INL
40
MAX
6080
50
)
70
MAX
≤ 1LSB)
REF
30
90
2483 F20
100
vs Output Data Rate and Temperature
24
22
VCC = 5V, V
20
18
16
V
RESOLUTION (BITS)
14
VIN = 0V
CA0/F
12
T
RES = LOG 2 (V
10
0
REF
= V
IN(CM)
REF(CM)
= EXT CLOCK
0
= 25°C
A
30
20
10
OUTPUT DATA RATE (READINGS/SEC)
Figure 22. Resolution (Noise
= 2.5V
/NOISE
REF
40
V
CC
RMS
6080
50
= V
REF
)
70
RMS
= 5V
90
2483 F22
≤ 1LSB)
100
vs Output Data Rate and Reference Voltage
0
OFFSET ERROR (ppm OF V
–5
–10
VCC = 5V, V
0
30
20
10
OUTPUT DATA RATE (READINGS/SEC)
40
REF
50
= 2.5V
6080
90
2483 F21
100
70
Figure 21. Offset Error vs Output
Data Rate and Reference Voltage
22
20
18
16
VCC = 5V, V
14
V
RESOLUTION (BITS)
12
10
= V
IN(CM)
VIN = 0V
= EXT CLOCK
CA0/F
0
= 25°C
T
A
RES = LOG 2 (V
0
20
10
OUTPUT DATA RATE (READINGS/SEC)
REF
REF(CM)
30
= 2.5V
REF
40
/INL
VCC = V
MAX
50
Figure 23. Resolution (INL
REF
)
70
6080
≤ 1LSB)
MAX
= 5V
90
2483 F23
100
vs Output Data Rate and Reference Voltage
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APPLICATIO S I FOR ATIO
Input Bandwidth
The combined effect of the internal SINC
4
digital filter and
of the analog and digital autocalibration circuits determines the LTC2483 input bandwidth. When the internal
oscillator is used, the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency f
connected to the CA0/F
11.8 • 10
–6
• f
EOSC
pin, the 3dB input bandwidth is
0
.
EOSC
is
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is
used, the shape of the LTC2483 input bandwidth is
shown in Figure 24. When an external oscillator of frequency f
is used, the shape of the LTC2483 input
EOSC
bandwidth can be derived from Figure 24, in which the
horizontal axis is scaled by f
The conversion noise (600nV
/279.2kHz.
EOSC
typical for V
RMS
= 5V) can
REF
be modeled by a white noise source connected to a noise
free converter. The noise spectral density is 47nV√Hz for
an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in order
to reduce the output referred noise and relatively high
bandwidth (at least 500kHz) necessary to drive the input
switched-capacitor network. A possible solution is a high
gain, low bandwidth amplifier stage followed by a high
bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2483, the
ADC input referred system noise calculation can be
simplified by Figure 25. The noise of an amplifier driving
the LTC2483 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency f
. From Figure 25, using fi as the x-axis selector, we
is n
i
. The amplifier noise spectral density
i
can find on the y-axis the noise equivalent bandwidth
of the input driving amplifier. This bandwidth in-
freq
i
cludes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these
effects can be calculated as N = n
• √freqi. The total
i
system noise (referred to the LTC2483 input) can now be
obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2483
internal noise, the noise of the IN
–
the noise of the IN
If the CA0/F
frequency f
0
EOSC
driving amplifier.
pin is driven by an external oscillator of
, Figure 25 can still be used for noise
calculation if the x-axis is scaled by f
large values of the ratio f
EOSC
+
driving amplifier and
/307200. For
EOSC
/307200, the Figure 25 plot
accuracy begins to decrease, but at the same time the
LTC2483 noise floor rises and the noise contribution of the
driving amplifiers lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2483 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2483
allows external lowpass filtering without degrading the DC
performance of the device.
The SINC
4
digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(f
). The LTC2483’s autocalibration circuits further sim-
S
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f
• f
OUTMAX
where fN is the notch frequency and f
= 256 • fN = 2048
S
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode, f
f
EOSC
= 13960Hz. In the external oscillator mode, fS =
S
/20. The performance of the normal mode rejection
is shown in Figures 26 and 27.
The regions of low rejection occurring at integer multiples
of f
have a very narrow bandwidth. Magnified details of
S
the normal mode rejection curves are shown in Figure 28
(rejection near DC) and Figure 29 (rejection at f
where f
represents the notch frequency. These curves
N
= 256fN)
S
have been derived for the external oscillator mode but they
can be used in all operating modes by appropriately
selecting the fN value.
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LTC2483
0
–1
–2
50Hz f
–3
–4
–5
INPUT SIGNAL ATTENUATION (dB)
–6
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
EOSC
1
60Hz f
= 256kHz
INTERNAL
OSCILLATOR
2
EOSC
3
= 307.2kHz
4
2483 F24
5
Figure 24. Input Signal Using the Internal Oscillator
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
INPUT NORMAL MODE REJECTION (dB)
–110
–120
0f
S2fS3fS4fS5fS6fS7fS8fS9fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
10fS11fS12f
2483 F26
S
Figure 26. Input Normal Mode Rejection,
External Oscillator (f
= 256kHz)
EOSC
50Hz Rejection
100
10
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
0.1
0.1110100 1k10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
2483 F25
Figure 25. Input Refered Noise Equivalent Bandwidth
of an Input Connected White Noise Source
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
INPUT NORMAL MODE REJECTION (dB)
–110
–120
0f
2fS3fS4fS5fS6fS7fS8fS9fS10f
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
S
2483 F27
Figure 27. Input Normal Mode Rejection at DC
(Internal Oscillator)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
INPUT NORMAL MODE REJECTION (dB)
–110
–120
fN02fN3fN4fN5fN6fN7fN8f
INPUT SIGNAL FREQUENCY (Hz)
fN = f
EOSC/5120
N
2483 F28
Figure 28. Input Normal Mode Rejection at DC
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
INPUT NORMAL MODE REJECTION (dB)
–110
–120
250f
252fN254fN256fN258fN260fN262f
N
INPUT SIGNAL FREQUENCY (Hz)
N
2483 F29
Figure 29. Input Normal Mode Rejection at fs = 256f
N
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APPLICATIO S I FOR ATIO
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 30, 31 and 32. Typical measured values of the
normal mode rejection of the LTC2483 operating with an
external oscillator and a 60Hz notch setting are shown in
Figure 30 superimposed over the theoretical calculated
curve. Similarly, the measured normal rejection of the
LTC2483 for 50Hz rejection (f
60Hz rejection (internal oscillator) are shown in Figures 31
and 32.
As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front
of the LTC2483. If passive RC components are placed in
front of the LTC2483, the input dynamic current should be
considered (see Input Current section). In this case, the
differential input current cancellation feature of the LTC2483
allows external RC networks without significant degradation in DC performance.
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The proprietary architecture used for the LTC2483 third order
= 256kHz) and 50Hz/
EOSC
modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of
full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed on volt level perturbations and the LTC2483 is
eminently suited for such tasks. When the perturbation is
differential, the specification of interest is the normal mode
rejection for large input signal levels. With a reference
voltage V
input range of 5V peak-to-peak. Figures 33 and 34 show
measurement results for the LTC2483 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peakto-peak (full scale) input signal. In Figure 33, the LTC2483
uses the external oscillator with the notch set at 60Hz and
in Figure 34 it uses the external oscillator with the notch set
at 50Hz. It is clear that the LTC2483 rejection performance
is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user
must observe that such signals do not violate the device
absolute maximum ratings.
#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port
#include “PCM73A.h” // Various defines
#include “lcd.c” // LCD driver functions
#define READ 0x01 // bitwise OR with address for read or write
#define WRITE 0x00
#define LTC248XADDR 0b01001000 // The one and only LTC248X in this circuit,
// with both address lines floating.
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the
// 8 bit config word.
// These do NOT apply to the LTC2483.
// Select gain - 1 to 256 (also depends on speed setting)
// Does NOT apply to LTC2485.
#define GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 (SPD = 1)
#define GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 (SPD = 1)
#define GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 (SPD = 1)
#define GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 (SPD = 1)
#define GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 (SPD = 1)
#define GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 (SPD = 1)
#define GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 (SPD = 1)
#define GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 (SPD = 1)
// Select rejection frequency - 50, 55, or 60Hz
#define R50 0b00000010
#define R55 0b00000000
#define R60 0b00000100
// Select speed mode
#define SLOW 0b00000000 // slow output rate with autozero
#define FAST 0b00000001 // fast output rate with no autozero
28
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/*
LTC2483.c
Basic voltmeter test program for LTC2483
Reads LTC2483, converts result to volts,
and prints voltage to a 2 line by 16 character LCD display.
Mark Thoren
Linear Technonlgy Corporation
June 23, 2005
Written for CCS PCM compiler, Version 3.182
*/
#include “LTC248X.h”
/*** read_LTC2483() ************************************************************
This is the funciton that actually does all the work of talking to the LTC2483.
Arguments: addr - device address
Returns: zero if conversion is in progress,
32 bit signed integer with lower 8 bits clear, 24 bit LTC2483
output word in the upper 24 bits. Data is left-justified for
compatibility with the 24 bit LTC2485.
LTC2483
the i2c_xxxx() functions do the following:
void i2c_start(void): generate an i2c start or repeat start condition
void i2c_stop(void): generate an i2c stop condition
char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack
boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device
These functions are very compiler specific, and can use either a hardware i2c
port or software emulation of an i2c port. This example uses software emulation.
A good starting point when porting to other processors is to write your own
i2c functions. Note that each processor has its own way of configuring
the i2c port, and different compilers may or may not have built-in functions
for the i2c port.
When in doubt, you can always write a “bit bang” function for troubleshooting
purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{ // To allow byte access to a 32 bit int or float.
int8 te0; //
int8 te1; // The make32() function in this compiler will
int8 te2; // also work, but a union of 4 bytes and a 32 bit int
int8 te3; // is probably more portable.
};
*******************************************************************************/
signed int32 read_LTC2483(char addr)
{
struct fourbytes // Define structure of four consecutive bytes
{ // To allow byte access to a 32 bit int or float.
int8 te0; //
int8 te1; // The make32() function in this compiler will
int8 te2; // also work, but a union of 4 bytes and a 32 bit int
int8 te3; // is probably more portable.
};
// Start communication with LTC2483:
i2c_start();
if(i2c_write(addr | READ))// If no acknowledge, return zero
{
i2c_stop();
return 0;
}
adc_code.by.te3 = i2c_read();
adc_code.by.te2 = i2c_read();
adc_code.by.te1 = i2c_read();
adc_code.by.te0 = 0;
i2c_stop();
return adc_code.bits32;
} // End of read_LTC2483()
/*** initialize() **************************************************************
Basic hardware initialization of controller and LCD, send Hello message to LCD
*******************************************************************************/
void initialize(void)
{
// General initialization stuff.
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
// This is the important part - configuring the SPI port
setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock
CKP = 0; // Set up clock edges - clock idles low, data changes on
CKE = 1; // falling edges, valid on rising edges.
lcd_init(); // Initialize LCD
delay_ms(6);
printf(lcd_putc, “Hello!”); // Obligatory hello message
delay_ms(500); // for half a second
} // End of initialize()
/*** main() ********************************************************************
Main program initializes microcontroller registers, then reads the LTC2483
repeatedly
*******************************************************************************/
void main()
{
signed int32 x; // Integer result from LTC2481
float voltage; // Variable for floating point math
int16 timeout;
initialize(); // Hardware initialization
while(1)
{
delay_ms(1); // Pace the main loop to something more than 1 ms
// This is a basic error detection scheme. The LTC2483 will never take more than
// 149.9ms to complete a conversion in the 55Hz
// rejection mode.
2483fa
30
LTC2483
D
WUUU
APPLICATIO S I FOR ATIO
// If read_LTC2483() does not return non-zero within this time period, something
// is wrong, such as an incorrect i2c address or bus conflict.
if((x = read_LTC2483(LTC248XADDR)) != 0)
{
// No timeout, everything is okay
timeout = 0; // reset timer
x ^= 0x80000000; // Invert MSB, result is 2’s complement
voltage = (float) x; // convert to float
voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31
lcd_putc(‘\f’); // Clear screen
lcd_gotoxy(1,1); // Goto home position
printf(lcd_putc, “V %01.4f”, voltage); // Display voltage
}
else
{
++timeout;
}
if(timeout > 200)
{
timeout = 200; // Prevent rollover
lcd_gotoxy(1,1);
printf(lcd_putc, “ERROR - TIMEOUT”);
delay_ms(500);
}
} // End of main loop
} // End of main()
PACKAGE DESCRIPTIO
3.50 ±0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.25 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION
ASSIGNMENT
2.38 ±0.05
(2 SIDES)
0.50
BSC
U
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
PACKAGE
OUTLINE
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SI
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
3.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
TOP AND BOTTOM OF PACKAGE
1.65 ± 0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
106
15
0.25 ± 0.05
0.50 BSC
0.38 ± 0.10
(DD10) DFN 1103
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2483fa
31
LTC2483
TYPICAL APPLICATIO
U
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
ISOTHERMAL
R2
2k
5V
R6
5k
1
2
3
CONTRAST
5V
3
REF
4
+
IN
LTC2483
–
IN
5
2 × 16 CHARACTER
(OPTREX DMC162488
GND D0
GNDCA1
5V
V
CC
LCD DISPLAY
OR SIMILAR)
D1 D2 D3
REF
C8
C7
1µF
0.1µF
1.7k
1.7k
2
6
V
CC
SCL
7
SDA
10
–
CAO/F
O
389
D7
D6
D5
D4
EN
RW
RS
CALIBRATE
2
1
DOWNUP
R3
10k
R4
10k
5V
R5
10k
PIC16F73
18
RC7
17
RC6
16
RC5
15
RC4
14
RC3
13
RC2
12
RC1
11
RC0
28
RB7
27
RB6
26
RB5
25
RB4
24
RB3
23
RB2
22
RB1
21
RB0
7
RA5
6
RA4
5
RA3
4
RA2
3
RA1
2
RA0
V
OSC1
OSC2
MCLR
V
V
2483 F35
20
DD
9
10
1
9
SS
19
SS
6MHz
R1
10k
5V
C6
0.1µF
Y1
D1
BAT54
5V
Figure 35. Voltage Measurement Circuit
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2
C Interface, Programmable Gain, and Temperature Sensor
I
LTC248216-Bit ∆Σ ADC with Easy Drive InputsPin Compatible with LTC2480/LTC2484
LTC248424-Bit ∆Σ ADC with Easy Drive InputsPin Compatible with LTC2480/LTC2482
LTC248524-Bit ∆Σ ADC with Easy Drive Inputs, I2C Interface andPin Compatible with LTC2481/LTC2483