Datasheet LTC2440 Datasheet (LINEAR TECHNOLOGY)

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LTC2440

24-Bit High Speed

FEATURES

Up to 3.5kHz Output Rate

Selectable Speed/Resolution

2μV

200nV

Noise at 880Hz Output Rate

RMS

Noise at 6.9Hz Output Rate with

RMS

Simultaneous 50/60Hz Rejection

0.0005% INL, No Missing Codes

Autosleep Enables 20μA Operation at 6.9Hz

<5μV Offset (4.5V < VCC < 5.5V, –40°C to 85°C)

Differential Input and Differential Reference with

GND to V

No Latency, Each Conversion is Accurate Even After

Common Mode Range

an Input Step

Internal Oscillator—No External Components

Pin Compatible with the LTC2410

24-Bit ADC in Narrow 16-Lead SSOP Package

APPLICATIONS

High Speed Multiplexing

Weight Scales

Auto Ranging 6-Digit DVMs

Direct Temperature Measurement

High Speed Data Acquisition

Differential

Δ∑

ADC with

Selectable Speed/Resolution

DESCRIPTION

The LTC®2440 is a high speed 24-bit No Latency Δ∑TM ADC with 5ppm INL and 5μV offset. It uses proprietary delta-sigma architecture enabling variable speed and resolution with no latency. Ten speed/resolution combinations (6.9Hz/200nV

to 3.5kHz/25μV

RMS

through a simple serial interface. Alternatively, by tying a single pin HIGH or LOW, a fast (880Hz/2μV noise (6.9Hz, 200nV

, 50/60Hz rejection) speed/reso-

RMS

lution combination can be easily selected. The accuracy (offset, full-scale, linearity, drift) and power dissipation are independent of the speed selected. Since there is no latency, a speed/resolution change may be made between conversions with no degradation in performance.

Following each conversion cycle, the LTC2440 automatically enters a low power sleep state. Power dissipation may be reduced by increasing the duration of this sleep state. For example, running at the 3.5kHz conversion speed but reading data at a 100Hz rate draws 240μA average current (1.1mW) while reading data at a 7Hz output rate draws only 25μA (125μW).The LTC2440 communicates through a ﬂ exible 3-wire or 4-wire digital interface that is compatible with the LTC2410 and is available in a narrow 16-lead SSOP package.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No Latency Δ∑ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

) are programmed

RMS

) or ultralow

RMS

TYPICAL APPLICATION

Simple 24-Bit 2-Speed Acquisition System

4.5V TO 5.5V

BUSY

LTC2440

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT

TO 0.5V

–0.5V

REF

GND

–

SCK

SDO

–

SDI

EXT

3-WIRE SPI INTERFACE

2440 TA01

6.9Hz, 200nV NOISE, 50/60Hz REJECTION

10-SPEED SERIAL PROGRAMMABLE

880Hz OUTPUT RATE, 2μV NOISE

2440 TA01

Speed vs RMS Noise

100

VCC = 5V V

= 5V

REF

= V

200nV AT 6.9Hz

RMS NOISE (μV)

(50/60Hz REJECTION)

0.1 1

–

= 0V

2μV AT 880Hz

10 100

CONVERSION RATE (Hz)

1000 10000

2440 TA02

2440fc

LTC2440

(Notes 1,2)

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) to GND ....................... –0.3V to 6V

Analog Input Pins Voltage

to GND ......................................–0.3V to (V

+ 0.3V)

Reference Input Pins Voltage

to GND ......................................–0.3V to (V

Digital Input Voltage to GND .........–0.3V to (V

Digital Output Voltage to GND .......–0.3V to (V

+ 0.3V)

Operating Temperature Range

LTC2440C ............................................... 0°C to 70°C

LTC2440I ............................................. –40°C to 85°C

Storage Temperature Range ...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................300°C

GND

REF

GND

SDI

TOP VIEW

–

GN PACKAGE

16-LEAD PLASTIC SSOP

= 125°C, θJA = 110°C/W

JMAX

GND

BUSY

SCK

SDO

EXT

GND

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2440CGN#PBF LTC2440CGN#TRPBF 2440 Narrow 16-Lead SSOP 0°C to 70°C LTC2440IGN#PBF LTC2440IGN#TRPBF 2440I Narrow 16-Lead SSOP –40°C to 85°C Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ V Integral Nonlinearity V

= 5V, REF+ = 5V, REF– = GND, V

REF

= 2.5V, REF– = GND, V

≤ VCC, –0.5 • V

REF

≤ VIN ≤ 0.5 • V

REF

INCM

= 1.25V, (Note 6)

INCM

, (Note 5)

REF

= 2.5V, (Note 6)

Offset Error 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ VCC (Note 12)

Offset Error Drift 2.5V ≤ REF Positive Full-Scale Error REF

REF

≤ VCC, REF– = GND, GND ≤ IN+ = IN– ≤ V

= 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25V

= 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V

Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF

Negative Full-Scale Error REF

= 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75V

REF

= 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF Total Unadjusted Error 5V ≤ V

5V ≤ V REF

≤ 5.5V, REF+ = 2.5V, REF– = GND, V

≤ 5.5V, REF+ = 5V, REF– = GND, V

= 2.5V, REF– = GND, V

= 1.25V, (Note 6)

INCM

Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND, GND ≤ IN– = IN+ ≤ V

INCM

= 1.25V

= 2.5V

24 Bits

15 ppm of V

ppm of V

REF REF

2.5 5 μV 20 nV/ °C

l l

101030

ppm of V ppm of V

0.2 ppm of V 101030

ppm of V ppm of V

0.2 ppm of V 15

15 15

ppm of V ppm of V ppm of V

REF

REF REF

/°C

REF REF

/°C

REF REF REF

120 dB

2440fc

LTC2440

ANALOG INPUT AND REFERENCE

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

–

IN V

REF

–

REF V

REF

S(IN+)

S(IN–)

S(REF+)

S(REF–)

DC_LEAK(IN+, IN–,

, REF–)

REF

SAMPLE(IN+, IN–,

, REF–)

REF

Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN– Voltage Input Differential Voltage Range (IN+ – IN–) Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF– Voltage Reference Differential Voltage Range (REF+

–

– REF

) IN+ Sampling Capacitance 3.5 pF IN– Sampling Capacitance 3.5 pF REF+ Sampling Capacitance 3.5 pF REF– Sampling Capacitance 3.5 pF Leakage Current, Inputs and Reference CS = VCC, IN+ = GND, IN– = GND,

Average Input/Reference Current During Sampling

= 25°C. (Note 3)

REF

= 5V, REF– = GND

GND – 0.3V VCC + 0.3V V

–V

/2 V

REF

0.1 V

GND VCC – 0.1V V

0.1 V

–100 10 100 nA

/2 V

REF

Varies, See Applications Section

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

High Level Input Voltage CS, f

Low Level Input Voltage CS, f

High Level Input Voltage

4.5V ≤ VCC ≤ 5.5V

4.5V ≤ VCC ≤ 5.5V (Note 8)

SCK

Low Level Input Voltage

4.5V ≤ VCC ≤ 5.5V (Note 8)

SCK

Digital Input Current CS, f

Digital Input Current

0V ≤ VIN ≤ V

0V ≤ VIN ≤ VCC (Note 8)

SCK

Digital Input Capacitance CS, f

Digital Input Capacitance

(Note 8) 10 pF

SCK

High Level Output Voltage

IO = –800μA

SDO, BUSY

Low Level Output Voltage

IO = 1.6mA

SDO, BUSY

High Level Output Voltage

IO = –800μA (Note 9)

SCK

Low Level Output Voltage

IO = 1.6mA (Note 9)

SCK

Hi-Z Output Leakage SDO

25 V

0.8 V

25 V

0.8 V

–10 10 μA

10 pF

VCC – 0.5V V

–10 10 μA

0.4V V

2440fc

LTC2440

POWER REQUIREMENTS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage Supply Current

Conversion Mode Sleep Mode

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

EOSC

HEO

LEO

CONV

ISCK

ESCK

LESCK

HESCK

DOUT_ISCK

DOUT_ESCK

KQMAX

KQMIN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to GND. Note 3: V

REF

Note 4: f f

EOSC

= 4.5 to 5.5V unless otherwise speciﬁ ed.

= REF+ – REF–, V

= IN+ – IN–, V

pin tied to GND or to external conversion clock source with

= 10MHz unless otherwise speciﬁ ed.

Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is deﬁ ned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time OSR = 256 (SDI = 0)

Internal SCK Frequency Internal Oscillator (Note 9)

Internal SCK Duty Cycle (Note 9) External SCK Frequency Range (Note 8) External SCK Low Period (Note 8) External SCK High Period (Note 8) Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11)

External SCK 32-Bit Data Output Time (Note 8)

↑

CS to SDO Low Z (Note 12) CS ↑ to SDO High Z

↑

CS to SCK (Note 9)

↑

CS to SCK ↑ SCK to SDO Valid

↑

SDO Hold After SCK (Note 5) SCK Set-Up Before CS SDI Setup Before SCK ↑ SDI Hold After SCK ↑

= (REF+ + REF–)/2;

REFCM

= (IN+ + IN–)/2.

INCM

= 25°C. (Note 3)

↑

CS = 0V (Note 7) CS = V

(Note 7)

OSR = 32768 (SDI = 1)

External Oscillator (Note 10, 13)

External Oscillator (Notes 9, 10)

(Note 12)

(Notes 8, 12)

(Note 5) (Note 5)

Note 7: The converter uses the internal oscillator. Note 8: The converter is in external SCK mode of operation such that the

SCK pin is used as a digital input. The frequency of the clock signal driving SCK during the data output is f

Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as a digital output. In this mode of operation, the SCK pin has a total equivalent load capacitance of C

Note 10: The external oscillator is connected to the f oscillator frequency, f

Note 11: The converter uses the internal oscillator. fO = 0V. Note 12: Guaranteed by design and test correlation. Note 13: There is an internal reset that adds an additional 1μs (typical) to

the conversion time.

4.5 5.5 V

l l

0.1 20 MHz

25 10000 ns

0.99

126

0.8 0.9

45 55 %

25 ns

30.9 35.3

25 ns

15 ns

50 ns

10 ns

, is expressed in kHz.

EOSC

40 • OSR + 170

025ns 025ns

and is expressed in Hz.

ESCK

EOSC

8 8

1.13 145

(kHz)

11 30

1.33 170

μA

ms ms

/10

EOSC

20 MHz

41.6 μs

320/f

EOSC

32/f

ESCK

5μs

25 ns

= 20pF.

LOAD

pin. The external

2440fc

s s

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity

Integral Nonlinearity f

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

–

= GND

REF

V f T

INCM

= 2.5V = GND = 25°C

= 3.5kHz

OUT

= 1.76kHz Integral Nonlinearity f

OUT

VCC = 5V

= 5V

REF

)

REF

–

REF

= 5V = GND

INCM

= GND

= 25°C

= 2.5V

)

REF

VCC = 5V

= 5V

REF

= 5V

REF

–

= GND

REF

LTC2440

OUT

= 2.5V

INCM

= GND

= 25°C

= 880Hz

–5

INL ERROR (ppm OF V

–10

–2.5

–1.5

–2

–1

Integral Nonlinearity f

VCC = 5V

= 5V

REF

= 5V

REF

–10

–

= GND

REF

–5

–2

–1.5

–2.5

–1

)

REF

INL ERROR (ppm OF V

–0.5

INCM

= GND

–0.5

VIN (V)

= 2.5V

= 25°C

VIN (V)

–5

INL ERROR (ppm OF V

1.5

0.5

= 440Hz Integral Nonlinearity f

OUT

2440 G01

2.5

–10

)

REF

–2.5

–2

VCC = 5V

= 5V

REF

–

REF

–1.5

= 5V = GND

–5

INL ERROR (ppm OF V

–10

–2

–1.5

0.5

1.5

2440 G04

2.5

–2.5

–5

INL ERROR (ppm OF V

–10

–2

–1.5

–0.5

–1

0.5

1.5

2.5

–2.5

VIN (V)

2440 G02

= 220Hz Integral Nonlinearity f

INCM

= GND

= 25°C

OUT

= 2.5V

)

REF

VCC = 5V

= 5V

REF

= 5V

REF

–

= GND

REF

–1

–0.5

0.5

1.5

2.5

VIN (V)

2440 G03

= 110Hz

OUT

= 2.5V

INCM

= GND

= 25°C

–5

INL ERROR (ppm OF V

–10

–2

–1.5

–1

–0.5

0.5

1.5

2.5

–2.5

VIN (V)

2440 G05

0.5

1.5

2.5

–1

–0.5

VIN (V)

2440 G06

Integral Nonlinearity f

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

INL ERROR (ppm OF V

–10

–

= GND

REF

–5

–2

–1.5

–2.5

–1

INCM

= GND

= 25°C

–0.5

= 2.5V

VIN (V)

= 55Hz Integral Nonlinearity f

OUT

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

–

= GND

REF

–5

INL ERROR (ppm OF V

–10

–2

–1.5

0.5

1.5

2.5

2440 G07

–2.5

Integral Nonlinearity

= 27.5Hz

OUT

= 2.5V

INCM

= GND

= 25°C

0.5

1.5

2.5

–1

–0.5

VIN (V)

2440 G08

= 13.75Hz

OUT

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

–

= GND

REF

–5

INL ERROR (ppm OF V

–10

–2

–1.5

–2.5

= 2.5V

INCM

= GND

= 25°C

0.5

1.5

2.5

–1

–0.5

VIN (V)

2440 G09

2440fc

LTC2440

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity f

= 6.875Hz

OUT

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

–

= GND

REF

–5

INL ERROR (ppm OF V

–10

–2

–1.5

–2.5

–1

Integral Nonlinearity vs Temperature

VCC = 5V

= 2.5V

REF

= 2.5V

REF

–5

–1.25

REF

–

= GND

TA = –55°C

TA = 25°C

–0.75

)

REF

INL ERROR (ppm OF V

–10

= 2.5V

INCM

= GND

= 25°C

–0.5

VIN (V)

= 1.25V

INCM

OSR = 32768

= GND

TA = 125°C

–0.25

VIN (V)

0.5

0.25

Integral Nonlinearity vs Conversion Rate Integral Nonlinearity vs V

= 3.75V

)

REF

INCM

= 1.25V

INCM

–5

VCC = 5V

INL ERROR (ppm OF V

–10

–1.25

= 2.5V

REF

= 2.5V

REF

–

= GND

REF

–0.75

INCM

OSR = 32768

= GND

= 25°C

–0.25

VIN (V)

)

10.0

REF

7.5

VCC = 5V

= 5V

REF

–

REF

= 5V = GND

–2.5V ≤ V

= 2.5V

INCM

= GND

= 25°C

≤ 2.5V

5.0

2.5

INL ERROR (ppm OF V

1.5

2.5

500 1000 1500 2000

2500 3000 3500

CONVERSION RATE (Hz)

2440 G10

2440 G11

0.25

= 2.5V

INCM

0.75

1.25

2440 G12

Integral Nonlinearity

0.75

2440 G13

1.25

vs Temperature –Full-Scale Error vs V

VCC = 5V

= 5V

REF

= 5V

REF

)

REF

–

= GND

REF

TA = 125°C

TA = –25°C

–5

INL ERROR (ppm OF V

–10

–2

–1.5

–2.5

INCM

OSR = 32768

= GND

–1

–0.5

= 2.5V

VIN (V)

TA = 25°C

0.5

1.5

2440 G14

2.5

)

REF

–10

–FULL-SCALE ERROR (ppm OF V

–20

REF

(V)

REF

2440 G15

+Full-Scale Error vs V

)

REF

–10

+FULL-SCALE ERROR (ppm OF V

–20

REF

–Full-Scale Error vs V

)

REF

= 2.5V

REF

FULL-SCALE ERROR (ppm OF V

(V)

REF

2440 G16

–

REF

INCM

4.5

= 2.5V = GND

= 1.25V

4.7

OSR = 32768 fO = GND

= 25°C

5.1

4.9 VCC (V)

5.3

5.5

2440 G17

+Full-Scale Error vs V

= 2.5V

REF

–1

)

REF

–

REF

–2

INCM

–3

–4

–5

–6

–7

–8

FULL-SCALE ERROR (ppm OF V

–9

–10

4.5

= 2.5V = GND

= 1.25V

4.7

OSR = 32768

= GND

= 25°C

4.9 VCC (V)

5.1

5.3

5.5

2440 G18

2440fc

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2440

Negative Full-Scale Error vs Temperature

)

REF

5.5V

–5

–10

FULL-SCALE ERROR (ppm OF V

–15

–20

–55

4.5V

–25 5

VCC = 4.5V

= 4.5V

REF

= 4.5V

REF

–

= GND

REF

= 2.25V

INCM

OSR = 32768

= GND

= 5.5V, 5V

= 5V

REF

= 5V

REF

–

= GND

REF

= 2.5V

INCM

OSR = 32768

= GND

65 95

125

Positive Full-Scale Error vs Temperature Offset Error vs V

)

REF

5.5V

–5

4.5V

–10

FULL-SCALE ERROR (ppm OF V

–15

–20

–55

–25 5

TEMPERATURE (°C)

2440 G19

Offset Error vs Conversion Rate Offset Error vs V

5.0 VCC = 5V

= 5V

REF

)

REF

–

REF

2.5

= 5V = GND

V f T

–2.5

OFFSET ERROR (ppm OF V

–5.0

500 1000 1500 2000

CONVERSION RATE (Hz)

= GND

= 25°C

= V

–

= GND

2500 3000 3500

2440 G22

5.0 VCC = 5V

= 5V

REF

2.5

REF

–

REF

)

REF

–2.5

OFFSET ERROR (ppm OF V

–5.0

INL vs Output Rate (OSR = 128) External Clock Sweep

Offset Error vs Temperature

5.0

2.5 VCC = 5V

OFFSET ERROR (μV)

–2.5

–5.0

–55

VCC = 5.5V

VCC = 4.5V

= 2.5V

REF

= 2.5V

REF

–

= GND

REF

= V

OSR = 256

= GND

53565

–25

TEMPERATURE (°C)

–

= GND

VCC = 4.5V

= 5.5V, 5V

= 5V

REF

= 5V

REF

–

= GND

REF

= V

OSR = 256

= GND

–

= GND

95 125

2440 G25

10MHz to 20MHz

EXTERNAL CLOCK 10MHz

(OR INTERNAL OSCILLATOR)

LINEARITY (BITS)

REF

TEMP = 25°C

SWEEP (V

2000

VCC = 4.5V

= 4.5V

REF

= 4.5V

REF

–

= GND

REF

= 2.25V

INCM

OSR = 32768

= GND

= 5.5V, 5V

= 5V

REF

= 5V

REF

–

= GND

REF

= 2.5V

INCM

OSR = 32768

= GND

65 95

TEMPERATURE (°C)

2440 G20

INCM

–

= V

(V)

/2) TO V

INCM

EXTERNAL CLOCK 20MHz

REF

2440 G23

2440 G26

OSR = 32768 = 5V = GND

= GND

= 25°C

INCM

= VCC = 5V

– V

REF

2500 3000 3500 4000

OUTPUT RATE (Hz)

125

5.0

)

REF

2.5

–2.5

OFFSET ERROR (ppm OF V

–5.0

3.5

3.0

2.5

2.0

RMS NOISE (μV)

1.5

1.0

0.5

RMS NOISE (μV)

2000

–

= GND

OSR = 32768

= GND

= 25°C

4.9 VCC (V)

5.1

4.5

= 2.5V

REF

= 2.5V

REF

–

= GND

REF

= V

4.7

RMS Noise vs Temperature

VCC = 4.5V VCC = 5V VCC = 5.5V

–55

VCC = 4.5V

= 2.5V

REF

= 2.5V

REF

–

= GND

REF

–

= V

OSR = 256

= GND

53565

–25

= GND

= 5.5V, 5V

= 5V

REF

= 5V

REF

–

= GND

REF

= V

OSR = 256

= GND

TEMPERATURE (°C)

RMS Noise vs Output Rate (OSR = 128) External Clock Sweep 10MHz to 20MHz

= VCC = 5V

REF

TEMP = 25°C

±V

REF

2500 3000 3500 4000

OUTPUT RATE (Hz)

5.3

2440 G21

–

= GND

95 125

5.5

2440 G24

2440 G27

2440fc

LTC2440

PIN FUNCTIONS

GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins internally connected for optimum ground current ﬂ ow and

decoupling. Connect each one of these pins to a ground

plane through a low impedance connection. All four pins must be connected to ground for proper operation.

(Pin 2): Positive Supply Voltage. Bypass to GND

(Pin 1) with a 10μF tantalum capacitor in parallel with 0.1μF ceramic capacitor as close to the part as possible.

(Pin 3), REF– (Pin 4): Differential Reference Input.

REF

The voltage on these pins can have any value between GND and V

as long as the reference positive input, REF+,

is maintained more positive than the reference negative

–

input, REF

(Pin 5), IN– (Pin 6): Differential Analog Input. The

, by at least 0.1V.

voltage on these pins can have any value between GND – 0.3V and V bipolar input range (V

• (V

) to 0.5 • (V

REF

+ 0.3V. Within these limits the converter

= IN+ – IN–) extends from –0.5

). Outside this input range the

REF

converter produces unique overrange and underrange output codes.

SDI (Pin 7): Serial Data Input. This pin is used to select the speed/resolution of the converter. If SDI is grounded (pin compatible with LTC2410) the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nV

RMS

) with simultaneous 50/60Hz rejection at 6.9Hz output rate. SDI may be driven logic HIGH or LOW anytime during the conversion or sleep state in order to change the speed/resolution. The conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution. SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle. One of ten speed/resolution ranges (from 6.9Hz/200nV

to 3.5kHz/21μV

RMS

) may be selected. The ﬁ rst conversion following a new selection is valid and performed at the newly selected speed/resolution.

EXT (Pin 10): Internal/External SCK Selection Pin. This pin is used to select internal or external SCK for outputting data. If EXT is tied low (pin compatible with the LTC2410), the device is in the external SCK mode and data is shifted out the device under the control of a user applied serial clock. If EXT is tied high, the internal serial clock mode

is selected. The device generates its own SCK signal and outputs this on the SCK pin. A framing signal BUSY (Pin 15) goes low indicating data is being output.

CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion.

SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = V

) the SDO pin is in a

high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. The Serial Clock Operation mode is determined by the logic level applied to the EXT pin.

fO (Pin 14): Frequency Control Pin. Digital input that controls the internal conversion clock. When fO is connected to VCC or GND, the converter uses its internal oscillator running at 9MHz. The conversion rate is determined by the selected OSR such that t (t

= 1.137ms at OSR = 256, t

CONV

32768). The ﬁ rst null is located at 8/ t

(in ms) = (40 • OSR + 170)/9000

CONV

= 146ms at OSR =

CONV

, 7kHz at OSR =

CONV

256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768. When f

kHz), the conversion time becomes t

170)/f

is driven by an oscillator with frequency f

= (40 • OSR +

CONV

(in ms) and the ﬁ rst null remains 8/t

EOSC

CONV

(in

BUSY (Pin 15): Conversion in Progress Indicator. For compatibility with the LTC2410, this pin should not be tied to ground. This pin is HIGH while the conversion is in progress and goes LOW indicating the conversion is complete and data is ready. It remains low during the sleep and data output states. At the conclusion of the data output state, it goes HIGH indicating a new conversion has begun.

2440fc

FUNCTIONAL BLOCK DIAGRAM

LTC2440

GND

REF REF

–

+ –

TEST CIRCUITS

SDO

DAC

1.69k

Hi-Z TO V VOL TO V VOH TO Hi-Z

–+

LOAD

= 20pF

2440 TA03

ADC

Figure 1. Functional Block Diagram

AUTOCALIBRATION

AND CONTROL

DECIMATING FIR

2440 F01

SDO

Hi-Z TO V VOH TO V VOL TO Hi-Z

INTERNAL

OSCILLATOR

(INT/EXT)

SDO

SCK

SERIAL

INTERFACE

1.69k

= 20pF

LOAD

OL OL

2440 TA04

SDI

BUSY

EXT

APPLICATIONS INFORMATION

CONVERTER OPERATION

Converter Operation Cycle

The LTC2440 is a high speed, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS). The interface, timing, operation cycle and data out format is compatible with the LTC2410.

CONVERT

SLEEP

FALSE

CS = LOW AND

SCK

TRUE

DATA OUTPUT

2440 F02

Figure 2. LTC2440 State Transition Diagram

2440fc

LTC2440

APPLICATIONS INFORMATION

Initially, the LTC2440 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10μA. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indeﬁ nitely in a static shift register while the converter is in the sleep state.

Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32-bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats.

Through timing control of the CS, SCK and EXT pins, the LTC2440 offers several ﬂ exible modes of operation (internal or external SCK). These various modes do not require programming conﬁ guration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section.

Ease of Use

The LTC2440 data output has no latency, ﬁ lter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. Speed/resolution adjustments may be made seamlessly between two conversions without settling errors.

The LTC2440 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2440 automatically enters an internal reset state when the power supply voltage V proximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection.

When the V converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2440 starts a normal conversion cycle and follows the succession of states described above. The ﬁ rst conversion result following POR is accurate within the speciﬁ cations of the device if the power supply voltage is restored within the operating range (4.5V to 5.5V) before the end of the POR time interval.

Reference Voltage Range

This converter accepts a truly differential external reference voltage. The absolute/common mode voltage speciﬁ cation for the REF GND to V must always be more positive than the REF

The LTC2440 can accept a differential reference voltage from 0.1V to V by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not signiﬁ cantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will improve the converter’s overall INL performance.

Input Voltage Range

The analog input is truly differential with an absolute/common mode range for the IN from GND – 0.3V to V ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2440 converts the bipolar differential input signal, V

voltage rises above this critical threshold, the

and REF– pins covers the entire range from

. For correct converter operation, the REF+ pin

. The converter output noise is determined

and IN– input pins extending

+ 0.3V. Outside these limits, the

= IN+ – IN–, from –FS = –0.5 • V

drops below ap-

–

pin.

to +FS =

REF

2440fc

APPLICATIONS INFORMATION

LTC2440

0.5 • V

where V

REF

= REF+ – REF–. Outside this range,

REF

the converter indicates the overrange or the underrange condition using distinct output codes.

Output Data Format

The LTC2440 serial output data stream is 32-bits long. The ﬁ rst 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the conversion result, MSB ﬁ rst. The remaining 5-bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. In the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see Table 3). Under these conditions, sub LSBs are included in the conversion result and represent useful information beyond the 24-bit level. The third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS). For input conditions in excess of twice full scale (|V

| ≥ V

), the converter

REF

may indicate either overrange or underrange. Once the input returns to the normal operating range, the conversion result is immediately accurate within the speciﬁ cations of the device.

Bit 31 (ﬁ rst output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW.

Bit 29 (third output bit) is the conversion result sign

indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW.

Bit 28 (fourth output bit) is the most signiﬁ cant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2440 Status Bits

Input Range

≥ 0.5 • V

< 0.5 • V

0V ≤ V

–0.5 • V

REF

< –0.5 • V

Bit 31

EOC

REF

≤ VIN < 0V 0001

REF

0011 0010

0000

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bits ranging from 28 to 5 are the 24-bit conversion result MSB ﬁ rst.

Bit 5 is the Least Signiﬁ cant Bit (LSB). Bits ranging from 4 to 0 are sub LSBs below the 24-bit

level. Bits 4 to bit 0 may be included in averaging or discarded without loss of resolution.

Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance.

In order to shift the conversion result out of the device, CS must ﬁ rst be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external

BIT 31

SDO

SCK

BUSY

EOC

Hi-Z

1 2 3 4 5 262732

SLEEP DATA OUTPUT CONVERSION

BIT 28BIT 29BIT 30

MSBSIG“0”

Figure 3. Output Data Timing

LSB

BIT 0BIT 27 BIT 5

2440 F03

2440fc

LTC2440

APPLICATIONS INFORMATION

microcontroller. Bit 31 (EOC) can be captured on the ﬁ rst rising edge of SCK. Bit 30 is shifted out of the device on the ﬁ rst falling edge of SCK. The ﬁ nal data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format.

As long as the voltage on the IN tained within the –0.3V to (V

and IN– pins is main-

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any differential input voltage V +FS = 0.5 • V

. For differential input voltages greater

REF

from –FS = –0.5 • V

REF

than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the value corresponding to –FS – 1LSB.

SERIAL INTERFACE PINS

The LTC2440 transmits the conversion results and receives the start of conversion command through a synchronous 2-wire, 3-wire or 4-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed/resolution.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an output and the LTC2440 creates its own serial clock. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected by tying EXT (Pin 10) LOW for external SCK and HIGH for internal SCK.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the result of the last conversion as a serial bit stream (MSB ﬁ rst) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the ﬁ rst rising edge of SCK occurs while CS = LOW.

Table 2. LTC2440 Output Data Format

Differential Input Voltage VIN*

* ≥ 0.5 • V

0.5 • V

REF

0.25 • V

0 0010000…0 –1LSB 0001111…1

–0.25 • V –0.25 • V

–0.5 • V VIN* < –0.5 • V *The differential input voltage V

** 0011000…0

REF

** – 1LSB 0 0 1 0 1 1 1 … 1

** 0010100…0

REF

** – 1LSB 0 0 1 0 0 1 1 … 1

REF

** 0001100…0

REF

** – 1LSB 0 0 0 1 0 1 1 … 1

REF

** 0001000…0

REF

** 0000111…1

REF

Bit 31

EOC

= IN+ – IN–. **The differential reference voltage V

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB Bit 27 Bit 26 Bit 25 … Bit 0

= REF+ – REF–.

REF

2440fc

APPLICATIONS INFORMATION

LTC2440

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections.

In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2440 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the ﬁ fth falling edge of SCK occurs with CS = LOW).

Serial Data Input (SDI)—Logic Level Speed Selection

The serial data input (SDI, Pin 7) is used to select the speed/resolution of the LTC2440. A simple 2-speed control is selectable by either driving SDI HIGH or LOW. If SDI is grounded (pin compatible with LTC2410) the device outputs data at 880Hz with 21 bits effective resolution. By tying SDI HIGH, the converter enters the ultralow noise mode (200nV

6.9Hz output rate. SDI may be driven logic HIGH or LOW anytime during the conversion or sleep state in order to change the speed/resolution. The conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution.

Changing SDI logic state during the data output cycle should be avoided as speed resolution other than 6.9Hz or 880Hz may be selected. For example, if SDI is changed from logic 0 to logic 1 after the second rising edge of SCK, the conversion rate will change from 880Hz to 55Hz (the following values are listed in Table 3: OSR4 = 0, OSR3 = 0, OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH, the conversion rate will switch to the desired 6.9Hz speed immediately following the conversion at 55Hz. The 55Hz rate conversion cycle will be a valid result as well as the ﬁ rst 6.9Hz result. On the other hand, if SDI is changed to a 1 anytime before the ﬁ rst rising edge of SCK, the following conversion rate will become 6.9Hz. If SDI is changed to a 1 after the 5th rising edge of SCK, the next conversion will remain 880Hz while all subsequent conversions will be at 6.9Hz.

) with simultaneous 50/60Hz rejection at

RMS

Serial Data Input (SDI)—Serial Input Speed Selection

SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle, see Figure 4. One of ten speed/resolution ranges (from

6.9Hz/200nV Table 3. The conversion following a new selection is valid and performed at the newly selected speed/resolution.

BUSY

The BUSY output (Pin 15) is used to monitor the state of conversion, data output and sleep cycle. While the part is converting, the BUSY pin is HIGH. Once the conversion is complete, BUSY goes LOW indicating the conversion is complete and data out is ready. The part now enters the LOW power sleep state. BUSY remains LOW while data is shifted out of the device. It goes HIGH at the conclusion of the data output cycle indicating a new conversion has begun. This rising edge may be used to ﬂ ag the completion of the data read cycle.

SERIAL INTERFACE TIMING MODES

The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI and MICROWIRE compatible. This interface offers several ﬂ exible modes of operation. These include internal/external serial clock, 2-wire or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (f LOW) or an external oscillator connected to the f See Table 4 for a summary.

External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 5.

The serial clock mode is selected by the EXT pin. To select the external serial clock mode, EXT must be tied low.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin.

to 3.5kHz/21μV

RMS

) may be selected, see

RMS

pin.

2440fc

LTC2440

APPLICATIONS INFORMATION

SCK

SDI

Hi-Z

SDO

BUSY

*OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE

OSR4* OSR3 OSR2 OSR1 OSR0

BIT 28 BIT 27 BIT 26 BIT 25 BIT 1 BIT 0

“0”

BIT 29

SIG

MSB

BIT 31

EOC

BIT 30

LSB

Hi-Z

2440 F04

Figure 4. SDI Speed/Resolution Programming

Table 3. SDI Speed/Resolution Programming

CONVERSION RATE

OSR4 OSR3 OSR2 OSR1 OSR0

INTERNAL

9MHz CLOCK

EXTERNAL

10.24MHz CLOCK

X 0 0 0 1 3.52kHz 4kHz 23μV 17 64 X 0 0 1 0 1.76kHz 2kHz 3.5μV 20 128 0 0 0 0 0 880Hz 1kHz 2μV 21.3 256* X 0 0 1 1 880Hz 1kHz 2μV 21.3 256 X 0 1 0 0 440Hz 500Hz 1.4μV 21.8 512 X 0 1 0 1 220Hz 250Hz 1μV 22.4 1024 X 0 1 1 0 110Hz 125Hz 750nV 22.9 2048 X 0 1 1 1 55Hz 62.5Hz 510nV 23.4 4096 X 1 0 0 0 27.5Hz 31.25Hz 375nV 24 8192 X 1 0 0 1 13.75Hz 15.625Hz 250nV 24.4 16384 X 1 1 1 1 6.875Hz 7.8125Hz 200nV 24.6 32768**

**Address allows tying SDI HIGH *Additional address to allow tying SDI LOW

RMS

NOISE ENOB OSR

Table 4. LTC2440 Interface Timing Modes

Conﬁ guration

SCK

Source

Conversion

Cycle

Control

Data

Output

Control

Connection

and

Waveforms

External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS CS Figures 8, 9

↑

Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10

2440fc

APPLICATIONS INFORMATION

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

4.5V TO 5.5V

1μF

REF

1, 8, 9, 16

LTC2440

REF

–

REF

–

GND

BUSY

SCK

SDO

SDI

EXT

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

3-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

SDO

SCK

(EXTERNAL)

BUSY

CONVERSION

TEST EOCTEST EOC

SLEEP DATA OUTPUT CONVERSION

BIT 31

EOC

Figure 5. External Serial Clock, Single Cycle Operation

EOC = 1 (BUSY = 1) while a conversion is in progress and EOC = 0 (BUSY = 0) if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete.

When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the ﬁ rst rising edge of SCK is seen. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the ﬁ rst rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) and BUSY goes HIGH indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z and BUSY monitored for the completion of a conversion. As described above, CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin.

BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30

LSB

BIT 0

SUB LSBMSBSIG

TEST EOC

Hi-ZHi-ZHi-Z

2440 F05

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the ﬁ fth falling edge (SDI must be properly loaded each cycle) and the 32nd falling edge of SCK, see Figure 6. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32-bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure

7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected by tying EXT LOW.

Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. Conversely, BUSY (Pin 15) may be used to monitor the status of the conversion cycle. EOC or BUSY may be used as an interrupt to an external

2440fc

LTC2440

APPLICATIONS INFORMATION

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

4.5V TO 5.5V

1μF

REF

1, 8, 9, 16

LTC2440

REF

–

REF

–

GND

BUSY

SCK

SDO

EXT

SDI

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

3-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

(EXTERNAL)

SDO

SCK

BUSY

TEST EOC TEST EOC

EOC

CONVERSIONSLEEP SLEEP

DATA OUTPUT

BIT 31BIT 0

Hi-Z

EOC

Hi-Z Hi-ZHi-Z

MSBSIG

DATA OUTPUT

Figure 6. External Serial Clock, Reduced Data Output Length

4.5V TO 5.5V 1μF

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

1, 8, 9, 16

LTC2440

REF

–

REF

–

GND

BUSY

SCK

SDO

SDI

EXT

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

3-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

BIT 8BIT 27 BIT 9BIT 28BIT 29BIT 30

TEST EOC

CONVERSION

2410 F06

SDO

SCK

(EXTERNAL)

BUSY

CONVERSION

BIT 31

EOC

SLEEP DATA OUTPUT CONVERSION

MSBSIG

LSB

BIT 5BIT 27 BIT 26BIT 28BIT 29BIT 30

BIT 0

Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)

2440 F07

2440fc

APPLICATIONS INFORMATION

LTC2440

controller indicating the conversion result is ready. EOC = 1 (BUSY = 1) while the conversion is in progress and EOC = 0 (BUSY = 0) once the conversion enters the low power sleep state. On the falling edge of EOC/BUSY, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the ﬁ rst rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the ﬁ rst rising edge of SCK. On the 32nd falling edge of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a new conversion has begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the EXT pin must be tied HIGH.

The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Alternatively, BUSY (Pin 15) may be used to monitor the status of the conversion in progress. BUSY is HIGH during the conversion and goes LOW at the conclusion. It remains LOW until the result is read from the device.

When testing EOC, if the conversion is complete (EOC =

0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the ﬁ rst rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time t of CS (if EOC = 0) or t

after EOC goes LOW (if CS is

EOCtest

LOW during the falling edge of EOC). The value of t is 500ns. If CS is pulled HIGH before time tE

after the falling edge

EOCtest

OCtest

EOCtest

, the device remains in the sleep state. The conversion result is held in the internal static shift register.

If CS remains LOW longer than t

, the ﬁ rst rising

EOCtest

edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins

SDO

SCK

(INTERNAL)

BUSY

4.5V TO 5.5V

1μF

LTC2440

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

–0.5V

TO 0.5V

REF

EOCtest

TEST EOC

Hi-Z Hi-Z Hi-Z Hi-Z

BIT 31

EOC

SLEEP DATA OUTPUT CONVERSIONCONVERSION

1, 8, 9, 16

MSBSIG

REF

–

REF

–

GND

BUSY

SCK

SDO

SDI

EXT

BIT 27 BIT 26BIT 28BIT 29BIT 30

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

3-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

BIT 5

LSB

BIT 0

TEST EOC

2440 F08

Figure 8. Internal Serial Clock, Single Cycle Operation

2440fc

LTC2440

APPLICATIONS INFORMATION

on this ﬁ rst rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the ﬁ rst rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the ﬁ rst and 32nd rising edge of SCK, see Figure 9. In order to properly select the OSR for the conversion following a data abort, ﬁ ve SCK rising edges must be seen prior to performing a data out abort (pulling CS HIGH). If CS is pulled high prior to the ﬁ fth SCK falling edge, the OSR selected depends on the number of SCK signals seen prior to data abort, where subsequent nonaborted conversion cycles return to the programmed OSR. On the rising edge of CS, the device aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring all 32-bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion.

Internal Serial Clock, 2-Wire I/O, Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected by tying EXT HIGH.

During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the conversion is complete, SCK, BUSY and SDO go LOW (EOC = 0) indicating the conversion has ﬁ nished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (≈500ns) then immediately begins outputting data. The data output cycle begins on the ﬁ rst rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each

SDO

SCK

(INTERNAL)

BUSY

EOCtest

Hi-Z Hi-Z

BIT 0

EOC

4.5V TO 5.5V

1μF

LTC2440

1, 8, 9, 16

REF

–

REF

–

GND

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

EOCtest

TEST EOCTEST EOC

Hi-Z Hi-Z Hi-Z

DATA OUTPUT

BIT 31

EOC

SLEEP DATA OUTPUT

BUSY

SCK

SDO

SDI

EXT

MSBSIG

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

3-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

BIT 27 BIT 26BIT 28BIT 29BIT 30

BIT 8

CONVERSIONCONVERSIONSLEEP

TEST EOC

2440 F09

Figure 9. Internal Serial Clock, Reduced Data Output Length

2440fc

APPLICATIONS INFORMATION

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

TO 0.5V

–0.5V

REF

SDO

SCK

(INTERNAL)

BUSY

BIT 31

EOC

4.5V TO 5.5V

1μF

REF

1, 8, 9, 16

MSBSIG

LTC2440

REF

–

REF

–

GND

BUSY

SCK

SDO

SDI

EXT

= EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR

2-WIRE SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION 10-SPEED/RESOLUTION PROGRAMMABLE 2μV NOISE, 880Hz OUTPUT RATE

BIT 5 BIT 0BIT 27 BIT 26BIT 28BIT 29BIT 30

LSB

SLEEP

Figure 10. Internal Serial Clock, Continuous Operation

falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the ﬁ rst rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital ﬁ ltering. Combined with a large oversampling ratio, the LTC2440 signiﬁ cantly simpliﬁ es antialiasing ﬁ lter requirements.

DATA OUTPUT CONVERSIONCONVERSION

rejection at the frequency f

±14% is better than 80dB,

2410 F10

see Figure 12.

is grounded, fS is set by the on-chip oscillator at

If f

1.8MHz ±5% (over supply and temperature variations). At an OSR of 32,768, the ﬁ rst NULL is at f no latency output rate is f

–20

–40

–60

–80

/8 = 6.9Hz. At the maximum

= 55Hz and the

The LTC2440’s speed/resolution is determined by the over sample ratio (OSR) of the on-chip digital ﬁ lter. The OSR ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz output rate. The value of OSR and the sample

determine the ﬁ lter characteristics of the device.

rate f

The ﬁ rst NULL of the digital ﬁ lter is at f

where fN = fS/OSR, see Figure 11 and Table 5. The

of f

and multiples

–100

NORMAL MODE REJECTION (dB)

–120

–140

60 120 240

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

180

2440 F11

Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)

2440fc

LTC2440

APPLICATIONS INFORMATION

Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator Running at 9MHz

OSR NOTCH (fN)

64 28.16kHz 128 14.08kHz 256 7.04kHz 512 3.52kHz

1024 1.76kHz 2048 880Hz 4096 440Hz 8192 220Hz

16384 110Hz

32768* 55Hz

*Simultaneous 50/60 rejection

–80

–90

–100

–110

–120

NORMAL MODE REJECTION (dB)

–130

OSR, the noise performance of the device is 200nV

RMS

with better than 80dB rejection of 50Hz ±2% and 60Hz ±2%. Since the OSR is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. The ﬁ rst multiple of f

occurs at 55Hz • 32,768 =

1.8MHz, see Figure 13. The ﬁ rst NULL becomes f

(an output rate of 880Hz) and f

= 7.04kHz with an OSR of 256

grounded. While the NULL

has shifted, the sample rate remains constant. As a result of constant modulator sampling rate, the linearity, offset and full-scale performance remains unchanged as does the ﬁ rst multiple of f

–20

–40

–60

–80

–100

NORMAL MODE REJECTION (dB)

–120

REJECTION > 120dB

1.8MHz

–140

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

51 55

49 53

2440 F12

–140

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

1000000 2000000

1440 F13

Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator) Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)

2440fc

APPLICATIONS INFORMATION

LTC2440

The sample rate fS and NULL fN, my also be adjusted by driving the f rate is f clock applied to f sample rate leads to notch frequencies f

pin with an external oscillator. The sample

= f

/5, where f

EOSC

. Combining a large OSR with a reduced

is the frequency of the

EOSC

near DC while

maintaining simple antialiasing requirements. A 100kHz clock applied to f

results in a NULL at 0.6Hz plus all

harmonics up to 20kHz, see Figure 14. This is useful in applications requiring digitalization of the DC component of a noisy input signal and eliminates the need of placing a 0.6Hz ﬁ lter in front of the ADC.

An external oscillator operating from 100kHz to 20MHz can be implemented using the LTC1799 (resistor set SOT-23 oscillator), see Figure 22. By ﬂ oating pin 4 (DIV) of the LTC1799, the output oscillator frequency is:

f MHz

OSC

⎛ ⎜

⎝

10••

SET

⎞ ⎟

⎠

The normal mode rejection characteristic shown in Figure 14 is achieved by applying the output of the LTC1799 (with R

= 100k) to the fO pin on the LTC2440 with SDI

SET

tied HIGH (OSR = 32768).

Reduced Power Operation

In addition to adjusting the speed/resolution of the LTC2440, the speed/resolution/power dissipation may also be adjusted using the automatic sleep mode. During the conversion cycle, the LTC2440 draws 8mA supply current independent of the programmed speed. Once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8μA. The device remains in this state as long as CS is HIGH and data is not shifted out. By adjusting the duration of the sleep state (hold CS HIGH longer) and the duration of the conversion cycle (programming OSR) the DC power dissipation can be reduced, see Figure 16.

For example, if the OSR is programmed at the fastest rate (OSR = 64, t

= 0.285ms) and the sleep state is 10ms,

CONV

the effective output rate is approximately 100Hz while the average supply current is reduced to 240μA. By further extending the sleep state to 100ms, the effective output rate of 10Hz draws on average 30μA. Noise, power, and speed can be optimized by adjusting the OSR (Noise/Speed) and sleep mode duration (Power).

–20

–40

–60

–80

–100

NORMAL MODE REJECTION (dB)

–120

–140

Figure 14. LTC2440 Normal Mode Rejection (External Oscillator at 90kHz)

246 10

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2440 F14

2440fc

LTC2440

APPLICATIONS INFORMATION

CONVERTER

STATE

SUPPLY

CURRENT

SLEEP CONVERT SLEEP CONVERT SLEEP

DATA

OUT

Figure 15. Reduced Power Timing Mode

LTC2440 Input Structure

Modern delta sigma converters have switched capacitor front ends that repeatedly sample the input voltage over some time period. The sampling process produces a small current pulse at the input and reference terminals as the capacitors are charged. The LTC2440 switches the input and reference to a 5pF sample capacitor at a frequency of 1.8MHz. A simpliﬁ ed equivalent circuit is shown in Figure 16.

The average input and reference currents can be expressed in terms of the equivalent input resistance of the sample capacitor, where:

DATA

OUT

8μA8μA8mA8μA

When using the internal oscillator, f

is 1.8MHz and the

8mA

2440 F15

equivalent resistance is approximately 110kΩ.

Driving the Input and Reference

Because of the small current pulses, excessive lead length at the analog or reference input may allow reﬂ ections or ringing to occur, affecting the conversion accuracy. The key to preserving the accuracy of the LTC2440 is complete settling of these sampling glitches at both the input and reference terminals. There are several recommended methods of doing this.

Req = 1/(f

• Ceq)

REF

IIN+

VIN+

IIN–

VIN–

–

REF

–

REF

SWITCHING FREQUENCY

= 1.8MHz INTERNAL OSCILLATOR

= f

LEAK

/5 EXTERNAL OSCILLATOR

EOSC

Figure 16. LTC2440 Input Structure

RSW (TYP)

500Ω

RSW (TYP)

500Ω

RSW (TYP)

500Ω

RSW (TYP)

500Ω

2440 F16

5pF (TYP)

= 3.5pF SAMPLE CAP + PARASITICS)

2440fc

APPLICATIONS INFORMATION

LTC2440

Direct Connection to Low Impedance Sources

If the ADC can be located physically close to the sensor, it can be directly connected to sensors or other sources with impedances up to 350Ω with no other components required (see Figure 17).

4.5V to 5.5V

1μF

REF

LTC2440

–

Figure 17. Direct Connection to Low Impedance (<350Ω) Source is Possible if the Sensor is Located Close to the ADC.

REF

–

2440 F17

Longer Connections to Low Impedance Sources

If longer lead lengths are unavoidable, adding an input capacitor close to the ADC input pins will average the charging pulses and prevent reﬂ ections or ringing (see Figure 18). Averaging the current pulses results in a DC input current that should be taken into account. The resulting 110kΩ input impedance will result in a gain error of 0.44% for a 350Ω bridge (within the full scale specs of many bridges) and a very low 12.6ppm error for a 2Ω thermocouple connection.

4.5V to 5.5V

1μF

REF

GND

2440 F18

LTC2440

–

REMOTE THERMOCOUPLE

Figure 18. Input Capacitors Allow Longer Connection Between the Low Impedance Source and the ADC.

1μF

Buffering the LTC2440

Many applications will require buffering, particularly where high impedance sources are involved or where the device being measured is located some distance from the LTC2440. When buffering the LTC2440 a few simple steps should be followed.

Figure 19 shows a network suitable for coupling the inputs of a LTC2440 to a LTC2051 chopper-stabilized op amp. The 3μV offset and low noise of the LTC2051 make it a good choice for buffering the LTC2440. Many other op amps will work, with varying performance characteristics.

The LTC2051 is conﬁ gured to be able to drive the 1μF capacitors at the inputs of the LTC2440. The 1μF capacitors should be located close to the ADC input pins.

The measured total unadjusted error of Figure 19 is well within the speciﬁ cations of the LTC2440 by itself. Most autozero ampliﬁ ers will degrade the overall resolution to some degree because of the extremely low input noise of the LTC2440, however the LTC2051 is a good general purpose buffer. The measured input referred noise of two LTC2051s buffering both LTC2440 inputs is approximately double that of the LTC2440 by itself, which reduces the effective resolution by 1-bit for all oversample ratios. Adding gain to the LTC2051 will increase gain and offset errors and will not appreciably increase the overall resolution, so it has limited beneﬁ t.

Procedure For Coupling Any Ampliﬁ er to the LTC2440

The LTC2051 is suitable for a wide range of DC and low frequency measurement applications. If another ampliﬁ er is to be selected, a general procedure for evaluating the suitability of an ampliﬁ er for use with the LTC2440 is suggested here:

1. Perform a thorough error and noise analysis on the ampliﬁ er and gain setting components to verify that the ampliﬁ er will perform as intended.

2. Measure the large signal response of the overall circuit. The capacitive load may affect the maximum slew rate of the ampliﬁ er. Verify that the slew rate is adequate for the

2440fc

LTC2440

APPLICATIONS INFORMATION

fastest expected input signal. Figure 20 shows the large signal response of the circuit in Figure 19.

3. Measure noise performance of the complete circuit. A good technique is to build one ampliﬁ er for each input, even if only one will be used in the end application. Bias both ampliﬁ er outputs to midscale, with the inputs tied together. Verify that the noise is as expected, taking into account the bandwidth of the LTC2440 inputs for the OSR being used, the ampliﬁ er’s broadband voltage noise and 1/f corner (if any) and any additional noise due to the ampliﬁ er’s current noise and source resistance.

8-12V

LT1236-5

0.01μF

10Ω

1μF

IN+

IN–

–

/2 LTC2051HV

For more information on testing high linearity ADCs, refer to Linear Technology Design Solutions 11.

Input Bandwidth and Frequency Rejection

The combined effect of the internal SINC

digital ﬁ lter and the digital and analog autocalibration circuits determines the LTC2440 input bandwidth and rejection characteristics. The digital ﬁ lter’s response can be adjusted by setting the oversample ratio (OSR) through the SPI interface or by supplying an external conversion clock to the f

4.7μF

0.1μ

1, 8, 9, 16

C2, C5 TAIYO YUDEN JMK107BJ105MA

BUSY

LTC2440

–

SCK

SDO

SDI

EXT

REF

2440 F19

pin.

μF0.01μF

Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Ampliﬁ er

100mV/DIV

100μs/DIV

2440 F20

Figure 20. Large Signal Input Settling Time Indicates Completed Settling with Selected Load Capacitance.

2mV/DIV

5ns/DIV

2440 F21

Figure 21. Dynamic Input Current is Attenuated by Load Capacitance and Completely Settled Before the Next Conversion Sample Resulting in No Reduction in Performance.

2440fc

APPLICATIONS INFORMATION

LTC2440

Table 6 lists the properties of the LTC2440 with various combinations of oversample ratio and clock frequency.

the modulator sample rate of 1.8MHz) exceeds 120dB. This is 8 times the maximum conversion rate.

Understanding these properties is the key to ﬁ ne tuning the characteristics of the LTC2440 to the application.

Effective Noise Bandwidth

The LTC2440 has extremely good input noise rejection from

Maximum Conversion Rate

The maximum conversion rate is the fastest possible rate at which conversions can be performed.

the ﬁ rst notch frequency all the way out to the modulator sample rate (typically 1.8MHz). Effective noise bandwidth is a measure of how the ADC will reject wideband input noise up to the modulator sample rate. The example on

First Notch Frequency

This is the ﬁ rst notch in the SINC

portion of the digital ﬁ lter

and depends on the fo clock frequency and the oversample

the following page shows how the noise rejection of the LTC2440 reduces the effective noise of an ampliﬁ er driving its input.

ratio. Rejection at this frequency and its multiples (up to

Table 6

Oversample

Ratio

(OSR)

64 23μV 17 3515.6 fO/2560 28125 fO/320 3148 fO/2850 1696 fO/5310 128 3.5μV 20 1757.8 f 256 2μV 21.3 878.9 f 512 1.4μV 21.8 439.5 f

1024 1μV 22.4 219.7 f 2048 750nV 22.9 109.9 f 4096 510nV 23.4 54.9 f

8192 375nV 24 27.5 f 16384 250nV 24.4 13.7 f 32768 200nV 24.6 6.9 f

*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantization noise.

ADC

Noise*

ENOB

REF

= 5V)*

Maximum Conversion Rate First Notch Frequency Effective Noise BW –3dB Point (Hz)

Internal

9MHz clock

External

/5120 14062.5 fO/640 1574 fO/5700 848 fO/10600

/10240 7031.3 fO/1280 787 fO/11400 424 fO/21200

/20480 3515.6 fO/2560 394 fO/22800 212 fO/42500

/40960 1757.8 fO/5120 197 fO/45700 106 fO/84900

/81920 878.9 fO/1020 98.4 fO/91400 53 fO/170000

/163840 439.5 fO/2050 49.2 fO/183000 26.5 fO/340000

/327680 219.7 fO/4100 24.6 fO/366000 13.2 fO/679000

/655360 109.9 fO/8190 12.4 fO/731000 6.6 fO/1358000

/1310720 54.9 fO/16380 6.2 fO/1463000 3.3 fO/2717000

Internal

9MHz clock

External

Internal

9MHz clock

External

Internal

9MHz clock

External

2440fc

LTC2440

APPLICATIONS INFORMATION

Example: If an ampliﬁ er (e.g. LT1219) driving the input of an LTC2440

has wideband noise of 33nV/√Hz, band-limited to 1.8MHz, the total noise entering the ADC input is:

33nV/√Hz • √1.8MHz = 44.3μV. When the ADC digitizes the input, its digital ﬁ lter ﬁ lters

out the wideband noise from the input signal. The noise reduction depends on the oversample ratio which deﬁ nes the effective bandwidth of the digital ﬁ lter.

At an oversample of 256, the noise bandwidth of the ADC is 787Hz which reduces the total ampliﬁ er noise to:

33nV/√Hz • √787Hz = 0.93μV. The total noise is the RMS sum of this noise with the 2μV

noise of the ADC at OSR=256.

√0.93μ/V Increasing the oversampling ratio to 32768 reduces the

noise bandwidth of the ADC to 6.2Hz which reduces the total ampliﬁ er noise to:

33nV/√Hz • √6.2Hz = 82nV.

+ 2μV2 = 2.2μV.

The total noise is the RMS sum of this noise with the 200nV noise of the ADC at OSR = 32768.

√82nV In this way, the digital ﬁ lter with its variable oversampling

ratio can greatly reduce the effects of external noise sources.

Using Non-Autozeroed Ampliﬁ ers for Lowest Noise Applications

Ultralow noise applications may require the use of low noise bipolar ampliﬁ ers that are not autozeroed. Because the LTC2440 has such exceptionally low offset, offset drift and 1/f noise, the offset drift and 1/f noise in the ampliﬁ ers may need to be compensated for to retain the system performance of which the ADC is capable.

The circuit of Figure 23 uses low noise bipolar ampliﬁ ers and correlated double sampling to achieve a resolution of 14nV, or 19 effective bits over a 10mV span. Each measurement is the difference between two ADC readings taken with opposite polarity bridge excitation. This cancels 1/f noise below 3.4Hz and eliminates errors due to parasitic thermocouples. Allow 750μs settling time after switching excitation polarity.

+ 2μV2 = 216nV.

2440fc

PACKAGE DESCRIPTION

LTC2440

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.045 ±.005

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.007 – .0098

(0.178 – 0.249)

.016 – .050

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

(0.406 – 1.270)

INCHES

(MILLIMETERS)

.150 – .165

.0250 BSC.0165 ±.0015

.015 ± .004

(0.38 ± 0.10)

0° – 8° TYP

.189 – .196*

(4.801 – 4.978)

.229 – .244

(5.817 – 6.198)

°

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

12 11 10

678

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.150 – .157** (3.810 – 3.988)

.004 – .0098

GN16 (SSOP) 0204

TYPICAL APPLICATIONS

4.5V TO 5.5V

1μF

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT RANGE

–0.5V

TO 0.5V

REF

1, 8, 9, 16

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2440

REF

–

REF

–

SDI

GND

BUSY

SCK

SDO

EXT

50Ω

3-WIRE SPI INTERFACE

Figure 22. Simple External Clock Source

LTC1799

OUT

GND

DIV SET

SET

0.1

μF

2440 TA05

2440fc

LTC2440

TYPICAL APPLICATION

REF

100k

REF

100k

2X SILICONIX SI9801

5,6,7,8

TOP_P

TOP_N

BOTTOM_P

BOTTOM_N

2X LT1677

–

100Ω 0.1%

–

0.1μF10μF

REF

LTC2440

–

REF

–

2440 F22

+7V

LT1461-5

10Ω

0.047μF

1k 0.1%

1μF

1k 0.1%

1μF

10Ω

Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-Autozeroed, Bipolar Ampliﬁ er. Circuit Gives 14nV Noise Level or 19 Effective Bits over a 10mV Span

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Building Block LTC1050 Precision Chopper Stabilized Op Amp No External Components 5μV Offset, 1.6μV LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/°C Max Drift

LTC1592 Ultraprecise 16-Bit SoftSpan

DAC Six Programmable Output Ranges LTC1655 16-Bit Rail-to-Rail Micropower DAC ±1LSB DNL, 600μA, Internal Reference, SO-8 LTC1799 Resistor Set SOT-23 Oscillator Single Resistor Frequency Set LTC2053 Rail-to-Rail Instrumentation Ampliﬁ er 10μV Offset with 50nV/°C Drift, 2.5μV LTC2400 24-Bit, No Latency Δ∑ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency Δ∑ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency Δ∑ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA LTC2410/LTC2413 24-Bit, No Latency Δ∑ ADC 800nV LTC2411 24-Bit, No Latency Δ∑ ADC in MSOP 1.45μV LTC2420LTC2424/

1-/4-/8-Channel, 20-Bit, No Latency Δ∑ ADCs 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/

LTC2428 SoftSpan is a trademark of Linear Technology Corporation.

Precise Charge, Balanced Switching, Low Power

Noise

P-P

Noise 0.01Hz to 10Hz

P-P

Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection

RMS

Noise, 6ppm INL

RMS

LTC2404/LTC2408

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

2440fc

LT 0208 REV C • PRINTED IN USA

Datasheet LTC2440 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual