LINEAR TECHNOLOGY LTC2433 Technical data

FEATURES

LTC2433-1

Differential Input

16-Bit No Latency ∆Σ ADC

U

DESCRIPTIO

■

16-Bit Differential ADC in a Tiny MSOP

■

Low Supply Current: 200µA, 4µA in Autosleep

■

Rail-to-Rail Differential Input/Reference

■

0.12LSB INL, No Missing Codes

■

0.16LSB Full-Scale Error and 5µV Offset

■

1.45µV RMS Noise, Independent of V

■

Very Low Transition Noise: <0.02LSB

■

Operates with a Reference as Low as 100mV with

REF

16-Bit Resolution

■

Internal Oscillator—No External Components
Required

■

87dB Min, Simultaneous 50Hz and 60Hz Notch Filter

■

Single Supply 2.7V to 5.5V Operation

■

Pin Compatible with the 20/24-Bit LTC2431/LTC2411

■

Available in 10-Lead MSOP Package

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APPLICATIO S

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain-Gage Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

The LTC®2433-1 is a differential input micropower 16-bit
No Latency ∆ΣTM analog-to-digital converter with an inte­grated oscillator. It provides 0.12LSB INL and 1.45µV
RMS noise independent of V

. It uses delta-sigma

REF

technology and provides single conversion settling of the
digital filter. Through a single pin, the LTC2433-1 can be
configured for better than 87dB input differential mode
rejection at 50Hz and 60Hz ±2%, or it can be driven by an
external oscillator for a user defined rejection frequency.
The internal oscillator requires no external frequency
setting components.

The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full­scale differential input range is from –0.5 •␣ V
V

. The reference common mode voltage, V

REF

the input common mode voltage, V

, may be indepen-

INCM

to 0.5 •

REF

REFCM

, and

dently set anywhere between GND and VCC. The DC
common mode input rejection is better than 140dB.

The LTC2433-1 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.

TYPICAL APPLICATIO

5V REF

4.9k

100Ω

1µF

(100mV)

110

V

CC

2

REF

4

+

IN

LTC2433-1

5

–

IN

3

REF

6

GND

U

Minimum Resolvable Signal vs V

90

80

= EXTERNAL CLOCK SOURCE

F

O

+

9

SCK

SDO

8

7

CS

24331 TA01

–

= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION

3-WIRE
SPI INTERFACE

70

60

50

40

30

20

10

MINIMUM RESOLVABLE SIGNAL (µV)*

0

0

13

*FOR V

REF

IS LIMITED BY STEP SIZE

2

V

(V)

REF

≥ 0.5V THE RESOLUTION

4

24331 TA02

REF

5

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LTC2433-1

WWWU

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

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W

(Notes 1, 2)

Supply Voltage (VCC) to GND.......................–0.3V to 7V

ORDER PART NUMBER

Analog Input Voltage

to GND.................................... –0.3V to (VCC + 0.3V)

Reference Input Voltage

to GND.................................... –0.3V to (VCC + 0.3V)

Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)

Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)

Operating Temperature Range

LTC2433-1C ............................................ 0°C to 70°C

LTC2433-1I ........................................ –40°C to 85°C

TOP VIEW

1

V

CC

+

2

REF

–

REF

3

+

IN

4

–

IN

5

MS10 PACKAGE

10-LEAD PLASTIC MSOP

T

= 125°C, θJA = 110°C/W

JMAX

10

F

O

SCK

9

SDO

8

CS

7

GND

6

LTC2433-1CMS
LTC2433-1IMS

MS PART MARKING

LTAEY
LTAEZ

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)..................300°C

ELECTRICAL CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4, 6)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) 0.1V ≤ V
Integral Nonlinearity (Note 15) 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, V

5V ≤ V
REF

Offset Error (Note 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 520 µV

GND ≤ IN

Offset Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 20 nV/°C

GND ≤ IN

Positive Full-Scale Error (Note 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 0.16 1.25 LSB

Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 0.04 ppm of V

Negative Full-Scale Error (Note 15) 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 0.16 1.25 LSB

Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ VCC, REF– = GND, 0.04 ppm of V

Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, V

Output Noise 5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, 1.45 µV

+

IN

+

IN

+

IN

+

IN

5V ≤ V
REF

GND ≤ IN– = IN+ ≤ VCC, (Note 12)

≤ VCC, –0.5 • V

REF

≤ 5.5V, REF+ = 5V, REF– = GND, V

CC

+

= 2.5V, REF– = GND, V

+

= IN– ≤ VCC, (Note 13)

+

= IN– ≤ V

= 0.75REF+, IN– = 0.25 • REF

= 0.75REF+, IN– = 0.25 • REF

= 0.25 • REF+, IN– = 0.75 • REF

= 0.25 • REF+, IN– = 0.75 • REF

≤ 5.5V, REF+ = 5V, REF– = GND, V

CC

+

= 2.5V, REF– = GND, V

CC

The ● denotes specifications which apply over the full operating

≤ VIN ≤ 0.5 • V

REF

= 1.25V, (Note 6) 0.30 LSB

INCM

+

+

= 1.25V, (Note 6) 0.25 LSB

INCM

Consult LTC Marketing for parts specified with wider operating temperature ranges.

, (Note 5) ● 16 Bits

REF

= 1.25V, (Note 6) 0.06 LSB

INCM

= 2.5V, (Note 6) ● 0.12 1.25 LSB

INCM

+

+

= 1.25V 0.20 LSB

INCM

= 2.5V 0.20 LSB

INCM

REF

REF

/°C

/°C

RMS

2

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LTC2433-1

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CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 130 140 dB

GND ≤ IN

Input Common Mode Rejection 2.5V ≤ REF+ ≤ VCC, REF– = GND, ● 140 dB
49Hz to 61.2Hz GND ≤ IN

Input Normal Mode Rejection (Note 5, 7) ● 87 dB
49Hz to 61.2Hz

Reference Common Mode 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, ● 130 140 dB
Rejection DC V

Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB
Power Supply Rejection, REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB

Simultaneous 50Hz/60Hz ±2%

–

= IN+ ≤ V

–

= IN+ ≤ VCC, (Notes 5, 7)

= 2.5V, IN– = IN+ = GND (Note 5)

REF

CC

The ● denotes specifications which apply over the full operating

(Note 5)

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A ALOG I PUT A D REFERE CE

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The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

+

IN

–

IN
V

IN

+

REF

–

REF
V

REF

CS (IN+)IN
CS (IN–)IN
CS (REF+)REF
CS (REF–)REF
I
I
I
I

(IN+)IN+ DC Leakage Current CS = VCC = 5V, IN+ = GND ● –100 1 100 nA

DC_LEAK

(IN–)IN– DC Leakage Current CS = VCC = 5V, IN– = 5.5V ● –100 1 100 nA

DC_LEAK

(REF+)REF+ DC Leakage Current CS = VCC = 5V, REF+ = 5.5V ● –100 1 100 nA

DC_LEAK

(REF–)REF– DC Leakage Current CS = VCC = 5V, REF– = GND ● –100 1 100 nA

DC_LEAK

Absolute/Common Mode IN+ Voltage ● GND – 0.3 VCC + 0.3 V
Absolute/Common Mode IN– Voltage ● GND – 0.3 VCC + 0.3 V
Input Differential Voltage Range ● –V

+

(IN

– IN–)
Absolute/Common Mode REF+ Voltage ● 0.1 V
Absolute/Common Mode REF– Voltage ● GND VCC – 0.1 V
Reference Differential Voltage Range ● 0.1 V

+

(REF

– REF–)

+

Sampling Capacitance 6 pF

–

Sampling Capacitance 6 pF

+

Sampling Capacitance 6 pF

–

Sampling Capacitance 6 pF

/2 V

REF

/2 V

REF

CC

CC

V

V

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LTC2433-1

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DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IH

V

IL

V

IH

V

IL

I

IN

I

IN

C

IN

C

IN

V

OH

V

OL

V

OH

V

OL

I

OZ

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V ● 2.5 V
CS, F

O

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V ● 0.8 V
CS, F

O

High Level Input Voltage 2.7V ≤ VCC ≤ 5.5V (Note 8) ● 2.5 V
SCK 2.7V ≤ V

Low Level Input Voltage 4.5V ≤ VCC ≤ 5.5V (Note 8) ● 0.8 V
SCK 2.7V ≤ V

Digital Input Current 0V ≤ VIN ≤ V
CS, F

O

Digital Input Current 0V ≤ VIN ≤ VCC (Note 8) ● –10 10 µA
SCK

Digital Input Capacitance 10 pF
CS, F

O

Digital Input Capacitance (Note 8) 10 pF
SCK

High Level Output Voltage IO = –800µA ● VCC – 0.5 V
SDO

Low Level Output Voltage IO = 1.6mA ● 0.4 V
SDO

High Level Output Voltage IO = –800µA (Note 9) ● VCC – 0.5 V
SCK

Low Level Output Voltage IO = 1.6mA (Note 9) ● 0.4 V
SCK

Hi-Z Output Leakage ● –10 10 µA
SDO

2.7V ≤ VCC ≤ 3.3V 2.0 V

2.7V ≤ VCC ≤ 5.5V 0.6 V

≤ 3.3V (Note 8) 2.0 V

CC

≤ 5.5V (Note 8) 0.6 V

CC

CC

The ● denotes specifications which apply over the full

● –10 10 µA

WU

POWER REQUIRE E TS

otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

CC

I

CC

Supply Voltage ● 2.7 5.5 V
Supply Current

Conversion Mode CS = 0V (Note 14)
Sleep Mode CS = V

Sleep Mode CS = V

The ● denotes specifications which apply over the full operating temperature range,

● 200 300 µA

(Notes 11, 14) ● 413 µA

CC

, 2.7V ≤ VCC ≤ 3.3V 2 µA

CC

(Notes 11, 14)

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LTC2433-1

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TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

EOSC

t

HEO

t

LEO

t

CONV

f

ISCK

D

ISCK

f

ESCK

t

LESCK

t

HESCK

t

DOUT_ISCK

t

DOUT_ESCK

t

1

t2 CS ↑ to SDO High Z ● 0 200 ns
t3 CS ↓ to SCK ↓ (Note 9) ● 0 200 ns
t4 CS ↓ to SCK ↑ (Note 8) ● 50 ns
t

KQMAX

t

KQMIN

t

5

t

6

External Oscillator Frequency Range ● 2.56 2000 kHz
External Oscillator High Period ● 0.25 390 µs
External Oscillator Low Period ● 0.25 390 µs
Conversion Time FO = 0V ● 143.8 146.7 149.6 ms

Internal SCK Frequency Internal Oscillator (Note 9) 17.5 kHz

Internal SCK Duty Cycle (Note 9) ● 45 55 %
External SCK Frequency Range (Note 8) ● 2000 kHz
External SCK Low Period (Note 8) ● 250 ns
External SCK High Period (Note 8) ● 250 ns
Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) ● 1.06 1.09 1.11 ms

External SCK 19-Bit Data Output Time (Note 8) ● 19/f
CS ↓ to SDO Low Z ● 0 200 ns

SCK ↓ to SDO Valid ● 220 ns
SDO Hold After SCK ↓ (Note 5) ● 15 ns
SCK Set-Up Before CS ↓ ● 50 ns
SCK Hold After CS ↓ ● 50 ns

The ● denotes specifications which apply over the full operating temperature

External Oscillator (Note 10)

● 20510/f

External Oscillator (Notes 9, 10) f

External Oscillator (Notes 9, 10)

● 152/f

(in kHz) ms

EOSC

/8 kHz

EOSC

(in kHz) ms

EOSC

(in kHz) ms

ESCK

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.
Note 3: V

V

REF

V

INCM

Note 4: F
with f

= 2.7V to 5.5V unless otherwise specified.

CC

= REF+ – REF–, V

= (REF+ + REF–)/2; VIN = IN+ – IN–,

REFCM

= (IN+ + IN–)/2.

pin tied to GND or to an external conversion clock source

O

= 139,800Hz unless otherwise specified.

EOSC

Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from

a precise analog input voltage. Maximum specifications are limited by
the LSB step size (V

/216) and the single shot measurement. Typical

REF

specifications are measured from the center of the quantization band.
Note 7: F

= GND (internal oscillator) or f

O

= 139,800Hz ±2%

EOSC

(external oscillator).
Note 8: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

and is expressed in kHz.

ESCK

Note 9: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, f

, is expressed in kHz.

EOSC

Note 11: The converter uses the internal oscillator.

= 0V.

F

O

Note 12: 1.45µV RMS noise is independent of V
performance is limited by the quantization, lowering V

. Since the noise

REF

improves the

REF

effective resolution.

Note 13: Guaranteed by design and test correlation.
Note 14: The low sleep mode current is valid only when CS is high.
Note 15: These parameters are guaranteed by design over the full

supply and temperature range. Automated testing procedures are
limited by the LSB step size (V

/65,536).

REF

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5

LTC2433-1

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PI FU CTIO S

VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.

REF+ (Pin 2), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF–, by at least 0.1V.

IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these analog inputs can have any value between
GND and VCC. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5 • (V
to 0.5 • (V
produces unique overrange and underrange output codes.

GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.

CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.

). Outside this input range the converter

REF

REF

)

SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.

SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull­up is automatically activated in Internal Serial Clock Op­eration mode. The Serial Clock Operation mode is deter­mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.

FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to GND (FO = 0V), the
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When FO is driven by an external
clock signal with a frequency f
signal as its system clock and the digital filter has 87dB
minimum rejection in the range f
110dB minimum rejection at f

, the converter uses this

EOSC

/2560 ±14% and

EOSC

/2560 ±4%.

EOSC

6

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LTC2433-1

1.69k

SDO

24361 TA04

Hi-Z TO V

OL

VOH TO V

OL

VOL TO Hi-Z

C

LOAD

= 20pF

V

CC

U

U

W

FU CTIO AL DIAGRA

V

CC

GND

+

IN
IN

REF
REF

+

–

–

DAC

+
–

INTERNAL

OSCILLATOR

AUTOCALIBRATION

AND CONTROL

∫∫∫

∑

ADC

DECIMATING FIR

SERIAL

INTERFACE

(INT/EXT)

24331 FD

F

O

SDO

SCK

CS

Figure 1. Functional Block Diagram

TEST CIRCUITS

SDO

1.69k

Hi-Z TO V
VOL TO V

OH

VOH TO Hi-Z

= 20pF

C

LOAD

OH

24361 TA03

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LTC2433-1

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APPLICATIO S I FOR ATIO

CONVERTER OPERATION

Converter Operation Cycle

The LTC2433-1 is a low power, ∆Σ ADC with differential
input/reference and an easy-to-use 3-wire serial interface
(see Figure 1). Its operation is made up of three states.
The converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).

Initially, the LTC2433-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.

Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new

CONVERT

SLEEP

FALSE

CS = LOW

AND

SCK

TRUE

DATA OUTPUT

Figure 2. LTC2433-1 State Transition Diagram

24331 F02

conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per­formed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2433-1 with
additional serial clock pulses. This results in additional
data bits which are logic HIGH.

Through timing control of the CS and SCK pins, the
LTC2433-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program­ming configuration registers; moreover, they do not dis­turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor­mance is directly related to the accuracy of the converter
system clock. The LTC2433-1 incorporates a highly accu­rate on-chip oscillator. This eliminates the need for exter­nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2433-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.

Ease of Use

The LTC2433-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.

8

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APPLICATIO S I FOR ATIO

LTC2433-1

The LTC2433-1 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de­scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re­spect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2433-1 automatically enters an internal reset state
when the power supply voltage VCC drops below approxi­mately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec­tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)

When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers. Following the POR signal, the
LTC2433-1 starts a normal conversion cycle and follows
the succession of states described above. The first con­version result following POR is accurate within the speci­fications of the device if the power supply voltage is restored
within the operating range (2.7V to 5.5V) before the end of
the POR time interval.

Reference Voltage Range

This converter accepts a truly differential external refer­ence voltage. The absolute/common mode voltage speci­fication for the REF+ and REF– pins covers the entire range
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.

The LTC2433-1 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is deter­mined by the thermal noise of the front-end circuits, and
as such, its value in microvolts is nearly constant with
reference voltage. A decrease in reference voltage will
significantly improve the converter’s effective resolution,
since the thermal noise (1.45µV) is well below the quan-
tization level of the device (75.6µV for a 5V reference). At
the minimum reference (100mV) the thermal noise

remains constant at 1.45µV RMS (or 8.7µV
quantization is reduced to 1.5µV per LSB. As a result,
lowering the reference improves the effective resolution
for low level input voltages.

Input Voltage Range

The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2433-1 converts the bipolar differen­tial input signal, VIN = IN+ – IN–, from – FS = – 0.5 • V
+FS = 0.5 • V
range, the converter indicates the overrange or the
underrange condition using distinct output codes.

Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to main­tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
Current sections. In addition, series resistors will intro­duce a temperature dependent offset error due to the input
leakage current. A 10nA input leakage current will develop
a 1LSB offset error on an 8k resistor if V
has a very strong temperature dependency.

Output Data Format

The LTC2433-1 serial output data stream is 19 bits long.
The first 3 bits represent status information indicating the
conversion state and sign. The next 16 bits are the conver­sion result, MSB first. The third and fourth bit together are
also used to indicate an underrange condition (the differ­ential input voltage is below –FS) or an overrange condi­tion (the differential input voltage is above +FS).

where V

REF

= REF+ – REF–. Outside this

REF

REF

), while the

P-P

to

REF

= 5V. This error

24331fa

9