Linear Technology LTC2374, LTC2372, LTC2373 Demo Manual

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DESCRIPTION

DEMO MANUAL DC2071A

LTC2374/LTC2373/LTC2372

16-Bit/18-Bit, 1.6Msps/1Msps/500ksps

8-Channel, SAR ADCs

Demonstration circuit 2071A features the LTC®2373 family. The LTC2374/LTC2373/LTC2372 are low noise, high speed, 8-channel, 16-/18-bit successive approximation register (SAR) ADCs. The following text refers to the LTC2373-18 but applies to all parts in the family, the only differences being the number of bits and the maximum sample rate. Operating from a single 5V supply, the LTC2373-18 has a highly configurable, low crosstalk, 8-channel input multi

fully

plexer, supporting polar and pseudo-differential bipolar analog input ranges.

DC2071 demonstrates the DC and AC performance of

The the LTC2373-18 in conjunction with the DC590 and DC890 data collection boards. Use the DC590 to demonstrate DC

differential, pseudo-differential uni-

performance such as peak-to-peak noise and DC linearity. Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR, THD, SINAD and SFDR. The demonstration circuit 2071 is intended to demonstrate recommended grounding, component place ment and Several

will be presented.

Design files for this circuit board, including the schematic and BOM, are available at

http://www.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

selection, routing and bypassing for this ADC.

suggested driver circuits for the analog inputs

linear.com/demo/DC2071A

ASSEMBLY OPTIONS

Table 1. DC2071A Assembly Options

Assembly Version U1 Part Number Max Conversion Rate Number of Bits Max CLK IN Frequency

DC2071A-A LTC2373CUH-18 1Msps 18 62MHz

DC2071A-B LTC2372CUH-18 0.5Msps 18 31MHz

DC2071A-C LTC2374CUH-16 1.6Msps 16 86.4MHz

DC2071A-D LTC2373CUH-16 1Msps 16 50MHz

DC2071A-E LTC2372CUH-16 0.5Msps 16 25MHz

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DEMO MANUAL DC2071A

DEFAULT INPUT LEVELS

BOARD PHOTO

0V TO 4.096V

±8.192V

0V TO 4.096V

–16V GND +16V

DC890

±4.096V

CLK 100MHz MAX

3.3V

Figure 1. DC2071A Connection Diagram

DC590 OR DC2026

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DC890 QUICK START PROCEDURE

DEMO MANUAL DC2071A

Check to make sure that all switches and jumpers are set as shown in the connection diagram of Figure 1. The default connections configure the ADC to use the onboard reference and regulators to generate the required common mode voltages. The analog input is DC coupled. Connect the DC2071A to a DC890 USB High Speed Data Collec tion Board using connector P1. Then, connect the DC890 to a host PC with a standard USB A/B cable. Apply ±16V to the indicated terminals. Then apply a low jitter signal source to J2–J7. Observe the recommended input voltage range for each analog input. Connect a low jitter 2.5V sine wave or square wave to connector J1. See Table 1 for the appropriate clock frequency. Note that J1 has a 50Ω termination resistor to ground.

DC590 QUICK START PROCEDURE

IMPORTANT! To avoid damage to the DC2071A, make sure that VCCIO (JP6) of the DC590 is set to

3.3V before connecting the DC590 to the DC2071A.

Run the PScope™ software (Pscope.exe version K88 or later) which can be downloaded from www.linear.com/

designtools/software.

Complete software documentation is available from the Help menu. Updates can be downloaded from the Tools menu. Check for updates periodically as new features may be added.

The PScope software should recognize the DC2071A and configure itself automatically.

Click the Collect data. The Collect button then changes to Pause, which can be clicked to stop data acquisition.

ribbon cable. Apply a signal source to J2-J7. No clock is required on J1 when using the DC590. The clock is provided by the DC590.

button (See Figure 7)

to begin acquiring

To use the DC590 with the DC2071A, it is necessary to apply ±16V and ground to the ±16V and GND terminals on the DC2071A. Connect the DC590 to a host PC with a standard USB A/B cable. Connect the DC2071A to a DC590 USB serial controller using the supplied 14-conductor

Run the QuikEval™ software (quikeval.exe version K109 or later) which is available from www.linear.com/design

tools/software. The

automatically. Click the Collect button (Figure 10) to begin reading the ADC.

correct control panel will be loaded

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DEMO MANUAL DC2071A

DC2071A SETUP

DC Power

The DC2071A requires ±16VDC and draws +100mA/ –40mA. Most of the supply current is consumed by the CPLD, op amps, regulators and discrete logic on the board. The +16VDC input voltage powers the ADC through LT1763 regulators which provide protection against accidental reverse bias. Additional regulators provide power for the CPLD and op amps. See Figure 1 for connection details.

Clock Source

You must provide a low jitter 2.5V

sine or square wave

to the clock input, J1. The clock input is AC coupled so the DC level of the clock signal is not important. A generator like the Rohde & Schwarz SMB100A high speed clock source is recommended. Even a good generator can start to produce noticeable jitter at low frequencies. Therefore it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate. The ratio of clock frequency to conversion rate is 62:1 for 18-bit parts and 50:1 or 54:1 for 16-bit parts. If the clock input is to be driven with logic, it is recommended that the

49.9Ω terminator (R3) be removed. Slow rising edges may compromise the SNR of the converter in the presence of high-amplitude higher frequency

input signals.

Data Output

Parallel

data output from this board (0V to 2.5V default), if not connected to the DC890, can be acquired by a logic analyzer and subsequently imported into a spreadsheet or mathematical package depending on what form of digital signal processing is desired. Alternatively, the data can be fed directly into an application circuit. Use pin-50 of P1 to latch the data. The data should be latched using the positive edge of this signal. The data output signal levels at P1 can also be increased to 0V to 3.3V if the application circuit requires a higher voltage. This is accomplished by moving JP3 to the 3.3V position.

Reference

The default reference is the LTC2373-18 internal 4.096V reference. Alternatively, if an external reference voltage is

desired, the LTC6655-4.096 reference (U9) can be used by setting the REF jumper (JP1) to the EXT position and installing a 0Ω resistor in the R19 position.

Analog Inputs

The four default driver circuits for the analog inputs of the LTC2373-18 on the DC2071A are shown in Figures2to5. The circuit of Figure 2 is a fully differential driver with 0V to 4.096V inputs. The output of this circuit is band limited to

approximately 13MHz. The

circuit of Figure 3 is a single-ended to differential driver with an input signal range of ±8.192V. This circuit is band limited to 1.6MHz at the output. The circuit of Figure 4 is a single-ended to differential driver with an input range of 0V to 4.096V. The output bandwidth of this circuit is 1.6MHz. The circuit of Figure 5 is a single-ended/fully differential input driver circuit with an input range of ±4.096V. The input band width of to Drive the A

this circuit is 4.8kHz. The output is band limited

3MHz. The default for this circuit is single-ended drive.

–

input to ±4.096V. Alternatively, by remov-

IN4

ing R117 and changing R114 to 100Ω this circuit can be driven fully differentially.

The

and A

IN1

driver circuits can be DC or AC coupled.

IN3

The default setting is DC coupled. AC coupling the inputs may degrade the distortion performance of the ADC due to nonlinearity of the coupling capacitors. AC coupling can be implemented on the DC2071A by putting the coupling jumpers (JP6, JP8 for A

and JP7 for A

IN1

) in the AC

IN3

position, and adding two 1kΩ resistors at the optional resistor locations (R91,

on the other side of each coupling capacitor

R97, R106, R110 for A

and R93, R100 for A

IN1

IN3

Another option available on the demo board is to drive each input single-ended and then convert the single-ended inputs to fully differential at the MUX outputs. This allows the user to have eight single-ended inputs but still have

the SNR of a fully differential input. To accomplish this, remove C31, R8, R15 and R128 then add C15, C24, C27, C29, R7, R13, R16, R17, R18, R129, R130, R131 and U7. The values for the passive devices are shown in the schematic of Figure 6.

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DC2071A SETUP

IN1

0V TO

4.096V

–

IN1

0V TO

4.096V

BNC

R94

0Ω

R109

0Ω

C79 OPT 1206

C92 OPT 1206

C77

10µF

6.3V

3 2 1

AC DC

C91

10µF

6.3V

3 2 1

AC DC

CM2

JP6 +IN1 COUPLING

CM2

JP8 –IN1 COUPLING

R91 OPT

R97 OPT

R106 OPT

R110 OPT

DEMO MANUAL DC2071A

C90 15pF

R96 10Ω

R105

10Ω

R92 OPT

R108 OPT

CH0

CH1

0.1µF

R101

R137

OPT

R104

C82

U24B

C84 OPT

C86 OPT

U24A

C75

0.1µF

LT6237

–

24.9Ω

–

LT6237

C74 10µF

6.3V

C89 10µF

6.3V

R95

24.9Ω

R107

24.9Ω

C80 15pF

±8.192V

Figure 2. 0V to 4.096V Fully Differential AC/DC Coupled Driver

OP AMP

C93

10µF

R112

IN2

0Ω

BNC

C96 OPT

–

OP AMP

LT1469

–

25V

0805

U25A

C98

10µF

25V

0805

VCM

R134

20Ω

C105

R116

20K

R125

20K

C99

10µF

6.3V

R120

4.99K

–

LT1469

R126

10K

C102

0.01µF C0G

U25B

R132, 20Ω

R133, 20Ω

R135 20Ω

C106

0.01µF C0G

LT5400-4

R113

0Ω

R121

0Ω

CH2

CH3

Figure 3. ±8.192V Single-Ended to Differential DC Coupled Driver

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DEMO MANUAL DC2071A

DC2071A SETUP

IN3

0V TO

4.096V

CM2

C78

R98

0Ω

BNC

10µF

6.3V

C81 OPT 1206

3 2 1

AC DC

R93 OPT

R100 OPT

JP7 IN3 COUPLING

C76 10µF

6.3V

C72 1µF

C83 15pF

R102 499Ω

C85 1µF

C87 10µF

6.3V

C73

0.1µF

3 7

IN1

+ –

LT6350

–

IN2

R98

–

0Ω

C88

0.1µF

–

Figure 4. 0V to 4.096V Single-Ended to Differential AC/DC Coupled Driver

C107

0.01µF

SHDN

OUT1

–

IN1

OUT2

U27

R99 10Ω

CH5

R103

10Ω

CH4

R111

VDD

OCM

4.7µF

– +

C95

10V

U28

C101 10µF

6.3V

R118

35.7Ω

R119

35.7Ω

CH6

CH7

IN4

±4.096V

IN4

±4.096V

C94

–

0Ω

BNC

R117 150Ω

R112

100Ω

BNC

R124 OPT

R114

R115

C97

0.22µF C0G 1812

R123

C100

0.22µF C0G 1812

0.1µF

R127

LTC6362

–

C108

0.01µF

SHDN

Figure 5. Single-Ended/Fully Differential Input to Fully Differential DC Coupled Driver

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DC2071A SETUP

DEMO MANUAL DC2071A

0.1µF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

C8 1200pF

C14 1200pF

C16 OPT

C20 OPT

C21 3300pF

C23 3300pF

C25 1500pF

C28 1500pF

C9 OPT

C17 OPT

C22 3300pF

C26 OPT

R129

R1300ΩR131

BUFOUT

0Ω

BUFOUT

R13

0Ω

R17

C103

25pF

–

LT6237

31 32

1 2 7 8

9 10 30

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

–

U7B

0.1µF

LT6237

0.1µF

C10 10µF 25V 0805

24.9Ω

MUXOUT

–

MUXOUT–ADCIN

C27

U7A

C29

ADCIN

–

C24

1000pF

R16

24.9Ω

10µF

25V

0805

C11

0.1µF

C15 1000pF

LTC237X

GND

27171514112623

VDDLBYP

GND

REFBUF

CNV SCK

SDI

SDO

BUSY

RDL

C13 47µF 10V 1210 X7R

REF

INT

C19

4.7µF

16 21 20 22 19

2 3

EXT

JP1

R111kR12

CCI0

C12

0.1µF

GND

OVDD

GND

REFBUF

OGND

GND

REFIN

RESET

GND

Figure 6. Eight Single-Ended Inputs Converted to Fully Differential

–

R18

C104 25pF

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DEMO MANUAL DC2071A

DC2071A SETUP

DC890 Data Collection

For SINAD, THD or SNR testing, a low noise, low distortion generator such as the B&K Type 1051 or Stanford Research SR1 should be used. A low jitter RF oscillator such as the Rohde & Schwarz SMB100A or DC1216A-A high speed clock source is used to drive the clock input. This demo board is tested in-house by attempting to duplicate the FFT plot shown in the Typical Performance Characteristics section of the LTC2373-18 data sheet. This involves using a 62MHz clock source, along with a sinusoidal generator

at a frequency of approximately 1kHz. The input signal level is approximately –1dBFS. A typical FFT obtained with DC2071A is shown in Figure 7. Note that to calculate the real SNR, the signal level (F1 amplitude = –1.001dB) has to be added back to the SNR that PScope displays.

With the example shown in Figure 7 this means that the actual SNR would be 100.60dB instead of the 99.60dB that PScope displays. Taking the RMS sum of the recalculated

SNR and the THD yields a SINAD of 100.4dB which is fairly

close to the typical number for this ADC.

Figure 7. PScope Screen Shot

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DC2071A SETUP

DEMO MANUAL DC2071A

To change the default settings for the LTC2373-18 sequencer in PScope, click on the Set Demo Bd Options button open the Configure Sequencer menu of Figure 9. In this menu it is possible to set the number of sequences up to 16, the channel configuration, format and gain compres sion setting return optimized for the default hardware settings of the DC2071A.

There are a number of scenarios that can produce mislead ing results when evaluating an ADC. One that is common is a sub-multiple of the sample rate and which will only

in the PScope tool bar shown in Figure 8. This will

for each sequence. There is also a button to

PScope to the default DC2071 settings which are

feeding the converter with an input frequency that is

Figure 8. PScope Tool Bar

exercise a small subset of the possible output codes. The proper method is to pick an M/N frequency for the

input sine wave frequency. N is the number of samples in the FFT. M is a prime number between one and N/2. Multiply M/N by the sample rate to obtain the input sine wave frequency. Another scenario that can yield poor results is if you do not have ppm

frequency accuracy or if it cannot be locked to the clock frequency. You can use an FFT with windowing to reduce the leakage, or spreading of the fundamental, to get a close approximation of the ADC performance. If an amplifier or clock source with poor phase noise is used, the windowing will not improve the SNR.

a signal generator capable of

Figure 9. PScope Configure Sequencer Menu

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DEMO MANUAL DC2071A

DC2071A SETUP

DC590 Data Collection

Due to the relatively low and somewhat unpredictable sample rate of the DC590, its usefulness is limited to noise measurement and data collection of slowly moving signals. A typical data capture and histogram are shown in Figure 10. To change the default settings for the LTC237318 sequencer in QuikEval click on the Sequence Config. button. This will open the Sequence Configuration menu of Figure 11. In this menu, it is possible to set the number of sequences up to 16, the channel configuration, format and gain compression setting for each sequence. There is also a button to return QuikEval to the default DC2071 settings which are optimized for the default hardware settings of the DC2071A.

To get the best noise performance from the DC2071 it is recommended to place the demo board in a grounded metal enclosure filled with tissue paper.

Layout

As with any high performance ADC, this part is sensitive to layout. The area immediately surrounding the ADC on the DC2071A should be used as a guideline for placement

and routing of the various components associated with the ADC. Here are some things to remember when lay

ing out necessary to obtain maximum performance. Keep bypass capacitors as close to supply pins as possible. Use indi vidual low impedance returns for all bypass capacitors. Use of a symmetrical layout around the analog inputs will minimize the effects of parasitic elements. Shield

analog input traces with ground to minimize coupling

from other traces. Keep traces as short as possible.

Component Selection

When driving a low noise, low distortion ADC such as the LTC2373-18, component selection is important so as to not degrade performance. Resistors should have low values to minimize noise and distortion. Metal film resistors are recommended to reduce distortion caused by self heating. Because of their low voltage coefficients, to further reduce distortion, NP0 or silver mica capacitors should be used. Any buffer used to drive the LTC2373-18

should have low distortion, low noise and a fast settling

time, such as the LT1469, LT6237, LT6350 or LTC6362.

a board for the LTC2373-18. A ground plane is

Figure 10. QuikEval Screen Shot

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DC2071A SETUP

DEMO MANUAL DC2071A

Figure 11. QuikEval Sequence Configuration Menu

DC2071A JUMPERS

Definitions

JP1: REF Selects INT or EXT reference for the ADC. The

default setting is INT.

JP2: Selects the common mode voltage for the ADC. Choices are EXT, 2.5V, 2.048V or GND. The default set ting is 2.048V.

VCCIO sets the output levels at J2 to either 3.3V or

2.5V. Use 2.5V to interface to the DC890 which is the default setting. Use 3.3V to interface to the DC590.

JP4: JTAG is used to program the CPLD. This is for fac tory use only.

EEPROM is for factory use only. The default posi-

tion is WP.

+IN1 COUPLING selects AC or DC coupling of +IN1.

JP6:

The default setting is DC.

JP7: IN3 COUPLING selects AC or DC coupling of IN3. The default setting is DC.

JP8: –IN1 COUPLING Selects AC or DC coupling of –IN1. The default setting is DC.

JP9: COM sets the DC bias voltage for the COM pin to either CM or GND. CM is the default setting.

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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DEMO MANUAL DC2071A

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC ) provides the enclosed product(s) under the following AS IS conditions:

This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LT C for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,

customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LT C currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and

observe good laboratory practice standards. Common sense is encouraged.

This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

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