Datasheet LTC2280 Datasheet (LINEAR TECHNOLOGY)

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FEATURES

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Integrated Dual 10-Bit ADCs

■

Sample Rate: 105Msps

■

Single 3V Supply (2.85V to 3.4V)

■

Low Power: 540mW

■

61.6dB SNR, 85dB SFDR

■

110dB Channel Isolation at 100MHz

■

Flexible Input: 1V

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

■

Pin Compatible Family

P-P

to 2V

P-P

Range

105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit) 80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit) 65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit) 40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit) 25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit) 10Msps: LTC2290 (12-Bit)

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64-Pin (9mm × 9mm) QFN Package

APPLICATIO S

LTC2280

Dual 10-Bit, 105Msps

Low Noise 3V ADC

DESCRIPTIO

The LTC®2280 is a 10-bit 105Msps, low noise 3V dual A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2280 is perfect for demanding imaging and communications applications with AC performance that includes 61.6dB SNR and 85dB SFDR for signals at the Nyquist frequency.

DC specs include ±0.1LSB INL (typ), ±0.1LSB DNL (typ) and ±0.6LSB INL, ±0.6LSB DNL over temperature. The transition noise is a low 0.08LSB

A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic.

A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

RMS

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Wireless and Wired Broadband Communication

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Imaging Systems

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Spectral Analysis

■

Portable Instrumentation

TYPICAL APPLICATIO

ANALOG INPUT A

CLK A

CLK B

ANALOG INPUT B

INPUT

S/H

–

CLOCK/DUTY CYCLE

CONTROL

CLOCK/DUTY CYCLE

CONTROL

INPUT

S/H

–

10-BIT PIPELINED ADC CORE

OUTPUT

DRIVERS

OUTPUT

DRIVERS

2280 TA01

D9A

•

D0A

OGND

MUX

D9B

•

D0B

OGND

SNR vs Input Frequency,

SNR (dBFS)

–1dB, 2V Range

100

INPUT FREQUENCY (MHz)

150

200

2280 TA02

2280fa

LTC2280

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ABSOLUTE AXI U RATI GS

OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ................................................. 4V

Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V

Digital Input Voltage .................... –0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

Power Dissipation............................................ 1500mW

Operating Temperature Range

LTC2280C ............................................... 0°C to 70°C

LTC2280I.............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

+ 0.3V)

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

64 GND

63 VDD62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OFA

56 DA9

55 DA8

54 DA7

53 DA6

52 DA5

51 DA4

50 OGND

49 OV

INA+

–

INA

REFHA 3 REFHA 4 REFLA 5 REFLA 6

CLKA CLKB 9

REFLB 11 REFLB 12 REFHB 13 REFHB 14

–

INB

GND

SENSEB

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

NC 24

OEB 23

MUX 21

VCMB

SHDNB 22

UP PACKAGE

= 125°C, θJA = 20°C/W

JMAX

NC 25

NC 26

NC 27

DB0 28

ORDER PART

NUMBER

DB1 29

QFN PART*

48 DA3 47 DA2 46 DA1 45 DA0 44 NC 43 NC 42 NC 41 NC 40 OFB 39 DB9 38 DB8 37 DB7 36 DB6 35 DB5 34 DB4 33 DB3

DB2 30

OGND 31

MARKING

LTC2280CUP

LTC2280UP

LTC2280IUP

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 10 Bits

Integral Linearity Error Differential Analog Input (Note 5) ● –0.6 ±0.1 0.6 LSB

Differential Linearity Error Differential Analog Input ● –0.6 ±0.1 0.6 LSB

Offset Error (Note 6) ● –12 ±212 mV

Gain Error External Reference ● –2.5 ±0.5 2.5 %FS

Offset Drift ±10 µV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°C

Gain Matching External Reference ±0.3 %FS

Offset Matching ±2mV

Transition Noise SENSE = 1V 0.08 LSB

The ● denotes the specifications which apply over the full operating

RMS

2280fa

LTC2280

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A ALOG I PUT

specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IN,CM

SENSE

MODE

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

Analog Input Range (A

Analog Input Common Mode (A

Analog Input Leakage Current 0V < A

SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA

MODE Input Leakage Current 0V < MODE < V

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

Full Power Bandwidth Figure 8 Test Circuit 575 MHz

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 61.6 dB

SFDR Spurious Free Dynamic Range 5MHz Input 85 dB

2nd or 3rd Harmonic

SFDR Spurious Free Dynamic Range 5MHz Input 85 dB

4th Harmonic or Higher

S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 61.6 dB

Intermodulation Distortion fIN = 40MHz, 41MHz 85 dB

Crosstalk fIN = 100MHz –110 dB

The ● denotes the specifications which apply over the full operating temperature range, otherwise

–

–A

) 2.85V < V

–

)/2 Differential Input Drive (Note 7) ● 1 1.5 1.9 V

Single Ended Input Drive (Note 7)

< 3.4V (Note 7) ● ±0.5V to ±1V V

● 0.5 1.5 2 V

–

, A

< V

● –1 1 µA

● –3 3 µA

RMS

The ● denotes the specifications which apply over the full operating temperature range,

30MHz Input 61.6 dB

70MHz Input ● 60 61.5 dB

140MHz Input 61.4 dB

30MHz Input 85 dB

70MHz Input ● 70 83 dB

140MHz Input 77 dB

30MHz Input 85 dB

70MHz Input ● 76 85 dB

140MHz Input 85 dB

30MHz Input 61.6 dB

70MHz Input ● 60 61.5 dB

140MHz Input 61.3 dB

2280fa

LTC2280

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UU U

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I

VCM Output Tempco ±25 ppm/°C

VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V

VCM Output Resistance –1mA < I

= 0 1.475 1.500 1.525 V

OUT

(Note 4)

< 1mA 4 Ω

OUT

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, SHDN, MUX)

LOGIC OUTPUTS

OVDD = 3V

SOURCE

SINK

= 2.5V

OVDD = 1.8V

High Level Input Voltage VDD = 3V ● 2V

Low Level Input Voltage VDD = 3V ● 0.8 V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10µA 2.995 V

Low Level Output Voltage IO = 10µA 0.005 V

High Level Output Voltage IO = –200µA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200µA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 25°C. (Note 4)

= 0V 50 mA

OUT

= 3V 50 mA

OUT

= –200µA ● 2.7 2.99 V

= 1.6mA ● 0.09 0.4 V

The ● denotes the specifications which apply over the

● –10 10 µA

2280fa

LTC2280

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POWER REQUIRE E TS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DISS

SHDN

NAP

Analog Supply Voltage (Note 9) ● 2.85 3 3.4 V

Output Supply Voltage (Note 9) ● 0.5 3 3.6 V

Supply Current Both ADCs at f

Power Dissipation Both ADCs at f

Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW

Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

= 25°C. (Note 8)

The ● denotes the specifications which apply over the full operating temperature

S(MAX)

● 180 210 mA

● 540 630 mW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pipeline Latency 5 Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup.

Note 4: V drive, unless otherwise noted.

Sampling Frequency (Note 9) ● 1 105 MHz

CLK Low Time Duty Cycle Stabilizer Off (Note 7) ● 4.5 4.76 500 ns

CLK High Time Duty Cycle Stabilizer Off (Note 7) ● 4.5 4.76 500 ns

Sample-and-Hold Aperture Delay 0 ns

CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns

MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns

BUS Relinquish Time (Note 7) ● 3.3 8.5 ns

= 3V, f

= 105MHz, input range = 2V

SAMPLE

The ● denotes the specifications which apply over the full operating temperature

● 3 4.76 500 ns

= 105MHz, input range = 1V

P-P

with differential

P-P

Duty Cycle Stabilizer On (Note 7)

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111.

Note 7: Guaranteed by design, not subject to test.

, they

Note 8: V drive. The supply current and power dissipation are the sum total for both channels with both channels active.

Note 9: Recommended operating conditions.

= 3V, f

SAMPLE

2280fa

LTC2280

CODE

70000

60000

50000

40000

30000

20000

10000

511

65528

512

2280 G09

510

COUNT

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TYPICAL PERFOR A CE CHARACTERISTICS

Crosstalk vs Input Frequency

–100

–105

–110

–115

CROSSTALK (dB)

–120

–125

–130

20 40 60 80

INPUT FREQUENCY (MHz)

8192 Point FFT, f

= 5MHz, –1dB,

2V Range, 105Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

2280 G01

2280 G04

100

Typical INL, 2V Range, 105Msps Typical DNL, 2V Range, 105Msps

1.0

0.8

0.6

0.4

0.2

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

256 512 1024

CODE

768

8192 Point FFT, fIN = 30MHz, –1dB, 2V Range, 105Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

2280 G02

2280 G05

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

256 512 1024

CODE

8192 Point FFT, fIN = 70MHz, –1dB, 2V Range, 105Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

768

2280 G03

2280 G06

8192 Point 2-Tone FFT, fIN = 28.2MHz and 26.8MHz, –1dB, 2V Range, 105Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

8192 Point FFT, fIN = 140MHz, –1dB, 2V Range, 105Msps

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

2280 G07

Grounded Input Histogram, 105Msps

2280 G08

2280fa

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TYPICAL PERFOR A CE CHARACTERISTICS

LTC2280

SNR vs Input Frequency, –1dB, 2V Range, 105Msps

SNR (dBFS)

100

INPUT FREQUENCY (MHz)

150

200

SNR vs Input Level, fIN = 70MHz, 2V Range, 105Msps

SNR (dBc AND dBFS)

–40 –30

–50

dBFS

dBc

–20

INPUT LEVEL (dBFS)

250

–10

300

2280 G10

2280 G13

350

SFDR (dBFS)

SFDR vs Input Frequency, –1dB, 2V Range, 105Msps

50 100

INPUT FREQUENCY (MHz)

200 300 350

150 250

SFDR vs Input Level, fIN = 70MHz, 2V Range, 105Msps

100

SFDR (dBc AND dBFS)

–40

–50

dBFS

dBc

–20

–30

INPUT LEVEL (dBFS)

–10

2280 G11

2280 G14

SNR and SFDR vs Sample Rate, 2V Range, f

SNR AND SFDR (dBFS)

20 40 60 80

vs Sample Rate,

VDD

= 5MHz, –1dB

SFDR

SNR

SAMPLE RATE (Msps)

100 120 140

2280 G12

5MHz Sine Wave Input, –1dB

200

190

180

170

160

(mA)

150

140

130

120

110

2V RANGE

SAMPLE RATE (Msps)

1V RANGE

60 120

100

2280 G15

vs Sample Rate, 5MHz Sine

OVDD

Wave Input, –1dB, OVDD = 1.8V

17.5

15.0

12.5

10.0

(mA)

7.5

OVDD

5.0

2.5

20 40

SAMPLE RATE (Msps)

80 120

60 100

2280 G16

SNR vs SENSE, fIN = 5MHz, –1dB

61.8

61.6

61.4

61.2

61.0

SNR (dBFS)

60.8

60.6

60.4

60.2

0.5 0.6 0.8

0.4

0.7

SENSE PIN (V)

0.9 1 1.1

2280 G17

2280fa

LTC2280

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PI FU CTIO S

(Pin 1): Channel A Positive Differential Analog

INA

Input.

–

(Pin 2): Channel A Negative Differential Analog

INA

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short together and bypass to Pins 13, 14 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2µF ceramic chip ca- pacitor and to ground with a 1µF ceramic chip capacitor.

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input range of ±V

(Pin 20): Channel B 1.5V Output and Input Common

CMB

Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to V

MUX (Pin 21): Digital Output Multiplexer Control. If MUX is High, Channel A comes out on DA0-DA9, OFA; Channel B comes out on DB0-DB9, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0DB9, OFB; Channel B comes out on DA0-DA9, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together. (This is not recommended at clock frequencies above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection Pin. Connecting SHDNB to GND and OEB to GND results in normal operation with the outputs enabled. Connecting SHDNB to GND and OEB to V tion with the outputs at high impedance. Connecting SHDNB to VDD and OEB to GND results in nap mode with the outputs at high impedance. Connecting SHDNB to V and OEB to VDD results in sleep mode with the outputs at high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to SHDNB pin function.

NC (Pins 24 to 27, 41 to 44): Do Not Connect These Pins.

. ±1V is the largest valid input range.

SENSEB

CMA

results in normal opera-

REFHB (Pins 13, 14): Channel B High Reference. Short together and bypass to Pins 11, 12 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2µF ceramic chip ca- pacitor and to ground with a 1µF ceramic chip capacitor.

–

(Pin 15): Channel B Negative Differential Analog

INB

Input.

(Pin 16): Channel B Positive Differential Analog

INB

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to V and a ±0.5V input range. VDD selects the internal reference

selects the internal reference

CMB

DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital Outputs. DB9 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output. High when an overflow or underflow has occurred.

DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital Outputs. DA9 is the MSB.

OFA (Pin 57): Channel A Overflow/Underflow Output. High when an overflow or underflow has occurred.

OEA (Pin 58): Channel A Output Enable Pin. Refer to SHDNA pin function.

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PI FU CTIO S

SHDNA (Pin 59): Channel A Shutdown Mode Selection Pin. Connecting SHDNA to GND and OEA to GND results in normal operation with the outputs enabled. Connecting SHDNA to GND and OEA to VDD results in normal operation with the outputs at high impedance. Connecting SHDNA to V the outputs at high impedance. Connecting SHDNA to V

and OEA to GND results in nap mode with

and OEA to VDD results in sleep mode with the outputs at high impedance.

MODE (Pin 60): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Note that MODE controls both channels. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle

FUNCTIONAL BLOCK DIAGRA

stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off.

(Pin 61): Channel A 1.5V Output and Input Common

CMA

Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. Do not connect to V

CMB

SENSEA (Pin 62): Channel A Reference Programming Pin. Connecting SENSEA to V and a ±0.5V input range. V

selects the internal reference

CMA

selects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input range of ±V

. ±1V is the largest valid input range.

SENSEA

GND (Exposed Pad) (Pin 65): ADC Power Ground. The Exposed Pad on the bottom of the package needs to be soldered to ground.

2.2µF

SENSE

INPUT

S/H

–

1.5V

REFERENCE

RANGE

SELECT

FIRST PIPELINED

ADC STAGE

REF

BUF

SECOND PIPELINED

ADC STAGE

DIFF

REF

AMP

REFH

0.1µF

2.2µF

THIRD PIPELINED

ADC STAGE

INTERNAL CLOCK SIGNALSREFH REFL

REFL

FOURTH PIPELINED

CLOCK/DUTY

CYCLE

CONTROL

CLK

ADC STAGE

CONTROL

LOGIC

SHDN

FIFTH PIPELINED

ADC STAGE

OEMODE

SIXTH PIPELINED

ADC STAGE

SHIFT REGISTER

AND CORRECTION

OUTPUT DRIVERS

OGND

2280 F01

•

1µF1µF

Figure 1. Functional Block Diagram (Only One Channel is Shown)

2280fa

LTC2280

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WUW

TI I G DIAGRA S

ANALOG

INPUT

CLK

D0-D9, OF

ANALOG INPUT A

ANALOG INPUT B

Dual Digital Output Bus Timing

(Only One Channel is Shown)

N + 2

N + 1

N – 5 N

N – 4 N – 3 N – 2 N – 1

N + 3

N + 4

N + 5

Multiplexed Digital Output Bus Timing

APA

APB

A + 1

B + 1

A + 2

A + 3

B + 2

B + 3

A + 4

B + 4

2280 TD01

CLKA = CLKB = MUX

D0A-D9A, OFA

D0B-D9B, OFB

A – 5

B – 5

A – 5

A – 4

B – 4

A – 4

A – 3

B – 3

A – 3

A – 2

B – 2

A – 2

A – 1

B – 1

2280 TD02

2280fa

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APPLICATIO S I FOR ATIO

LTC2280

DYNAMIC PERFORMANCE

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC.

Total Harmonic Distortion

Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:

2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.

Input Bandwidth

The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal.

Aperture Delay Time

The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)

where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth.

Intermodulation Distortion

If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.

If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb,

The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be:

SNR

Crosstalk

Crosstalk is the coupling from one channel (being driven by a full-scale signal) onto the other channel (being driven by a –1dBFS signal).

CONVERTER OPERATION

As shown in Figure 1, the LTC2280 is a dual CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive

= –20log (2π • fIN • t

JITTER

)

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applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2280 has two phases of operation, determined by the state of the CLK input pin.

Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa.

When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the

third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation.

Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2280 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C

SAMPLE

) through NMOS transistors. The capacitors shown attached to each input (C

PARASITIC

) are the summation of all other capaci-

tance associated with each input.

During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from

LTC2280

15Ω

CLK

15Ω

–

Figure 2. Equivalent Input Circuit

PARASITIC

1pF

PARASITIC

1pF

SAMPLE

4pF

SAMPLE

4pF

2280 F02

2280fa

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LTC2280

high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen.

Single-Ended Input

For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, A should be driven with the input signal and A

–

should be

connected to 1.5V or VCM.

Common Mode Bias

For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor.

Input Drive Impedance

As with all high performance, high speed ADCs, the dynamic performance of the LTC2280 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2F

ENCODE

); however, this is

not always possible and the incomplete settling may

degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.

For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2280 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz.

2.2µF

0.1µFT1

ANALOG

INPUT

Figure 3. Single-Ended to Differential Conversion Using a Transformer

1:1

T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1µF

25Ω

12pF

LTC2280

–

2280 F03

Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies.

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2.2µF

12pF

LTC2280

–

2280 F04

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

–

25Ω

Figure 4. Differential Drive with an Amplifier

Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required.

2.2µF

12pF

LTC2280

–

2280 F05

ANALOG

INPUT

0.1µF

25Ω

0.1µF

2.2µF

ANALOG

0.1µF

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

12Ω

0.1µF

8pF

Figure 6. Recommended Front End Circuit for Input Frequencies Between 70MHz and 170MHz

2.2µF

ANALOG

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

25Ω

0.1µF

Figure 7. Recommended Front End Circuit for Input Frequencies Between 170MHz and 300MHz

–

LTC2280

2280 F06

LTC2280

2280 F07

Figure 5. Single-Ended Drive

The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input.

For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth.

ANALOG

0.1µF

INPUT

0.1µF

T1 = MA/COM, ETC 1-1-13 RESISTORS, CAPACITORS, INDUCTORS ARE 0402 PACKAGE SIZE

25Ω

6.8nH

0.1µF

6.8nH

Figure 8. Recommended Front End Circuit for Input Frequencies Above 300MHz

2.2µF

LTC2280

–

2280 F08

2280fa

SENSE

1.5V

0.75V

2.2µF

12k

1µF

12k

2280 F10

LTC2280

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LTC2280

Reference Operation

Figure 9 shows the LTC2280 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range.

The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry.

LTC2280

4Ω

1.5V

2.2µF

1.5V BANDGAP REFERENCE

0.5V

The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Each ADC channel has an independent reference with its own bypass capacitors. The two channels can be used with the same or different input ranges.

Other voltage ranges between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. For the best channel matching, connect an external reference to SENSEA and SENSEB.

RANGE

DETECT

AND

REFH

REFL

CONTROL

INTERNAL ADC HIGH REFERENCE

DIFF AMP

INTERNAL ADC LOW REFERENCE

BUFFER

2280 F09

TIE TO V TIE TO V

RANGE = 2 • V

0.5V < V

FOR 2V RANGE;

FOR 1V RANGE;

SENSE

1µF

2.2µF

1µF

FOR

< 1V

SENSE

0.1µF

Figure 9. Equivalent Reference Circuit

Figure 10. 1.5V Range ADC

Input Range

The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 0.7dB. See the Typical Performance Characteristics section.

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or TTL level signal. A sinusoidal clock can also be used along with a low jitter squaring circuit before the CLK pin (Figure 11).

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CLEAN

FERRITE

BEAD

0.1µF

CLK

SUPPLY

LTC2280

2280 F11

4.7µF

NC7SVU04

SINUSOIDAL

CLOCK

INPUT

Figure 11. Sinusoidal Single-Ended CLK Drive

0.1µF

50Ω

The noise performance of the LTC2280 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.

In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source.

It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting a differential clock to the single-ended CLK input. The use of a transformer provides no incremental contribution to phase noise. The LVDS or PECL to CMOS translators provide little degradation below 70MHz, but at 140MHz will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact.

CLEAN

FERRITE

BEAD

0.1µF

CLK

0.1µF

SUPPLY

LTC2280

CLK

FERRITE

BEAD

2280 F12

LTC2280

2280 F13

4.7µF

100Ω

IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

ETC1-1T

DIFFERENTIAL

CLOCK

INPUT

Figure 13. LVDS or PECL CLK Drive Using a Transformer

5pF-30pF

The transformer shown in the example may be terminated with the appropriate termination for the signaling in use. The use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. The center tap may be bypassed to ground through a capacitor close to the ADC if the differential signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10Ω to 20Ω ohm series resistor to act as both a low pass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2280 is 105Msps. The lower limit of the LTC2280 sample rate is determined by droop of the sample-and-hold circuits. The pipelined

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architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2280 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. Using the clock duty cycle stabilizer is recommended for most applications. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors.

This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock.

For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±5%) duty cycle.

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors.

As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2280 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry.

LTC2280

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

2280 F14

OGND

0.5V TO 3.6V

0.1µF

TYPICAL DATA OUTPUT

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.

Table 1. Output Codes vs Input Voltage

A (2V Range) OF (Offset Binary) (2’s Complement)

>+1.000000V 1 11 1111 1111 01 1111 1111

+0.998047V 0 11 1111 1111 01 1111 1111 +0.996094V 0 11 1111 1110 01 1111 1110

+0.001953V 0 10 0000 0001 00 0000 0001

0.000000V 0 10 0000 0000 00 0000 0000 –0.001953V 0 01 1111 1111 11 1111 1111 –0.003906V 0 01 1111 1110 11 1111 1110

–0.998047V 0 00 0000 0001 10 0000 0001 –1.000000V 0 00 0000 0000 10 0000 0000

<–1.000000V 1 00 0000 0000 10 0000 0000

–

– A

D9 – D0 D9 – D0

Figure 14. Digital Output Buffer

For full speed operation the capacitive load should be kept under 10pF.

Lower OVDD voltages will also help reduce interference from the digital outputs.

Data Format

Using the MODE pin, the LTC2280 parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin.

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Table 2. MODE Pin Function

Clock Duty

MODE Pin Output Format Cycle Stabilizer

0 Offset Binary Off

1/3V

2/3V

Overflow Bit

When OF outputs a logic high the converter is either overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example, if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. Channels A and B have independent output enable pins (OEA, OEB).

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to V results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have

Offset Binary On

2’s Complement On

2’s Complement Off

to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 30mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap modes, all digital outputs are disabled and enter the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA, SHDNB). Channel A is controlled by SHDNA and OEA, and Channel B is controlled by SHDNB and OEB. The nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2280 can be multiplexed onto a single data bus if the sample rate is 80Msps or less. The MUX pin is a digital input that swaps the two data busses. If MUX is High, Channel A comes out on DA0-DA9, OFA; Channel B comes out on DB0-DB9, OFB. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB9, OFB; Channel B comes out on DA0-DA9, OFA. To multiplex both channels onto a single output bus, connect MUX, CLKA and CLKB together (see the Timing Diagram for the multiplexed mode). The multiplexed data is available on either data bus—the unused data bus can be disabled with its OE pin.

Grounding and Bypassing

The LTC2280 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402

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ceramic capacitor is recommended. The large 2.2µF ca- pacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.

The LTC2280 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.

Heat Transfer

Most of the heat generated by the LTC2280 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area.

Clock Sources for Undersampling

Undersampling raises the bar on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.

In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a 3V canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.

The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If you are sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the source to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply.

For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs.

The differential pairs must be close together, and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.

2280fa

LTC2280

C21

0.1µF

C27

0.1µF

CMB

C20

2.2µF

C18 1µF

C23 1µF

C34

0.1µF

C31

C17

0.1µF

C14

0.1µF

C25

0.1µF

C28

2.2µF

C35

0.1µF

C24

0.1µF

C36

4.7µF

PWR

GND

2280 AI01

0.1µF

R16

33Ω

R32

OPT

R39

OPT

R10

R14

49.9Ω

R20

24.9Ω

R18

R24

R17

OPT

R22

24.9Ω

R23

C29

0.1µF

C33

0.1µF

CLOCK

INPUT

NC7SVU04

NC7SV86P5X

C22

0.1µF

C15

0.1µF

C12

4.7µF

6.3V

BEAD

C19

0.1µF

C11

0.1µF

2.2µF

C10

2.2µF

C9 1µF

C13 1µF

R15

ANALOG

INPUT B

••

CMB

0.1µF

C44

0.1µF

24.9Ω

OPT

24.9Ω

0.1µF

ANALOG

INPUT A

••

CMA

2/3V

1/3V

GND

JP1 MODE

R34

4.7k

N1A

33Ω

N1B

33Ω

N1C

33Ω

N1D

33Ω

N2A

33Ω

N2B

33Ω

N2C

33Ω

N2D

33Ω

N3A

33Ω

N3B

33Ω

N3C

33Ω

N3D

33Ω

N4A

33Ω

N4B

33Ω

N4C

33Ω

N5A

33Ω

N5B

33Ω

N5C

33Ω

N5D

33Ω

N6A

33Ω

N6B

33Ω

N6C

33Ω

N6D

33Ω

C39

1µF

C38

0.01µF

BYP

GND

ADJ

OUT

SHDN

GND

LT1763

GND

R26

100k

R25

105k

C37

10µF

6.3V

C46

0.1µF

GND

C45

100µF

6.3V

OPT

C40

0.1µF

C48

0.1µF

C47

0.1µF

EXT

REF B

CMB

EXT REF

JP3 SENSE

EXT

REF A

EXT REF

JP2 SENSEA

0.1µF

74VCX245BQX

T/R

GND

74VCX245BQX

T/R

GND

24LC025

SCL

SDA

74VCX245BQX

T/R

GND

74VCX245BQX

T/R

GND

U10

U11

N7A

33Ω

N7B

33Ω

N7C

33Ω

N7D

33Ω

N8A

33Ω

N8B

33Ω

100

SCL

SDA

R33

4.7k

ENABLE

CCIN

EDGE-CON-100

R35

100k

C41

0.1µF

R38

R37

4.99k

R36

4.99k

CCIN

SCL

SDA

INA

–

REFHA

REFLA

CLKA CLKB

REFLB

REFHB

INB

–

INB

DA3

DA2

DA1

DA0

OFB

DB9

DB8

DB7

DB6

DB5

DB4

DB3

GND

SENSEA

VCMA

MODE

SHDNA

OEA

OFA

DA9

DA8

DA7

DA6

DA5

DA4

OGND

GND

SENSEB

VCMB

MUX

SHDNB

OEB

DB0

DB1

DB2

OGND

LTC2280

ASSEMBLY TYPE

DC851A-W

DC851A-Y

LTC2280IUP

R5, R9, R18, R24

24.9Ω

12.4Ω

C6, C31

12pF

8pF

T1, T2

ETC1-1T

ETC1-1-13

INPUT FREQUENCY

< 70MHz

> 70MHz

*VERSION TABLE

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APPLICATIO S I FOR ATIO

WUU

2280fa

LTC2280

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WUU

APPLICATIO S I FOR ATIO

Silkscreen Top

Top Side

2280fa

LTC2280

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WUU

APPLICATIO S I FOR ATIO

Inner Layer 2 GND

Inner Layer 3 Power

Bottom Side

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PACKAGE DESCRIPTIO

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LTC2280

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

9 .00 ± 0.10

(4 SIDES)

PIN 1 TOP MARK (SEE NOTE 5)

7.15 ±0.05 (4 SIDES)

8.10 ±0.05 9.50 ±0.05

PACKAGE OUTLINE

0.75 ± 0.05

7.15 ± 0.10 (4-SIDES)

R = 0.115

TYP

PIN 1

CHAMFER

6463

0.40 ± 0.10

1 2

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

0.200 REF

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

0.25 ± 0.05

0.50 BSC

(UP64) QFN 1003

2280fa

LTC2280

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RELATED PARTS

PART NUMBER DESCRIPTION COMMENTS

LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2221 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2222 12-Bit, 105Msps ADC 475mW, 67.9dB SNR, 7mm × 7mm QFN Package

LTC2223 12-Bit, 80Msps ADC 366mW, 68dB SNR, 7mm × 7mm QFN Package

LTC2224 12-Bit, 135Msps ADC 630mW, 67.5dB SNR, 7mm × 7mm QFN Package

LTC2225 12-Bit, 10Msps ADC 60mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2226 12-Bit, 25Msps ADC 75mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2227 12-Bit, 40Msps ADC 120mW, 71.4dB SNR, 5mm × 5mm QFN Package

LTC2228 12-Bit, 65Msps ADC 205mW, 71.3dB SNR, 5mm × 5mm QFN Package

LTC2230 10-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2231 10-Bit, 135Msps ADC 630mW, 67.5dB SNR, 9mm × 9mm QFN Package

LTC2232 10-Bit, 105Msps ADC 475mW, 61.3dB SNR, 7mm × 7mm QFN Package

LTC2233 10-Bit, 80Msps ADC 366mW, 61.3dB SNR, 7mm × 7mm QFN Package

LTC2245 14-Bit, 10Msps ADC 60mW, 74.4dB SNR, 5mm × 5mm QFN Package

LTC2246 14-Bit, 25Msps ADC 75mW, 74.5dB SNR, 5mm × 5mm QFN Package

LTC2247 14-Bit, 40Msps ADC 120mW, 74.4dB SNR, 5mm × 5mm QFN Package

LTC2248 14-Bit, 65Msps ADC 205mW, 74.3dB SNR, 5mm × 5mm QFN Package

LTC2249 14-Bit, 80Msps ADC 222mW, 73dB SNR, 5mm × 5mm QFN Package

LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package

LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package

LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package

LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm × 5mm QFN Package

LTC2282 12-Bit, Dual, 105Msps ADC 540mW, 70.1dB SNR, 9mm × 9mm QFN Package

LTC2284 14-Bit, Dual, 105Msps ADC 540mW, 72.4dB SNR, 9mm × 9mm QFN Package

LTC2286 10-Bit, Dual, 25Msps ADC 150mW, 61.8dB SNR, 9mm × 9mm QFN Package

LTC2287 10-Bit, Dual, 40Msps ADC 235mW, 61.8dB SNR, 9mm × 9mm QFN Package

LTC2288 10-Bit, Dual, 65Msps ADC 400mW, 61.8dB SNR, 9mm × 9mm QFN Package

LTC2289 10-Bit, Dual, 80Msps ADC 422mW, 61dB SNR, 9mm × 9mm QFN Package

LTC2290 12-Bit, Dual, 10Msps ADC 120mW, 71.3dB SNR, 9mm × 9mm QFN Package

LTC2291 12-Bit, Dual, 25Msps ADC 150mW, 71.4dB SNR, 9mm × 9mm QFN Package

LTC2292 12-Bit, Dual, 40Msps ADC 235mW, 71.4dB SNR, 9mm × 9mm QFN Package

LTC2293 12-Bit, Dual, 65Msps ADC 400mW, 71.3dB SNR, 9mm × 9mm QFN Package

LTC2294 12-Bit, Dual, 80Msps ADC 422mW, 70.6dB SNR, 9mm × 9mm QFN Package

LTC2295 14-Bit, Dual, 10Msps ADC 120mW, 74.4dB SNR, 9mm × 9mm QFN Package

LTC2296 14-Bit, Dual, 25Msps ADC 150mW, 74.5dB SNR, 9mm × 9mm QFN Package

LTC2297 14-Bit, Dual, 40Msps ADC 235mW, 74.4dB SNR, 9mm × 9mm QFN Package

LTC2298 14-Bit, Dual, 65Msps ADC 400mW, 74.3dB SNR, 9mm × 9mm QFN Package

LTC2299 14-Bit, Dual, 80Msps ADC 444mW, 73dB SNR, 9mm × 9mm QFN Package

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507

●

www.linear.com

2280fa

LT 0406 • PRINTED IN USA

Datasheet LTC2280 Datasheet (LINEAR TECHNOLOGY)

Specifications and Main Features

Frequently Asked Questions

User Manual