LINEAR TECHNOLOGY LTC2280 Technical data

FEATURES

www.BDTIC.com/LINEAR

■

Integrated Dual 10-Bit ADCs

■

Sample Rate: 105Msps

■

Single 3V Supply (2.85V to 3.4V)

■

Low Power: 540mW

■

61.6dB SNR, 85dB SFDR

■

110dB Channel Isolation at 100MHz

■

Flexible Input: 1V

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

■

Shutdown and Nap Modes

■

Pin Compatible Family

P-P

to 2V

P-P

Range

105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit)
80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)
65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)
40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)
25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit)
10Msps: LTC2290 (12-Bit)

■

64-Pin (9mm × 9mm) QFN Package

U

APPLICATIO S

LTC2280

Dual 10-Bit, 105Msps

Low Noise 3V ADC

U

DESCRIPTIO

The LTC®2280 is a 10-bit 105Msps, low noise 3V dual
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2280 is perfect for
demanding imaging and communications applications
with AC performance that includes 61.6dB SNR and 85dB
SFDR for signals at the Nyquist frequency.

DC specs include ±0.1LSB INL (typ), ±0.1LSB DNL (typ)
and ±0.6LSB INL, ±0.6LSB DNL over temperature. The
transition noise is a low 0.08LSB

A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.

A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor­mance at full speed for a wide range of clock duty cycles.

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

RMS

.

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Spectral Analysis

■

Portable Instrumentation

U

TYPICAL APPLICATIO

ANALOG
INPUT A

CLK A

CLK B

ANALOG
INPUT B

+

INPUT

S/H

–

CLOCK/DUTY CYCLE

CONTROL

CLOCK/DUTY CYCLE

CONTROL

+

INPUT

S/H

–

10-BIT
PIPELINED
ADC CORE

10-BIT
PIPELINED
ADC CORE

OUTPUT

DRIVERS

OUTPUT

DRIVERS

2280 TA01

OV

D9A

•

•

•

D0A

OGND

MUX

OV

D9B

•

•

•

D0B

OGND

SNR vs Input Frequency,

DD

SNR (dBFS)

DD

65

64

63

62

61

60

59

58

57

56

55

0

–1dB, 2V Range

100

50

INPUT FREQUENCY (MHz)

150

200

2280 TA02

2280fa

1

LTC2280

www.BDTIC.com/LINEAR

WW

W

U

ABSOLUTE AXI U RATI GS

OVDD = VDD (Notes 1, 2)

Supply Voltage (VDD) ................................................. 4V

Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V

Digital Input Voltage .................... –0.3V to (V

Digital Output Voltage ................ –0.3V to (OV

Power Dissipation............................................ 1500mW

Operating Temperature Range

LTC2280C ............................................... 0°C to 70°C

LTC2280I.............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

+ 0.3V)

DD

+ 0.3V)

DD

+ 0.3V)

DD

UUW

PACKAGE/ORDER I FOR ATIO

TOP VIEW

DD

64 GND

63 VDD62 SENSEA

61 VCMA

60 MODE

59 SHDNA

58 OEA

57 OFA

56 DA9

55 DA8

54 DA7

53 DA6

52 DA5

51 DA4

50 OGND

49 OV

1

A

INA+

–

2

A

INA

REFHA 3
REFHA 4
REFLA 5
REFLA 6

7

V

DD

8

CLKA
CLKB 9

10

V

DD

REFLB 11
REFLB 12
REFHB 13
REFHB 14

–

15

A

INB

+

16

A

INB

19

17

18

DD

V

GND

SENSEB

64-LEAD (9mm × 9mm) PLASTIC QFN

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

T

65

20

NC 24

OEB 23

MUX 21

VCMB

SHDNB 22

UP PACKAGE

= 125°C, θJA = 20°C/W

JMAX

NC 25

NC 26

NC 27

DB0 28

ORDER PART

NUMBER

DB1 29

QFN PART*

48 DA3
47 DA2
46 DA1
45 DA0
44 NC
43 NC
42 NC
41 NC
40 OFB
39 DB9
38 DB8
37 DB7
36 DB6
35 DB5
34 DB4
33 DB3

32

DD

DB2 30

OV

OGND 31

MARKING

LTC2280CUP

LTC2280UP

LTC2280IUP

Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.

U

CO VERTER CHARACTERISTICS

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution (No Missing Codes) ● 10 Bits

Integral Linearity Error Differential Analog Input (Note 5) ● –0.6 ±0.1 0.6 LSB

Differential Linearity Error Differential Analog Input ● –0.6 ±0.1 0.6 LSB

Offset Error (Note 6) ● –12 ±212 mV

Gain Error External Reference ● –2.5 ±0.5 2.5 %FS

Offset Drift ±10 µV/°C

Full-Scale Drift Internal Reference ±30 ppm/°C

External Reference ±5 ppm/°C

Gain Matching External Reference ±0.3 %FS

Offset Matching ±2mV

Transition Noise SENSE = 1V 0.08 LSB

The ● denotes the specifications which apply over the full operating

RMS

2

2280fa

LTC2280

www.BDTIC.com/LINEAR

UU

A ALOG I PUT

specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

IN

V

IN,CM

I

IN

I

SENSE

I

MODE

t

AP

t

JITTER

CMRR Analog Input Common Mode Rejection Ratio 80 dB

U

Analog Input Range (A

Analog Input Common Mode (A

Analog Input Leakage Current 0V < A

SENSEA, SENSEB Input Leakage 0V < SENSEA, SENSEB < 1V ● –3 3 µA

MODE Input Leakage Current 0V < MODE < V

Sample-and-Hold Acquisition Delay Time 0 ns

Sample-and-Hold Acquisition Delay Time Jitter 0.2 ps

Full Power Bandwidth Figure 8 Test Circuit 575 MHz

W

DY A IC ACCURACY

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SNR Signal-to-Noise Ratio 5MHz Input 61.6 dB

SFDR Spurious Free Dynamic Range 5MHz Input 85 dB

2nd or 3rd Harmonic

SFDR Spurious Free Dynamic Range 5MHz Input 85 dB

4th Harmonic or Higher

S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 61.6 dB

I

MD

Intermodulation Distortion fIN = 40MHz, 41MHz 85 dB

Crosstalk fIN = 100MHz –110 dB

The ● denotes the specifications which apply over the full operating temperature range, otherwise

+

–

–A

IN

) 2.85V < V

IN

+

–

+A

)/2 Differential Input Drive (Note 7) ● 1 1.5 1.9 V

IN

IN

Single Ended Input Drive (Note 7)

< 3.4V (Note 7) ● ±0.5V to ±1V V

DD

● 0.5 1.5 2 V

+

–

, A

< V

IN

IN

DD

DD

● –1 1 µA

● –3 3 µA

RMS

The ● denotes the specifications which apply over the full operating temperature range,

30MHz Input 61.6 dB

70MHz Input ● 60 61.5 dB

140MHz Input 61.4 dB

30MHz Input 85 dB

70MHz Input ● 70 83 dB

140MHz Input 77 dB

30MHz Input 85 dB

70MHz Input ● 76 85 dB

140MHz Input 85 dB

30MHz Input 61.6 dB

70MHz Input ● 60 61.5 dB

140MHz Input 61.3 dB

2280fa

3

LTC2280

www.BDTIC.com/LINEAR

UU U

I TER AL REFERE CE CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage I

VCM Output Tempco ±25 ppm/°C

VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V

VCM Output Resistance –1mA < I

= 0 1.475 1.500 1.525 V

OUT

(Note 4)

< 1mA 4 Ω

OUT

UU

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (CLK, OE, SHDN, MUX)

V

IH

V

IL

I

IN

C

IN

LOGIC OUTPUTS

OVDD = 3V

C

OZ

I

SOURCE

I

SINK

V

OH

V

OL

OV

= 2.5V

DD

V

OH

V

OL

OVDD = 1.8V

V

OH

V

OL

High Level Input Voltage VDD = 3V ● 2V

Low Level Input Voltage VDD = 3V ● 0.8 V

Input Current VIN = 0V to V

Input Capacitance (Note 7) 3 pF

Hi-Z Output Capacitance OE = High (Note 7) 3 pF

Output Source Current V

Output Sink Current V

High Level Output Voltage IO = –10µA 2.995 V

Low Level Output Voltage IO = 10µA 0.005 V

High Level Output Voltage IO = –200µA 2.49 V

Low Level Output Voltage IO = 1.6mA 0.09 V

High Level Output Voltage IO = –200µA 1.79 V

Low Level Output Voltage IO = 1.6mA 0.09 V

= 25°C. (Note 4)

A

= 0V 50 mA

OUT

= 3V 50 mA

OUT

= –200µA ● 2.7 2.99 V

I

O

I

= 1.6mA ● 0.09 0.4 V

O

The ● denotes the specifications which apply over the

DD

● –10 10 µA

4

2280fa

LTC2280

www.BDTIC.com/LINEAR

WU

POWER REQUIRE E TS

range, otherwise specifications are at T

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V

DD

OV

IV

P

DISS

P

SHDN

P

NAP

DD

DD

Analog Supply Voltage (Note 9) ● 2.85 3 3.4 V

Output Supply Voltage (Note 9) ● 0.5 3 3.6 V

Supply Current Both ADCs at f

Power Dissipation Both ADCs at f

Shutdown Power (Each Channel) SHDN = H, OE = H, No CLK 2 mW

Nap Mode Power (Each Channel) SHDN = H, OE = L, No CLK 15 mW

= 25°C. (Note 8)

A

The ● denotes the specifications which apply over the full operating temperature

S(MAX)

S(MAX)

● 180 210 mA

● 540 630 mW

UW

TI I G CHARACTERISTICS

range, otherwise specifications are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

f

s

t

L

t

H

t

AP

t

D

t

MD

Pipeline Latency 5 Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.

Note 4: V
drive, unless otherwise noted.

DD

Sampling Frequency (Note 9) ● 1 105 MHz

CLK Low Time Duty Cycle Stabilizer Off (Note 7) ● 4.5 4.76 500 ns

CLK High Time Duty Cycle Stabilizer Off (Note 7) ● 4.5 4.76 500 ns

Sample-and-Hold Aperture Delay 0 ns

CLK to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns

MUX to DATA Delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns
Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns

BUS Relinquish Time (Note 7) ● 3.3 8.5 ns

= 3V, f

= 105MHz, input range = 2V

SAMPLE

The ● denotes the specifications which apply over the full operating temperature

● 3 4.76 500 ns

● 3 4.76 500 ns

= 105MHz, input range = 1V

P-P

with differential

DD

with differential

P-P

Duty Cycle Stabilizer On (Note 7)

Duty Cycle Stabilizer On (Note 7)

Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 and 11 1111 1111.

Note 7: Guaranteed by design, not subject to test.

, they

Note 8: V
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.

Note 9: Recommended operating conditions.

= 3V, f

DD

SAMPLE

2280fa

5

LTC2280

CODE

70000

60000

50000

40000

30000

20000

10000

0

511

65528

512

2280 G09

510

0

0

COUNT

www.BDTIC.com/LINEAR

UW

TYPICAL PERFOR A CE CHARACTERISTICS

Crosstalk vs Input Frequency

–100

–105

–110

–115

CROSSTALK (dB)

–120

–125

–130

0

20 40 60 80

INPUT FREQUENCY (MHz)

8192 Point FFT, f

= 5MHz, –1dB,

IN

2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

2280 G01

2280 G04

100

Typical INL, 2V Range, 105Msps Typical DNL, 2V Range, 105Msps

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

256 512 1024

0

CODE

768

8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

2280 G02

2280 G05

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

256 512 1024

0

CODE

8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

768

2280 G03

2280 G06

8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, 105Msps

0

–10

–20

–30

–40

–50

–60

–70

AMPLITUDE (dB)

–80

–90

–100

–110

–120

0 1020304050

FREQUENCY (MHz)

6

2280 G07

Grounded Input Histogram,
105Msps

2280 G08

2280fa

UW

www.BDTIC.com/LINEAR

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2280

SNR vs Input Frequency, –1dB,
2V Range, 105Msps

65

64

63

62

61

60

59

SNR (dBFS)

58

57

56

55

0

100

50

INPUT FREQUENCY (MHz)

150

200

SNR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps

80

70

60

50

40

30

SNR (dBc AND dBFS)

20

10

0

–40 –30

–50

dBFS

dBc

–20

INPUT LEVEL (dBFS)

250

–10

300

2280 G10

2280 G13

350

SFDR (dBFS)

0

SFDR vs Input Frequency, –1dB,
2V Range, 105Msps

95

90

85

80

75

70

65

0

50 100

INPUT FREQUENCY (MHz)

200 300 350

150 250

SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps

100

90

80

70

60

50

40

30

SFDR (dBc AND dBFS)

20

10

0

–40

–50

dBFS

dBc

–20

–30

INPUT LEVEL (dBFS)

–10

2280 G11

2280 G14

SNR and SFDR vs Sample Rate,
2V Range, f

90

80

70

SNR AND SFDR (dBFS)

60

50

0

20 40 60 80

I

vs Sample Rate,

VDD

= 5MHz, –1dB

IN

SFDR

SNR

SAMPLE RATE (Msps)

100 120 140

2280 G12

5MHz Sine Wave Input, –1dB

200

190

180

170

160

(mA)

DD

150

IV

140

130

120

0

110

0

2V RANGE

40

20

SAMPLE RATE (Msps)

1V RANGE

60 120

80

100

2280 G15

I

vs Sample Rate, 5MHz Sine

OVDD

Wave Input, –1dB, OVDD = 1.8V

17.5

15.0

12.5

10.0

(mA)

7.5

OVDD

I

5.0

2.5

0

0

20 40

SAMPLE RATE (Msps)

80 120

60 100

2280 G16

SNR vs SENSE, fIN = 5MHz, –1dB

61.8

61.6

61.4

61.2

61.0

SNR (dBFS)

60.8

60.6

60.4

60.2

0.5 0.6 0.8

0.4

0.7

SENSE PIN (V)

0.9 1 1.1

2280 G17

2280fa

7

LTC2280

www.BDTIC.com/LINEAR

U

UU

PI FU CTIO S

+

A

(Pin 1): Channel A Positive Differential Analog

INA

Input.

–

A

(Pin 2): Channel A Negative Differential Analog

INA

Input.

REFHA (Pins 3, 4): Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.

REFLA (Pins 5, 6): Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1µF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2µF ceramic chip capacitor
and to ground with a 1µF ceramic chip capacitor.

VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input
range of ±V

V

(Pin 20): Channel B 1.5V Output and Input Common

CMB

Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V

MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA9, OFA; Channel B
comes out on DB0-DB9, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0­DB9, OFB; Channel B comes out on DA0-DA9, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together. (This is not recommended
at clock frequencies above 80Msps.)

SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to V
and OEB to VDD results in sleep mode with the outputs at
high impedance.

OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.

NC (Pins 24 to 27, 41 to 44): Do Not Connect These Pins.

. ±1V is the largest valid input range.

SENSEB

.

CMA

results in normal opera-

DD

DD

REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1µF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2µF ceramic chip ca-
pacitor and to ground with a 1µF ceramic chip capacitor.

–

A

(Pin 15): Channel B Negative Differential Analog

INB

Input.

+

A

(Pin 16): Channel B Positive Differential Analog

INB

Input.

GND (Pins 17, 64): ADC Power Ground.

SENSEB (Pin 19): Channel B Reference Programming Pin.

Connecting SENSEB to V
and a ±0.5V input range. VDD selects the internal reference

selects the internal reference

CMB

8

DB0 – DB9 (Pins 28 to 30, 33 to 39): Channel B Digital
Outputs. DB9 is the MSB.

OGND (Pins 31, 50): Output Driver Ground.

OVDD (Pins 32, 49): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.

DA0 – DA9 (Pins 45 to 48, 51 to 56): Channel A Digital
Outputs. DA9 is the MSB.

OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.

OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.

2280fa