LINEAR TECHNOLOGY LTC2274 Technical data

DESIGN FEATURES L

FREQUENCY (MHz)

0

AMPLITUDE (dBFS)

10 20 30 40 50

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

79.4ps/DIV

100mV/DIV

UNIT INTERVAL (UI)

0

BIT ERROR RATE (BER)

0.80.4 1.00.60.2

1.0E–14

1.0E–12

1.0E–10

1.0E–08

1.0E–06

1.0E–04

1.0E–02

1.0E+00

Serial Interface for High Speed Data
Converters Simplifies Layout over
Traditional Parallel Devices

by Clarence Mayott

Introduction

The LTC2274 is a 105Msps, 16-bit
ADC that simplifies the digital connec­tion between the ADC and FPGA by
replacing the usual parallel interface
with a novel high speed serial interface,
thus reducing the typical number of
required data input/output (I/O) lines
from 16 CMOS or 32 LVDS parallel
data lines to a single, self-clocking,
differential pair communicating at

2.1Gbps. This frees up valuable FPGA
pins and board space. It also allows
flexibility to route across analog and
digital boundaries—in noise sensi­tive applications, the serial interface
provides an effective isolation barrier
between digital and analog circuitry
and serves to eliminate coupling be­tween the digital outputs and analog
inputs to reduce digital feedback.

Current Mode Logic and
8B/10B Encoding Allows
High Speed Serial Data
Transfer

The LTC2274 achieves excellent signal
to noise ratio (SNR) performance of

77.6dBFS and spurious free dynamic
range (SFDR) of 100dB at baseband,
as shown in Figure 1. The input topol­ogy of the LTC2274 family is based on
its predecessor, the LTC2207 family,

The LTC2274 ADC replaces

the usual parallel interface

with a novel high speed

serial interface, thus

reducing the typical number

of required data input/

output lines from 16 CMOS

or 32 LVDS to a single, self-

clocking, differential pair

communicating at 2.1Gbps.

and achieves similar AC performance.
However, the LTC2274 differs from the
LTC2207 in its output structure. The
LTC2274 uses an 8B/10B encoder to
encode and serialize the data before it
is transmitted. 8B/10B encoding is a
process that takes 8 bits of data and
encodes them into 10 bits to ensure
zero DC offset and a limited run length.
To encode a 16-bit word, the LTC2274
must transmit 20 bits of serial data.
This requires that the serial data must
be transmitted at 20 times the clock
frequency of the ADC. Sampling at
105Msps requires the LTC2274 to
transmit serial data at 2.1GHz. This
is beyond the usable range of LVDS
signaling, and therefore requires a
faster, more robust differential signal­ing scheme. The LTC2274’s differential

signaling uses current mode logic
(CML), which is capable of transmitting
data in excess of 10GHz.

Current mode logic uses a differ­ential output transistor pair (usually
N-type) to steer current into resistive
loads. The output swing and offset
depends on the bias current and
termination resistance. The output
driver bias current is typically 16mA,
generating a signal swing potential
of 400mV

(800mV

P–P

differential)

P–P

across the combined internal and
external termination resistance of 25Ω
on each output. LVDS typically uses

3.5mA to develop its signal swing, and
the capacitance of the ESD protection
diodes becomes a limiting factor for
transmission speed. CML uses more
current, and therefore this capacitance
becomes less of a limiting factor to
data throughput.

CML is typically faster than LVDS.
A typical LVDS output stage requires
four transistors to steer current into
the load, usually using both P-channel
and N-channel devices. A mixture of
N- and P-channel makes it difficult to
produce devices that have the same
characteristics. P-channel devices are
often slower—that is, if an N-channel

Figure 1. Typical LTC2274 performance
at 105Msps f

Linear Technology Magazine • September 2008

= 4.93MHz

IN

a. CMLOUT eye diagram 2.1GBps

Figure 2. Signal integrity of CMLOUT

b. CMLOUT Dual-Dirac BER
bathtub curve, 2.1GBps

13

L DESIGN FEATURES

50Ω50Ω50Ω 50Ω

DATA

+

DATA

–

GND

SERIAL CML DRIVER SERIAL CML RECEIVER

1.2V TO 3.3V

16mA

CMLOUT

+

OV

DD

CMLOUT

–

50Ω

TRANSMISSION LINE

50Ω

TRANSMISSION LINE

100Ω

50Ω 50Ω

DATA

+

DATA

–

GND

SERIAL CML DRIVER SERIAL CML RECEIVER

1.4V TO 3.3V

50Ω

TRANSMISSION LINE

50Ω

TRANSMISSION LINE

16mA

CMLOUT

+

OV

DD

CMLOUT

–

50Ω50Ω

0.01µF

0.01µF

50Ω 50Ω

DATA

+

DATA

–

GND

SERIAL CML DRIVER SERIAL CML RECEIVER

1.4V TO 3.3V VTERM

16mA

CMLOUT

+

OV

DD

CMLOUT

–

50Ω

TRANSMISSION LINE

50Ω

TRANSMISSION LINE

and a P-channel device are cascaded,
the P-channel cannot pull up the signal
as fast as the N-channel can pull down.
This causes the output waveform to be
distorted, which can lead to bit errors,
and limits the speed at which LVDS
can transfer data.

The LTC2274 CML driver is imple­mented with only N-channel devices,
which allows faster throughput rates.
Since CML only sinks current, it has
true differential signal, which improves
signal integrity. The eye diagram and
bathtub curves of the LTC2274 are
shown in Figure 2. The eye diagram
shows very little variation cycle to
cycle of the CML logic output, and the
bathtub curve shows that total jitter
in the signal is less than 0.35UI (unit
interval). This equates into a very clean
uniform signal that can easily received
by a properly terminated receiver.

a. Recommended CML termination, directly-coupled mode

Termination of CML

CML must be terminated for proper
operation. Figure 3a shows a recom­mended design in which an FPGA
receiver uses internal 50Ω pull up re-
sistors for termination. These resistors
pull up to the OV
OV

must be between 1.2V and 3.3V

DD

to ensure proper operation. The signal
has a common mode voltage of OV
– 0.2V. The directly-coupled differen­tial termination of Figure 3b may be
used in the absence of a receiver ter­mination voltage within the required
range. In this case, the common mode
voltage is shifted down to approxi­mately 400mV below OVDD, requiring
an OV

in the range of 1.4V to 3.3V.

DD

If the serial receiver’s common mode
input requirements are not compatible
with the directly-coupled termination
modes, the DC balanced 8B/10B
encoded data permits the addition of
DC blocking capacitors as shown in
Figure 3c. In this AC-coupled mode,
the termination voltage is determined
by the receiver’s requirements. The
coupling capacitors should be se­lected appropriately for the intended
operating bit-rate, usually between
1nF and 10nF. In AC coupled mode,
the output common mode voltage is
approximately 400mV below OVDD, so
the OV

14

supply voltage should be in

DD

of the LTC2274.

DD

DD

b. CML termination, directly-coupled differential mode

c. CML termination, AC-coupled mode

Figure 3. CML termination schemes

Linear Technology Magazine • September 2008