LTC2258-12
LTC2257-12/LTC2256-12
12-Bit, 65/40/25Msps
Ultralow Power 1.8V ADCs
FEATURES
n
71.1dB SNR
n
88dB SFDR
n
Low Power: 79mW/47mW/34mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS or DDR LVDS Outputs
n
Selectable Input Ranges: 1V
n
800MHz Full-Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Confi guration
n
Pin Compatible 14-Bit and 12-Bit Versions
n
40-Pin (6mm × 6mm) QFN Package
P-P
to 2V
P-P
APPLICATIONS
n
Communications
n
Cellular Base Stations
n
Software Defi ned Radios
n
Portable Medical Imaging
n
Multi-Channel Data Acquisition
n
Nondestructive Testing
DESCRIPTION
®
The LTC
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 71.1dB SNR and 88dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17ps
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL
(typical) and no missing codes over temperature. The
transition noise is a low 0.3LSB
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2258-12/LTC2257-12/LTC2256-12 are sam-
RMS
.
RMS
+
and ENC– inputs may be driven differentially
TYPICAL APPLICATION
ANALOG
INPUT
65MHz
CLOCK
+
INPUT
S/H
–
CLOCK/DUTY
CYCLE
CONTROL
12-BIT
PIPELINED
ADC CORE
1.8V
V
DD
GND
CORRECTION
LOGIC
OUTPUT
DRIVERS
225812 TA01a
1.2V
TO 1.8V
D11
•
•
•
D0
OV
DD
CMOS
OR
LVDS
OGND
LTC2258-12 2-Tone FFT,
fIN = 68MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
20 30
225812 TA01b
225812f
1
LTC2258-12
LTC2257-12/LTC2256-12
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages (VDD, OVDD) ....................... –0.3V to 2V
+
–
, A
Analog Input Voltage (A
IN
PAR/SER, SENSE) (Note 3) ...........–0.3V to (V
Digital Input Voltage (ENC
,
IN
+
, ENC–, CS,
+ 0.2V)
DD
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
PIN CONFIGURATIONS
FULL-RATE CMOS OUTPUT MODE
VDDSENSE
3940 38 37 36 35 34 33 32 31
+
A
1
IN
–
A
2
IN
GND
3
REFH
4
REFH
5
REFL
6
REFL
7
PAR/SER
8
9
V
DD
V
10
DD
12 13 14 15
11 20
+
ENC
40-LEAD (6mm × 6mm) PLASTIC QFN
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
REFVCM
V
–
CS
SCK
ENC
UJ PACKAGE
T
= 150°C, θJA = 32°C/W
JMAX
OF
DNC
D11
41
16 17 18 19
SDI
SDO
DNC
D10D9D8
D0
DNC
30
D7
29
D6
CLKOUT
CLKOUT
OV
DD
OGND
D5
D4
D3
D2
+
–
28
27
26
25
24
23
22
21
D1
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Operating Temperature Range:
LTC2258C, LTC2257C, LTC2256C............. 0°C to 70°C
LTC2258I, LTC2257I, LTC2256I ............ –40°C to 85°C
Storage Temperature Range ................... –65°C to 150°C
DOUBLE DATA RATE CMOS OUTPUT MODE
VDDSENSE
3940 38 37 36 35 34 33 32 31
+
A
1
IN
–
A
2
IN
GND
3
REFH
4
REFH
5
REFL
6
REFL
7
PAR/SER
8
9
V
DD
V
10
DD
12 13 14 15
11 20
+
ENC
40-LEAD (6mm × 6mm) PLASTIC QFN
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
REFVCM
V
–
CS
SCK
ENC
UJ PACKAGE
T
= 150°C, θJA = 32°C/W
JMAX
OF
DNC
D10_11
41
16 17 18 19
SDI
SDO
DNC
DNC
DNC
D8_9
DNC
DNC
30
29
28
27
26
25
24
23
22
21
D0_1
D6_7
DNC
CLKOUT
CLKOUT
OV
DD
OGND
D4_5
DNC
D2_3
DNC
+
–
2
DOUBLE DATA RATE LVDS OUTPUT MODE
VDDSENSE
+
A
1
IN
–
A
2
IN
GND
3
REFH
4
REFH
5
REFL
6
REFL
7
PAR/SER
8
9
V
DD
V
10
DD
11 20
ENC+ENC
40-LEAD (6mm × 6mm) PLASTIC QFN
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
TOP VIEW
REFVCM
V
3940 38 37 36 35 34 33 32 31
12 13 14 15
–
T
OF+OF–D10_11+D10_11–D8_9+D8_9
41
16 17 18 19
CS
SDI
SCK
SDO
UJ PACKAGE
= 150°C, θJA = 32°C/W
JMAX
DNC
DNC
–
D0_1
–
+
30
29
28
27
26
25
24
23
22
21
D0_1
D6_7
D6_7
CLKOUT
CLKOUT
OV
DD
OGND
D4_5
D4_5
D2_3
D2_3
+
–
+
–
+
–
+
–
225812f
LTC2258-12
LTC2257-12/LTC2256-12
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2258CUJ-12#PBF LTC2258CUJ-12#TRPBF LTC2258UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2258IUJ-12#PBF LTC2258IUJ-12#TRPBF LTC2258UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2257CUJ-12#PBF LTC2257CUJ-12#TRPBF LTC2257UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2257IUJ-12#PBF LTC2257IUJ-12#TRPBF LTC2257UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
LTC2256CUJ-12#PBF LTC2256CUJ-12#TRPBF LTC2256UJ-12 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C
LTC2256IUJ-12#PBF LTC2256IUJ-12#TRPBF LTC2256UJ-12 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to:
For more information on tape and reel specifi cations, go to:
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS
Resolution (No Missing Codes)
Integral Linearity Error Differential Analog Input (Note 6)
Differential Linearity Error Differential Analog Input
Offset Error (Note 7)
Gain Error Internal Reference
Offset Drift ±20 ±20 ±20 µV/°C
Full-Scale Drift Internal Reference
Transition Noise External Reference 0.32 0.32 0.32 LSB
External Reference
External Reference
http://www.linear.com/leadfree/
http://www.linear.com/tapeandreel/
LTC2261-12 LTC2260-12 LTC2259-12
l
12 12 12 Bits
l
–1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 LSB
l
–0.4 ±0.1 0.4 –0.4 ±0.1 0.4 –0.4 ±0.1 0.4 LSB
l
–9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV
l
±1.5
–1.5
±0.4 1.5 –1.5
±30
±10
±1.5
±0.4 1.5 –1.5
±30
±10
±1.5
±0.4 1.5
±30
±10
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
%FS
%FS
ppm/°C
ppm/°C
RMS
225812f
3
LTC2258-12
LTC2257-12/LTC2256-12
ANALOG INPUT
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR Analog Input Common Mode Rejection Ratio 80 dB
BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz
Analog Input Range (A
Analog Input Common Mode (A
External Voltage Reference Applied to SENSE External Reference Mode
Analog Input Common Mode Current Per Pin, 65Msps
Analog Input Leakage Current 0 < A
PAR/SER Input Leakage Current 0 < PAR/SER < V
SENSE Input Leakage Current 0.625V < SENSE < 1.3V
Sample-and-Hold Acquisition Delay Time 0 ns
Sample-and-Hold Acquisition Delay Jitter 0.17 ps
= 25°C. (Note 5)
A
+
– A
IN
IN
–
) 1.7V < VDD < 1.9V
+
–
+ A
IN
)/2 Differential Analog Input (Note 8)
IN
Per Pin, 40Msps
Per Pin, 25Msps
+
–
, A
< VDD, No Encode
IN
IN
DD
l
l
VCM – 100mV V
l
l
l
l
0.625 1.250 1.300 V
–1 1 µA
–3 3 µA
–6 6 µA
1 to 2 V
CM
VCM + 100mV V
81
50
31
P-P
µA
µA
µA
RMS
DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2258-12 LTC2257-12 LTC2256-12
SYMBOL PARAMETER CONDITIONS
SNR Signal-to-Noise Ratio 5MHz Input
30MHz
l
70MHz Input
140MHz Input
SFDR Spurious Free Dynamic Range
2nd or 3rd Harmonic
5MHz Input
30MHz
l
70MHz Input
140MHz Input
Spurious Free Dynamic Range
4th Harmonic or Higher
5MHz Input
30MHz
l
70MHz Input
140MHz Input
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
30MHz
l
70MHz Input
140MHz Input
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifi cations which apply over the
71.1
69
71
70.9
70.7
789090
90
84
839090
90
90
69.17171
70.9
70.3
69.6
799090
839090
68.9
70.8
70.7
70.6
70.4
90
84
90
90
70.7
70.6
70.6
70.2
69
799090
839090
68.3
70.5
70.5
70.1
69.9
90
84
90
84
70.5
70.4
70
69.5
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage I
V
CM
VCM Output Temperature Drift ±25 ppm/°C
Output Resistance –600µA < I
V
CM
Output Voltage I
V
REF
Output Temperature Drift ±25 ppm/°C
V
REF
Output Resistance –400µA < I
V
REF
V
Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V
REF
= 0 0.5 • VDD – 25mV 0.5 • V
OUT
< 1mA 4
OUT
= 0 1.225 1.250 1.275 V
OUT
< 1mA 7
OUT
DD
0.5 • VDD + 25mV V
225812f
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
DB
dB
4
LTC2258-12
LTC2257-12/LTC2256-12
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
+
–
, ENC
ENCODE INPUTS (ENC
Differential Encode Mode (ENC
V
ID
V
ICM
V
IN
R
IN
C
IN
Differential Input Voltage (Note 8)
Common Mode Input Voltage Internally Set
Input Voltage Range ENC+, ENC– to GND
Input Resistance (See Figure 10) 10 k
Input Capacitance (Note 8) 3.5 pF
Single-Ended Encode Mode (ENC
V
IH
V
IL
V
IN
R
IN
C
IN
High Level Input Voltage VDD = 1.8V
Low Level Input Voltage VDD = 1.8V
Input Voltage Range ENC+ to GND
Input Resistance (See Figure 11) 30 k
Input Capacitance (Note 8) 3.5 pF
DIGITAL INPUTS (CS, SDI, SCK)
V
IH
V
IL
I
IN
C
IN
High Level Input Voltage VDD = 1.8V
Low Level Input Voltage VDD = 1.8V
Input Current VIN = 0V to 3.6V
Input Capacitance (Note 8) 3 pF
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
R
OL
I
OH
C
OUT
Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200
Logic High Output Leakage Current SDO = 0V to 3.6V
Output Capacitance (Note 8) 4 pF
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
= 1.8V
OV
DD
V
V
OV
V
V
OV
V
V
OH
OL
OH
OL
OH
OL
High Level Output Voltage IO = –500µA
Low Level Output Voltage IO = 500µA
= 1.5V
DD
High Level Output Voltage IO = –500µA 1.488 V
Low Level Output Voltage IO = 500µA 0.010 V
= 1.2V
DD
High Level Output Voltage IO = –500µA 1.185 V
Low Level Output Voltage IO = 500µA 0.010 V
DIGITAL DATA OUTPUTS (LVDS MODE)
V
V
R
OD
OS
TERM
Differential Output Voltage 100 Differential Load, 3.5mA Mode
Common Mode Output Voltage 100 Differential Load, 3.5mA Mode
On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100
)
–
Not Tied to GND)
–
Tied to GND)
= 25°C. (Note 5)
A
Externally Set (Note 8)
100 Differential Load, 1.75mA Mode
100 Differential Load, 1.75mA Mode
l
0.2 V
1.2
l
1.1
l
0.2 3.6 V
l
1.2 V
l
l
l
l
l
l
l
l
l
0 3.6 V
1.3 V
–10 10 µA
–10 10 µA
1.750 1.790 V
0.010 0.050 V
247 350
175
l
1.125 1.250
1.375 V
1.250
1.6
0.6 V
0.6 V
454 mV
mV
V
V
V
225812f
5
LTC2258-12
LTC2257-12/LTC2256-12
POWER REQUIREMENTS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS
CMOS Output Modes: Full Data Rate and Double Data Rate
V
DD
OV
I
VDD
I
OVDD
P
DISS
LVDS Output Mode
V
DD
OV
I
VDD
I
OVDD
P
DISS
All Output Modes
P
SLEEP
P
NAP
P
DIFFCLK
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
DD
Analog Supply Current DC Input
Digital Supply Current Sine Wave Input, OVDD=1.2V 2.3 1.5 0.9 mA
Power Dissipation DC Input
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
DD
Analog Supply Current Sine Wave Input
Digital Supply Current
(0V
= 1.8V)
DD
Power Dissipation Sine Input, 1.75mA Mode
Sleep Mode Power 0.5 0.5 0.5 mW
Nap Mode Power 9 9 9 mW
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
= 25°C. (Note 9)
A
Sine Wave Input
Sine Wave Input, OV
DD
=1.2V
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
Sine Input, 3.5mA Mode
LTC2258-12 LTC2257-12 LTC2256-12
l
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
l
1.1 1.9 1.1 1.9 1.1 1.9 V
l
l
l
l
l
l
l
l
l
43.6
44.2
78.5
82.3
49 26.3
27.2
89 47.3
50.8
30 18.9
19.1
54 34
35.5
21 mA
38 mW
1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 1.9 1.7 1.9 1.7 1.9 V
48.1 54 30.6 35 22.7 26 mA
18.8
36.72140
120.4
152.6
135
170
18.8
36.72140
88.9
121.1
101
135
18.8
36.72140
74.7
106.985119
10 10 10 mW
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
mA
mW
mA
mA
mW
mW
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
LTC2258-12 LTC2257-12 LTC2256-12
SYMBOL PARAMETER CONDITIONS
f
S
t
L
Sampling Frequency (Note 10)
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
t
H
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
t
AP
Sample-and-Hold
l
1 65 1 40 1 25 MHz
l
7.3
7.69
500
l
11.88
2.0
7.69
500
l
7.3
7.69
500
l
2.0
7.69
11.88
500
2.00
2.00
12.5
12.5
12.5
12.5
500
500192.002020
500
500192.002020
000ns
Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
t
D
t
C
t
SKEW
ENC to Data Delay CL = 5pF (Note 8)
ENC to CLKOUT Delay CL = 5pF (Note 8)
DATA to CLKOUT Skew tD – tC (Note 8)
Pipeline Latency Full Data Rate Mode
Double Data Rate Mode
l
1.1 1.7 3.1 ns
l
l
1 1.4 2.6 ns
0 0.3 0.6 ns
5.0
5.5
500
500
500
500
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
ns
ns
ns
ns
Cycles
Cycles
225812f
6
LTC2258-12
LTC2257-12/LTC2256-12
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Data Outputs (LVDS Mode)
t
D
t
C
t
SKEW
SPI Port Timing (Note 8)
t
SCK
t
S
t
H
t
DS
t
DH
t
DO
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 5: V
40MHz (LTC2257), or 25MHz (LTC2256), LVDS outputs with internal
ENC to Data Delay CL = 5pF (Note 8)
ENC to CLKOUT Delay CL = 5pF (Note 8)
DATA to CLKOUT Skew tD – tC (Note 8)
Pipeline Latency 5.5 Cycles
SCK Period Write Mode
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
SDI Hold Time
SCK Falling to SDO Valid Readback Mode, C
= OVDD
DD
= 1.8V, f
= 65MHz (LTC2258),
SAMPLE
= 25°C. (Note 5)
A
Readback Mode, C
without latchup.
DD
DD
SDO
SDO
, they
DD
l
1.1 1.8 3.2 ns
l
l
l
= 20pF, R
= 20pF, R
PULLUP
PULLUP
= 2k
= 2k
l
l
l
l
l
l
termination disabled, differential ENC+/ENC– = 2V
range = 2V
with differential drive, unless otherwise noted.
P-P
1 1.5 2.7 ns
0 0.3 0.6 ns
40
250
5ns
5ns
5ns
5ns
125 ns
sine wave, input
P-P
Note 6: Integral nonlinearity is defi ned as the deviation of a code from a
best fi t straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code fl ickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: V
25MHz (LTC2256), ENC
input range = 2V
DD
= 1.8V, f
P-P
= 65MHz (LTC2258), 40MHz (LTC2257), or
SAMPLE
+
= single-ended 1.8V square wave, ENC– = 0V,
with differential drive, 5pF load on each digital output
unless otherwise noted.
Note 10: Recommended operating conditions.
ns
ns
TIMING DIAGRAMS
ANALOG
INPUT
–
ENC
+
ENC
D0-D11, OF
+
CLKOUT
–
CLKOUT
Full-Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
N
t
H
t
t
N + 1
t
L
D
N – 5 N – 4 N – 3 N – 2 N – 1
C
N + 2
N + 3
N + 4
225812 TD01
225812f
7
LTC2258-12
LTC2257-12/LTC2256-12
TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
t
AP
ANALOG
INPUT
ENC
ENC
D0_1
•
•
•
D10_11
–
+
N
t
H
t
L
t
D
D0
D10
N-5
N-5
D1
D11
N + 1
N-5D0N-4
D10
N-5
N-4
D1
D11
N-4
t
N-4
N + 2
D
D0
D10
N-3
N-3
D1
D11
N + 3
N-3
N-3
D0
D10
N-2
N-2
D1
D11
N + 4
N-2
N-2
CLKOUT
CLKOUT
ANALOG
INPUT
ENC
ENC
D0_1
D0_1
D10_11
D10_11
CLKOUT
CLKOUT
OF
+
–
OF
N-5
t
C
OF
N-4
t
C
OF
N-3
OF
N-2
225812 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs Are Differential and Have LVDS Levels
t
AP
N + 4
D1
N-2
D11
N-2
OF
N-3
225812 TD03
D1
D11
N-4
N-4
t
D
t
C
N + 2
D0
D10
N-3
N-3
N + 3
D1
D0
N-3
D11
OF
N-3
N-3
D10
N-2
N-2
N
t
H
–
+
t
D0
D10
N-5
N-5
t
D
C
+
–
•
•
•
+
–
+
OF
–
OF
+
–
OF
N-5
t
L
D1
D11
N + 1
N-5D0N-4
D10
N-5
OF
N-4
N-4
8
225812f
TIMING DIAGRAMS
LTC2258-12
LTC2257-12/LTC2256-12
SPI Port Timing (Readback Mode)
SCK
SDI
SDO
CS
t
S
R/W
HIGH IMPEDANCE
t
DS
A6
A5 A4 A3 A2 A1 A0 XX
t
DH
t
DO
XX XX XX XX XX XX XX
D7 D6 D5 D4 D3 D2 D1 D0
SPI Port Timing (Write Mode)
CS
SCK
SDI
SDO
R/W
HIGH IMPEDANCE
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
TYPICAL PERFORMANCE CHARACTERISTICS
t
SCK
t
H
225812 TD04
LTC2258-12: Integral
Nonlinearity (INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048 3072 4096
OUTPUT CODE
225812 G01
LTC2258-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
OUTPUT CODE
2048 3072 4096
225812 G02
LTC2258-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0102030
FREQUENCY (MHz)
225812 G03
225812f
9
LTC2258-12
LTC2257-12/LTC2256-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2258-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10 20 30
FREQUENCY (MHz)
LTC2258-12: 8k Point 2-Tone FFT,
= 68MHz, 69MHz, –1dBFS,
f
IN
65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
20 30
LTC2258-12: SFDR vs Input
Frequency, –1dB, 2V Range,
65Msps
95
90
85
80
SFDR (dBFS)
75
70
65
0
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
225812 G04
225812 G07
225812 G10
LTC2258-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
20 30
LTC2258-12: Shorted Input
Histogram
18000
16000
14000
12000
10000
COUNT
8000
6000
4000
2000
0
2049
2051 2053
OUTPUT CODE
LTC2258-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
110
100
90
80
70
60
50
40
SFDR (dBc AND dBFS)
30
20
10
0
–80
–60 –50 –40 –30 –20 –10 0
–70
dBFS
dBc
INPUT LEVEL (dBFS)
225812 G05
225812 G08
225812 G12
LTC2258-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
20 30
LTC2258-12: SNR vs Input
Frequency, –1dB, 2V Range,
65Msps
72
71
70
69
SNR (dBFS)
68
67
66
0
LTC2258-12: I
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
50
LVDS OUTPUTS
45
(mA)
40
VDD
I
35
30
0
CMOS OUTPUTS
20 40 60
SAMPLE RATE (Msps)
225812 G06
225812 G09
225812 G13
10
225812f
LTC2257-12/LTC2256-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2258-12
LTC2258-12: IO
vs Sample
VDD
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
45
(mA)
VDD
IO
40
35
30
25
20
15
10
5
0
0
1.8V CMOS
SAMPLE RATE (Msps)
3.5mA LVDS
1.75mA LVDS
1.2V CMOS
20 40 60
LTC2257-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048 3072 4096
OUTPUT CODE
LTC2257-12: 8k Point FFT, fIN = 69MHz
–1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
225812 G14
225812 G22
225812 G25
LTC2258-12: SNR vs SENSE,
fIN = 5MHz, –1dB
72
71
70
69
SNR (dBFS)
68
67
66
0.6
0.7 0.8 0.9 1.1 1.2 1.31
SENSE PIN (V)
LTC2257-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
225812 G15
20
225812 G23
LTC2257-12: Integral Nonlinearity
(INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048 3072 4096
OUTPUT CODE
LTC2257-12: 8k Point FFT, fIN = 29MHz
–1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
225812 G21
20
225812 G24
LTC2257-12: 8k Point 2-Tone FFT,
LTC2257-12: 8k Point FFT, fIN = 139MHz
–1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
20
0
10
FREQUENCY (MHz)
20
225812 G26
fIN = 68MHz, 69MHz, –1dBFS,
40Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
10
FREQUENCY (MHz)
20
225812 G27
225812f
11
LTC2258-12
LTC2257-12/LTC2256-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2257-12: Shorted Input
Histogram
18000
16000
14000
12000
10000
COUNT
8000
6000
4000
2000
0
2049
2051 2053
OUTPUT CODE
LTC2257-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 40Msps
110
100
90
80
70
60
50
40
SFDR (dBc AND dBFS)
30
20
10
0
–80
–70
dBFS
dBc
–60 –50 –40 –30 –20 –10 0
INPUT LEVEL (dBFS)
225812 G28
225812 G32
LTC2257-12: SNR vs Input
Frequency, –1dB, 2V Range,
40Msps
72
71
70
69
SNR (dBFS)
68
67
66
0
LTC2257-12: I
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
VDD
5MHz Sine Wave Input, –1dB
35
30
LVDS OUTPUTS
(mA)
VDD
I
25
CMOS OUTPUTS
20
0
20 40
SAMPLE RATE (Msps)
225812 G29
vs Sample Rate,
225812 G33
LTC2257-12: SFDR vs Input
Frequency, –1dB, 2V Range,
40Msps
95
90
85
80
SFDR (dBFS)
75
70
65
0
LTC2257-12: IO
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
vs Sample
VDD
225812 G30
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
45
40
35
30
25
(mA)
VDD
20
IO
15
10
5
0
02040
3.5mA LVDS
1.75mA LVDS
1.8V CMOS
SAMPLE RATE (Msps)
1.2V CMOS
225812 G34
72
71
70
69
SNR (dBFS)
68
67
66
12
LTC2257-12: SNR vs SENSE,
fIN = 5MHz, –1dB
0.6
0.7 0.8 0.9 1.1 1.2 1.31
SENSE PIN (V)
225812 G35
LTC2256-12: Integral Nonlinearity
(INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
2048 3072 4096
OUTPUT CODE
225812 G41
LTC2256-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1024
OUTPUT CODE
2048 3072 4096
225812 G42
225812f
LTC2257-12/LTC2256-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2258-12
LTC2256-12: 8k Point FFT, f
–1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
5
FREQUENCY (MHz)
LTC2256-12: 8k Point FFT, f
–1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
5
FREQUENCY (MHz)
LTC2256-12: SNR vs Input
Frequency, –1dB, 2V Range,
25Msps
72
71
70
69
SNR (dBFS)
68
67
66
0
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
= 5MHz
IN
10
225812 G43
= 140MHz
IN
10
225814 G46
225812 G49
LTC2256-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
5
FREQUENCY (MHz)
LTC2256-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
5
FREQUENCY (MHz)
LTC2256-12: SFDR vs Input
Frequency, –1dB, 2V Range,
25Msps
95
90
85
80
SFDR (dBFS)
75
70
65
0
100 150 200 250 300 350
50
INPUT FREQUENCY (MHz)
10
10
225812 G44
225814 G47
225812 G50
LTC2256-12: 8k Point FFT, f
–1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
AMPLITUDE (dBFS)
–90
–100
–110
–120
0
5
FREQUENCY (MHz)
LTC2256-12: Shorted Input
Histogram
18000
16000
14000
12000
10000
COUNT
8000
6000
4000
2000
0
2049
2051 2053
OUTPUT CODE
LTC2256-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 25Msps
110
100
90
80
70
60
50
40
SFDR (dBc AND dBFS)
30
20
10
0
–80
–60 –50 –40 –30 –20 –10 0
–70
dBFS
INPUT LEVEL (dBFS)
dBc
= 70MHz
IN
10
225812 G45
225812 G48
225812 G52
225812f
13
LTC2258-12
LTC2257-12/LTC2256-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2256-12: I
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB
24
LVDS OUTPUTS
(mA)
20
VDD
I
16
0
SAMPLE RATE (Msps)
CMOS OUTPUTS
10 20
PIN FUNCTIONS
226112 G53
LTC2256-12: IO
vs Sample Rate,
VDD
5MHz Sine Wave Input, –1dB, 5pF
on Each Data Output
45
(mA)
VDD
IO
40
35
30
25
20
15
10
5
0
0
3.5mA LVDS
1.75mA LVDS
1.8V CMOS
10 20
SAMPLE RATE (Msps)
1.2V CMOS
225812 G54
LTC2256-12: SNR vs SENSE,
= 5MHz, –1dB
f
IN
72
71
70
69
SNR (dBFS)
68
67
66
0.6
0.7 0.8 0.9 1.1 1.2 1.31.0
SENSE PIN (V)
225812 G55
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
+
(Pin 1): Positive Differential Analog Input.
A
IN
–
(Pin 2): Negative Differential Analog Input.
A
IN
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2µF ceramic capacitor and to ground with a
0.1µF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V
to enable the
DD
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the V
of the part and not be driven by a
DD
logic signal.
V
(Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
DD
to ground with 0.1µF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
+
ENC
(Pin 11): Encode Input. Conversion starts on the
rising edge.
–
ENC
(Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = V
), CS controls the clock duty cycle
DD
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = V
), SCK controls the
DD
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
14
225812f
PIN FUNCTIONS
LTC2258-12
LTC2257-12/LTC2256-12
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
V
), SDI can be used to power down the part. When SDI
DD
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessar y and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = V
), SDO is not used
DD
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OV
(Pin 26): Output Driver Supply. Bypass to ground
DD
with a 0.1µF ceramic capacitor.
V
(Pin 37): Common Mode Bias Output, Nominally
CM
Equal to V
/2. VCM should be used to bias the common
DD
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
V
(Pin 38): Reference Voltage Output, Nominally 1.25V.
REF
Bypass to ground with a 1µF ceramic capacitor.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to V
selects the internal reference and a ±1V input
DD
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
SENSE
.
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
)
DD
D0 to D11 (Pins 19-24, 29-34): Digital Outputs. D11 is
the MSB.
CLKOUT
CLKOUT
–
(Pin 27): Inverted version of CLKOUT+.
+
(Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT
+
. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pins 17, 18, 35): Do not connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
DOUBLE DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OV
)
DD
D0_1 to D10_11 (Pins 20, 22, 24, 30, 32, 34): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each output pin. The even data bits (D0, D2, D4, D6, D8,
D10) appear when CLKOUT+ is low. The odd data bits (D1,
+
D3, D5, D7, D9, D11) appear when CLKOUT
–
CLKOUT
CLKOUT
(Pin 27): Inverted version of CLKOUT+.
+
(Pin 28): Data Output Clock. The digital outputs
is high.
normally transi tion at the same time as the falling and r is-
+
ing edges of CLKOUT
. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 18, 19, 21, 23, 29, 31, 33, 35): Do not
connect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overfl ow or underfl ow has occurred.
225812f
15
LTC2258-12
LTC2257-12/LTC2256-12
PIN FUNCTIONS
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
–
/D0_1+ to D10_11–/D10_11+ (Pins 19/20, 21/22,
D0_1
23/24, 29/30, 31/32, 33/34): Double Data Rate Digital
O u t p u t s . T w o d a t a b i t s a r e m u l t i p l e x e d o n t o e a c h d i f f e r e n t i a l
output pair. The even data bits (D0, D2, D4, D6, D8, D10)
FUNCTIONAL BLOCK DIAGRAM
+
A
IN
A
V
0.1µF
V
1µF
INPUT
S/H
–
IN
CM
REF
V
1.25V
REFERENCE
RANGE
SELECT
DD
/2
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
+
appear when CLKOUT
D5, D7, D9, D11) appear when CLKOUT
–
CLKOUT
/CLKOUT+ (Pins 27/28): Data Output Clock.
is low. The odd data bits (D1, D3,
+
is high.
The digital outputs normally transition at the same time
+
as the falling and rising edges of CLKOUT
+
CLKOUT
can also be delayed relative to the digital outputs
. The phase of
by programming the mode control registers.
–
/OF+ (Pins 35/ 36): Over/Under Flow Digi tal Output. OF+
OF
is high when an overfl ow or underfl ow has occurred.
V
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
DD
GND
SENSE
16
REF
BUF
DIFF
REF
AMP
REFH
0.1µF 0.1µF
Figure 1. Functional Block Diagram
0.1µF
2.2µF
REFL
REFL
INTERNAL CLOCK SIGNALSREFH
CLOCK/DUTY
CYCLE
CONTROL
+
ENC
ENC
OV
DD
OF
D11
225812 F01
•
•
•
D0
CLKOUT
CLKOUT
+
–
225812f
MODE
CONTROL
REGISTERS
–
SCKPAR/SER SDI
SDOCS
OUTPUT
DRIVERS
OGND
APPLICATIONS INFORMATION
LTC2258-12
LTC2257-12/LTC2256-12
CONVERTER OPERATION
The LTC2258-12/LTC2257-12/LTC2256-12 are low power
12-bit 65Msps/40Msps/25Msps A/D converters that are
powered by a single 1.8V supply. The analog inputs should
be driven differentially. The encode input can be driven
differentially or single-ended for lower power consumption. The digital outputs can be CMOS, double data rate
CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system.)
Many additional features can be chosen by programming
the mode control registers through a serial SPI port. See
the Serial Programming Mode section.
ANALOG INPUT
The analog input is a differential CMOS sample-and-hold
circuit (Figure 2). The inputs should be driven differentially
around a common mode voltage set by the V
pin, which is nominally V
/2. For the 2V input range, the
DD
output
CM
inputs should swing from V
– 0.5V to VCM + 0.5V. There
CM
should be 180° phase difference between the inputs.
INPUT DRIVE CIRCUITS
Input fi ltering
If possible, there should be an RC lowpass fi lter right at
the analog inputs. This lowpass fi lter isolates the drive
circuitry from the A/D sample-and-hold switching, and
also limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC fi lter. The RC component
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with V
, setting the A/D input at its optimal
CM
DC level. At higher input frequencies a transmission line
A
A
ENC
ENC
IN
IN
+
–
+
–
LTC2258-12
10
10Ω
1.2V
1.2V
V
V
10k
10k
50
DD
C
PARASITIC
DD
V
1.8pF
C
PARASITIC
1.8pF
DD
R
25
R
25
C
SAMPLE
ON
3.5pF
C
SAMPLE
3.5pF
ON
ANALOG
INPUT
0.1µF
T1
1:1
25
25
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
25
0.1µF
25
V
0.1µF
A
12pF
A
CM
+
IN
–
IN
LTC2258-12
225812 F03
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
225812 F02
Figure 2. Equivalent Input Circuit
225812f
17
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
Amplifi er Circuits
Figure 7 shows the analog input being driven by a high
speed dif ferential amplifi er. The output of the amplifi er is AC
coupled to the A/D so the amplifi er’s output common mode
voltage can be optimally set to minimize distortion.
50
ANALOG
0.1µF
INPUT
0.1µF
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1
T2
25
25
0.1µF
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
V
0.1µF
4.7pF
CM
A
A
+
IN
–
IN
LTC2258-12
225812 F04
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifi er. If the gain
block is single-ended, then a transformer circuit (Figures 4
to 6) should convert the signal to differential before driving the A/D.
50
ANALOG
0.1µF
INPUT
0.1µF
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1
T2
25
25
0.1µF
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 270MHz
50
0.1µF
0.1µF
ANALOG
INPUT
0.1µF
0.1µF
2.7nH
25
T1
25
2.7nH
V
A
A
CM
IN
IN
+
–
V
CM
0.1µF
+
A
IN
1.8pF
–
A
IN
LTC2258-12
LTC2258-12
225812 F05
18
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
225812 F06
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 270MHz
225812f
APPLICATIONS INFORMATION
LTC2258-12
LTC2257-12/LTC2256-12
Reference
The LTC2258-12/2257-12/2256-12 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to V
. For a 1V input range
DD
using the external reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9.)
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
will then be 1.6 • V
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
ANALOG
INPUT
+
+
–
–
SENSE
0.1µF
0.1µF
.
200
200
25
25
0.1µF
12pF
12pF
V
A
IN
A
IN
CM
+
LTC2258-12
–
225812 F07
The V
, REFH and REFL pins should be bypassed as
REF
shown in Figure 8. The 0.1µF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the back side of the circuit board).
LTC2258-12
1.25V
TIE TO V
TIE TO GND FOR 1V RANGE;
FOR 2V RANGE;
DD
RANGE = 1.6 • V
0.65V < V
SENSE
0.1µF
0.1µF
FOR
SENSE
< 1.300V
V
1µF
SENSE
REFH
0.1µF2.2µF
REFL
REF
5
RANGE
DETECT
AND
CONTROL
1.25V BANDGAP
REFERENCE
0.625V
BUFFER
INTERNAL ADC
HIGH REFERENCE
0.8x
DIFF AMP
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifi er
INTERNAL ADC
LOW REFERENCE
Figure 8. Reference Circuit
V
REF
1µF
1.25V
EXTERNAL
REFERENCE
SENSE
1µF
LTC2258-12
225812 F09
Figure 9. Using an External 1.25V Reference
225812 F08
225812f
19
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10) and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinusoidal, PECL or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken
above V
(up to 3.6V), and the common mode range
DD
is from 1.1V to 1.6V. In the differential encode mode,
–
should stay at least 200mV above ground to avoid
ENC
falsely triggering the single-ended encode mode. For good
+
jitter performance ENC
and ENC– should have fast rise
and fall times.
T h e s i n g l e - e n d e d e n c o d e m o d e s h o u l d b e u s e d w i t h C M O S
–
encode inputs. To select this mode, ENC
+
to ground and ENC
+
input. ENC
can be taken above VDD (up to 3.6V) so 1.8V
is driven with a square wave encode
to 3.3V CMOS logic levels can be used. The ENC
is 0.9V. For good jitter performance ENC
is connected
+
+
threshold
s hou ld hav e f a st
rise and fall times.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%(±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency or is turned off, the duty cycle
stabilizer circuit requires one hundred clock cycles to lock
onto the input clock. The duty cycle stabilizer is enabled
by mode control register A2 (serial programming mode),
or by CS (parallel programming mode).
ENC
ENC
LTC2258-12
15k
+
–
30k
V
DD
DIFFERENTIAL
V
DD
COMPARATOR
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
LTC2258-12
+
1.8V TO 3.3V
0V
ENC
ENC
–
30k
CMOS LOGIC
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
225812 F10
BUFFER
225812 F11
25
D1
T1: COILCRAFT WBC4 - 1WL
D1: AVAGO HSMS - 2822
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
0.1µF
T1
1:4
Figure 12. Sinusoidal Encode Drive
0.1µF
PECL OR
LVDS
CLOCK
0.1µF
Figure 13. PECL or LVDS Encode Drive
ENC
ENC
100
100
+
–
LTC2258-12
225812 F13
0.1µF
ENC
ENC
+
LTC2258-12
–
225812 F12
20
225812f
APPLICATIONS INFORMATION
LTC2258-12
LTC2257-12/LTC2256-12
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle st abilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2258-12/LTC2257-12/LTC2256-12 can operate in
three digital output modes: full rate CMOS, double data
rate CMOS (to halve the number of output lines), or double
data rate LVDS (to reduce digital noise in the system). The
output mode is set by mode control register A3 (serial
programming mode), or by SCK (parallel programming
m o d e ) . N o t e t h a t d o u b l e d a t a r a t e C M O S c a n n o t b e s e l e c t e d
in the parallel programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 12 digital outputs (D0-D11),
overfl ow (OF), and the data output clocks (CLKOUT
CLKOUT
powered by OV
A/D core power and ground. OV
1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double Data Rate CMOS Mode
In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the
number of data lines by six, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 6 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11), overfl ow (OF), and the data output clocks
(CLKOUT
puts are powered by OV
from the A/D core power and ground. OV
from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS
logic outputs.
–
) have CMOS output levels. The outputs are
and OGND which are isolated from the
DD
can range from 1.1V to
DD
+
, CLKOUT–) have CMOS output levels. The out-
and OGND which are isolated
DD
can range
DD
+
,
Double Data Rate LVDS Mode
In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair.
There are 6 LVDS output pairs (D0_1
D10_11
(OF
each have an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground. In LVDS
mode, OV
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
T h i s c u r r e n t c a n b e a d j u s t e d b y s e r i a l l y p r o g r a m m i n g m o d e
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any refl ections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
Overfl ow Bit
The overfl ow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged.
The overfl ow bit has the same pipeline latency as the
data bits.
+
/D10_11–) for the digital output data. Overfl ow
+
/OF–) and the data output clock (CLKOUT+/CLKOUT–)
DD
must be 1.8V.
DD
+
/D0_1– through
and OGND which are
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
225812f
21
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
In full-rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT
+
so the rising edge of CLKOUT
can be used to latch the
+
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
the falling and rising edges of CLKOUT
setup-and-hold time when latching the data, the CLKOUT
. To allow adequate
+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2258-12/LTC2257-12/LTC2256-12 can also phase
+
shift the CLKOUT
/CLKOUT– signals by serially programming mode control register A2. The output clock can be
shifted by 0°, 45°, 90° or 135°. To use the phase shifting
feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
+
CLKOUT
and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase
shifts of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
,
voltage, the digital data output bits and the overfl ow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially programming mode control register A4.
Table 1. Output Codes vs Input Voltage
+
A
(2V RANGE) OF
>+1.000000V
+0.999512V
+0.999024V
+0.000488V
0.000000V
–0.000488V
–0.000976V
–0.999512V
–1.000000V
≤–1.000000V
–
– A
IN
IN
D11-D0
(OFFSET BINARY)
1
1111 1111 1111
0
1111 1111 1111
0
1111 1111 1110
0
1000 0000 0001
0
1000 0000 0000
0
0111 1111 1111
0
0111 1111 1110
0
0000 0000 0001
0
0000 0000 0000
1
0000 0000 0000
D11-D0
(2’s COMPLEMENT)
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Randomizer
ENC
D0-D11, OF
CLKOUT
Interference from the A/D digital outputs is sometimes
unavoidable. Digital interference may be from capacitive or
+
PHASE
SHIFT
0°
45°
90°
+
135°
180°
225°
270°
315°
225812 F14
MODE CONTROL BITS
CLKINV
CLKPHASE1
0
0
0
0
1
1
1
1
CLKPHASE0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
22
Figure 14. Phase Shifting CLKOUT
225812f
APPLICATIONS INFORMATION
LTC2258-12
LTC2257-12/LTC2256-12
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
The digital output is “randomized” by applying an exclusive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output randomizer is enabled by
serially programming mode control register A4.
Alternate Bit Polarity
Another feature that reduces digital feedback on the circuit
board is the alternate bit polarity mode. When this mode
CLKOUT CLKOUT
OF
OF
is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11)
are inverted before the output buffers. The even bits (D0,
D2, D4, D6, D8, D10), OF and CLKOUT are not affected.
This can reduce digital currents in the circuit board ground
plane and reduce digital noise, particularly for very small
analog input signals.
When there is a very small signal at the input of the A/D
that is centered around midscale, the digital outputs toggle
between mostly 1s and mostly 0s. This simultaneous
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To fi rst order,
this cancels current fl ow in the ground plane, reducing
the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit
polarity mode is independent of the digital output random-
PC BOARD
CLKOUT
FPGA
D11
D10
•
•
D2
RANDOMIZER
ON
D1
D0
Figure 15. Functional Equivalent of Digital Output Randomizer
•
D11/D0
D10/D0
D2/D0
D1/D0
D0
225812 F15
OF
D11/D0
D11
D10/D0
LTC2258-12
D2/D0
D1/D0
D0
Figure 16. Unrandomizing a Randomized Digital
Output Signal
D10
•
•
•
D2
D1
D0
225812 F15
225812f
23
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
izer—either, both or neither function can be on at the same
time. When alternate bit polarity mode is on, the data
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D11-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard: Outputs change from 1010101010101
to 0101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including
OF and CLKOUT are disabled. The high impedance disabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down, resulting in 0.5mW power consumption. Sleep mode
is enabled by mode control register A1 (serial programming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on V
REF
,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
mode requires at least 100 clock cycles. If the application
demands very accurate DC settling then an additional
50µs should be allowed so the on-chip references can
settle from the slight temperature shift caused by the
change in supply current as the A/D leaves nap mode.
Nap mode is enabled by mode control register A1 in the
serial programming mode.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2258-12/LTC2257-12/
LTC2256-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more fl exibility and can program all available modes.
The parallel inter face is more limited and can only program
some of the more commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V
. The CS, SCK and SDI pins are binary logic
DD
inputs that set certain operating modes. These pins can
be tied to V
or ground, or driven by 1.8V, 2.5V or 3.3V
DD
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD)
PIN DESCRIPTION
CS Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK Digital Output Mode Control Bit
0 = Full-Rate CMOS Output Mode
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
SDI Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode
24
225812f
APPLICATIONS INFORMATION
LTC2258-12
LTC2257-12/LTC2256-12
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the fi rst 16 rising edges of
SCK. Any SCK rising edges after the fi rst 16 are ignored.
The data transfer ends when CS is taken high again.
The fi rst bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The fi nal eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the timing
diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left fl oating and no pull-up resistor is
needed.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
s h o u l d b e p r o g r a m m e d a s s o o n a s p o s s i b l e a f t e r t h e p o w e r
supplies turn on and are stable. The fi rst serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
Table 3. Serial Programming Mode Register Map
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7 D6 D5 D4 D3 D2 D1 D0
RESETXXXXXXX
Bit 7 RESET Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. This Bit is Automatically Set Back to Zero After the Reset is Complete
Bits 6-0 Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7 D6 D5 D4 D3 D2 D1 D0
XXXXXXPWROFF1PWROFF0
Bits 7-2 Unused, Don’t Care Bits.
Bits 1-0 PWROFF1:PWROFF0 Power Down Control Bits
00 = Normal Operation
01 = Nap Mode
10 = Not Used
11 = Sleep Mode
225812f
25
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7 D6 D5 D4 D3 D2 D1 D0
XXXXCLKINV CLKPHASE1 CLKPHASE0 DCS
Bits 7-4 Unused, Don’t Care Bits.
Bit 3 CLKINV Output Clock Invert Bit
Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
Bit 0 DCS Clock Duty Cycle Stabilizer Bit
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7 D6 D5 D4 D3 D2 D1 D0
X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0
Bit 7 Unused, Don’t Care Bit.
Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits
Bit 3 TERMON LVDS Internal Termination Bit
Bit 2 OUTOFF Output Disable Bit
Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits
0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
00 = No CLKOUT Delay (As Shown in the Timing Diagrams)
01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8)
10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4)
11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT Phase Delay Feature is Used, the Clock Duty Cycle Stabilizer Must Also be Turned On
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 1.6× the Current Set by ILVDS2:ILVDS0
0 = Digital Outputs are Enabled
1 = Digital Outputs are Disabled and Have High Output Impedance
00 = Full-Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
26
225812f
LTC2258-12
LTC2257-12/LTC2256-12
APPLICATIONS INFORMATION
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7 D6 D5 D4 D3 D2 D1 D0
X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP
Bit 7-6 Unused, Don’t Care Bits.
Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
Bit 2 ABP Alternate Bit Polarity Mode Control Bit
Bit 1 RAND Data Output Randomizer Mode Control Bit
Bit 0 TWOSCOMP Two’s Complement Mode Control Bit
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D11-D0 Alternate Between 1 0101 1010 0101 and 0 1010 0101 1010
111 = Alternating Output Pattern. OF, D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111
Note: Other Bit Combinations are not Used
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Note: ABP = 1 forces the output format to be Offset Binary
GROUNDING AND BYPASSING
The LTC2258-12 /LTC2257-12/LTC2256-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track
or underneath the ADC.
High qu alit y c eramic bypass capacitors should be used at
the V
, OVDD, VCM, V
DD
, REFH and REFL pins. Bypass
REF
c a p a c i t o r s m u s t b e l o c a t e d a s c l o s e t o t h e p i n s a s p o s s i b l e .
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The V
as possible. To make space for this the capacitor on V
capacitor should be located as close to the pin
CM
REF
can be further away or on the back of the PC board. The
t ra ce s co nn ec t i ng t he pin s an d b ypa ss ca pa ci tor s m us t be
kept short and should be made as wide as possible.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fi ll and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
Most of the heat generated by the ADC is transferred from
the die through the bottom-side exposed pad and package
leads onto the printed circuit board. For good electrical and
thermal performance, the exposed pad must be soldered
to a large grounded pad on the PC board.
225812f
27
LTC2258-12
LTC2257-12/LTC2256-12
TYPICAL APPLICATIONS
T2
MABAES0060
••
ANALOG INPUT
R9 10
R10 10
R15 100
R39
33.2
1%
R40
33.2
1%
C51
4.7pF
LTC2258 Schematic
SENSE
R14
1k
C17
1µF
C23
1µF
R16
100
C12
0.1µF
C13
1µF
C15
0.1µF
C21
0.1µF
0.1µF
C18
R27 10
R28 10
C20
2.2µF
PAR/SER
10
ENCODE CLOCK
C19
0.1µF
1
AIN
2
AIN
3
GND
4
REFH
5
REFH
6
REFL
7
REFL
8
PAR/SER
9
V
DD
V
DD
GND ENC
31323334353637383940
SENSE V
V
DD
+
–
41
R13
100
REFVCM
+
ENC–CS SCK SDI SDO DNC DNC D0 D1
OF+OF–D11 D10 D9 D8
LTC2258CUJ
CLKOUT
CLKOUT
OV
OGND
30
D7
29
D6
28
+
27
–
26
DD
25
24
D5
23
D4
22
D3
21
D2
20191817161514131211
DIGITAL
OUTPUTS
C37
0.1µF
DIGITAL
OUTPUTS
0V
DD
28
225812 TA02
SPI BUS
225812f
TYPICAL APPLICATIONS
Silkscreen Top Top Side
LTC2258-12
LTC2257-12/LTC2256-12
225812 TA03
Inner Layer 2 GND Inner Layer 3
225812 TA04
225812 TA05
225812 TA06
225812f
29
LTC2258-12
LTC2257-12/LTC2256-12
TYPICAL APPLICATIONS
Inner Layer 4 Inner Layer 5 Power
225812 TA07
225812 TA08
Bottom Side
225812 TA09
30
225812f
PACKAGE DESCRIPTION
LTC2258-12
LTC2257-12/LTC2256-12
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
4.42 ±0.05
4.42 ±0.05
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ± 0.10
(4 SIDES)
PIN 1 TOP MARK
(SEE NOTE 6)
4.50 ±0.05
5.10 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.75 ± 0.05
6.50 ±0.05
R = 0.10
TYP
4.50 REF
(4-SIDES)
R = 0.115
TYP
4.42 ±0.10
PIN 1 NOTCH
R = 0.45 OR
0.35 s 45°
CHAMFER
4039
0.40 ± 0.10
1
2
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
Howev er, no resp onsi bilit y is a ssume d for it s use. L inea r Technol ogy Co rpor atio n make s no repr esen tat i o n t ha t t h e i n te r co n n ec t io n o f i t s c i rc u it s a s d es c ri b e d h e r ei n w il l n o t i n fr i n ge o n e x is ti n g p at e n t r i g ht s .
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
225812f
31
LTC2258-12
LTC2257-12/LTC2256-12
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994 Low Noise, Low Distortion Fully Differential Input/
LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN
LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2205 16-Bit, 65Msps, 3.3V ADC 590mW, 79dB SNR, 100dB SFDR, 48-Pin QFN
LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN
LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN
LTC2209 16-Bit, 160Msps, 3.3V ADC, LVDS Outputs 1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN
LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN
LTC2249 14-Bit, 80Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN
LTC2256-14/
LTC2257-14/
LTC2258-14
LTC2259-12/
LTC2260-12/
LTC2261-12
LTC2259-14/
LTC2260-14/
LTC2261-14
LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
LTC2299 Dual 14-Bit, 80Msps ADC 230mW, 71.6dB SNR, 5mm × 5mm QFN Package
LTC5517 40MHz to 900MHz Direct Conversion Quadrature
LTC5527 400MHz to 3.7GHz High Linearity Downconverting
LTC5557 400MHz to 3.8GHz High Linearity Downconverting
LTC5575 800MHz to 2.7GHz Direct Conversion Quadrature
LTC6400-20 1.8GHz Low Noise, Low Distortion Differential ADC
LTC6604-2.5/
LTC6604 -5/
LTC6604-10/
LTC6604-15
Output Amplifi er/Driver
14-Bit, 25/40/65Msps 1.8V ADCs,
Ultralow Power
12-Bit, 80/105/125Msps 1.8V ADCs,
Ultralow Power
14-Bit, 80/105/125Msps 1.8V ADCs,
Ultralow Power
Demodulator
Mixer
Mixer
Demodulator
Driver for 300MHz IF
Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter
with ADC Driver
Low Distortion: –94dBc at 1MHz
35mW/49mW/81mW, 74dB SNR, 88dB SFDR
DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN Package
87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR
DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN Package
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR
DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN Package
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB,
3.3V Supply Operation, Integrated Transformer
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator
Integrated RF and LO Transformer
Fixed Gain 10V/V, 2.1nV√Hz Total Input Noise, 3mm × 3mm QFN-16 Package
Dual Matched 4th Order LP Filters with Differential Drivers. Low Noise, Low
Distortion Amplifi ers
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
225812f
LT 0309 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2009
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