LINEAR TECHNOLOGY LTC2209 Technical data

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Understanding the Effect of Clock Jitter on High Speed ADCs

Design Note 1013

Derek Redmayne (LTC Applications Engineer), Eric Trelewicz (LTC Applications
Manager) and Alison Smith (High Speed ADC Product Marketing Engineer)

Digitizing high speed signals to a high resolution requires
careful selection of a clock that will not compromise the
sampling performance of the Analog to Digital Converter
(ADC). In this article we hope to give the reader a bet­ter understanding of clock jitter and how it affects the
performance of the high speed ADC.

As an example we will highlight the latest high perfor­mance ADC from Linear Technology, the 16-bit, 160Msps
LTC2209. This ADC exhibits a signal to noise ratio (SNR)
of 77.4dB, with 100dB SFDR throughout much of the
baseband region. Like most high speed ADCs on the
market today, the LTC2209 uses a sample-and -hold (S&H)
circuit that essentially takes a snapshot of the ADC input
at an instant in time. When the S&H switch is closed,
the network at the input of the ADC is connected to the
sample capacitor. At the instant the switch is opened
one half clock cycle later, the voltage on the capacitor
is recorded and held. Variation in the time at which the
switch is op ened is kn own as aper tur e uncer ta int y, or ji t­ter, and will result in an error voltage that is proportional
to the magnitude of the jitter and the input signal slew
rate. In other words, the greater the input frequency and
amplitude, the more susceptible you are to jitter on the
clock source. Figure 1 demonstrates this relationship of
slew rate proportional to jitter.

Describing a clock as “low jitter” has become almost
meaningless. This is because it means different things
to different interest groups. For a programmable logic
vendor 30ps or even 50ps is considered low jitter. High
performance ADCs need a clock with <1ps depending
on the input frequency. More precisely, spectral power
distribution of t he sampled signal is the determining fa ctor,
as opposed to simply the highest frequency component,
unless a full scale signal at the upper end of the spectrum
is expected. For a simplistic example, a uniform band of
power from DC to 1MHz is 6dB less sensitive than a single

tone, or a narrow band, with equivalent power at 1MHz.

There are various contributors to jitter in any scenario,
extending from the oscillator to any frequency dividers,
clock buffers and any noise acquired due to coupling
effects, in addition to the internal aperture jitter of the
ADC itself.

The internal aperture jitter of the LTC2209 is 70fempto
seconds. For the level of performance exhibited by the
LTC2209 and other members in Linear Technology’s high
speed 16-bit family, 0.5ps, the best available from many
oscillator vendors, may pr oduce discernable compromise
in SNR for some sampling scenarios. It is not the ADC
but the sampling scenario that dictates the required jitter
performance. Any ADC that exhibit s 77dB SNR at 140MHz
input frequency would r equire the same jitter p erformance
to achieve full data sheet SNR. It is the input frequency
not the clock frequency that is the determining factor with
respect to jitter performance. On the LTC2209 a clock
that has 10ps jitter would only cause a loss of about

HIGHER FREQUENCY
INPUT SIGNAL

LOWER FREQUENCY
INPUT SIGNAL

dv

dv

dt = CLOCK JITTER

DN1013 F01

Figure 1. Slew Rate Exacerbates the Effects of Clock Jitter.

08/06/1013

0.7dB SNR at an input frequency of 1MHz. At 140MHz
the SNR would degrade to 41.1dB. Figure 2 demonstrates
the effects of clock jitter on the SNR of the LTC2209 as
a function of sampled input frequency with a family of
curves of increasing clock jitter from a perfect clock to
100ps of jitter. At 100ps, the ADC SNR begins to degrade
with input frequencies of only 200kHz!

90

100ps

OSC JITTER

0fs

200fs

500fs

1ps

2ps

5ps

10ps

20ps

50ps

DN1013 F02

80

70

60

50

SNR (dB)

40

30

20

1

Figure 2 Jitter Degradation of SNR as a Function of
Input Frequency

10 100 1000

INPUT FREQUENCY (MHz)

phase noise, equation (3). The spectral density mea­surements assume the AM component ε(t) of the noise
is negligible compared to the phase noise component
ϕ(t). This is a reasonable assumption with any quality
frequency source.

V(t) = [V

+ ε(t)]sin[2πfOt + ϕ(t)] (3)

O

The spectral density denoted as L(f) is stated as the
ratio of the single sideband phase noise power in a 1Hz
bandwidth at an offset frequency, also called the Fourier
frequency, relative to the carrier power, equation (4).

L f

=

()

Power Density one phase ulation sideban

(mod

()4

dd

)

Carrier Power

Jitter is the integral of spectral phase density with re­spect to frequency between two limits in frequency and
expressed in time, equation (5). The result is frequency
independent.

f

1

σπ=

2

2

25

fdf

L ()

()

∫

f

f

1

O

The theoretical limit on SNR resulting from clock jitter is
given as equation (1)

SNR(dBFS) = –20log(2πf

where f

is the input frequency and σ is the jitter in RMS

in

σ) (1)

in

seconds.

The jitter related noise power is proportional to the input
power (dBFS). As the input level is raised or decre ased the
noise component related to jitter changes accordingly. If,
for example, we have a –1dBFS input signal at a 70MHz
IF, sampled by a clock with 1ps jitter we can expect an
SNR of 68dBFS. At –5dBFS, the noise component related
to jitter would drop 4dB to an SNR of 72dBFS.

To calculate the total SNR degradation we add the jitter
noise power to the published SNR of the ADC, equation
(2):

SNR degradation (dBFS) = 10log

(–SNRadc/10)

( 10

(–SNRjitter/10)

+ 10

)

(2)

Understanding Clock Oscillator Jitter Specs.

Clock oscillators are usually specifi ed in terms of spectral
density of phase noise in dBc/Hz. An oscillator output can
be decomposed into an amplitude term with associated
amplitude noise and a frequency term with associated

Most oscillators that rate jitter are rated between 12kHz
and 20MHz. This is due to historical reasons related to
optical communic ations and is not applicable to most other
practic al cases. Perfor mance may in fact fall apar t beyond
these limits so take care not to be lured in without careful
examination. For many oscillators where close-in phase
noise dominates, the lower limit has the most impact on
the published fi gure. While this expression is convenient
as it yields a single number useful for calculation of ADC
SNR degradation, it is not as informative as the spectral
density. For example, two oscillators having different
spectral content may have the same jitter over the same
integration limits but may not produce the same SNR.
Elevated wideband noise may not produce a poor jitter
spec, but will degrade SNR. Close-in phase noise causes
the fundamental signal to spread into adjacent frequency
bins of an FFT reducing dynamic range, whereas broad­band phase noise will uniformly elevate the noise fl oor
throughout the entire Nyquist zone thus reducing the
overall SNR performance of the ADC. Jitter does not af­fect SFDR unless the clock also cont ains spurs. The lower
frequency limit of integration should correspond to the
frequency resolution of any manipulations o f the sampled
data- as the size of an FFT increases for example.