查询LTC1983-3供应商
FEATURES
■
Fixed Output Voltages: –3V, –5V or Low Noise V
to –VIN Inverted Output
■
±4% Output Voltage Accuracy
■
Low Quiesient Current: 25µA
■
100mA Output Current Capability
■
3V to 5.5V Operating Voltage Range (LTC1983-3)
■
2.3V to 5.5V Operating Voltage Range (LTC1983-5)
■
Internal 900kHz Oscillator
■
“Zero Current” Shutdown
■
Short-Circuit and Over-Temperature Protected
■
Low Profile (1mm) ThinSOTTM Package
U
APPLICATIO S
■
–3V Generation in Single-Supply Systems
■
Portable Equipment
■
LCD Bias Supplies
■
GaAs FET Bias Supplies
IN
LTC1983-3/LTC1983-5
100mA Regulated
Charge-Pump Inverters
in ThinSOT
U
DESCRIPTIO
The LTC®1983-3 and LTC1983-5 are inverting charge
pump DC/DC converters that produce negative regulated
outputs. The parts require only three tiny external capacitors and can provide up to 100mA of output current. The
devices can operate in open loop mode (creating a –V
supply) or regulated output mode depending on the input
supply voltage and the output current.
The LTC1983-3/LTC1983-5 have many useful features for
portable applications including very low quiescent current
(25µA typical) and a zero current shutdown mode pro-
grammed through the SHDN pin.
The LTC1983-3/LTC1983-5 are over-temperature and
short-circuit protected. The parts are available in a 6-pin
low profile (1mm) ThinSOT package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
IN
TYPICAL APPLICATIO
–3V at 100mA DC/DC Converter
V
3V TO 5.5V
10µF
OFF ON
IN
C
IN
: TAIYO YUDEN LMK212BJ105
C
FLY
, C
: TAIYO YUDEN JMK316BJ106ML
C
IN
OUT
V
IN
LTC1983-3
SHDN
+
C
C
FLY
1µF
V
GND
OUT
C
–
1983-3 TA01
U
= –3V
V
OUT
= UP TO 100mA
I
OUT
C
OUT
10µF
(V)
OUT
V
–3.3
–3.2
–3.1
–3.0
–2.9
–2.8
–2.7
V
OUT
0
20 40 60 80
I
OUT
vs I
OUT
VIN = 5V
VIN = 3.3V
(mA)
100
1983 TA02
sn1983 1983fs
1
LTC1983-3/LTC1983-5
VCC 1
V
OUT
2
C
+
3
6 SHDN
5 GND
4 C
–
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC SOT-23
WW
W
ABSOLUTE AXI U RATI GS
U
UUW
PACKAGE/ORDER I FOR ATIO
(Note 1)
VIN to GND................................................... –0.3V to 6V
SHDN Voltage ..............................................–0.3V to 6V
V
to GND (LTC1983-3)..................0.2V to V
OUT
V
to GND (LTC1983-5)..................0.2V to V
OUT
I
Max ............................................................. 125mA
OUT
OUT
OUT
Max
Max
Output Short-Circuit Duration..........................Indefinite
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, C
The ● denotes the specifications which apply over the full operating
T
= 1µF, C
FLY
JMAX
= 125°C, θJA = 256°C/W
= 10µF
OUT
ORDER PART
NUMBER
LTC1983ES6-3
LTC1983ES6-5
S6 PART
MARKING
LTPC
LTYB
unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage (Regulated Output Mode) (LTC1983-3) ● 3.0 5.5 V
Min Startup Voltage 2.3 V
V
IN
V
(LTC1983-3) VIN ≥ 3.3V, I
OUT
V
(LTC1983-5) VIN ≥ 5V, VIN –5V ≥ I
OUT
VIN Operating Current V
VIN Operating Current (Open-Loop Mode) (LTC1983-5) VIN = 3.3V 2.5 mA
VIN Shutdown Current SHDN = 0V, VIN ≤ 5.5V ● 0.1 1 µA
Output Ripple 3.3 ≤ VIN ≤ 5.5 60 mV
Open-Loop Output Impedance (LTC1983-3): R
Open-Loop Output Impedance (LTC1983-5): R
Oscillator Frequency (Non-Burst Mode® Operation) 900 kHz
SHDN Input High ● 1.1 V
SHDN Input Low ● 0.3 V
SHDN Input Current V
OUT
OUT
V
≥ 5V, I
IN
≤ 5.5V, I
IN
V
= 4.75V 4 mA
IN
VIN = 3.3V, V
VIN = 3.3V, I
V
= 5V, I
IN
= 5.5V ● 2.2 4 µA
SHDN
≤ 25mA ● –2.88 –3 –3.12 V
OUT
≤ 100mA ● –2.88 –3 –3.12 V
OUT
• R
OUT
OUT
= 0µA, SHDN = V
OUT
= –3V 11 Ω
OUT
≈ 50mA 11 Ω
OUT
≈ 60mA 8.5 Ω
OUT
IN
● – 4.8 –5 –5.2 V
● 25 60 µA
P-P
Burst Mode is a registered trademark of Linear Technology
Corporation.
Note 1: Absolute Maximum Ratings are those values beyond
which the life of a device may be impaired.
2
Note 2: The LTC1983E-3/LTC1983E-5 are guaranteed to meet
performance specifications from 0°C to 70°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
sn1983 1983fs
UW
TYPICAL PERFOR A CE CHARACTERISTICS
LTC1983-3/LTC1983-5
Efficiency vs I
90
80
70
60
50
40
EFFICIENCY (%)
30
20
10
0
0
Efficiency vs I
100
V
OUT
= 25°C
T
A
75
50
EFFICIENCY (%)
25
OUT
VIN = 2.3V
20 60
40
I
(mA)
OUT
OUT
= –3V
(LTC1983-5)
VIN = 5V
VIN = 3.3V
TA = 25°C
80
= 3.3V
V
IN
VIN = 5V
1983 G01
100
Output Impedance vs
Input Voltage
12.5
12.0
11.5
11.0
10.5
(Ω)
OUT
10.0
R
9.5
9.0
8.5
8.0
2.35
–3V
vs I
OUT
–2.1
–2.3
–2.5
–2.7
(V)
OUT
V
–2.9
–3.1
–3.3
I
= 25mA
OUT
= 25°C
T
A
R
OUT
3.35 5.35
OUT
–40°C, 0°C, 40°C
4.35
VIN (V)
1983 TA02
Over Temperature
120°C
80°C
Output Impedance
vs I
(LTC1983-5)
OUT
30
TA = 25°C
25
20
(Ω)
OUT
R
15
10
5
0
20 60
–3V
vs I
OUT
(VIN = 5V)
3.3
VIN = 5V
3.2
3.1
(–V)
3.0
OUT
V
2.9
2.8
VIN = 2.3V
VIN = 3.3V
40
I
(mA)
OUT
Over Temperature
OUT
–40°C
0°C
40°C
80°C
VIN = 5V
80
1983 G03
100
0
0.01
0.1 1 100
I
(mA)
OUT
Open-Loop Current
vs Temperature (LTC1983-5)
4.9
VIN = 5V
4.7
4.5
4.3
(mA)
IN
I
4.1
3.9
3.7
3.5
–40
10
TEMPERATURE (°C)
10
1983 GO4
60 110
1983 G07
–3.5
0
20 40
OUTPUT CURRENT (mA)
Open-Loop Input Current
vs VIN (LTC1983-5)
4.5
TA = 25°C
4.0
3.5
3.0
(mA)
IN
I
2.5
2.0
1.5
2.3
2.8
3.3 3.3 4.3
80 120
60 100
VIN (V)
1983 G05
4.8
1983 G09
2.7
0
40 60 80
20
OUTPUT CURRENT (mA)
Burst Mode Current
vs Temperature (LTC1983-3)
50
VIN = 5V
45
40
35
30
(µA)
IN
I
25
20
15
10
–40
10 60
TEMPERATURE (°C)
100 120
1983 G06
110
1983 G08
sn1983 1983fs
3
LTC1983-3/LTC1983-5
TEMPERATURE (°C)
–50
0
V
THRESHOLD
(V)
0.1
0.3
0.4
0.5
1.0
0.7
0
50
1983 G12
0.2
0.8
0.9
0.6
100
150
UW
TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode Input Current
vs VIN (LTC1983-3)
31.0
TA = 25°C
30.5
30.0
29.5
29.0
28.5
28.0
INPUT CURRENT (µA)
27.5
27.0
26.5
3.1
3.6 4.6
4.1
VIN (V)
5.1 5.5
1983 G10
SHDN Pin Input Current
vs Temperature R
3.5
3.0
2.5
2.0
SHDN
I
1.5
1.0
(Ω)
OUT
R
1400
1200
1000
800
(Ω)
OUT
600
R
400
R
vs Temperature
OUT
(I
= 10mA)
OUT
18
I
= 10mA
OUT
16
14
12
10
8
6
4
2
0
–50
vs C
OUT
= 5V
V
IN
= 25°C
T
A
VIN = 3V
0
50
TEMPERATURE (
(V
FLY
IN
VIN = 5V
= 5V)
°C)
100
1983 G11
150
SHDN Pin Threshold Voltage
vs Temperature
V
Start-Up into 100mA
OUT
Resistive Load
V
OUT
1V
V
IN
5V
0.5
0
–50
V
OUT
V
OUT
20mV
4
0 50 150
TEMPERATURE (°C)
100
Ripple at 100mA Load
1µs/DIV 1983 G16
1983 G13
200
V
OUT
20mV
0
0.01
V
Ripple at 30mA Load
OUT
0.1 1
C
(µF)
FLY
2.5µs/DIV
1983 G14
1983 G17
V
OUT
20mV
I
OUT
100mA
50µs/DIV 1983 G15
V
Load Step Reponse from
OUT
I
OUT
= 0 to I
= 100mA
OUT
100µs/DIV
1983 G18
sn1983 1983fs
LTC1983-3/LTC1983-5
U
UU
PI FU CTIO S
V
(Pin 1): Charge Pump Input Voltage. May be between
IN
2.3V and 5.5V. VIN should be bypassed with a ≥4.7µF low
ESR capacitor as close as possible to the pin for best
performance.
V
(Pin 2): Regulated Output Voltage for the IC. V
OUT
OUT
should be bypassed with a ≥4.7µF low ESR capacitor as
close as possible to the pin for best performance.
C+ (Pin 3): Charge Pump Flying Capacitor Positive Terminal. This node is switched between VIN and GND (It is
connected to VCC during shutdown).
W
BLOCK DIAGRA
LTC1983-X
+
C
S1A
C– (Pin 4): Charge Pump Flying Capacitor Negative Terminal. This node is switched between GND and V
OUT
(It is
connected to GND during shutdown).
GND (Pin 5): Signal and Power Ground for the 6-Pin
SOT-23 package. This pin should be tied to a ground plane
for best performance.
SHDN (Pin 6): Shutdown. Grounding this pin shuts down
the IC. Tie to VIN to enable. This pin should not be pulled
above the VIN voltage or below GND.
V
IN
C
IN
10µF
C
FLY
1µF
V
OUT
C
OUT
10µF
S2A
–
C
S1B
S2B
CHARGE PUMP
CLOCK1
CLOCK2
CONTROL
LOGIC
COMP1
SHDN
V
REF
+
–
1µA
1983 BD
sn1983 1983fs
5
LTC1983-3/LTC1983-5
U
OPERATIO
(Refer to Block Diagram)
The LTC1983-3/LTC1983-5 use a switched capacitor
charge pump to invert a positive input voltage to a regulated –3V ±4% (LTC1983-3) or –5 ±4% (LTC1983-5)
output voltage. Regulation is achieved by sensing the
output voltage through an internal resistor divider and
enabling the charge pump when the output voltage droops
above the upper trip point of COMP1. When the charge
pump is enabled, a 2-phase, nonoverlapping clock controls the charge pump switches. Clock 1 closes the S1
switches which enables the flying capacitor to charge up
to the VIN voltage. Clock 2 closes the S2 switches that
invert the VIN voltage and connect the bottom plate of C
to the output capacitor at V
. This sequence of charging
OUT
FLY
and discharging continues at a free-running frequency of
900kHz (typ) until the output voltage has been pumped
down to the lower trip point of COMP1 and the charge
pump is disabled. When the charge pump is disabled, the
LTC1983 draws only 25µA (typ) from VIN which provides
high efficiency at low load conditions.
In shutdown mode, all circuitry is turned off and the part
draws less than 1µA from the VIN supply. V
disconnected from VIN and C
. The SHDN pin has a
FLY
OUT
is also
threshold of approximately 0.7V. The part enters shutdown when a low is applied to the SHDN pin . The SHDN
pin should not be floated; it must be driven with a logic
high or low.
Open-Loop Operation
The LTC1983-3/LTC1983-5 inverting charge pumps regulate at –3V/–5V respectively, unless the input voltage is too
low or the output current is too high. The equations for
output voltage regulation are as follows:
VIN –5.06V > I
VIN –3.06V > I
OUT
OUT
• R
• R
(LTC1983-5)
OUT
(LTC1983-3)
OUT
If this condition is not met, then the part will run in open
loop mode and act as a low output impedance inverter for
which the output voltage will be:
V
= –[VIN –(I
OUT
OUT
• R
OUT
)]
For all R
values, check the corresponding curves in
OUT
the Typical Performance Characteristics section (Note:
C
= 1µF for all R
FLY
curves). The R
OUT
value will be
OUT
different for different flying caps, as shown in the following equation:
=Ω+
OUT OUT
()–.
111
fC
OSC FLY
R R curve
1
•
Short-Circuit/Thermal Protection
During short-circuit conditions, the LTC1983 will draw
several hundred milliamps from VIN causing a rise in the
junction temperature. On-chip thermal shutdown circuitry disables the charge pump once the junction temperature exceeds ≈155°C, and reenables the charge pump
once the junction temperature falls back to ≈145°C. The
LTC1983 will cycle in and out of thermal shutdown
indefinitely without latchup or damage until the V
OUT
short is removed.
Capacitor Selection
For best performance, it is recommended that low ESR
capacitors be used for both CIN and C
and ripple. The CIN and C
capacitors should be either
OUT
to reduce noise
OUT
ceramic or tantalum and should be 4.7µF or greater.
Aluminum electrolytic are not recommended because of
their high equivalent series resistance (ESR). If the source
impedance is very low, CIN may not be needed. Increasing
the size of C
voltage ripple. The flying capacitor and C
to 10µF or greater will reduce output
OUT
should also
OUT
have low equivalent series inductance (ESL). The board
layout is critical as well for inductance for the same reason
(the suggested board layout should be used).
A ceramic capacitor is recommended for the flying capacitor with a value in the range of 0.1µF to 4.7µF. Note that
a large value flying cap (>1µF) will increase output ripple
unless C
is also increased. For very low load applica-
OUT
tions, C1 may be reduced to 0.01µF to 0.047µF. This will
reduce output ripple at the expense of efficiency and
maximum output current.
6
sn1983 1983fs
V
OUT
V
OUT
LTC1983-X
10µF
TANTALUM
10µF
TANTALUM
V
OUT
V
OUT
LTC1983-X
15µF
TANTALUM
1µF
CERAMIC
3.9Ω
1983 F01
OPERATIO
LTC1983-3/LTC1983-5
U
(Refer to Block Diagram)
There are many aspects of the capacitors that must be
taken into account. First, the temperature stability of the
dielectric is a main concern. For ceramic capacitors, a
three character code specifies the temperature stability
(e.g. X7R, Y5V, etc.). The first two characters represent
the temperature range that the capacitor is specified and
the third represents the absolute tolerance that the capacitor is specified to over that temperature range. The
ceramic capacitor used for the flying and output capacitors should be X5R or better. Second, the voltage coef-
ficient of capacitance for the capacitor must be checked
and the actual value usually needs to be derated for the
operating voltage (the actual value has to be larger than
the value needed to take into account the loss of capacitance due to voltage bias across the capacitor). Third, the
frequency characteristics need to be taken into account
because capacitance goes down as the frequency of
oscillation goes up. Typically, the manufacturers have
capacitance vs frequency curves for their products. This
curve must be referenced to be sure the capacitance will
not be too small for the application. Finally, the capacitor
ESR and ESL must be low for reasons mentioned in the
following section.
Output Ripple
Normal LTC1983 operation produces voltage ripple on the
V
pin. Output voltage ripple is required for the LTC1983
OUT
to regulate. Low frequency ripple exists due to the hysteresis in the sense comparator and propagation delays in the
charge pump enable/disable circuits. High frequency ripple
is also present mainly due to ESR of the output capacitor.
Typical output ripple under maximum load is 60mV
with a low ESR 10µF output capacitor. The magnitude of
the ripple voltage depends on several factors. High input
voltage to negative output voltage differentials [(VIN +
V
) >1V] increase the output ripple since more charge
OUT
is delivered to C
per clock cycle. A large flying capacitor
OUT
(>1µF) also increases ripple for the same reason. Large
output current load and/or a small output capacitor (<10µF)
P-P
results in higher ripple due to higher output voltage dV/dt.
High ESR capacitors (ESR > 0.1Ω) on the output pin cause
high frequency voltage spikes on V
with every clock
OUT
cycle.
There are several ways to reduce the output voltage ripple.
A larger C
the low and high frequency ripple due to the lower C
capacitor (22µF or greater) will reduce both
OUT
OUT
charging and discharging dV/dt and the lower ESR typically found with higher value (larger case size) capacitors.
A low ESR ceramic output capacitor will minimize the high
frequency ripple, but will not reduce the low frequency
ripple unless a high capacitance value is chosen. A reasonable compromise is to use a 10µF to 22µF tantalum
capacitor in parallel with a 1µF to 4.7µF ceramic capacitor
on V
to reduce both the low and high frequency ripple.
OUT
However, the best solution is to use 10µF to 22µF, X5R
ceramic capacitors which are available in 1206 package
sizes. An RC filter may also be used to reduce high
frequency voltage spikes (see Figure 1).
In low load or high VIN applications, smaller values for
C
may be used to reduce output ripple. A smaller flying
FLY
capacitor (0.01µF to 0.047µF) delivers less charge per
clock cycle to the output capacitor resulting in lower
output ripple. However, the smaller value flying caps also
reduce the maximum I
Figure 1. Output Ripple Reduction Techniques
capability as well as efficiency.
OUT
sn1983 1983fs
7
LTC1983-3/LTC1983-5
U
OPERATIO
(Refer to Block Diagram)
Inrush Currents
During normal operation, VIN will experience current transients in the several hundred milliamp range whenever the
charge pump is enabled. During start-up, these inrush
currents may approach 1 to 2 amps. For this reason, it is
important to minimize the source resistance between the
input supply and the V
pin. Too much source resistance
IN
may result in regulation problems or even prevent startup. One way that this can be avoided (especially when the
source impedance can’t be lowered due to system constraints) is to use a large VIN capacitor with low ESR right
at the VIN pin. If ceramic capacitors are used, you may
need to add 1µF to 10µF tantalum capacitor in parallel to
limit input voltage transients. Input voltage transients will
occur if V
is applied via a switch or a plug. One example
IN
of this situation is in USB applications.
Ultralow Quiescent Current Regulated Supply
The LTC1983 contains an internal resistor divider (refer to
the Block Diagram) that draws only 1µA (typ for the 3V
version) from V
during normal operation. During shut-
OUT
down, the resistor divider is disconnected from the output
and the part draws only leakage current from the output.
During no-load conditions, applying a 1Hz to 100Hz, 2%
to 5% duty cycle signal to the SHDN pin ensures that the
circuit of Figure 2 comes out of shutdown frequently
enough to maintain regulation even under low-load conditions. Since the part spends nearly all of its time in
shutdown, the no-load quiescent current is essentially
zero. However, the part will still be in operation during the
time the SHDN pin is high, so the current will not be zero
and can be calculated using the following equations to
determine the approximate maximum current: I
IN(MAX)
=
[(Time out of shutdown) • (Burst Mode operation quiescent current) + (Normal operating IIN) • (Time output is
being charged before the LTC1983 enters Burst Mode
operation)]/(Period of SHDN signal). This number will be
highly dependent on the amount of board leakage current
and how many devices are connected to V
(each will
OUT
draw some leakage current) and must be calculated and
verified for each different board design.
V
IN
TANTALUM
Figure 2. Ultralow Quiescent Current Regulated Supply
3.3V TO 5.5V
C
IN
10µF
SHDN PIN WAVEFORMS:
LOW IQ MODE
≤ 100µA)
(I
OUT
(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)
LTC1983-3
V
SHDN
IN
GND
V
OUT
+
C
C
FLY
1µF
CERAMIC
V
LOAD ENABLE MODE
OUT
= 100µA TO 100mA)
(I
OUT
–
C
FROM MPU
SHDN
–3V ± 4%
C
OUT
10µF
CERAMIC
1983 F02
The LTC1983 must be out of shutdown for a minimum
duration of 200µs to allow enough time to sense the output
and keep it in regulation. A 1Hz, 2% duty cycle signal will
keep V
in regulation under no-load conditions. Even
OUT
though the term no-load is used, there will always be board
leakage current and leakage current drawn by anything
connected to V
. This is why it is necessary to wake the
OUT
part up every once in a while to verify regulation. As the
V
load current increases, the frequency with which the
OUT
part is taken out of shutdown must also be increased to
prevent V
from drooping below the – 2.88V (for the 3V
OUT
version) during the OFF phase (see Figure 3). A 100Hz, 2%
duty cycle signal on the SHDN pin ensures proper regulation with load currents as high as 100µA. When load
current greater than 100µA is needed, the SHDN pin must
be forced high as in normal operation.
Each time the LTC1983 comes out of shutdown, the part
delivers a minimum of one clock cycle worth of charge to
the output. Under high VIN (>4V) and/or low I
(<10µA)
OUT
conditions, this behavior may cause a net excess of charge
to be delivered to the output capacitor if a high frequency
signal is used on the SHDN pin (e.g., 50Hz to 100Hz).
Under such conditions, V
will slowly drift positive and
OUT
may even go out of regulation. To avoid this potential
8
sn1983 1983fs
OUTPUT CURRENT (µA)
1
10
100
1000
MAXIMUM SHDN OFF TIME (ms)
1000
1983 F03b
1 10 100
SHDN ON PULSE WIDTH = 200µs
C
OUT
= 10µF
U
OPERATIO
problem in the low IQ mode, it is necessary to switch the
part in and out of shutdown at the minimum allowable
frequency (refer to Figure 3) for a given output load.
General Layout Considerations
Due to the high switching frequency and high transient
currents produced by the LTC1983, careful board layout is
a must. A clean board layout using a ground plane and
short connections to all capacitors will improve performance and ensure proper regulation under all conditions
(refer to Figures 4a and 4b). You will not get advertised
performance with careless layout.
(Refer to Block Diagram)
LTC1983-3/LTC1983-5
Figure 3
VIN: 2.3V TO 5.5V
1 V
IN
V
OUT
2 V
3 C
OUT
SHDN 6
GND 5
+
C
–
C
C
FLY
OUT
C
IN
4
1983 F04a
Figure 4a. Recommended Component
Placement for a Single Layer Board
BOTTOM LAYER TOP LAYER
1 V
IN
V
OUT
2 V
3 C
OUT
+
SHDN 6
GND 5
–
C
4
C
IN
C
OUT
C
FLY
1983 F04b
Figure 4b. Recommended Component
Placement for a Double Layer Board
sn1983 1983fs
9
LTC1983-3/LTC1983-5
U
TYPICAL APPLICATIO S
2.5V to –2.5V DC/DC Converter
2.5V
OFF ON
V
2.5V TO 5.5V
OFF ON
V
IN
4.7µF
CERAMIC
V
IN
LTC1983-5
SHDN
+
C
0.47µF
CERAMIC
V
GND
OUT
C
–
100mA Inverting DC/DC Converter
IN
10µF
CERAMIC
V
IN
LTC1983-5
SHDN
+
C
1µF
CERAMIC
V
OUT
GND
–
C
1983 TA03
1983 TA04
1µF
CERAMIC
10µF
V
OUT
–2.5V
V
OUT
–V
IN
10
sn1983 1983fs
PACKAGE DESCRIPTIO
0.754
U
S6 Package
6-Lead Plastic SOT-23
(Reference LTC DWG # 05-08-1636)
0.854 ±0.127
LTC1983-3/LTC1983-5
2.90 BSC
(NOTE 4)
3.254
0.95 BSC
1.9 BSC
RECOMMENDED SOLDER PAD LAYOUT
0.20 BSC
DATUM ‘A’
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 – 0.20
(NOTE 3)
2.80 BSC
1.50 – 1.75
(NOTE 4)
1.00 MAX
0.95 BSC
0.80 – 0.90
PIN ONE ID
1.90 BSC
0.30 – 0.45 TYP
6 PLCS (NOTE 3)
0.01 – 0.10
S6 TSOT-23 0801
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
sn1983 1983fs
11
LTC1983-3/LTC1983-5
U
TYPICAL APPLICATIO
Combined Unregulated Doubler
and Regulated Inverter
OFF ON
V
IN
CERAMIC
D1
V
BOOST
C
IN
10µF
C
BOOST
1µF
= 2VIN –2(VD)
V
IN
LTC1983-3/
LTC1983-5
SHDN
+
C
D2
V
OUT
GND
–
C
C
10µF
CERAMIC
1983 TA05
OUT2
C
10µF
CERAMIC
C
1µF
CERAMIC
V
BOOST
V
OUT1
FLY
OUT
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1261 Switched-Capacitor Regulated Voltage Inverter Selectable Fixed Output Voltages
LTC1261L Switched-Capacitor Regulated Voltage Inverter Adjustable and Fixed Output Voltages, Up to 20mA I
LTC1429 Clock-Synchronized Switched-Capacitor Voltage Inverter Synchronizable Up to 2MHz System Clock
LTC1514/LTC1515 Step-Up/Step-Down Switched-Capacitor DC/DC Converters VIN 2V to 10V, Adjustable or Fixed V
LTC1516 Micropower Regulated 5V Charge Pump DC/DC Converter I
LTC1522 Micropower Regulated 5V Charge Pump DC/DC Converter I
LTC1550L/LTC1551L Low Noise, Switched-Capacitor Regulated Voltage Inverters 900kHz Charge Pump, 1mV
= 20mA (VIN ≥ 2V), I
OUT
= 10mA (VIN ≥ 2.7V), I
OUT
= 50mA (VIN ≥ 3V)
OUT
OUT
Ripple
P-P
, I
OUT
OUT
= 20mA (VIN ≥ 3V)
LT1611 1.4MHz Inverting Mode Switching Regulator –5V at 150mA from a 5V Input, 5-Lead ThinSOT
LT1617/LT1617-1 Micropower, Switched-Capacitor Voltage Inverter VIN 1.2V/1V to 15V; 350mA/100mA Current Limit
LTC1682/-3.3/-5 Doubler Charge Pumps with Low Noise LDO MS8 and SO-8 Packages, I
LTC1751/-3.3/-5 Doubler Charge Pumps V
=5V at 100mA; V
OUT
LTC1754/-3.3/-5 Doubler Charge Pumps with Shutdown ThinSOT Package; IQ = 13µA; I
LTC1928-5 Doubler Charge Pump with Low Noise LDO ThinSOT Output Noise = 60µV
= 80mA, Output Noise = 60µV
OUT
=3.3V at 80mA; ADJ; MSOP Packages
OUT
= 50mA
OUT
; V
RMS
= 5V; VIN = 2.7V to 4V
OUT
LTC3200 Constant Frequency Doubler Charge Pump Low Noise, 5V Output or Adjustable
OUT
to 50mA
, MSOP
RMS
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
sn1983 1983fs
LT/TP 0302 2K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2002
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