Current Mode Operation for Excellent Line and Load
Transient Response
n
Low Quiescent Current: 270µA
n
Shutdown Mode Draws Only 8µA Supply Current
n
±2.5% Reference Accuracy
n
Tiny 6-Lead SOT-23 Package
applicaTions
n
Lithium-Ion-Powered Applications
n
Cellular Telephones
n
Wireless Modems
n
Portable Computers
n
Scanners
The LTC®1872 is a constant frequency current mode step-
up DC/DC controller providing excellent AC and DC load
and line regulation. The device incorporates an accurate
undervoltage lockout feature that shuts down the LTC1872
when the input voltage falls below 2.0V.
The LTC1872 boasts a ±2.5% output voltage accuracy
and consumes only 270µA of quiescent current. For ap
plications where efficiency is a prime consideration, the
LTC1872
is configured for Burst Mode operation, which
enhances efficiency at low output current.
In shutdown, the device draws a mere 8µA. The high
550kHz constant operating frequency allows the use of a
small external inductor.
The LTC1872 is available in a small footprint 6-lead
SOT-23.
L, LT , LT C , LT M, Burst Mode, Linear Technology and the Linear logo are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
, NGATE Voltages ............. –0.3V to (VIN + 0.3V)
, ITH/RUN Voltages .............................. –0.3V to 2.4V
FB
TH
/RUN 1
GND 2
V
FB
T
JMAX
3
6 NGATE
5 V
4 SENSE
S6 PACKAGE
= 150°C, θJA = 230°C/W
IN
Lead Temperature (Soldering, 10 sec) ...................300°C
orDer inForMaTion
LEAD FREE FINISHTAPE AND REELPART MARKINGPACKAGE DESCRIPTIONTEMPERATURE RANGE
LTC1872ES6#PBFLTC1872ES6#TRPBFLTMK6-Lead Plastic SOT-23–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to:
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
http://www.linear.com/leadfree/
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified. (Note 2)
PARAMETERCONDITIONSMINTYPMAXUNITS
Input DC Supply Current
Normal Operation
Sleep Mode
Shutdown
UVLO
Undervoltage Lockout ThresholdV
Shutdown Threshold (at I
Start-Up Current SourceV
Regulated Feedback Voltage0°C to 70°C(Note 5)
V
Input Current(Note 5)1050nA
FB
Oscillator FrequencyV
Gate Drive Rise TimeC
Gate Drive Fall TimeC
Peak Current Sense Voltage(Note 6)114120mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1872E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
dissipation P
T
is calculated from the ambient temperature TA and power
J
according to the following formula:
D
= TA + (PD •θJA°C/W)
J
TH
/RUN)
Typicals at V
2.4V ≤ VIN ≤ 9.8V
2.4V ≤ VIN ≤ 9.8V
2.4V ≤ VIN ≤ 9.8V, V
VIN < UVLO Threshold
Falling
IN
V
Rising
IN
/RUN = 0V0.250.50.85µA
ITH
–40°C to 85°C(Note 5)
= 0.8V500550650kHz
FB
LOAD
LOAD
= 4.2V (Note 4)
IN
/RUN = 0V
ITH
l
1.55
1.85
l
0.150.350.55V
l
0.780
l
0.770
= 3000pF40ns
= 3000pF40ns
Dynamic supply current is higher due to the gate charge being
Note 4:
delivered at the switching frequency.
Note 5: The LTC1872 is tested in a feedback loop that servos V
output of the error amplifier.
Note 6: Guaranteed by design at duty cycle = 30%. Peak current sense
voltage is V
increases due to slope compensation as shown in Figure 2.
/6.67 at duty cycle <40%, and decreases as duty cycle
REF
270
230
8
6
2.00
2.10
0.800
0.800
420
370
22
10
2.35
2.40
0.820
0.830
to the
FB
µA
µA
µA
µA
1872fa
V
V
V
V
2
For more information www.linear.com/LTC1872
Page 3
Typical perForMance characTerisTics
LTC1872
Reference Voltage
vs Temperature
825
VIN = 4.2V
820
815
810
805
800
795
VOLTAGE (mV)
FB
V
790
785
780
775
–355
–15
–55
85
45125
25
TEMPERATURE (°C)
105
65
1872 G01
Maximum Current Sense Trip
Voltage vs Duty Cycle
130
120
110
100
– (mV)
90
SENSE
– V
80
IN
V
70
60
50
2030
4050
DUTY CYCLE (%)
6070
Normalized Oscillator Frequency
vs Temperature
10
VIN = 4.2V
8
6
4
2
0
–2
–4
–6
NORMALIZED FREQUENCY (%)
–8
–10
–355
–55
VIN = 4.2V
= 25°C
T
A
80 90
–15
TEMPERATURE (°C)
100
1872 G04
45125
65
25
85
105
1872 G02
Shutdown Threshold
vs Temperature
600
VIN = 4.2V
560
520
480
440
400
360
/RUN VOLTAGE (mV)
320
TH
I
280
240
200
–355
–15
–55
TEMPERATURE (°C)
Undervoltage Lockout Trip
Voltage vs Temperature
2.24
VIN FALLING
2.20
2.16
2.12
2.08
2.04
2.00
1.96
UVLO TRIP VOLTAGE (V)
1.92
1.88
1.84
–355
–15
–55
45125
65
25
25
TEMPERATURE (°C)
85
105
1872 G05
85
45125
105
65
1872 G03
pin FuncTions
ITH/RUN (Pin 1): This pin performs two functions. It
serves as the error amplifier compensation point as well
as the run control input. Nominal voltage range for this
pin is 0.7V to 1.9V. Forcing this pin below 0.35V causes
the device to be shut down. In shutdown all functions are
disabled and the NGATE pin is held low.
GND (Pin 2): Ground Pin.
(Pin 3): Receives the feedback voltage from an external
V
FB
resistive divider across the output.
–
SENSE
(Pin 4): The Negative Input to the Current Com-
parator.
(Pin 5): Supply Pin. Must be closely decoupled to
V
IN
GND Pin 2.
NGATE (Pin 6): Gate Drive for the External N-Channel
MOSFET. This pin swings from 0V to V
For more information www.linear.com/LTC1872
IN
.
1872fa
3
Page 4
LTC1872
FuncTional DiagraM
–
SENSE
V
IN
5
4
4
+
ICMP
–
OSC
FREQ
FOLDBACK
V
IN
+
0.3V
GND
2
–
SLOPE
COMP
–
+
0.5µA
V
IN
VOLTAGE
REFERENCE
UNDERVOLTAGE
LOCKOUT
0.3V
0.15V
V
0.8V
REF
0.35V
V
RS
R
Q
S
+
–
/RUN
I
1
TH
+
–
BURST
CMP
SHDN
CMP
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
OVP
SLEEP
EAMP
SHDN
UV
IN
NGATE
6
+
V
REF
+
–
60mV
V
REF
+
0.8V
V
FB
–
1.2V
3
V
IN
1872FD
operaTion
(Refer to Functional Diagram)
Main Control Loop
The LTC1872 is a constant frequency current mode
switching regulator. During normal operation, the external
N-channel power MOSFET is turned on each cycle by the
oscillator and turned off when the current comparator
(ICMP) resets the RS latch. The peak inductor current
at which ICMP resets the RS latch is controlled by the
voltage on the I
/RUN pin, which is the output of the
TH
error amplifier EAMP. An external resistive divider connected between V
and ground allows the EAMP to
OUT
receive an output feedback voltage V
current increases, it causes a slight decrease in V
4
relative to the 0.8V reference, which in turn causes the
/RUN voltage to increase until the average inductor
I
TH
current matches the new load current.
The main control loop is shut down by pulling the ITH/
RUN pin low. Releasing I
current source to charge up the external compensation
network. When the I
control loop is enabled with the I
pulled up to its zero current level of approximately 0.7V.
As the external compensation network continues to charge
. When the load
FB
For more information www.linear.com/LTC1872
up, the corre
allowing normal operation.
FB
/RUN allows an internal 0.5µA
TH
/RUN pin reaches 0.35V, the main
TH
/RUN voltage then
TH
sponding output current trip level follows,
1872fa
Page 5
operaTion
V
0.7
()
LTC1872
Comparator OVP guards against transient overshoots
> 7.5% by turning off the external N-channel power
MOSFET and keeping it off until the fault is removed.
Burst Mode Operation
The LTC1872
enters Burst Mode operation at low load
currents. In this mode, the peak current of the inductor is
set as if V
the voltage at the I
/RUN = 1V (at low duty cycles) even though
ITH
/RUN pin is at a lower value. If the
TH
inductor’s average current is greater than the load requirement, the voltage at the I
/RUN voltage goes below 0.85V, the sleep signal goes
I
TH
/RUN pin will drop. When the
TH
high, turning off the external MOSFET. The sleep signal
goes low when the I
/RUN voltage goes above 0.925V
TH
and the LTC1872 resumes normal operation. The next
oscillator cycle will turn the external MOSFET on and the
switching cycle repeats.
Undervoltage Lockout
To prevent operation of the N-channel MOSFET below safe
input voltage levels, an undervoltage lockout is incorpo
rated into the LTC1872. When the input supply voltage
drops below approximately 2.0V,
the N-channel MOSFET
and all circuitry is turned off except the undervoltage block,
which draws only several microamperes.
Overvoltage Protection
The overvoltage comparator in the LTC1872 will turn the
external MOSFET off when the feedback voltage has risen
7.5% above the reference voltage of 0.8V. This comparator
has a typical hysteresis of 20mV.
Slope Compensation and Inductor’s Peak Current
The inductor’s peak current is determined by:
−
IPK=
ITH
10 R
SENSE
when the LTC1872 is operating below 40% duty cycle.
However, once the duty cycle exceeds 40%, slope compensation begins and effectively reduces the peak inductor
.
current
The amount of reduction is given by the curves
in Figure 2.
Short-Circuit Protection
Since the power switch in a boost converter is not in
series with the power path from input to load, turning off
the switch provides no protection from a short-circuit at
the output. External means such as a fuse in series with
the boost inductor must be employed to handle this fault
condition.
110
100
90
80
(%)
70
60
OUT(MAX)
/I
50
OUT
SF = I
Figure 2. Maximum Output Current vs Duty Cycle
For more information www.linear.com/LTC1872
I
= 0.4I
RIPPLE
AT 5% DUTY CYCLE
40
30
20
VIN = 4.2V
10
070 80 90 1006010 20 30 40 50
= 0.2I
I
RIPPLE
AT 5% DUTY CYCLE
DUTY CYCLE (%)
PK
PK
1872 F02
1872fa
5
Page 6
LTC1872
V
V
IN
0.03
SENSE
applicaTions inForMaTion
The basic LTC1872 application circuit is shown in
Figure1. External component selection is driven by the
OUT
and
(= C2).
load requirement and begins with the selection of L1
R
diode D1 is selected followed by C
R
R
(= R1). Next, the power MOSFET and the output
SENSE
(= C1) and C
IN
Selection for Output Current
SENSE
is chosen based on the required output current.
SENSE
With the current comparator monitoring the voltage developed across R
, the threshold of the comparator
SENSE
determines the inductor’s peak current. The output current
the LTC1872 can provide is given by:
I
OUT
where I
0.12
=
R
SENSE
is the inductor peak-to-peak ripple current
RIPPLE
I
−
RIPPLE
(see Inductor Value Calculation section) and V
V
IN
2
V
OUT
+ V
D
is the
D
forward drop of the output diode at the full rated output
current.
A reasonable starting point for setting ripple current is:
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use
of a smaller inductor for the same amount of inductor ripple
current.
However, this is at the expense of efficiency due
to an increase in MOSFET gate charge losses.
The inductance value also has a direct effect on ripple
current. The ripple current, I
inductance or frequency and increases with higher V
, decreases with higher
RIPPLE
OUT
.
The inductor’s peak-to-peak ripple current is given by:
I
RIPPLE
V
V
IN
=
f L
( )
OUT
V
+ VD−V
+ V
OUT
IN
D
where f is the operating frequency. Accepting larger values
of I
allows the use of low inductances, but results
RIPPLE
in higher output voltage ripple and greater core losses.
A reasonable starting point for setting ripple current is:
I
RIPPLE
= 0.4 I
()
OUT MAX
()
V
OUT
V
IN
+ V
D
+
D
V
I
RIPPLE
= O.4
()
I
()
OUT
OUT
Rearranging the above equation, it becomes:
R
for Duty Cycle <40%
SENSE
=
10
()
1
I
()
OUT
V
V
OUT
IN
+ V
D
However, for operation that is above 40% duty cycle, slope
compensation’s effect has to be taken into consideration
to select the appropriate value to provide the required
amount of current. Using the scaling factor (SF, in %) in
Figure 2, the value of R
R
SENSE
=
()
10
SF
I
()
OUT
SENSE
100
()
is:
V
V
OUT
IN
+ V
D
In Burst Mode operation, the ripple current is normally set
such that the inductor current is continuous during the
burst periods. Therefore, the peak-to-peak ripple current
must not exceed:
I
RIPPLE
≤
R
This implies a minimum inductance of:
IN
L
MIN
V
=
0.03
f
R
SENSE
A smaller value than L
V
+ VD−V
OUT
V
+ V
OUT
could be used in the circuit;
MIN
IN
D
however, the inductor current will not be continuous
during burst periods.
6
1872fa
For more information www.linear.com/LTC1872
Page 7
applicaTions inForMaTion
P
I
I
CIN Required I
0.3
()
I
LTC1872
Inductor Selection
When selecting the inductor, keep in mind that inductor
saturation current has to be greater than the current limit
set by the current sense resistor. Also, keep in mind that
the DC resistance of the inductor will affect the efficiency.
Off the shelf inductors are available from Murata, Coilcraft,
Toko, Panasonic, Coiltronics and many other suppliers.
Power MOSFET Selection
The main selection criteria for the power MOSFET are the
threshold voltage V
, the “on” resistance R
GS(TH)
reverse transfer capacitance C
and total gate charge.
RSS
DS(ON)
,
Since the LTC1872 is designed for operation down to low
input voltages, a logic level threshold MOSFET (R
guaranteed at V
= 2.5V) is required for applications
GS
DS(ON)
that work close to this voltage. When these MOSFETs are
used, make sure that the input supply to the LTC1872 is
less than the absolute maximum V
The required minimum R
DS(ON)
rating, typically 8V.
GS
of the MOSFET is governed
by its allowable power dissipation given by:
I
IN
P
2
1+δp
()
R
DS(ON)
≅
DC
()
where PP is the allowable power dissipation and δp is the
temperature dependency of R
given for a MOSFET in the form of a normalized R
. (1 + δp) is generally
DS(ON)
DS(ON)
vs temperature curve, but δp = 0.005/°C can be used as
an approximation for low voltage MOSFETs. DC is the
maximum operating duty cycle of the LTC1872.
Output Diode Selection
It is important to adequately specify the diode peak current and average power dissipation so as not to exceed
the diode ratings.
Schottky diodes are recommended for low for
ward drop
and fast switching times. Remember to keep lead length
short and observe proper grounding (see Board Layout
Checklist) to avoid ringing and increased dissipation.
C
IN
and C
Selection
OUT
To prevent large input voltage ripple, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current for a boost
converter is approximately equal to:
where I
≈
RMS
is as defined in the Inductor Value Calcula-
RIPPLE
RIPPLE
tion section.
Note that capacitor manufacturer’s ripple current ratings are
often based on 2000 hours of life. This makes it advisable to
further derate the capacitor, or to choose a capacitor rated
at a higher temperature than required. Several capacitors
may be paralleled to meet the size or height requirements
in the design. Due to the high operating frequency of the
LTC1872, ceramic capacitors can also be used for C
IN
.
Always consult the manufacturer if there is any question.
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering.
The output ripple (∆V
) is approximated by:
OUT
Under normal load conditions, the average current con
ducted by the diode in a boost converter is equal to the
output load current:
D(avg)
OUT
=
OUT
≈ IO•
-
ΔV
For more information www.linear.com/LTC1872
V
OUT
ESR
2
1
OUT
•
1
2
2
1872fa
+ V
I
D
RIPPLE
IN
+
2
+
2πfC
V
7
Page 8
LTC1872
applicaTions inForMaTion
where f is the operating frequency, C
capacitance and I
is the ripple current in the inductor.
RIPPLE
is the output
OUT
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR (size)
product of any aluminum electrolytic at a somewhat higher
price. The output capacitor RMS current is approximately
equal to:
IPK• DC−DC
2
where IPK is the peak inductor current and DC is the switch
duty cycle.
When using electrolytic output capacitors, if the ripple and
ESR requirements are met, there is likely to be far more
capacitance than required.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. An excellent choice of
tantalum capacitors is the AVX TPS and KEMET T510
series of surface mount tantalum capacitors. Also,
ceramic capacitors in X5R pr X7R dielectrics offer excellent performance.
Low Supply Operation
Setting Output Voltage
The LTC1872 develops a 0.8V reference voltage between
the feedback (Pin 3) terminal and ground (see Figure 4).
By selecting resistor R1, a constant current is caused to
flow through R1 and R2 to set the overall output voltage.
The regulated output voltage is determined by:
= 0.8V 1+
OUT
105
100
95
90
85
NORMALIZED VOLTAGE (%)
80
75
2.0
Figure 3. Line Regulation of V
LTC1872
V
R2
R1
V
REF
V
ITH
2.22.42.62.8
INPUT VOLTAGE (V)
REF
3
V
FB
R2
R1
1872 F03
and V
V
OUT
3.0
ITH
Although the LTC1872 can function down to approximately 2.0V, the maximum allowable output current is
reduced when
VIN decreases below 3V. Figure 3 shows
the amount of change as the supply is reduced down to
2V. Also shown in Figure 3 is the effect of VIN on V
VIN goes below 2.3V.
8
as
REF
For more information www.linear.com/LTC1872
1872 F04
Figure 4. Setting Output Voltage
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Page 9
applicaTions inForMaTion
LTC1872
For most applications, an 80k resistor is suggested for
R1. To prevent stray pickup, locate resistors R1 and R2
close to LTC1872.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (η1 + η2 + η3 + ...)
where η1, η2, etc. are the individual losses as a percentage of input power.
Although all
dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1872 circuits: 1) LTC1872 DC bias current, 2)
MOSFET gate charge current, 3) I2R losses and 4) voltage
drop of the output diode.
1. The VIN current is the DC supply current, given in the
electrical characteristics, that excludes MOSFET driver
and control currents. VIN current results in a small loss
which increases with VIN.
2. MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each
time a MOSFET gate is switched from low to high to
low again, a packet of charge, dQ, moves from V
to ground. The resulting dQ/dt is a current out of V
IN
IN
which is typically much larger than the contoller’s DC
supply current. In continuous mode, I
2
R losses are predicted from the DC resistances of
3. I
GATECHG
= f(Qp).
the MOSFET, inductor and current sense resistor.
The MOSFET R
multiplied by duty cycle times
DS(ON)
the average output current squared can be summed
with I2R losses in the inductor ESR in series with the
current sense resistor.
4. The output diode is a major source of power loss at high
currents. The diode loss is calculated by multiplying
the forward voltage by the load current.
5. Transition losses apply to the external MOSFET and
increase at higher operating frequencies and input
voltages. Transition losses can be estimated from:
Transition Loss = 2(VIN)2I
IN(MAX)CRSS
Other losses, including CIN and C
(f)
ESR dissipative
OUT
losses, and inductor core losses, generally account for
less than 2% total additional loss.
For more information www.linear.com/LTC1872
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9
Page 10
LTC1872
applicaTions inForMaTion
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC1872. These items are illustrated graphically in
the layout diagram in Figure 5. Check the following in
your layout:
1. The Schottky diode should be closely connected
between the output capacitor and the drain of the
external MOSFET.
The (+) plate of C
2.
should connect to the sense resis-
IN
tor as closely as possible. This capacitor provides AC
current to the inductor.
3. The input decoupling capacitor (0.1µF) should be
connected closely between VIN (Pin 5) and ground
(Pin 2).
1
ITH/RUN
LTC1872
R
ITH
C
ITH
2
GND
3
V
FB
R2
NGATE
SENSE
6
5
V
IN
0.1µF
4
–
4. Connect the end of R
as close to VIN (Pin 5) as
SENSE
possible. The VIN pin is the SENSE+ of the current
comparator.
5. The trace from SENSE– (Pin 4) to the Sense resistor
should be kept short. The trace should connect close
to R
SENSE
.
6. Keep the switching node NGATE away from sensitive
small signal nodes.
7. The VFB pin should connect directly to the feedback
resistors. The resistive divider R1 and R2 must be
connected between the (+) plate of C
and signal
OUT
ground.
V
IN
R
S
+
C
IN
L1
+
M1
D1
V
OUT
C
OUT
R1
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 5. LTC1872 Layout Diagram (See PC Board Layout Checklist)
Dimensions in inches (millimeters) unless otherwise noted.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
0.95 BSC
0.80 – 0.90
0.30 – 0.45
6 PLCS (NOTE 3)
0.20 BSC
DATUM ‘A’
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 – 0.20
(NOTE 3)
1.00 MAX
0.01 – 0.10
1.90 BSC
S6 TSOT-23 0302
12
1872fa
For more information www.linear.com/LTC1872
Page 13
LTC1872
revision hisTory
REVDATEDESCRIPTIONPAGE NUMBER
A09/15Revised package drawing12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
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